config: Move the memory instantiation outside FSConfig

This patch moves the instantiation of the memory controller outside
FSConfig and instead relies on the mem_ranges to pass the information
to the caller (e.g. fs.py or one of the regression scripts). The main
motivation for this change is to expose the structural composition of
the memory system and allow more tuning and configuration without
adding a large number of options to the makeSystem functions.

The patch updates the relevant example scripts to maintain the current
functionality. As the order that ports are connected to the memory bus
changes (in certain regresisons), some bus stats are shuffled
around. For example, what used to be layer 0 is now layer 1.

Going forward, options will be added to support the addition of
multi-channel memory controllers.

configs/common/FSConfig.py

@@ -55,7 +55,7 @@ class MemBus(CoherentBus):
     default = Self.badaddr_responder.pio
 
 
-def makeLinuxAlphaSystem(mem_mode, MemClass, mdesc = None):
+def makeLinuxAlphaSystem(mem_mode, mdesc = None):
     IO_address_space_base = 0x80000000000
     class BaseTsunami(Tsunami):
         ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
@@ -73,11 +73,9 @@ def makeLinuxAlphaSystem(mem_mode, MemClass, mdesc = None):
     # base address (including the PCI config space)
     self.bridge = Bridge(delay='50ns',
                          ranges = [AddrRange(IO_address_space_base, Addr.max)])
-    self.physmem = MemClass(range = AddrRange(mdesc.mem()))
+    self.mem_ranges = [AddrRange(mdesc.mem())]
-    self.mem_ranges = [self.physmem.range]
     self.bridge.master = self.iobus.slave
     self.bridge.slave = self.membus.master
-    self.physmem.port = self.membus.master
     self.disk0 = CowIdeDisk(driveID='master')
     self.disk2 = CowIdeDisk(driveID='master')
     self.disk0.childImage(mdesc.disk())
@@ -104,15 +102,13 @@ def makeLinuxAlphaSystem(mem_mode, MemClass, mdesc = None):
 
     return self
 
-def makeLinuxAlphaRubySystem(mem_mode, MemClass, mdesc = None):
+def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
     class BaseTsunami(Tsunami):
         ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
         ide = IdeController(disks=[Parent.disk0, Parent.disk2],
                             pci_func=0, pci_dev=0, pci_bus=0)
-        
+    self = LinuxAlphaSystem()
-    physmem = MemClass(range = AddrRange(mdesc.mem()))
+    self.mem_ranges = [AddrRange(mdesc.mem())]
-    self = LinuxAlphaSystem(physmem = physmem)
-    self.mem_ranges = [self.physmem.range]
     if not mdesc:
         # generic system
         mdesc = SysConfig()
@@ -121,13 +117,6 @@ def makeLinuxAlphaRubySystem(mem_mode, MemClass, mdesc = None):
     # Create pio bus to connect all device pio ports to rubymem's pio port
     self.piobus = NoncoherentBus()
 
-    #
-    # Pio functional accesses from devices need direct access to memory
-    # RubyPort currently does support functional accesses.  Therefore provide
-    # the piobus a direct connection to physical memory
-    #
-    self.piobus.master = physmem.port
-
     self.disk0 = CowIdeDisk(driveID='master')
     self.disk2 = CowIdeDisk(driveID='master')
     self.disk0.childImage(mdesc.disk())
@@ -157,7 +146,7 @@ def makeLinuxAlphaRubySystem(mem_mode, MemClass, mdesc = None):
 
     return self
 
-def makeSparcSystem(mem_mode, MemClass, mdesc = None):
+def makeSparcSystem(mem_mode, mdesc = None):
     # Constants from iob.cc and uart8250.cc
     iob_man_addr = 0x9800000000
     uart_pio_size = 8
@@ -180,13 +169,10 @@ def makeSparcSystem(mem_mode, MemClass, mdesc = None):
     self.t1000 = T1000()
     self.t1000.attachOnChipIO(self.membus)
     self.t1000.attachIO(self.iobus)
-    self.physmem = MemClass(range = AddrRange(Addr('1MB'), size = '64MB'))
+    self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
-    self.physmem2 = MemClass(range = AddrRange(Addr('2GB'), size ='256MB'))
+                       AddrRange(Addr('2GB'), size ='256MB')]
-    self.mem_ranges = [self.physmem.range, self.physmem2.range]
     self.bridge.master = self.iobus.slave
     self.bridge.slave = self.membus.master
-    self.physmem.port = self.membus.master
-    self.physmem2.port = self.membus.master
     self.rom.port = self.membus.master
     self.nvram.port = self.membus.master
     self.hypervisor_desc.port = self.membus.master
@@ -225,7 +211,7 @@ def makeSparcSystem(mem_mode, MemClass, mdesc = None):
 
     return self
 
-def makeArmSystem(mem_mode, machine_type, MemClass, mdesc = None,
+def makeArmSystem(mem_mode, machine_type, mdesc = None,
                   dtb_filename = None, bare_metal=False):
     assert machine_type
 
@@ -273,8 +259,7 @@ def makeArmSystem(mem_mode, machine_type, MemClass, mdesc = None,
     if bare_metal:
         # EOT character on UART will end the simulation
         self.realview.uart.end_on_eot = True
-        self.physmem = MemClass(range = AddrRange(Addr(mdesc.mem())))
+        self.mem_ranges = [AddrRange(mdesc.mem())]
-        self.mem_ranges = [self.physmem.range]
     else:
         self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
         if dtb_filename is not None:
@@ -288,11 +273,8 @@ def makeArmSystem(mem_mode, machine_type, MemClass, mdesc = None,
 
         boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
                      'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem()
-
+        self.mem_ranges = [AddrRange(self.realview.mem_start_addr,
-        self.physmem = MemClass(range = AddrRange(self.realview.mem_start_addr,
+                                     size = mdesc.mem())]
-                                                  size = mdesc.mem()),
-                                conf_table_reported = True)
-        self.mem_ranges = [self.physmem.range]
         self.realview.setupBootLoader(self.membus, self, binary)
         self.gic_cpu_addr = self.realview.gic.cpu_addr
         self.flags_addr = self.realview.realview_io.pio_addr + 0x30
@@ -300,8 +282,6 @@ def makeArmSystem(mem_mode, machine_type, MemClass, mdesc = None,
         if mdesc.disk().lower().count('android'):
             boot_flags += " init=/init "
         self.boot_osflags = boot_flags
-
-    self.physmem.port = self.membus.master
     self.realview.attachOnChipIO(self.membus, self.bridge)
     self.realview.attachIO(self.iobus)
     self.intrctrl = IntrControl()
@@ -313,7 +293,7 @@ def makeArmSystem(mem_mode, machine_type, MemClass, mdesc = None,
     return self
 
 
-def makeLinuxMipsSystem(mem_mode, MemClass, mdesc = None):
+def makeLinuxMipsSystem(mem_mode, mdesc = None):
     class BaseMalta(Malta):
         ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
         ide = IdeController(disks=[Parent.disk0, Parent.disk2],
@@ -327,11 +307,9 @@ def makeLinuxMipsSystem(mem_mode, MemClass, mdesc = None):
     self.iobus = NoncoherentBus()
     self.membus = MemBus()
     self.bridge = Bridge(delay='50ns')
-    self.physmem = MemClass(range = AddrRange('1GB'))
+    self.mem_ranges = [AddrRange('1GB')]
-    self.mem_ranges = [self.physmem.range]
     self.bridge.master = self.iobus.slave
     self.bridge.slave = self.membus.master
-    self.physmem.port = self.membus.master
     self.disk0 = CowIdeDisk(driveID='master')
     self.disk2 = CowIdeDisk(driveID='master')
     self.disk0.childImage(mdesc.disk())
@@ -369,7 +347,6 @@ def connectX86ClassicSystem(x86_sys, numCPUs):
     APIC_range_size = 1 << 12;
 
     x86_sys.membus = MemBus()
-    x86_sys.physmem.port = x86_sys.membus.master
 
     # North Bridge
     x86_sys.iobus = NoncoherentBus()
@@ -409,19 +386,13 @@ def connectX86RubySystem(x86_sys):
     # North Bridge
     x86_sys.piobus = NoncoherentBus()
 
-    #
-    # Pio functional accesses from devices need direct access to memory
-    # RubyPort currently does support functional accesses.  Therefore provide
-    # the piobus a direct connection to physical memory
-    #
-    x86_sys.piobus.master = x86_sys.physmem.port
     # add the ide to the list of dma devices that later need to attach to
     # dma controllers
     x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
     x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports)
 
 
-def makeX86System(mem_mode, MemClass, numCPUs = 1, mdesc = None, self = None,
+def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None,
                   Ruby = False):
     if self == None:
         self = X86System()
@@ -434,8 +405,7 @@ def makeX86System(mem_mode, MemClass, numCPUs = 1, mdesc = None, self = None,
     self.mem_mode = mem_mode
 
     # Physical memory
-    self.physmem = MemClass(range = AddrRange(mdesc.mem()))
+    self.mem_ranges = [AddrRange(mdesc.mem())]
-    self.mem_ranges = [self.physmem.range]
 
     # Platform
     self.pc = Pc()
@@ -518,17 +488,16 @@ def makeX86System(mem_mode, MemClass, numCPUs = 1, mdesc = None, self = None,
     self.intel_mp_table.base_entries = base_entries
     self.intel_mp_table.ext_entries = ext_entries
 
-def makeLinuxX86System(mem_mode, MemClass, numCPUs = 1, mdesc = None,
+def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None,
                        Ruby = False):
     self = LinuxX86System()
 
     # Build up the x86 system and then specialize it for Linux
-    makeX86System(mem_mode, MemClass, numCPUs, mdesc, self, Ruby)
+    makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
 
     # We assume below that there's at least 1MB of memory. We'll require 2
     # just to avoid corner cases.
-    phys_mem_size = sum(map(lambda mem: mem.range.size(),
+    phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges))
-                            self.memories.unproxy(self)))
     assert(phys_mem_size >= 0x200000)
 
     self.e820_table.entries = \

configs/example/fs.py

@@ -102,17 +102,16 @@ else:
 np = options.num_cpus
 
 if buildEnv['TARGET_ISA'] == "alpha":
-    test_sys = makeLinuxAlphaSystem(test_mem_mode, TestMemClass, bm[0])
+    test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
 elif buildEnv['TARGET_ISA'] == "mips":
-    test_sys = makeLinuxMipsSystem(test_mem_mode, TestMemClass, bm[0])
+    test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
 elif buildEnv['TARGET_ISA'] == "sparc":
-    test_sys = makeSparcSystem(test_mem_mode, TestMemClass, bm[0])
+    test_sys = makeSparcSystem(test_mem_mode, bm[0])
 elif buildEnv['TARGET_ISA'] == "x86":
-    test_sys = makeLinuxX86System(test_mem_mode, TestMemClass,
+    test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0])
-                                  options.num_cpus, bm[0])
 elif buildEnv['TARGET_ISA'] == "arm":
-    test_sys = makeArmSystem(test_mem_mode, options.machine_type,
+    test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0],
-                             TestMemClass, bm[0], options.dtb_filename,
+                             options.dtb_filename,
                              bare_metal=options.bare_metal)
 else:
     fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
@@ -164,18 +163,24 @@ for i in xrange(np):
 
 CacheConfig.config_cache(options, test_sys)
 
+# Create the appropriate memory controllers and connect them to the
+# memory bus
+test_sys.mem_ctrls = [TestMemClass(range = r, conf_table_reported = True)
+                      for r in test_sys.mem_ranges]
+for i in xrange(len(test_sys.mem_ctrls)):
+    test_sys.mem_ctrls[i].port = test_sys.membus.master
+
 if len(bm) == 2:
     if buildEnv['TARGET_ISA'] == 'alpha':
-        drive_sys = makeLinuxAlphaSystem(drive_mem_mode, DriveMemClass, bm[1])
+        drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
     elif buildEnv['TARGET_ISA'] == 'mips':
-        drive_sys = makeLinuxMipsSystem(drive_mem_mode, DriveMemClass, bm[1])
+        drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
     elif buildEnv['TARGET_ISA'] == 'sparc':
-        drive_sys = makeSparcSystem(drive_mem_mode, DriveMemClass, bm[1])
+        drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
     elif buildEnv['TARGET_ISA'] == 'x86':
-        drive_sys = makeX86System(drive_mem_mode, DriveMemClass, np, bm[1])
+        drive_sys = makeX86System(drive_mem_mode, np, bm[1])
     elif buildEnv['TARGET_ISA'] == 'arm':
-        drive_sys = makeArmSystem(drive_mem_mode, options.machine_type,
+        drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
-                                  DriveMemClass, bm[1])
 
     # Create a source clock for the system and set the clock period
     drive_sys.clk_domain = SrcClockDomain(clock =  options.sys_clock)
@@ -201,6 +206,13 @@ if len(bm) == 2:
     drive_sys.iobridge.slave = drive_sys.iobus.master
     drive_sys.iobridge.master = drive_sys.membus.slave
 
+    # Create the appropriate memory controllers and connect them to the
+    # memory bus
+    drive_sys.mem_ctrls = [DriveMemClass(range = r, conf_table_reported = True)
+                           for r in drive_sys.mem_ranges]
+    for i in xrange(len(drive_sys.mem_ctrls)):
+        drive_sys.mem_ctrls[i].port = drive_sys.membus.master
+
     drive_sys.init_param = options.init_param
     root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
 elif len(bm) == 1:

configs/example/ruby_fs.py

@@ -83,10 +83,9 @@ if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
 TestMemClass = Simulation.setMemClass(options)
 
 if buildEnv['TARGET_ISA'] == "alpha":
-    system = makeLinuxAlphaRubySystem(test_mem_mode, TestMemClass, bm[0])
+    system = makeLinuxAlphaRubySystem(test_mem_mode, bm[0])
 elif buildEnv['TARGET_ISA'] == "x86":
-    system = makeLinuxX86System(test_mem_mode, TestMemClass,
+    system = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], True)
-                                options.num_cpus, bm[0], True)
     Simulation.setWorkCountOptions(system, options)
 else:
     fatal("incapable of building non-alpha or non-x86 full system!")
@@ -127,5 +126,13 @@ for (i, cpu) in enumerate(system.cpu):
 
     system.ruby._cpu_ruby_ports[i].access_phys_mem = True
 
+# Create the appropriate memory controllers and connect them to the
+# PIO bus
+system.mem_ctrls = [TestMemClass(range = r,
+                                 conf_table_reported = True)
+                    for r in system.mem_ranges]
+for i in xrange(len(system.physmem)):
+    system.mem_ctrls[i].port = system.piobus.master
+
 root = Root(full_system = True, system = system)
 Simulation.run(options, root, system, FutureClass)

configs/ruby/MESI_CMP_directory.py

@@ -140,8 +140,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
         
         cntrl_count += 1
 
-    phys_mem_size = sum(map(lambda mem: mem.range.size(),
+    phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
-                            system.memories.unproxy(system)))
     assert(phys_mem_size % options.num_dirs == 0)
     mem_module_size = phys_mem_size / options.num_dirs
 

configs/ruby/MI_example.py

@@ -105,8 +105,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
 
         cntrl_count += 1
 
-    phys_mem_size = sum(map(lambda mem: mem.range.size(),
+    phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
-                            system.memories.unproxy(system)))
     assert(phys_mem_size % options.num_dirs == 0)
     mem_module_size = phys_mem_size / options.num_dirs
 

configs/ruby/MOESI_CMP_directory.py

@@ -135,8 +135,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
 
         cntrl_count += 1
 
-    phys_mem_size = sum(map(lambda mem: mem.range.size(),
+    phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
-                            system.memories.unproxy(system)))
     assert(phys_mem_size % options.num_dirs == 0)
     mem_module_size = phys_mem_size / options.num_dirs
 

configs/ruby/MOESI_CMP_token.py

@@ -156,8 +156,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
 
         cntrl_count += 1
 
-    phys_mem_size = sum(map(lambda mem: mem.range.size(),
+    phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
-                            system.memories.unproxy(system)))
     assert(phys_mem_size % options.num_dirs == 0)
     mem_module_size = phys_mem_size / options.num_dirs
 

configs/ruby/MOESI_hammer.py

@@ -131,8 +131,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
 
         cntrl_count += 1
 
-    phys_mem_size = sum(map(lambda mem: mem.range.size(),
+    phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
-                            system.memories.unproxy(system)))
     assert(phys_mem_size % options.num_dirs == 0)
     mem_module_size = phys_mem_size / options.num_dirs
 

configs/ruby/Network_test.py

@@ -103,8 +103,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
 
         cntrl_count += 1
 
-    phys_mem_size = sum(map(lambda mem: mem.range.size(),
+    phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
-                            system.memories.unproxy(system)))
     assert(phys_mem_size % options.num_dirs == 0)
     mem_module_size = phys_mem_size / options.num_dirs
 

configs/ruby/Ruby.py

@@ -183,8 +183,7 @@ def create_system(options, system, piobus = None, dma_ports = []):
         total_mem_size.value += dir_cntrl.directory.size.value
         dir_cntrl.directory.numa_high_bit = numa_bit
 
-    phys_mem_size = sum(map(lambda mem: mem.range.size(),
+    phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
-                            system.memories.unproxy(system)))
     assert(total_mem_size.value == phys_mem_size)
 
     ruby_profiler = RubyProfiler(ruby_system = ruby,

tests/configs/alpha_generic.py

@@ -59,7 +59,7 @@ class LinuxAlphaSystemBuilder(object):
         pass
 
     def create_system(self):
-        system = FSConfig.makeLinuxAlphaSystem(self.mem_mode, DDR3_1600_x64)
+        system = FSConfig.makeLinuxAlphaSystem(self.mem_mode)
         self.init_system(system)
         return system
 

tests/configs/arm_generic.py

@@ -60,9 +60,7 @@ class LinuxArmSystemBuilder(object):
 
     def create_system(self):
         system = FSConfig.makeArmSystem(self.mem_mode,
-                                        self.machine_type,
+                                        self.machine_type, None, False)
-                                        DDR3_1600_x64,
-                                        None, False)
 
         # We typically want the simulator to panic if the kernel
         # panics or oopses. This prevents the simulator from running

tests/configs/base_config.py

@@ -221,6 +221,14 @@ class BaseFSSystem(BaseSystem):
     def init_system(self, system):
         BaseSystem.init_system(self, system)
 
+        # create the memory controllers and connect them, stick with
+        # the physmem name to avoid bumping all the reference stats
+        system.physmem = [self.mem_class(range = r,
+                                         conf_table_reported = True)
+                          for r in system.mem_ranges]
+        for i in xrange(len(system.physmem)):
+            system.physmem[i].port = system.membus.master
+
         # create the iocache, which by default runs at the system clock
         system.iocache = IOCache(addr_ranges=system.mem_ranges)
         system.iocache.cpu_side = system.iobus.master

tests/configs/memtest-ruby.py

@@ -91,6 +91,8 @@ system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
 for cpu in cpus:
     cpu.clk_domain = system.cpu_clk_domain
 
+system.mem_ranges = AddrRange('256MB')
+
 Ruby.create_system(options, system)
 
 # Create a separate clock domain for Ruby

tests/configs/pc-o3-timing.py

@@ -39,4 +39,5 @@ from m5.objects import *
 from x86_generic import *
 
 root = LinuxX86FSSystemUniprocessor(mem_mode='timing',
+                                    mem_class=DDR3_1600_x64,
                                     cpu_class=DerivO3CPU).create_root()

tests/configs/pc-simple-atomic.py

@@ -39,4 +39,5 @@ from m5.objects import *
 from x86_generic import *
 
 root = LinuxX86FSSystemUniprocessor(mem_mode='atomic',
+                                    mem_class=DDR3_1600_x64,
                                     cpu_class=AtomicSimpleCPU).create_root()

tests/configs/pc-simple-timing-ruby.py

@@ -55,7 +55,7 @@ options.num_cpus = 2
 
 #the system
 mdesc = SysConfig(disk = 'linux-x86.img')
-system = FSConfig.makeLinuxX86System('timing', DDR3_1600_x64, options.num_cpus,
+system = FSConfig.makeLinuxX86System('timing', options.num_cpus,
                                      mdesc=mdesc, Ruby=True)
 
 system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp')
@@ -84,5 +84,11 @@ for (i, cpu) in enumerate(system.cpu):
     # Set access_phys_mem to True for ruby port
     system.ruby._cpu_ruby_ports[i].access_phys_mem = True
 
+system.physmem = [DDR3_1600_x64(range = r,
+                                conf_table_reported = True)
+                  for r in system.mem_ranges]
+for i in xrange(len(system.physmem)):
+    system.physmem[i].port = system.piobus.master
+
 root = Root(full_system = True, system = system)
 m5.ticks.setGlobalFrequency('1THz')

tests/configs/pc-simple-timing.py

@@ -39,5 +39,6 @@ from m5.objects import *
 from x86_generic import *
 
 root = LinuxX86FSSystemUniprocessor(mem_mode='timing',
+                                    mem_class=DDR3_1600_x64,
                                     cpu_class=TimingSimpleCPU).create_root()
 

tests/configs/pc-switcheroo-full.py

@@ -42,6 +42,7 @@ from x86_generic import *
 import switcheroo
 
 root = LinuxX86FSSwitcheroo(
+    mem_class=DDR3_1600_x64,
     cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, DerivO3CPU)
     ).create_root()
 

tests/configs/realview-o3-checker.py

@@ -39,5 +39,6 @@ from m5.objects import *
 from arm_generic import *
 
 root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
+                                    mem_class=DDR3_1600_x64,
                                     cpu_class=DerivO3CPU,
                                     checker=True).create_root()

tests/configs/realview-o3-dual.py

@@ -38,5 +38,7 @@
 from m5.objects import *
 from arm_generic import *
 
-root = LinuxArmFSSystem(mem_mode='timing', cpu_class=DerivO3CPU,
+root = LinuxArmFSSystem(mem_mode='timing',
+                        mem_class=DDR3_1600_x64,
+                        cpu_class=DerivO3CPU,
                         num_cpus=2).create_root()

tests/configs/realview-o3.py

@@ -39,4 +39,5 @@ from m5.objects import *
 from arm_generic import *
 
 root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
+                                    mem_class=DDR3_1600_x64,
                                     cpu_class=DerivO3CPU).create_root()

tests/configs/realview-simple-atomic-dual.py

@@ -38,5 +38,7 @@
 from m5.objects import *
 from arm_generic import *
 
-root = LinuxArmFSSystem(mem_mode='atomic', cpu_class=AtomicSimpleCPU,
+root = LinuxArmFSSystem(mem_mode='atomic',
+                        mem_class=DDR3_1600_x64,
+                        cpu_class=AtomicSimpleCPU,
                         num_cpus=2).create_root()

tests/configs/realview-simple-atomic.py

@@ -39,5 +39,6 @@ from m5.objects import *
 from arm_generic import *
 
 root = LinuxArmFSSystemUniprocessor(mem_mode='atomic',
+                                    mem_class=DDR3_1600_x64,
                                     cpu_class=AtomicSimpleCPU).create_root()
 

tests/configs/realview-simple-timing-dual.py

@@ -38,5 +38,7 @@
 from m5.objects import *
 from arm_generic import *
 
-root = LinuxArmFSSystem(mem_mode='timing', cpu_class=TimingSimpleCPU,
+root = LinuxArmFSSystem(mem_mode='timing',
+                        mem_class=DDR3_1600_x64,
+                        cpu_class=TimingSimpleCPU,
                         num_cpus=2).create_root()

tests/configs/realview-simple-timing.py

@@ -39,4 +39,5 @@ from m5.objects import *
 from arm_generic import *
 
 root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
+                                    mem_class=DDR3_1600_x64,
                                     cpu_class=TimingSimpleCPU).create_root()

tests/configs/realview-switcheroo-atomic.py

@@ -40,6 +40,7 @@ from arm_generic import *
 import switcheroo
 
 root = LinuxArmFSSwitcheroo(
+    mem_class=DDR3_1600_x64,
     cpu_classes=(AtomicSimpleCPU, AtomicSimpleCPU)
     ).create_root()
 

tests/configs/realview-switcheroo-full.py

@@ -40,6 +40,7 @@ from arm_generic import *
 import switcheroo
 
 root = LinuxArmFSSwitcheroo(
+    mem_class=DDR3_1600_x64,
     cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, DerivO3CPU)
     ).create_root()
 

tests/configs/realview-switcheroo-o3.py

@@ -40,6 +40,7 @@ from arm_generic import *
 import switcheroo
 
 root = LinuxArmFSSwitcheroo(
+    mem_class=DDR3_1600_x64,
     cpu_classes=(DerivO3CPU, DerivO3CPU)
     ).create_root()
 

tests/configs/realview-switcheroo-timing.py

@@ -40,6 +40,7 @@ from arm_generic import *
 import switcheroo
 
 root = LinuxArmFSSwitcheroo(
+    mem_class=DDR3_1600_x64,
     cpu_classes=(TimingSimpleCPU, TimingSimpleCPU)
     ).create_root()
 

tests/configs/rubytest-ruby.py

@@ -80,6 +80,8 @@ tester = RubyTester(check_flush = check_flush, checks_to_complete = 100,
 system = System(tester = tester, physmem = SimpleMemory(null = True),
                 clk_domain = SrcClockDomain(clock = options.sys_clock))
 
+system.mem_ranges = AddrRange('256MB')
+
 Ruby.create_system(options, system)
 
 # Create a separate clock domain for Ruby

tests/configs/simple-timing-ruby.py

@@ -74,6 +74,8 @@ system = System(cpu = cpu, physmem = SimpleMemory(null = True),
 # CPUs frequency
 system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
 
+system.mem_ranges = AddrRange('256MB')
+
 Ruby.create_system(options, system)
 
 # Create a separate clock for Ruby

tests/configs/t1000-simple-atomic.py

@@ -31,7 +31,7 @@ from m5.objects import *
 m5.util.addToPath('../configs/common')
 import FSConfig
 
-system = FSConfig.makeSparcSystem('atomic', SimpleMemory)
+system = FSConfig.makeSparcSystem('atomic')
 system.clk_domain = SrcClockDomain(clock = '1GHz')
 system.cpu_clk_domain = SrcClockDomain(clock = '1GHz')
 cpu = AtomicSimpleCPU(cpu_id=0, clk_domain = system.cpu_clk_domain)
@@ -40,6 +40,14 @@ system.cpu = cpu
 cpu.createInterruptController()
 cpu.connectAllPorts(system.membus)
 
+# create the memory controllers and connect them, stick with
+# the physmem name to avoid bumping all the reference stats
+system.physmem = [SimpleMemory(range = r,
+                               conf_table_reported = True)
+                  for r in system.mem_ranges]
+for i in xrange(len(system.physmem)):
+    system.physmem[i].port = system.membus.master
+
 root = Root(full_system=True, system=system)
 
 m5.ticks.setGlobalFrequency('2GHz')

tests/configs/tsunami-inorder.py

@@ -39,4 +39,5 @@ from m5.objects import *
 from alpha_generic import *
 
 root = LinuxAlphaFSSystemUniprocessor(mem_mode='timing',
+                                      mem_class=DDR3_1600_x64,
                                       cpu_class=InOrderCPU).create_root()

tests/configs/tsunami-o3-dual.py

@@ -38,5 +38,7 @@
 from m5.objects import *
 from alpha_generic import *
 
-root = LinuxAlphaFSSystem(mem_mode='timing', cpu_class=DerivO3CPU,
+root = LinuxAlphaFSSystem(mem_mode='timing',
+                          mem_class=DDR3_1600_x64,
+                          cpu_class=DerivO3CPU,
                           num_cpus=2).create_root()

tests/configs/tsunami-o3.py

@@ -39,4 +39,5 @@ from m5.objects import *
 from alpha_generic import *
 
 root = LinuxAlphaFSSystemUniprocessor(mem_mode='timing',
+                                      mem_class=DDR3_1600_x64,
                                       cpu_class=DerivO3CPU).create_root()

tests/configs/tsunami-simple-atomic-dual.py

@@ -38,5 +38,7 @@
 from m5.objects import *
 from alpha_generic import *
 
-root = LinuxAlphaFSSystem(mem_mode='atomic', cpu_class=AtomicSimpleCPU,
+root = LinuxAlphaFSSystem(mem_mode='atomic',
+                          mem_class=DDR3_1600_x64,
+                          cpu_class=AtomicSimpleCPU,
                           num_cpus=2).create_root()

tests/configs/tsunami-simple-atomic.py

@@ -39,4 +39,5 @@ from m5.objects import *
 from alpha_generic import *
 
 root = LinuxAlphaFSSystemUniprocessor(mem_mode='atomic',
+                                      mem_class=DDR3_1600_x64,
                                       cpu_class=AtomicSimpleCPU).create_root()

tests/configs/tsunami-simple-timing-dual.py

@@ -38,5 +38,7 @@
 from m5.objects import *
 from alpha_generic import *
 
-root = LinuxAlphaFSSystem(mem_mode='timing', cpu_class=TimingSimpleCPU,
+root = LinuxAlphaFSSystem(mem_mode='timing',
+                          mem_class=DDR3_1600_x64,
+                          cpu_class=TimingSimpleCPU,
                           num_cpus=2).create_root()

tests/configs/tsunami-simple-timing.py

@@ -39,4 +39,5 @@ from m5.objects import *
 from alpha_generic import *
 
 root = LinuxAlphaFSSystemUniprocessor(mem_mode='timing',
+                                      mem_class=DDR3_1600_x64,
                                       cpu_class=TimingSimpleCPU).create_root()

tests/configs/tsunami-switcheroo-full.py

@@ -40,6 +40,7 @@ from alpha_generic import *
 import switcheroo
 
 root = LinuxAlphaFSSwitcheroo(
+    mem_class=DDR3_1600_x64,
     cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, DerivO3CPU)
     ).create_root()
 

tests/configs/twosys-tsunami-simple-atomic.py

@@ -32,8 +32,8 @@ m5.util.addToPath('../configs/common')
 from FSConfig import *
 from Benchmarks import *
 
-test_sys = makeLinuxAlphaSystem('atomic', SimpleMemory,
+test_sys = makeLinuxAlphaSystem('atomic',
-                                 SysConfig('netperf-stream-client.rcS'))
+                                SysConfig('netperf-stream-client.rcS'))
 
 # Create the system clock domain
 test_sys.clk_domain = SrcClockDomain(clock = '1GHz')
@@ -57,7 +57,10 @@ test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
 test_sys.iobridge.slave = test_sys.iobus.master
 test_sys.iobridge.master = test_sys.membus.slave
 
-drive_sys = makeLinuxAlphaSystem('atomic', SimpleMemory,
+test_sys.physmem = SimpleMemory(range = test_sys.mem_ranges[0])
+test_sys.physmem.port = test_sys.membus.master
+
+drive_sys = makeLinuxAlphaSystem('atomic',
                                  SysConfig('netperf-server.rcS'))
 # Create the system clock domain
 drive_sys.clk_domain = SrcClockDomain(clock = '1GHz')
@@ -77,6 +80,9 @@ drive_sys.iobridge = Bridge(delay='50ns', ranges = drive_sys.mem_ranges)
 drive_sys.iobridge.slave = drive_sys.iobus.master
 drive_sys.iobridge.master = drive_sys.membus.slave
 
+drive_sys.physmem = SimpleMemory(range = drive_sys.mem_ranges[0])
+drive_sys.physmem.port = drive_sys.membus.master
+
 root = makeDualRoot(True, test_sys, drive_sys, "ethertrace")
 
 maxtick = 199999999

tests/configs/x86_generic.py

@@ -58,7 +58,6 @@ class LinuxX86SystemBuilder(object):
     def create_system(self):
         mdesc = SysConfig(disk = 'linux-x86.img')
         system = FSConfig.makeLinuxX86System(self.mem_mode,
-                                             DDR3_1600_x64,
                                              numCPUs=self.num_cpus,
                                              mdesc=mdesc)
         system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')