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X86: Fix address size handling so real mode works properly.

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Virtual (pre-segmentation) addresses are truncated based on address size, and
any non-64 bit linear address is truncated to 32 bits. This means that real
mode addresses aren't truncated down to 16 bits after their segment bases are
added in.
This commit is contained in:
Gabe Black 2012-03-31 12:27:33 -07:00
parent 74043c4f5c
commit a7859f7e45
2 changed files with 4 additions and 1 deletions
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2
src/arch/x86/isa/microops/ldstop.isa
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@ -361,7 +361,7 @@ let {{
exec_output = "" exec_output = ""
calculateEA = ''' calculateEA = '''
EA = bits(SegBase + scale * Index + Base + disp, addressSize * 8 - 1, 0); EA = SegBase + bits(scale * Index + Base + disp, addressSize * 8 - 1, 0);
''' '''
def defineMicroLoadOp(mnemonic, code, bigCode='', def defineMicroLoadOp(mnemonic, code, bigCode='',

3
src/arch/x86/tlb.cc
View file

@ -281,6 +281,9 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
return new GeneralProtection(0); return new GeneralProtection(0);
} }
} }
if (m5Reg.mode != LongMode ||
(flags & (AddrSizeFlagBit << FlagShift)))
vaddr &= mask(32);
// If paging is enabled, do the translation. // If paging is enabled, do the translation.
if (m5Reg.paging) { if (m5Reg.paging) {
DPRINTF(TLB, "Paging enabled.\n"); DPRINTF(TLB, "Paging enabled.\n");