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arm: compute ID_PFR{0,1} registers 

Compute the proper values of the aforementioned registers from
the system configuration rather than configuring the values themselves.

Change-Id: Ie7685b5d8b5f2dd9d6380b4af74f16d596b2bfd1
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Curtis Dunham 2016-12-19 11:03:27 -06:00
parent 282cf5807d
commit a73937b60c
2 changed files with 9 additions and 13 deletions
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9
src/arch/arm/ArmISA.py
View File

@ -57,15 +57,6 @@ class ArmISA(SimObject):
midr = Param.UInt32(0x410fc0f0, "MIDR value")
# See section B4.1.93 - B4.1.94 of the ARM ARM
#
# !ThumbEE | !Jazelle | Thumb | ARM
# Note: ThumbEE is disabled for now since we don't support CP14
# config registers and jumping to ThumbEE vectors
id_pfr0 = Param.UInt32(0x00000031, "Processor Feature Register 0")
# !Timer | Virti | !M Profile | TrustZone | ARMv4
id_pfr1 = Param.UInt32(0x00001011, "Processor Feature Register 1")
# See section B4.1.89 - B4.1.92 of the ARM ARM
# VMSAv7 support
id_mmfr0 = Param.UInt32(0x10201103, "Memory Model Feature Register 0")

13
src/arch/arm/isa.cc
View File

@ -358,10 +358,6 @@ ISA::clear()
miscRegs[MISCREG_CPACR] = 0;
miscRegs[MISCREG_ID_PFR0] = p->id_pfr0;
miscRegs[MISCREG_ID_PFR1] = p->id_pfr1;
miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
@ -772,6 +768,15 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
case MISCREG_HSCTLR:
return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830;
case MISCREG_ID_PFR0:
// !ThumbEE | !Jazelle | Thumb | ARM
return 0x00000031;
case MISCREG_ID_PFR1:
// !Timer | Virti | !M Profile | TrustZone | ARMv4
return 0x00000001
| (haveSecurity ? 0x00000010 : 0x0)
| (haveVirtualization ? 0x00001000 : 0x0);
// Generic Timer registers
case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: