Rearrange the FS configs to be more shared. Also check in the full-system tests. Reference stats coming soon.
configs/test/fs.py:
Pull out a lot of common code and put it into configs/common/FSConfig.py.
--HG--
extra : convert_revision : 175b18d75f82ddecbcc9a6418fe40df314db55d5
This commit is contained in:
Kevin Lim
parent
acf9cf21a2
commit
a6c2e5cca0
3 changed files with 125 additions and 81 deletions
104
configs/common/FSConfig.py
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104
configs/common/FSConfig.py
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# Copyright (c) 2006 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Kevin Lim
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import m5
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from m5.objects import *
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from FullO3Config import *
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from SysPaths import *
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from Util import *
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script.dir = '/z/saidi/work/m5.newmem/configs/boot'
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linux_image = env.get('LINUX_IMAGE', disk('linux-latest.img'))
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class CowIdeDisk(IdeDisk):
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image = CowDiskImage(child=RawDiskImage(read_only=True),
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read_only=False)
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def childImage(self, ci):
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self.image.child.image_file = ci
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class BaseTsunami(Tsunami):
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ethernet = NSGigE(configdata=NSGigEPciData(),
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pci_bus=0, pci_dev=1, pci_func=0)
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etherint = NSGigEInt(device=Parent.ethernet)
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ide = IdeController(disks=[Parent.disk0, Parent.disk2],
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pci_func=0, pci_dev=0, pci_bus=0)
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def MyLinuxAlphaSystem(cpu, mem_mode, linux_image, icache=None, dcache=None, l2cache=None):
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self = LinuxAlphaSystem()
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self.iobus = Bus(bus_id=0)
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self.membus = Bus(bus_id=1)
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self.bridge = Bridge()
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self.physmem = PhysicalMemory(range = AddrRange('128MB'))
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self.bridge.side_a = self.iobus.port
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self.bridge.side_b = self.membus.port
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self.physmem.port = self.membus.port
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self.disk0 = CowIdeDisk(driveID='master')
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self.disk2 = CowIdeDisk(driveID='master')
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self.disk0.childImage(linux_image)
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self.disk2.childImage(disk('linux-bigswap2.img'))
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self.tsunami = BaseTsunami()
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self.tsunami.attachIO(self.iobus)
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self.tsunami.ide.pio = self.iobus.port
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self.tsunami.ide.dma = self.iobus.port
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self.tsunami.ide.config = self.iobus.port
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self.tsunami.ethernet.pio = self.iobus.port
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self.tsunami.ethernet.dma = self.iobus.port
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self.tsunami.ethernet.config = self.iobus.port
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self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = linux_image,
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read_only = True))
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self.intrctrl = IntrControl()
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self.cpu = cpu
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connectCpu(self.cpu, self.membus, icache, dcache, l2cache)
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for each_cpu in listWrapper(self.cpu):
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each_cpu.itb = AlphaITB()
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each_cpu.dtb = AlphaDTB()
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self.cpu.clock = '2GHz'
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self.sim_console = SimConsole(listener=ConsoleListener(port=3456))
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self.kernel = binary('vmlinux')
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self.pal = binary('ts_osfpal')
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self.console = binary('console')
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self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
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return self
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class TsunamiRoot(Root):
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pass
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def DualRoot(clientSystem, serverSystem):
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self = Root()
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self.client = clientSystem
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self.server = serverSystem
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self.etherdump = EtherDump(file='ethertrace')
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self.etherlink = EtherLink(int1 = Parent.client.tsunami.etherint[0],
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int2 = Parent.server.tsunami.etherint[0],
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dump = Parent.etherdump)
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self.clock = '1THz'
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return self
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@ -2,8 +2,10 @@ import optparse, os, sys
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import m5
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from m5.objects import *
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m5.AddToPath('../common')
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from FSConfig import *
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from SysPaths import *
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from FullO3Config import *
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from Util import *
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parser = optparse.OptionParser()
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@ -19,90 +21,27 @@ if args:
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print "Error: script doesn't take any positional arguments"
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sys.exit(1)
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# Base for tests is directory containing this file.
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test_base = os.path.dirname(__file__)
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script.dir = '/z/saidi/work/m5.newmem/configs/boot'
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linux_image = env.get('LINUX_IMAGE', disk('linux-latest.img'))
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class CowIdeDisk(IdeDisk):
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image = CowDiskImage(child=RawDiskImage(read_only=True),
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read_only=False)
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def childImage(self, ci):
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self.image.child.image_file = ci
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class BaseTsunami(Tsunami):
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ethernet = NSGigE(configdata=NSGigEPciData(),
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pci_bus=0, pci_dev=1, pci_func=0)
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etherint = NSGigEInt(device=Parent.ethernet)
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ide = IdeController(disks=[Parent.disk0, Parent.disk2],
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pci_func=0, pci_dev=0, pci_bus=0)
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class MyLinuxAlphaSystem(LinuxAlphaSystem):
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iobus = Bus(bus_id=0)
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membus = Bus(bus_id=1)
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bridge = Bridge()
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physmem = PhysicalMemory(range = AddrRange('128MB'))
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bridge.side_a = iobus.port
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bridge.side_b = membus.port
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physmem.port = membus.port
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disk0 = CowIdeDisk(driveID='master')
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disk2 = CowIdeDisk(driveID='master')
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disk0.childImage(linux_image)
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disk2.childImage(disk('linux-bigswap2.img'))
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tsunami = BaseTsunami()
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tsunami.attachIO(iobus)
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tsunami.ide.pio = iobus.port
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tsunami.ide.dma = iobus.port
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tsunami.ide.config = iobus.port
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tsunami.ethernet.pio = iobus.port
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tsunami.ethernet.dma = iobus.port
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tsunami.ethernet.config = iobus.port
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simple_disk = SimpleDisk(disk=RawDiskImage(image_file = linux_image,
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read_only = True))
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intrctrl = IntrControl()
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if options.detailed:
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cpu = DetailedO3CPU()
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cpu2 = DetailedO3CPU()
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mem_mode = 'Timing'
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elif options.timing:
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cpu = TimingSimpleCPU()
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mem_mode = 'timing'
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cpu2 = TimingSimpleCPU()
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mem_mode = 'Timing'
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else:
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cpu = AtomicSimpleCPU()
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cpu.mem = membus
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cpu.icache_port = membus.port
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cpu.dcache_port = membus.port
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cpu.itb = AlphaITB()
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cpu.dtb = AlphaDTB()
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cpu.clock = '2GHz'
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sim_console = SimConsole(listener=ConsoleListener(port=3456))
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kernel = binary('vmlinux')
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pal = binary('ts_osfpal')
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console = binary('console')
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boot_osflags = 'root=/dev/hda1 console=ttyS0'
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class TsunamiRoot(Root):
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pass
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def DualRoot(clientSystem, serverSystem):
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self = Root()
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self.client = clientSystem
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self.server = serverSystem
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self.etherdump = EtherDump(file='ethertrace')
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self.etherlink = EtherLink(int1 = Parent.client.tsunami.etherint[0],
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int2 = Parent.server.tsunami.etherint[0],
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dump = Parent.etherdump)
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self.clock = '1THz'
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return self
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cpu2 = AtomicSimpleCPU()
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mem_mode = 'Atomic'
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if options.dual:
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root = DualRoot(
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MyLinuxAlphaSystem(readfile=script('netperf-stream-nt-client.rcS')),
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MyLinuxAlphaSystem(readfile=script('netperf-server.rcS')))
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MyLinuxAlphaSystem(cpu, mem_mode, linux_image),
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MyLinuxAlphaSystem(cpu2, mem_mode, linux_image))
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root.client.readfile = script('netperf-stream-nt-client.rcS')
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root.server.readfile = script('netperf-server.rcS')
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else:
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root = TsunamiRoot(clock = '2GHz', system = MyLinuxAlphaSystem())
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root = TsunamiRoot(clock = '2GHz', system = MyLinuxAlphaSystem(cpu, mem_mode, linux_image))
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m5.instantiate(root)
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1
tests/halt.sh
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1
tests/halt.sh
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m5 exit
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