scons: Fix warnings issued by clang 3.2svn (XCode 4.6)
This patch fixes the warnings that clang3.2svn emit due to the "-Wall" flag. There is one case of an uninitialised value in the ARM neon ISA description, and then a whole range of unused private fields that are pruned.
This commit is contained in:
parent
08a5fd328b
commit
a62afd094b
23 changed files with 17 additions and 53 deletions
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@ -89,8 +89,11 @@ class LinuxAlphaSystem : public AlphaSystem
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/** Event to halt the simulator if the kernel calls panic() */
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/** Event to halt the simulator if the kernel calls panic() */
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BreakPCEvent *kernelPanicEvent;
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BreakPCEvent *kernelPanicEvent;
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#if 0
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/** Event to halt the simulator if the kernel calls die_if_kernel */
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/** Event to halt the simulator if the kernel calls die_if_kernel */
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BreakPCEvent *kernelDieEvent;
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BreakPCEvent *kernelDieEvent;
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#endif
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#endif
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#endif
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/**
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/**
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@ -2820,6 +2820,7 @@ let {{
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4, vcvts2fpCode, fromInt = True)
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4, vcvts2fpCode, fromInt = True)
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vcvts2hCode = '''
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vcvts2hCode = '''
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destElem = 0;
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FPSCR fpscr = (FPSCR) FpscrExc;
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FPSCR fpscr = (FPSCR) FpscrExc;
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float srcFp1 = bitsToFp(srcElem1, (float)0.0);
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float srcFp1 = bitsToFp(srcElem1, (float)0.0);
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if (flushToZero(srcFp1))
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if (flushToZero(srcFp1))
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@ -2836,6 +2837,7 @@ let {{
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twoRegNarrowMiscInst("vcvt", "NVcvts2h", "SimdCvtOp", ("uint16_t",), vcvts2hCode)
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twoRegNarrowMiscInst("vcvt", "NVcvts2h", "SimdCvtOp", ("uint16_t",), vcvts2hCode)
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vcvth2sCode = '''
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vcvth2sCode = '''
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destElem = 0;
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FPSCR fpscr = (FPSCR) FpscrExc;
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FPSCR fpscr = (FPSCR) FpscrExc;
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VfpSavedState state = prepFpState(VfpRoundNearest);
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VfpSavedState state = prepFpState(VfpRoundNearest);
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__asm__ __volatile__("" : "=m" (srcElem1), "=m" (destElem)
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__asm__ __volatile__("" : "=m" (srcElem1), "=m" (destElem)
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@ -627,7 +627,7 @@ X86ISA::Interrupts::Interrupts(Params * p) :
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pendingStartup(false), startupVector(0),
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pendingStartup(false), startupVector(0),
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startedUp(false), pendingUnmaskableInt(false),
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startedUp(false), pendingUnmaskableInt(false),
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pendingIPIs(0), cpu(NULL),
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pendingIPIs(0), cpu(NULL),
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intSlavePort(name() + ".int_slave", this, this, latency)
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intSlavePort(name() + ".int_slave", this, this)
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{
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{
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pioSize = PageBytes;
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pioSize = PageBytes;
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memset(regs, 0, sizeof(regs));
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memset(regs, 0, sizeof(regs));
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@ -399,8 +399,9 @@
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// Really only the LSB matters, but the decoder
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// Really only the LSB matters, but the decoder
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// will sign extend it, and there's no easy way to
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// will sign extend it, and there's no easy way to
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// specify only checking the first byte.
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// specify only checking the first byte.
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-0x80: SyscallInst::int80('xc->syscall(Rax)',
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0xffffffffffffff80:
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IsSyscall, IsNonSpeculative, IsSerializeAfter);
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SyscallInst::int80('xc->syscall(Rax)',
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IsSyscall, IsNonSpeculative, IsSerializeAfter);
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}
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}
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}
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}
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0x6: decode MODE_SUBMODE {
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0x6: decode MODE_SUBMODE {
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@ -1327,8 +1327,6 @@ class DistStor
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Counter max_track;
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Counter max_track;
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/** The number of entries in each bucket. */
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/** The number of entries in each bucket. */
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Counter bucket_size;
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Counter bucket_size;
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/** The number of buckets. Equal to (max-min)/bucket_size. */
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size_type buckets;
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/** The smallest value sampled. */
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/** The smallest value sampled. */
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Counter min_val;
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Counter min_val;
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@ -548,13 +548,6 @@ class TrafficGen : public MemObject
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* state is complete.
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* state is complete.
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*/
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*/
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bool traceComplete;
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bool traceComplete;
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/**
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* Used to store the Tick when the next generate should
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* occur. It is to remove a transaction as soon as we
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* enter the state.
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*/
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Tick oldEmitTime;
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};
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};
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/** Pointer to owner of request handler */
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/** Pointer to owner of request handler */
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@ -582,8 +575,7 @@ class TrafficGen : public MemObject
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public:
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public:
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TrafficGenPort(const std::string& name, TrafficGen& _owner)
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TrafficGenPort(const std::string& name, TrafficGen& _owner)
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: QueuedMasterPort(name, &_owner, queue), queue(_owner, *this),
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: QueuedMasterPort(name, &_owner, queue), queue(_owner, *this)
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owner(_owner)
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{ }
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{ }
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protected:
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protected:
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@ -594,9 +586,6 @@ class TrafficGen : public MemObject
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MasterPacketQueue queue;
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MasterPacketQueue queue;
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// Owner of the port
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TrafficGen& owner;
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};
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};
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TrafficGenPort port;
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TrafficGenPort port;
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@ -78,8 +78,6 @@ class IGbE(EtherDevice):
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cxx_header = "dev/i8254xGBe.hh"
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cxx_header = "dev/i8254xGBe.hh"
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hardware_address = Param.EthernetAddr(NextEthernetAddr,
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hardware_address = Param.EthernetAddr(NextEthernetAddr,
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"Ethernet Hardware Address")
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"Ethernet Hardware Address")
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use_flow_control = Param.Bool(False,
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"Should we use xon/xoff flow contorl (UNIMPLEMENTD)")
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rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO")
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rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO")
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tx_fifo_size = Param.MemorySize('384kB', "Size of the tx FIFO")
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tx_fifo_size = Param.MemorySize('384kB', "Size of the tx FIFO")
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rx_desc_cache_size = Param.Int(64,
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rx_desc_cache_size = Param.Int(64,
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@ -51,8 +51,6 @@
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*/
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*/
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class TsunamiIO : public BasicPioDevice
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class TsunamiIO : public BasicPioDevice
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{
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{
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private:
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struct tm tm;
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protected:
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protected:
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@ -58,7 +58,6 @@ using namespace Net;
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IGbE::IGbE(const Params *p)
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IGbE::IGbE(const Params *p)
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: EtherDevice(p), etherInt(NULL), drainManager(NULL),
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: EtherDevice(p), etherInt(NULL), drainManager(NULL),
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useFlowControl(p->use_flow_control),
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rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size), rxTick(false),
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rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size), rxTick(false),
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txTick(false), txFifoTick(false), rxDmaPacket(false), pktOffset(0),
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txTick(false), txFifoTick(false), rxDmaPacket(false), pktOffset(0),
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fetchDelay(p->fetch_delay), wbDelay(p->wb_delay),
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fetchDelay(p->fetch_delay), wbDelay(p->wb_delay),
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@ -70,9 +70,6 @@ class IGbE : public EtherDevice
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// The drain event if we have one
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// The drain event if we have one
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DrainManager *drainManager;
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DrainManager *drainManager;
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// cached parameters from params struct
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bool useFlowControl;
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// packet fifos
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// packet fifos
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PacketFifo rxFifo;
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PacketFifo rxFifo;
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PacketFifo txFifo;
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PacketFifo txFifo;
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@ -66,11 +66,11 @@ class IntDev
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class IntSlavePort : public MessageSlavePort
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class IntSlavePort : public MessageSlavePort
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{
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{
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IntDev * device;
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IntDev * device;
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Tick latency;
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public:
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public:
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IntSlavePort(const std::string& _name, MemObject* _parent,
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IntSlavePort(const std::string& _name, MemObject* _parent,
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IntDev* dev, Tick _latency) :
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IntDev* dev) :
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MessageSlavePort(_name, _parent), device(dev), latency(_latency)
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MessageSlavePort(_name, _parent), device(dev)
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{
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{
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}
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}
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@ -44,7 +44,7 @@ class Consumer
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{
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{
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public:
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public:
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Consumer(ClockedObject *_em)
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Consumer(ClockedObject *_em)
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: m_last_scheduled_wakeup(0), m_last_wakeup(0), em(_em)
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: m_last_scheduled_wakeup(0), em(_em)
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{
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{
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}
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}
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@ -93,7 +93,6 @@ class Consumer
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private:
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private:
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Tick m_last_scheduled_wakeup;
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Tick m_last_scheduled_wakeup;
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std::set<Tick> m_scheduled_wakeups;
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std::set<Tick> m_scheduled_wakeups;
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Tick m_last_wakeup;
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ClockedObject *em;
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ClockedObject *em;
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class ConsumerEvent : public Event
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class ConsumerEvent : public Event
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@ -66,8 +66,6 @@ class BlockBloomFilter : public AbstractBloomFilter
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int m_filter_size;
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int m_filter_size;
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int m_filter_size_bits;
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int m_filter_size_bits;
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int m_count_bits;
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int m_count;
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};
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};
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#endif // __MEM_RUBY_FILTERS_BLOCKBLOOMFILTER_HH__
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#endif // __MEM_RUBY_FILTERS_BLOCKBLOOMFILTER_HH__
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@ -71,8 +71,6 @@ class BulkBloomFilter : public AbstractBloomFilter
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int m_sector_bits;
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int m_sector_bits;
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int m_count_bits;
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int m_count;
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};
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};
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#endif // __MEM_RUBY_FILTERS_BULKBLOOMFILTER_HH__
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#endif // __MEM_RUBY_FILTERS_BULKBLOOMFILTER_HH__
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@ -80,9 +80,6 @@ class H3BloomFilter : public AbstractBloomFilter
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int m_par_filter_size;
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int m_par_filter_size;
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int m_par_filter_size_bits;
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int m_par_filter_size_bits;
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int m_count_bits;
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int m_count;
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int primes_list[6];// = {9323,11279,10247,30637,25717,43711};
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int primes_list[6];// = {9323,11279,10247,30637,25717,43711};
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int mults_list[6]; //= {255,29,51,3,77,43};
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int mults_list[6]; //= {255,29,51,3,77,43};
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int adds_list[6]; //= {841,627,1555,241,7777,65391};
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int adds_list[6]; //= {841,627,1555,241,7777,65391};
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int m_par_filter_size;
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int m_par_filter_size;
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int m_par_filter_size_bits;
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int m_par_filter_size_bits;
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int m_count_bits;
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int m_count;
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bool isParallel;
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bool isParallel;
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};
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};
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@ -71,9 +71,6 @@ class MultiGrainBloomFilter : public AbstractBloomFilter
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std::vector<int> m_page_filter;
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std::vector<int> m_page_filter;
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int m_page_filter_size;
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int m_page_filter_size;
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int m_page_filter_size_bits;
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int m_page_filter_size_bits;
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int m_count_bits;
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int m_count;
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};
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};
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#endif // __MEM_RUBY_FILTERS_MULTIGRAINBLOOMFILTER_HH__
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#endif // __MEM_RUBY_FILTERS_MULTIGRAINBLOOMFILTER_HH__
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@ -73,9 +73,6 @@ class NonCountingBloomFilter : public AbstractBloomFilter
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int m_filter_size;
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int m_filter_size;
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int m_offset;
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int m_offset;
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int m_filter_size_bits;
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int m_filter_size_bits;
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int m_count_bits;
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int m_count;
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};
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};
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#endif // __MEM_RUBY_FILTERS_NONCOUNTINGBLOOMFILTER_HH__
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#endif // __MEM_RUBY_FILTERS_NONCOUNTINGBLOOMFILTER_HH__
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@ -75,7 +75,7 @@ class flitBuffer_d
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private:
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private:
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std::vector<flit_d *> m_buffer;
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std::vector<flit_d *> m_buffer;
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int size, max_size;
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int max_size;
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};
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};
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inline std::ostream&
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inline std::ostream&
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@ -58,7 +58,7 @@ class flitBuffer
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private:
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private:
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std::vector<flit *> m_buffer;
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std::vector<flit *> m_buffer;
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int size, max_size;
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int max_size;
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};
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};
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inline std::ostream&
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inline std::ostream&
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@ -73,7 +73,6 @@ class DMASequencer : public RubyPort
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bool m_is_busy;
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bool m_is_busy;
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uint64_t m_data_block_mask;
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uint64_t m_data_block_mask;
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DMARequest active_request;
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DMARequest active_request;
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int num_active_requests;
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};
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};
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#endif // __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__
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#endif // __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__
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@ -119,8 +119,7 @@ RubyPort::getSlavePort(const std::string &if_name, PortID idx)
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RubyPort::PioPort::PioPort(const std::string &_name,
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RubyPort::PioPort::PioPort(const std::string &_name,
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RubyPort *_port)
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RubyPort *_port)
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: QueuedMasterPort(_name, _port, queue), queue(*_port, *this),
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: QueuedMasterPort(_name, _port, queue), queue(*_port, *this)
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ruby_port(_port)
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{
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{
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DPRINTF(RubyPort, "creating master port on ruby sequencer %s\n", _name);
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DPRINTF(RubyPort, "creating master port on ruby sequencer %s\n", _name);
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}
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}
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@ -99,8 +99,6 @@ class RubyPort : public MemObject
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MasterPacketQueue queue;
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MasterPacketQueue queue;
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RubyPort *ruby_port;
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public:
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public:
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PioPort(const std::string &_name, RubyPort *_port);
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PioPort(const std::string &_name, RubyPort *_port);
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Reference in a new issue