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extra : convert_revision : 888b6e3bcd432a9318d4b8741a8b274c6f37f1a8
This commit is contained in:
Gabe Black 2007-08-26 20:27:53 -07:00
parent e7e2d5ce90
commit a51e2fd8bd
126 changed files with 4676 additions and 3749 deletions
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82
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=DerivO3CPU type=DerivO3CPU
children=dcache fuPool icache l2cache toL2Bus workload children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
BTBEntries=4096 BTBEntries=4096
BTBTagSize=16 BTBTagSize=16
LFSTSize=1024 LFSTSize=1024
@ -21,6 +21,7 @@ SQEntries=32
SSITSize=1024 SSITSize=1024
activity=0 activity=0
backComSize=5 backComSize=5
cachePorts=200
choiceCtrBits=2 choiceCtrBits=2
choicePredictorSize=8192 choicePredictorSize=8192
clock=500 clock=500
@ -35,6 +36,7 @@ decodeToRenameDelay=1
decodeWidth=8 decodeWidth=8
defer_registration=false defer_registration=false
dispatchWidth=8 dispatchWidth=8
dtb=system.cpu.dtb
fetchToDecodeDelay=1 fetchToDecodeDelay=1
fetchTrapLatency=1 fetchTrapLatency=1
fetchWidth=8 fetchWidth=8
@ -52,6 +54,7 @@ iewToRenameDelay=1
instShiftAmt=2 instShiftAmt=2
issueToExecuteDelay=1 issueToExecuteDelay=1
issueWidth=8 issueWidth=8
itb=system.cpu.itb
localCtrBits=2 localCtrBits=2
localHistoryBits=11 localHistoryBits=11
localHistoryTableSize=2048 localHistoryTableSize=2048
@ -74,8 +77,18 @@ renameToFetchDelay=1
renameToIEWDelay=2 renameToIEWDelay=2
renameToROBDelay=1 renameToROBDelay=1
renameWidth=8 renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8 squashWidth=8
system=system system=system
tracer=system.cpu.tracer
trapLatency=13 trapLatency=13
wbDepth=1 wbDepth=1
wbWidth=8 wbWidth=8
@ -85,21 +98,21 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache] [system.cpu.dcache]
type=BaseCache type=BaseCache
adaptive_compression=false addr_range=0:18446744073709551615
assoc=2 assoc=2
block_size=64 block_size=64
compressed_bus=false cpu_side_filter_ranges=
compression_latency=0
hash_delay=1 hash_delay=1
latency=1000 latency=1000
lifo=false lifo=false
max_miss_count=0 max_miss_count=0
mem_side_filter_ranges=
mshrs=10 mshrs=10
prefetch_access=false prefetch_access=false
prefetch_cache_check_push=true prefetch_cache_check_push=true
prefetch_data_accesses_only=false prefetch_data_accesses_only=false
prefetch_degree=1 prefetch_degree=1
prefetch_latency=10 prefetch_latency=10000
prefetch_miss=false prefetch_miss=false
prefetch_past_page=false prefetch_past_page=false
prefetch_policy=none prefetch_policy=none
@ -107,12 +120,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true prefetch_use_cpu_id=true
prefetcher_size=100 prefetcher_size=100
prioritizeRequests=false prioritizeRequests=false
protocol=Null
repl=Null repl=Null
size=262144 size=262144
split=false split=false
split_size=0 split_size=0
store_compressed=false
subblock_size=0 subblock_size=0
tgts_per_mshr=20 tgts_per_mshr=20
trace_addr=0 trace_addr=0
@ -121,6 +132,10 @@ write_buffers=8
cpu_side=system.cpu.dcache_port cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1] mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=AlphaDTB
size=64
[system.cpu.fuPool] [system.cpu.fuPool]
type=FUPool type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
@ -128,11 +143,11 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL
[system.cpu.fuPool.FUList0] [system.cpu.fuPool.FUList0]
type=FUDesc type=FUDesc
children=opList0 children=opList
count=6 count=6
opList=system.cpu.fuPool.FUList0.opList0 opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList0] [system.cpu.fuPool.FUList0.opList]
type=OpDesc type=OpDesc
issueLat=1 issueLat=1
opClass=IntAlu opClass=IntAlu
@ -206,11 +221,11 @@ opLat=24
[system.cpu.fuPool.FUList4] [system.cpu.fuPool.FUList4]
type=FUDesc type=FUDesc
children=opList0 children=opList
count=0 count=0
opList=system.cpu.fuPool.FUList4.opList0 opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList0] [system.cpu.fuPool.FUList4.opList]
type=OpDesc type=OpDesc
issueLat=1 issueLat=1
opClass=MemRead opClass=MemRead
@ -218,11 +233,11 @@ opLat=1
[system.cpu.fuPool.FUList5] [system.cpu.fuPool.FUList5]
type=FUDesc type=FUDesc
children=opList0 children=opList
count=0 count=0
opList=system.cpu.fuPool.FUList5.opList0 opList=system.cpu.fuPool.FUList5.opList
[system.cpu.fuPool.FUList5.opList0] [system.cpu.fuPool.FUList5.opList]
type=OpDesc type=OpDesc
issueLat=1 issueLat=1
opClass=MemWrite opClass=MemWrite
@ -248,11 +263,11 @@ opLat=1
[system.cpu.fuPool.FUList7] [system.cpu.fuPool.FUList7]
type=FUDesc type=FUDesc
children=opList0 children=opList
count=1 count=1
opList=system.cpu.fuPool.FUList7.opList0 opList=system.cpu.fuPool.FUList7.opList
[system.cpu.fuPool.FUList7.opList0] [system.cpu.fuPool.FUList7.opList]
type=OpDesc type=OpDesc
issueLat=3 issueLat=3
opClass=IprAccess opClass=IprAccess
@ -260,21 +275,21 @@ opLat=3
[system.cpu.icache] [system.cpu.icache]
type=BaseCache type=BaseCache
adaptive_compression=false addr_range=0:18446744073709551615
assoc=2 assoc=2
block_size=64 block_size=64
compressed_bus=false cpu_side_filter_ranges=
compression_latency=0
hash_delay=1 hash_delay=1
latency=1000 latency=1000
lifo=false lifo=false
max_miss_count=0 max_miss_count=0
mem_side_filter_ranges=
mshrs=10 mshrs=10
prefetch_access=false prefetch_access=false
prefetch_cache_check_push=true prefetch_cache_check_push=true
prefetch_data_accesses_only=false prefetch_data_accesses_only=false
prefetch_degree=1 prefetch_degree=1
prefetch_latency=10 prefetch_latency=10000
prefetch_miss=false prefetch_miss=false
prefetch_past_page=false prefetch_past_page=false
prefetch_policy=none prefetch_policy=none
@ -282,12 +297,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true prefetch_use_cpu_id=true
prefetcher_size=100 prefetcher_size=100
prioritizeRequests=false prioritizeRequests=false
protocol=Null
repl=Null repl=Null
size=131072 size=131072
split=false split=false
split_size=0 split_size=0
store_compressed=false
subblock_size=0 subblock_size=0
tgts_per_mshr=20 tgts_per_mshr=20
trace_addr=0 trace_addr=0
@ -296,23 +309,27 @@ write_buffers=8
cpu_side=system.cpu.icache_port cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0] mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=AlphaITB
size=48
[system.cpu.l2cache] [system.cpu.l2cache]
type=BaseCache type=BaseCache
adaptive_compression=false addr_range=0:18446744073709551615
assoc=2 assoc=2
block_size=64 block_size=64
compressed_bus=false cpu_side_filter_ranges=
compression_latency=0
hash_delay=1 hash_delay=1
latency=1000 latency=1000
lifo=false lifo=false
max_miss_count=0 max_miss_count=0
mem_side_filter_ranges=
mshrs=10 mshrs=10
prefetch_access=false prefetch_access=false
prefetch_cache_check_push=true prefetch_cache_check_push=true
prefetch_data_accesses_only=false prefetch_data_accesses_only=false
prefetch_degree=1 prefetch_degree=1
prefetch_latency=10 prefetch_latency=10000
prefetch_miss=false prefetch_miss=false
prefetch_past_page=false prefetch_past_page=false
prefetch_policy=none prefetch_policy=none
@ -320,12 +337,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true prefetch_use_cpu_id=true
prefetcher_size=100 prefetcher_size=100
prioritizeRequests=false prioritizeRequests=false
protocol=Null
repl=Null repl=Null
size=2097152 size=2097152
split=false split=false
split_size=0 split_size=0
store_compressed=false
subblock_size=0 subblock_size=0
tgts_per_mshr=5 tgts_per_mshr=5
trace_addr=0 trace_addr=0
@ -343,6 +358,9 @@ responder_set=false
width=64 width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload] [system.cpu.workload]
type=LiveProcess type=LiveProcess
cmd=gzip input.log 1 cmd=gzip input.log 1
@ -366,7 +384,7 @@ bus_id=0
clock=1000 clock=1000
responder_set=false responder_set=false
width=64 width=64
port=system.physmem.port system.cpu.l2cache.mem_side port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem] [system.physmem]
type=PhysicalMemory type=PhysicalMemory

589
tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt
View file

@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits 65796417 # Number of BTB hits global.BPredUnit.BTBHits 65676436 # Number of BTB hits
global.BPredUnit.BTBLookups 73152793 # Number of BTB lookups global.BPredUnit.BTBLookups 73156986 # Number of BTB lookups
global.BPredUnit.RASInCorrect 162 # Number of incorrect RAS predictions. global.BPredUnit.RASInCorrect 166 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 4224786 # Number of conditional branches incorrect global.BPredUnit.condIncorrect 4207318 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 70143727 # Number of conditional branches predicted global.BPredUnit.condPredicted 70088985 # Number of conditional branches predicted
global.BPredUnit.lookups 75959317 # Number of BP lookups global.BPredUnit.lookups 76017379 # Number of BP lookups
global.BPredUnit.usedRAS 1707904 # Number of times the RAS was used to get a target. global.BPredUnit.usedRAS 1692882 # Number of times the RAS was used to get a target.
host_inst_rate 95235 # Simulator instruction rate (inst/s) host_inst_rate 211348 # Simulator instruction rate (inst/s)
host_mem_usage 154544 # Number of bytes of host memory used host_mem_usage 182448 # Number of bytes of host memory used
host_seconds 5938.47 # Real time elapsed on the host host_seconds 2675.93 # Real time elapsed on the host
host_tick_rate 31305923 # Simulator tick rate (ticks/s) host_tick_rate 60738573 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 11533351 # Number of conflicting loads. memdepunit.memDep.conflictingLoads 16721732 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 9283325 # Number of conflicting stores. memdepunit.memDep.conflictingStores 11866335 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 125815870 # Number of loads inserted to the mem dependence unit. memdepunit.memDep.insertedLoads 126743752 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 42503953 # Number of stores inserted to the mem dependence unit. memdepunit.memDep.insertedStores 43041597 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 565552443 # Number of instructions simulated sim_insts 565552443 # Number of instructions simulated
sim_seconds 0.185909 # Number of seconds simulated sim_seconds 0.162532 # Number of seconds simulated
sim_ticks 185909249000 # Number of ticks simulated sim_ticks 162531946000 # Number of ticks simulated
system.cpu.commit.COM:branches 62547159 # Number of branches committed system.cpu.commit.COM:branches 62547159 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 21750592 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_lim_events 20242536 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 363164843 system.cpu.commit.COM:committed_per_cycle.samples 315316083
system.cpu.commit.COM:committed_per_cycle.min_value 0 system.cpu.commit.COM:committed_per_cycle.min_value 0
0 150226418 4136.59% 0 101801168 3228.54%
1 99566964 2741.65% 1 100686280 3193.19%
2 34056070 937.76% 2 36605446 1160.91%
3 10333475 284.54% 3 9846862 312.29%
4 20301573 559.02% 4 9756830 309.43%
5 15829471 435.88% 5 22230548 705.02%
6 8882909 244.60% 6 12726034 403.60%
7 2217371 61.06% 7 1420379 45.05%
8 21750592 598.92% 8 20242536 641.98%
system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist system.cpu.commit.COM:committed_per_cycle.end_dist
@ -43,70 +43,72 @@ system.cpu.commit.COM:loads 115049510 # Nu
system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 154862033 # Number of memory references committed system.cpu.commit.COM:refs 154862033 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 4224164 # The number of times a branch was mispredicted system.cpu.commit.branchMispredicts 4206693 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 52370845 # The number of squashed insts skipped by commit system.cpu.commit.commitSquashedInsts 60367294 # The number of squashed insts skipped by commit
system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedInsts 565552443 # Number of Instructions Simulated
system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
system.cpu.cpi 0.657443 # CPI: Cycles Per Instruction system.cpu.cpi 0.574772 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.657443 # CPI: Total CPI of All Threads system.cpu.cpi_total 0.574772 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 115591547 # number of ReadReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 3246.088003 # average ReadReq miss latency system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2434.144734 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_accesses 111194484 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_hits 115095381 # number of ReadReq hits system.cpu.dcache.ReadReq_avg_miss_latency 32074.811872 # average ReadReq miss latency
system.cpu.dcache.ReadReq_miss_latency 1610598500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5025.209404 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_miss_rate 0.004292 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_hits 110978275 # number of ReadReq hits
system.cpu.dcache.ReadReq_misses 496166 # number of ReadReq misses system.cpu.dcache.ReadReq_miss_latency 6934863000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_mshr_hits 273177 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_miss_rate 0.001944 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_latency 542787500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_misses 216209 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001929 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_hits 901354 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 222989 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency 1086495500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.ReadReq_mshr_miss_rate 0.001944 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_avg_miss_latency 3474.707454 # average WriteReq miss latency system.cpu.dcache.ReadReq_mshr_misses 216209 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2824.359825 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_accesses 37821041 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_hits 38691611 # number of WriteReq hits system.cpu.dcache.WriteReq_avg_miss_latency 31690.076841 # average WriteReq miss latency
system.cpu.dcache.WriteReq_miss_latency 2639770000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5379.514968 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_miss_rate 0.019257 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_hits 37483812 # number of WriteReq hits
system.cpu.dcache.WriteReq_misses 759710 # number of WriteReq misses system.cpu.dcache.WriteReq_miss_latency 10686812923 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_mshr_hits 502007 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_miss_rate 0.008916 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_latency 727846000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_misses 337229 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006532 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_hits 1630280 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_misses 257703 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_miss_latency 1814128453 # number of WriteReq MSHR miss cycles
system.cpu.dcache.avg_blocked_cycles_no_mshrs 427.272727 # average number of cycles each access was blocked system.cpu.dcache.WriteReq_mshr_miss_rate 0.008916 # mshr miss rate for WriteReq accesses
system.cpu.dcache.avg_blocked_cycles_no_targets 0 # average number of cycles each access was blocked system.cpu.dcache.WriteReq_mshr_misses 337229 # number of WriteReq MSHR misses
system.cpu.dcache.avg_refs 319.928337 # Average number of references to valid blocks. system.cpu.dcache.avg_blocked_cycles_no_mshrs 500 # average number of cycles each access was blocked
system.cpu.dcache.blocked_no_mshrs 1210 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets 1750 # average number of cycles each access was blocked
system.cpu.dcache.blocked_no_targets 2 # number of cycles access was blocked system.cpu.dcache.avg_refs 314.126008 # Average number of references to valid blocks.
system.cpu.dcache.blocked_cycles_no_mshrs 517000 # number of cycles access was blocked system.cpu.dcache.blocked_no_mshrs 1 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 4 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 7000 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 155042868 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses 149015525 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 3384.385481 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency 31840.379452 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 2643.342307 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 5241.100093 # average overall mshr miss latency
system.cpu.dcache.demand_hits 153786992 # number of demand (read+write) hits system.cpu.dcache.demand_hits 148462087 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 4250368500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency 17621675923 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.008100 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate 0.003714 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1255876 # number of demand (read+write) misses system.cpu.dcache.demand_misses 553438 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 775184 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits 2531634 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 1270633500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency 2900623953 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.003100 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate 0.003714 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 480692 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses 553438 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 155042868 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses 149015525 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 3384.385481 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency 31840.379452 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 2643.342307 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 5241.100093 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 153786992 # number of overall hits system.cpu.dcache.overall_hits 148462087 # number of overall hits
system.cpu.dcache.overall_miss_latency 4250368500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency 17621675923 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.008100 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate 0.003714 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1255876 # number of overall misses system.cpu.dcache.overall_misses 553438 # number of overall misses
system.cpu.dcache.overall_mshr_hits 775184 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits 2531634 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 1270633500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency 2900623953 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.003100 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate 0.003714 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 480692 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses 553438 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -118,92 +120,104 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 476596 # number of replacements system.cpu.dcache.replacements 468780 # number of replacements
system.cpu.dcache.sampled_refs 480692 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 472876 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4095.610639 # Cycle average of tags in use system.cpu.dcache.tagsinuse 4095.312024 # Cycle average of tags in use
system.cpu.dcache.total_refs 153786992 # Total number of references to valid blocks. system.cpu.dcache.total_refs 148542650 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 28323000 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 41060000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 338024 # number of writebacks system.cpu.dcache.writebacks 334093 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 44010110 # Number of cycles decode is blocked system.cpu.decode.DECODE:BlockedCycles 42961711 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 636 # Number of times decode detected a branch misprediction system.cpu.decode.DECODE:BranchMispred 654 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 3910489 # Number of times decode resolved a branch system.cpu.decode.DECODE:BranchResolved 4159669 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 686828869 # Number of instructions handled by decode system.cpu.decode.DECODE:DecodedInsts 688665550 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 203536444 # Number of cycles decode is idle system.cpu.decode.DECODE:IdleCycles 143212697 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 106139742 # Number of cycles decode is running system.cpu.decode.DECODE:RunCycles 123677184 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 8653682 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashCycles 9747531 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 1958 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:SquashedInsts 1998 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 9478548 # Number of cycles decode is unblocking system.cpu.decode.DECODE:UnblockCycles 5464492 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 75959317 # Number of branches that fetch encountered system.cpu.dtb.accesses 162979892 # DTB accesses
system.cpu.fetch.CacheLines 65390933 # Number of cache lines fetched system.cpu.dtb.acv 0 # DTB access violations
system.cpu.fetch.Cycles 182129217 # Number of cycles fetch has run and was not squashing or blocked system.cpu.dtb.hits 162933690 # DTB hits
system.cpu.fetch.IcacheSquashes 2901518 # Number of outstanding Icache misses that were squashed system.cpu.dtb.misses 46202 # DTB misses
system.cpu.fetch.Insts 693889852 # Number of instructions fetch has processed system.cpu.dtb.read_accesses 122208199 # DTB read accesses
system.cpu.fetch.SquashCycles 4411999 # Number of cycles fetch has spent squashing system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.fetch.branchRate 0.204291 # Number of branch fetches per cycle system.cpu.dtb.read_hits 122186821 # DTB read hits
system.cpu.fetch.icacheStallCycles 65390933 # Number of cycles fetch is stalled on an Icache miss system.cpu.dtb.read_misses 21378 # DTB read misses
system.cpu.fetch.predictedBranches 67504321 # Number of branches that fetch has predicted taken system.cpu.dtb.write_accesses 40771693 # DTB write accesses
system.cpu.fetch.rate 1.866206 # Number of inst fetches per cycle system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 40746869 # DTB write hits
system.cpu.dtb.write_misses 24824 # DTB write misses
system.cpu.fetch.Branches 76017379 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 65923007 # Number of cache lines fetched
system.cpu.fetch.Cycles 196871509 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 1349795 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 697858274 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 4233156 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.233854 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 65923007 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 67369318 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.146836 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 371818526 system.cpu.fetch.rateDist.samples 325063615
system.cpu.fetch.rateDist.min_value 0 system.cpu.fetch.rateDist.min_value 0
0 255080243 6860.34% 0 194115151 5971.61%
1 9944321 267.45% 1 10367448 318.94%
2 12043396 323.91% 2 15852914 487.69%
3 10077209 271.02% 3 14602370 449.22%
4 7005486 188.41% 4 12321515 379.05%
5 3160802 85.01% 5 14794025 455.11%
6 3551742 95.52% 6 6009823 184.88%
7 3151910 84.77% 7 3340187 102.75%
8 67803417 1823.56% 8 53660182 1650.76%
system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 65390933 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses 65922920 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 5347.983454 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 7890.798226 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4573.991031 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 5470.620843 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 65389966 # number of ReadReq hits system.cpu.icache.ReadReq_hits 65922018 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 5171500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency 7117500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000015 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 967 # number of ReadReq misses system.cpu.icache.ReadReq_misses 902 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 75 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits 87 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 4080000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency 4934500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 892 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 73307.136771 # Average number of references to valid blocks. system.cpu.icache.avg_refs 73084.277162 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 65390933 # number of demand (read+write) accesses system.cpu.icache.demand_accesses 65922920 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 5347.983454 # average overall miss latency system.cpu.icache.demand_avg_miss_latency 7890.798226 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 4573.991031 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 5470.620843 # average overall mshr miss latency
system.cpu.icache.demand_hits 65389966 # number of demand (read+write) hits system.cpu.icache.demand_hits 65922018 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 5171500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency 7117500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000015 # miss rate for demand accesses system.cpu.icache.demand_miss_rate 0.000014 # miss rate for demand accesses
system.cpu.icache.demand_misses 967 # number of demand (read+write) misses system.cpu.icache.demand_misses 902 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 75 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits 87 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 4080000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency 4934500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 892 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses 902 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 65390933 # number of overall (read+write) accesses system.cpu.icache.overall_accesses 65922920 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 5347.983454 # average overall miss latency system.cpu.icache.overall_avg_miss_latency 7890.798226 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 4573.991031 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 5470.620843 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 65389966 # number of overall hits system.cpu.icache.overall_hits 65922018 # number of overall hits
system.cpu.icache.overall_miss_latency 5171500 # number of overall miss cycles system.cpu.icache.overall_miss_latency 7117500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000015 # miss rate for overall accesses system.cpu.icache.overall_miss_rate 0.000014 # miss rate for overall accesses
system.cpu.icache.overall_misses 967 # number of overall misses system.cpu.icache.overall_misses 902 # number of overall misses
system.cpu.icache.overall_mshr_hits 75 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits 87 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 4080000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency 4934500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 892 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses 902 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -215,81 +229,81 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 33 # number of replacements system.cpu.icache.replacements 32 # number of replacements
system.cpu.icache.sampled_refs 892 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 902 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 761.711791 # Cycle average of tags in use system.cpu.icache.tagsinuse 770.534444 # Cycle average of tags in use
system.cpu.icache.total_refs 65389966 # Total number of references to valid blocks. system.cpu.icache.total_refs 65922018 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 2468 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.idleCycles 190397 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 67136036 # Number of branches executed system.cpu.iew.EXEC:branches 67319692 # Number of branches executed
system.cpu.iew.EXEC:nop 41949449 # number of nop insts executed system.cpu.iew.EXEC:nop 42991424 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.608660 # Inst execution rate system.cpu.iew.EXEC:rate 1.842347 # Inst execution rate
system.cpu.iew.EXEC:refs 164353457 # number of memory reference insts executed system.cpu.iew.EXEC:refs 163918711 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 41112797 # Number of stores executed system.cpu.iew.EXEC:stores 41167815 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 478961290 # num instructions consuming a value system.cpu.iew.WB:consumers 490977460 # num instructions consuming a value
system.cpu.iew.WB:count 594114153 # cumulative count of insts written-back system.cpu.iew.WB:count 595732364 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.812310 # average fanout of values written-back system.cpu.iew.WB:fanout 0.805927 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 389064913 # num instructions producing a value system.cpu.iew.WB:producers 395691865 # num instructions producing a value
system.cpu.iew.WB:rate 1.597861 # insts written-back per cycle system.cpu.iew.WB:rate 1.832664 # insts written-back per cycle
system.cpu.iew.WB:sent 594699658 # cumulative count of insts sent to commit system.cpu.iew.WB:sent 596897738 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 4485637 # Number of branch mispredicts detected at execute system.cpu.iew.branchMispredicts 4671822 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 10981 # Number of cycles IEW is blocking system.cpu.iew.iewBlockCycles 211982 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 125815870 # Number of dispatched load instructions system.cpu.iew.iewDispLoadInsts 126743752 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 6586227 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispSquashedInsts 3268805 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 42503953 # Number of dispatched store instructions system.cpu.iew.iewDispStoreInsts 43041597 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 654225210 # Number of instructions dispatched to IQ system.cpu.iew.iewDispatchedInsts 662373944 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 123240660 # Number of load instructions executed system.cpu.iew.iewExecLoadInsts 122750896 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 4346710 # Number of squashed instructions skipped in execute system.cpu.iew.iewExecSquashedInsts 6416858 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 598129643 # Number of executed instructions system.cpu.iew.iewExecutedInsts 598879902 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 518 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIQFullEvents 1310 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 8653682 # Number of cycles IEW is squashing system.cpu.iew.iewSquashCycles 9747531 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 4417 # Number of cycles IEW is unblocking system.cpu.iew.iewUnblockCycles 36871 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 2615 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.cacheBlocked 104 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 7105932 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.forwLoads 10085062 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 1847 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.ignoredResponses 15402 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 296430 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.memOrderViolation 28955 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 5860 # Number of loads that were rescheduled system.cpu.iew.lsq.thread.0.rescheduledLoads 5897 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 10766360 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedLoads 11694242 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 2691430 # Number of stores squashed system.cpu.iew.lsq.thread.0.squashedStores 3229074 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 296430 # Number of memory order violations system.cpu.iew.memOrderViolationEvents 28955 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 519296 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 540642 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 3966341 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedTakenIncorrect 4131180 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.521044 # IPC: Instructions Per Cycle system.cpu.ipc 1.739821 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.521044 # IPC: Total IPC of All Threads system.cpu.ipc_total 1.739821 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 602476353 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0 605296760 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist system.cpu.iq.ISSUE:FU_type_0.start_dist
(null) 0 0.00% # Type of FU issued No_OpClass 0 0.00% # Type of FU issued
IntAlu 435905994 72.35% # Type of FU issued IntAlu 438526639 72.45% # Type of FU issued
IntMult 6492 0.00% # Type of FU issued IntMult 6526 0.00% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued
FloatAdd 27 0.00% # Type of FU issued FloatAdd 29 0.00% # Type of FU issued
FloatCmp 5 0.00% # Type of FU issued FloatCmp 5 0.00% # Type of FU issued
FloatCvt 5 0.00% # Type of FU issued FloatCvt 5 0.00% # Type of FU issued
FloatMult 4 0.00% # Type of FU issued FloatMult 4 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued
MemRead 124769613 20.71% # Type of FU issued MemRead 124781721 20.61% # Type of FU issued
MemWrite 41794213 6.94% # Type of FU issued MemWrite 41981831 6.94% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 3485464 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_cnt 6717566 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.005785 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_busy_rate 0.011098 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist system.cpu.iq.ISSUE:fu_full.start_dist
(null) 0 0.00% # attempts to use FU when none available No_OpClass 0 0.00% # attempts to use FU when none available
IntAlu 2980889 85.52% # attempts to use FU when none available IntAlu 5391256 80.26% # attempts to use FU when none available
IntMult 104 0.00% # attempts to use FU when none available IntMult 67 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available
FloatCmp 0 0.00% # attempts to use FU when none available FloatCmp 0 0.00% # attempts to use FU when none available
@ -297,80 +311,105 @@ system.cpu.iq.ISSUE:fu_full.start_dist
FloatMult 0 0.00% # attempts to use FU when none available FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available
MemRead 331227 9.50% # attempts to use FU when none available MemRead 838838 12.49% # attempts to use FU when none available
MemWrite 173244 4.97% # attempts to use FU when none available MemWrite 487405 7.26% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples 371818526 system.cpu.iq.ISSUE:issued_per_cycle.samples 325063615
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 125625601 3378.68% 0 85796359 2639.37%
1 89616652 2410.23% 1 67542387 2077.82%
2 55904072 1503.53% 2 80092036 2463.89%
3 46310572 1245.52% 3 31532999 970.06%
4 27240019 732.62% 4 32045835 985.83%
5 12675210 340.90% 5 15660373 481.76%
6 11517465 309.76% 6 10783606 331.74%
7 2752555 74.03% 7 1095697 33.71%
8 176380 4.74% 8 514323 15.82%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 1.620351 # Inst issue rate system.cpu.iq.ISSUE:rate 1.862087 # Inst issue rate
system.cpu.iq.iqInstsAdded 612275739 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsAdded 619382498 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 602476353 # Number of instructions issued system.cpu.iq.iqInstsIssued 605296760 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 42659982 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsExamined 52509739 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 2623 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsIssued 11652 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 5 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedNonSpecRemoved 5 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 21979774 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedOperandsExamined 28327252 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadReq_accesses 481584 # number of ReadReq accesses(hits+misses) system.cpu.itb.accesses 65923045 # ITB accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 6174.721472 # average ReadReq miss latency system.cpu.itb.acv 0 # ITB acv
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2416.099471 # average ReadReq mshr miss latency system.cpu.itb.hits 65923007 # ITB hits
system.cpu.l2cache.ReadReq_hits 455285 # number of ReadReq hits system.cpu.itb.misses 38 # ITB misses
system.cpu.l2cache.ReadReq_miss_latency 162389000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_accesses 256667 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_miss_rate 0.054609 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_avg_miss_latency 4174.217956 # average ReadExReq miss latency
system.cpu.l2cache.ReadReq_misses 26299 # number of ReadReq misses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2174.217956 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadReq_mshr_miss_latency 63541000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_miss_latency 1071384000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054609 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 26299 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_misses 256667 # number of ReadExReq misses
system.cpu.l2cache.Writeback_accesses 338024 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_mshr_miss_latency 558050000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.Writeback_hits 338024 # number of Writeback hits system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 256667 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 217111 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 4357.993028 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2357.993028 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 30930 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 811375500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.857538 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 186181 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 439013500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.857538 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 186181 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 80592 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4188.374777 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2188.374777 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 337549500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 80592 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 176365500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 80592 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 334093 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 334093 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 334093 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 30.164987 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 4.206809 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 481584 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses 473778 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 6174.721472 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency 4251.480192 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2416.099471 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 2251.480192 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 455285 # number of demand (read+write) hits system.cpu.l2cache.demand_hits 30930 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 162389000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency 1882759500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.054609 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate 0.934716 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 26299 # number of demand (read+write) misses system.cpu.l2cache.demand_misses 442848 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 63541000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 997063500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.054609 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate 0.934716 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 26299 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses 442848 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 819608 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses 473778 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 6174.721472 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency 4251.480192 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2416.099471 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 2251.480192 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 793309 # number of overall hits system.cpu.l2cache.overall_hits 30930 # number of overall hits
system.cpu.l2cache.overall_miss_latency 162389000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency 1882759500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.032087 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate 0.934716 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 26299 # number of overall misses system.cpu.l2cache.overall_misses 442848 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 63541000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency 997063500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.032087 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate 0.934716 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 26299 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses 442848 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -382,31 +421,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 931 # number of replacements system.cpu.l2cache.replacements 14218 # number of replacements
system.cpu.l2cache.sampled_refs 26299 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 15715 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 25071.267749 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 8150.643180 # Cycle average of tags in use
system.cpu.l2cache.total_refs 793309 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 66110 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 904 # number of writebacks system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.numCycles 371818526 # number of cpu cycles simulated system.cpu.numCycles 325063615 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 11517489 # Number of cycles rename is blocking system.cpu.rename.RENAME:BlockCycles 11040699 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 32462126 # Number of times rename has blocked due to IQ full system.cpu.rename.RENAME:IQFullEvents 31586100 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 206624315 # Number of cycles rename is idle system.cpu.rename.RENAME:IdleCycles 150557156 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 21712 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:LSQFullEvents 290380 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 889109667 # Number of register rename lookups that rename has made system.cpu.rename.RENAME:RenameLookups 895272473 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 674900294 # Number of instructions processed by rename system.cpu.rename.RENAME:RenamedInsts 679363424 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 515718683 # Number of destination operands rename has renamed system.cpu.rename.RENAME:RenamedOperands 518606333 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 111518348 # Number of cycles rename is running system.cpu.rename.RENAME:RunCycles 116560800 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 8653682 # Number of cycles rename is squashing system.cpu.rename.RENAME:SquashCycles 9747531 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 33504424 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UnblockCycles 37157112 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 51863794 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:UndoneMaps 54751444 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 268 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializeStallCycles 317 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 59569309 # count of insts added to the skid buffer system.cpu.rename.RENAME:skidInsts 72001269 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 24 # count of temporary serializing insts renamed system.cpu.rename.RENAME:tempSerializingInsts 25 # count of temporary serializing insts renamed
system.cpu.timesIdled 32 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 103 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

18
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -11,12 +11,14 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
children=workload children=dtb itb tracer workload
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false defer_registration=false
dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -25,11 +27,23 @@ phase=0
progress_interval=0 progress_interval=0
simulate_stalls=false simulate_stalls=false
system=system system=system
tracer=system.cpu.tracer
width=1 width=1
workload=system.cpu.workload workload=system.cpu.workload
dcache_port=system.membus.port[2] dcache_port=system.membus.port[2]
icache_port=system.membus.port[1] icache_port=system.membus.port[1]
[system.cpu.dtb]
type=AlphaDTB
size=64
[system.cpu.itb]
type=AlphaITB
size=48
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload] [system.cpu.workload]
type=LiveProcess type=LiveProcess
cmd=gzip input.log 1 cmd=gzip input.log 1
@ -53,7 +67,7 @@ bus_id=0
clock=1000 clock=1000
responder_set=false responder_set=false
width=64 width=64
port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem] [system.physmem]
type=PhysicalMemory type=PhysicalMemory

36
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt
View file

@ -1,18 +1,34 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 963880 # Simulator instruction rate (inst/s) host_inst_rate 2906348 # Simulator instruction rate (inst/s)
host_mem_usage 148548 # Number of bytes of host memory used host_mem_usage 174252 # Number of bytes of host memory used
host_seconds 624.41 # Real time elapsed on the host host_seconds 207.08 # Real time elapsed on the host
host_tick_rate 481939681 # Simulator tick rate (ticks/s) host_tick_rate 1453183573 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 601856965 # Number of instructions simulated sim_insts 601856964 # Number of instructions simulated
sim_seconds 0.300928 # Number of seconds simulated sim_seconds 0.300931 # Number of seconds simulated
sim_ticks 300928482000 # Number of ticks simulated sim_ticks 300930958000 # Number of ticks simulated
system.cpu.dtb.accesses 153970296 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.dtb.hits 153965363 # DTB hits
system.cpu.dtb.misses 4933 # DTB misses
system.cpu.dtb.read_accesses 114516673 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 114514042 # DTB read hits
system.cpu.dtb.read_misses 2631 # DTB read misses
system.cpu.dtb.write_accesses 39453623 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 39451321 # DTB write hits
system.cpu.dtb.write_misses 2302 # DTB write misses
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 601861917 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 601861897 # ITB hits
system.cpu.itb.misses 20 # ITB misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 601856965 # number of cpu cycles simulated system.cpu.numCycles 601861917 # number of cpu cycles simulated
system.cpu.num_insts 601856965 # Number of instructions executed system.cpu.num_insts 601856964 # Number of instructions executed
system.cpu.num_refs 154862034 # Number of memory references system.cpu.num_refs 154866966 # Number of memory references
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

12
tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
View file

@ -11,12 +11,14 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=TimingSimpleCPU type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus tracer workload children=dcache dtb icache itb l2cache toL2Bus tracer workload
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false defer_registration=false
dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -65,6 +67,10 @@ write_buffers=8
cpu_side=system.cpu.dcache_port cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1] mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=AlphaDTB
size=64
[system.cpu.icache] [system.cpu.icache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615
@ -101,6 +107,10 @@ write_buffers=8
cpu_side=system.cpu.icache_port cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0] mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=AlphaITB
size=48
[system.cpu.l2cache] [system.cpu.l2cache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615

60
tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 1799420 # Simulator instruction rate (inst/s) host_inst_rate 1730291 # Simulator instruction rate (inst/s)
host_mem_usage 199568 # Number of bytes of host memory used host_mem_usage 181616 # Number of bytes of host memory used
host_seconds 334.47 # Real time elapsed on the host host_seconds 347.84 # Real time elapsed on the host
host_tick_rate 2297009943 # Simulator tick rate (ticks/s) host_tick_rate 2208778962 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 601856965 # Number of instructions simulated sim_insts 601856964 # Number of instructions simulated
sim_seconds 0.768288 # Number of seconds simulated sim_seconds 0.768293 # Number of seconds simulated
sim_ticks 768287940000 # Number of ticks simulated sim_ticks 768292872000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 23626.361612 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency 23626.361612 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21626.361612 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21626.361612 # average ReadReq mshr miss latency
@ -76,14 +76,26 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 451299 # number of replacements system.cpu.dcache.replacements 451299 # number of replacements
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4094.970134 # Cycle average of tags in use system.cpu.dcache.tagsinuse 4094.968001 # Cycle average of tags in use
system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 342925000 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 343385000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 325723 # number of writebacks system.cpu.dcache.writebacks 325723 # number of writebacks
system.cpu.icache.ReadReq_accesses 601856966 # number of ReadReq accesses(hits+misses) system.cpu.dtb.accesses 153970296 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.dtb.hits 153965363 # DTB hits
system.cpu.dtb.misses 4933 # DTB misses
system.cpu.dtb.read_accesses 114516673 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 114514042 # DTB read hits
system.cpu.dtb.read_misses 2631 # DTB read misses
system.cpu.dtb.write_accesses 39453623 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 39451321 # DTB write hits
system.cpu.dtb.write_misses 2302 # DTB write misses
system.cpu.icache.ReadReq_accesses 601861898 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 601856171 # number of ReadReq hits system.cpu.icache.ReadReq_hits 601861103 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 19875000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency 19875000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses
@ -92,16 +104,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # ms
system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 757051.787421 # Average number of references to valid blocks. system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 601856966 # number of demand (read+write) accesses system.cpu.icache.demand_accesses 601861898 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 25000 # average overall miss latency system.cpu.icache.demand_avg_miss_latency 25000 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.icache.demand_hits 601856171 # number of demand (read+write) hits system.cpu.icache.demand_hits 601861103 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 19875000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency 19875000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
system.cpu.icache.demand_misses 795 # number of demand (read+write) misses system.cpu.icache.demand_misses 795 # number of demand (read+write) misses
@ -112,11 +124,11 @@ system.cpu.icache.demand_mshr_misses 795 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 601856966 # number of overall (read+write) accesses system.cpu.icache.overall_accesses 601861898 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 25000 # average overall miss latency system.cpu.icache.overall_avg_miss_latency 25000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 601856171 # number of overall hits system.cpu.icache.overall_hits 601861103 # number of overall hits
system.cpu.icache.overall_miss_latency 19875000 # number of overall miss cycles system.cpu.icache.overall_miss_latency 19875000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_misses 795 # number of overall misses system.cpu.icache.overall_misses 795 # number of overall misses
@ -138,11 +150,15 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 24 # number of replacements system.cpu.icache.replacements 24 # number of replacements
system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 673.685789 # Cycle average of tags in use system.cpu.icache.tagsinuse 673.685273 # Cycle average of tags in use
system.cpu.icache.total_refs 601856171 # Total number of references to valid blocks. system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 601861918 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 601861898 # ITB hits
system.cpu.itb.misses 20 # ITB misses
system.cpu.l2cache.ReadExReq_accesses 254163 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 254163 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
@ -224,14 +240,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 13394 # number of replacements system.cpu.l2cache.replacements 13394 # number of replacements
system.cpu.l2cache.sampled_refs 14881 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 14881 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 8423.446687 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 8423.428104 # Cycle average of tags in use
system.cpu.l2cache.total_refs 52084 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 52084 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 768287940000 # number of cpu cycles simulated system.cpu.numCycles 768292872000 # number of cpu cycles simulated
system.cpu.num_insts 601856965 # Number of instructions executed system.cpu.num_insts 601856964 # Number of instructions executed
system.cpu.num_refs 154862034 # Number of memory references system.cpu.num_refs 154866966 # Number of memory references
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

12
tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=DerivO3CPU type=DerivO3CPU
children=dcache fuPool icache l2cache toL2Bus tracer workload children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
BTBEntries=4096 BTBEntries=4096
BTBTagSize=16 BTBTagSize=16
LFSTSize=1024 LFSTSize=1024
@ -36,6 +36,7 @@ decodeToRenameDelay=1
decodeWidth=8 decodeWidth=8
defer_registration=false defer_registration=false
dispatchWidth=8 dispatchWidth=8
dtb=system.cpu.dtb
fetchToDecodeDelay=1 fetchToDecodeDelay=1
fetchTrapLatency=1 fetchTrapLatency=1
fetchWidth=8 fetchWidth=8
@ -53,6 +54,7 @@ iewToRenameDelay=1
instShiftAmt=2 instShiftAmt=2
issueToExecuteDelay=1 issueToExecuteDelay=1
issueWidth=8 issueWidth=8
itb=system.cpu.itb
localCtrBits=2 localCtrBits=2
localHistoryBits=11 localHistoryBits=11
localHistoryTableSize=2048 localHistoryTableSize=2048
@ -130,6 +132,10 @@ write_buffers=8
cpu_side=system.cpu.dcache_port cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1] mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=SparcDTB
size=64
[system.cpu.fuPool] [system.cpu.fuPool]
type=FUPool type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
@ -303,6 +309,10 @@ write_buffers=8
cpu_side=system.cpu.icache_port cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0] mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=SparcITB
size=64
[system.cpu.l2cache] [system.cpu.l2cache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615

576
tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt
View file

@ -1,122 +1,122 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits 183168209 # Number of BTB hits global.BPredUnit.BTBHits 183932235 # Number of BTB hits
global.BPredUnit.BTBLookups 207693172 # Number of BTB lookups global.BPredUnit.BTBLookups 208089812 # Number of BTB lookups
global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 83686538 # Number of conditional branches incorrect global.BPredUnit.condIncorrect 84447535 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 256168234 # Number of conditional branches predicted global.BPredUnit.condPredicted 256528366 # Number of conditional branches predicted
global.BPredUnit.lookups 256168234 # Number of BP lookups global.BPredUnit.lookups 256528366 # Number of BP lookups
global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
host_inst_rate 108517 # Simulator instruction rate (inst/s) host_inst_rate 100069 # Simulator instruction rate (inst/s)
host_mem_usage 202532 # Number of bytes of host memory used host_mem_usage 184776 # Number of bytes of host memory used
host_seconds 13726.13 # Real time elapsed on the host host_seconds 14046.38 # Real time elapsed on the host
host_tick_rate 80131991 # Simulator tick rate (ticks/s) host_tick_rate 78132380 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 457134527 # Number of conflicting loads. memdepunit.memDep.conflictingLoads 458856790 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 154100032 # Number of conflicting stores. memdepunit.memDep.conflictingStores 141228058 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 745124340 # Number of loads inserted to the mem dependence unit. memdepunit.memDep.insertedLoads 745627925 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 301027499 # Number of stores inserted to the mem dependence unit. memdepunit.memDep.insertedStores 302069201 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1489514761 # Number of instructions simulated sim_insts 1405610550 # Number of instructions simulated
sim_seconds 1.099902 # Number of seconds simulated sim_seconds 1.097477 # Number of seconds simulated
sim_ticks 1099901861500 # Number of ticks simulated sim_ticks 1097476890500 # Number of ticks simulated
system.cpu.commit.COM:branches 86246390 # Number of branches committed system.cpu.commit.COM:branches 86246390 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 9028629 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_lim_events 9005633 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 1956850179 system.cpu.commit.COM:committed_per_cycle.samples 1955398373
system.cpu.commit.COM:committed_per_cycle.min_value 0 system.cpu.commit.COM:committed_per_cycle.min_value 0
0 1082285235 5530.75% 0 1080294174 5524.68%
1 575067444 2938.74% 1 576226777 2946.85%
2 119112331 608.69% 2 118746551 607.28%
3 121687931 621.86% 3 121516054 621.44%
4 26918285 137.56% 4 26673737 136.41%
5 9398970 48.03% 5 9328411 47.71%
6 9197638 47.00% 6 9370387 47.92%
7 4153716 21.23% 7 4236649 21.67%
8 9028629 46.14% 8 9005633 46.06%
system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist system.cpu.commit.COM:committed_per_cycle.end_dist
system.cpu.commit.COM:count 1489514761 # Number of instructions committed system.cpu.commit.COM:count 1489528973 # Number of instructions committed
system.cpu.commit.COM:loads 402511688 # Number of loads committed system.cpu.commit.COM:loads 402516086 # Number of loads committed
system.cpu.commit.COM:membars 51356 # Number of memory barriers committed system.cpu.commit.COM:membars 51356 # Number of memory barriers committed
system.cpu.commit.COM:refs 569359656 # Number of memory references committed system.cpu.commit.COM:refs 569373868 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 83686538 # The number of times a branch was mispredicted system.cpu.commit.branchMispredicts 84447535 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1489514761 # The number of committed instructions system.cpu.commit.commitCommittedInsts 1489528973 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 2243499 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitNonSpecStalls 2243501 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 1386494932 # The number of squashed insts skipped by commit system.cpu.commit.commitSquashedInsts 1399558822 # The number of squashed insts skipped by commit
system.cpu.committedInsts 1489514761 # Number of Instructions Simulated system.cpu.committedInsts 1405610550 # Number of Instructions Simulated
system.cpu.committedInsts_total 1489514761 # Number of Instructions Simulated system.cpu.committedInsts_total 1405610550 # Number of Instructions Simulated
system.cpu.cpi 1.476859 # CPI: Cycles Per Instruction system.cpu.cpi 1.561566 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.476859 # CPI: Total CPI of All Threads system.cpu.cpi_total 1.561566 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 432423106 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses 422711123 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 21577.217813 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency 22402.386533 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4456.675710 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4523.374198 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 432175035 # number of ReadReq hits system.cpu.dcache.ReadReq_hits 422473917 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 5352682000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency 5313980500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000574 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate 0.000561 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 248071 # number of ReadReq misses system.cpu.dcache.ReadReq_misses 237206 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 707847 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits 708416 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 1105572000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency 1072971500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000574 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate 0.000561 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 248071 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses 237206 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency 7012.500000 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency 7025 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 5012.500000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency 5025 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits
system.cpu.dcache.SwapReq_miss_latency 280500 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_latency 281000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
system.cpu.dcache.SwapReq_mshr_miss_latency 200500 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency 201000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 165036365 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 165053813 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 45516.173877 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency 45668.908621 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5913.886312 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5916.368381 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 164687129 # number of WriteReq hits system.cpu.dcache.WriteReq_hits 164707389 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 15895886500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency 15820806000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.002116 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate 0.002099 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 349236 # number of WriteReq misses system.cpu.dcache.WriteReq_misses 346424 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 1810277 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits 1802643 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 2065342000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency 2049572000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.002116 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.002099 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 349236 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 346424 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 1139.085750 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 1145.843097 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 597459471 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses 587764936 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 35573.948573 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency 36212.645854 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 5308.683809 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 5350.210750 # average overall mshr miss latency
system.cpu.dcache.demand_hits 596862164 # number of demand (read+write) hits system.cpu.dcache.demand_hits 587181306 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 21248568500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency 21134786500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.001000 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate 0.000993 # miss rate for demand accesses
system.cpu.dcache.demand_misses 597307 # number of demand (read+write) misses system.cpu.dcache.demand_misses 583630 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 2518124 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits 2511059 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 3170914000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency 3122543500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.001000 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate 0.000993 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 597307 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses 583630 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 597459471 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses 587764936 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 35573.948573 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency 36212.645854 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 5308.683809 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 5350.210750 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 596862164 # number of overall hits system.cpu.dcache.overall_hits 587181306 # number of overall hits
system.cpu.dcache.overall_miss_latency 21248568500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency 21134786500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.001000 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate 0.000993 # miss rate for overall accesses
system.cpu.dcache.overall_misses 597307 # number of overall misses system.cpu.dcache.overall_misses 583630 # number of overall misses
system.cpu.dcache.overall_mshr_hits 2518124 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits 2511059 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 3170914000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency 3122543500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.001000 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate 0.000993 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 597307 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses 583630 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -128,89 +128,89 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 519953 # number of replacements system.cpu.dcache.replacements 508412 # number of replacements
system.cpu.dcache.sampled_refs 524049 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 512508 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4095.788106 # Cycle average of tags in use system.cpu.dcache.tagsinuse 4095.762102 # Cycle average of tags in use
system.cpu.dcache.total_refs 596936748 # Total number of references to valid blocks. system.cpu.dcache.total_refs 587253754 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 72857000 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 80526000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 346070 # number of writebacks system.cpu.dcache.writebacks 343259 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 407153301 # Number of cycles decode is blocked system.cpu.decode.DECODE:BlockedCycles 406688141 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 3453639261 # Number of instructions handled by decode system.cpu.decode.DECODE:DecodedInsts 3452580675 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 763587746 # Number of cycles decode is idle system.cpu.decode.DECODE:IdleCycles 760521931 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 783418811 # Number of cycles decode is running system.cpu.decode.DECODE:RunCycles 785512506 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 242953531 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashCycles 239555254 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 2690321 # Number of cycles decode is unblocking system.cpu.decode.DECODE:UnblockCycles 2675795 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 256168234 # Number of branches that fetch encountered system.cpu.fetch.Branches 256528366 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 355186488 # Number of cache lines fetched system.cpu.fetch.CacheLines 355016142 # Number of cache lines fetched
system.cpu.fetch.Cycles 1201174807 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.Cycles 1201036760 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 10202313 # Number of outstanding Icache misses that were squashed system.cpu.fetch.IcacheSquashes 10894008 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 3743631874 # Number of instructions fetch has processed system.cpu.fetch.Insts 3738352844 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 91259594 # Number of cycles fetch has spent squashing system.cpu.fetch.SquashCycles 89458561 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.116450 # Number of branch fetches per cycle system.cpu.fetch.branchRate 0.116872 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 355186488 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.icacheStallCycles 355016142 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 183168209 # Number of branches that fetch has predicted taken system.cpu.fetch.predictedBranches 183932235 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.701803 # Number of inst fetches per cycle system.cpu.fetch.rate 1.703158 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 2199803710 system.cpu.fetch.rateDist.samples 2194953627
system.cpu.fetch.rateDist.min_value 0 system.cpu.fetch.rateDist.min_value 0
0 1353815392 6154.26% 0 1348933053 6145.61%
1 255570605 1161.79% 1 256313247 1167.74%
2 82946121 377.06% 2 82698191 376.77%
3 38413739 174.62% 3 38326183 174.61%
4 83998079 381.84% 4 84519360 385.06%
5 40983172 186.30% 5 41105906 187.27%
6 33041033 150.20% 6 32923583 150.00%
7 20511116 93.24% 7 20556634 93.65%
8 290524453 1320.68% 8 289577470 1319.29%
system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 355186427 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses 355016079 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 7448.556625 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 7452.363368 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 5296.447076 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 5292.836041 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 355185076 # number of ReadReq hits system.cpu.icache.ReadReq_hits 355014725 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 10063000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency 10090500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 1351 # number of ReadReq misses system.cpu.icache.ReadReq_misses 1354 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 61 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits 63 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 7155500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency 7166500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 1351 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses 1354 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 262905.311621 # Average number of references to valid blocks. system.cpu.icache.avg_refs 262196.990399 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 355186427 # number of demand (read+write) accesses system.cpu.icache.demand_accesses 355016079 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 7448.556625 # average overall miss latency system.cpu.icache.demand_avg_miss_latency 7452.363368 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 5296.447076 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 5292.836041 # average overall mshr miss latency
system.cpu.icache.demand_hits 355185076 # number of demand (read+write) hits system.cpu.icache.demand_hits 355014725 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 10063000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency 10090500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_misses 1351 # number of demand (read+write) misses system.cpu.icache.demand_misses 1354 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 61 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits 63 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 7155500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency 7166500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 1351 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses 1354 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 355186427 # number of overall (read+write) accesses system.cpu.icache.overall_accesses 355016079 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 7448.556625 # average overall miss latency system.cpu.icache.overall_avg_miss_latency 7452.363368 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 5296.447076 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 5292.836041 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 355185076 # number of overall hits system.cpu.icache.overall_hits 355014725 # number of overall hits
system.cpu.icache.overall_miss_latency 10063000 # number of overall miss cycles system.cpu.icache.overall_miss_latency 10090500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_misses 1351 # number of overall misses system.cpu.icache.overall_misses 1354 # number of overall misses
system.cpu.icache.overall_mshr_hits 61 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits 63 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 7155500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency 7166500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 1351 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses 1354 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -222,183 +222,183 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 207 # number of replacements system.cpu.icache.replacements 208 # number of replacements
system.cpu.icache.sampled_refs 1351 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 1354 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1040.211796 # Cycle average of tags in use system.cpu.icache.tagsinuse 1042.348080 # Cycle average of tags in use
system.cpu.icache.total_refs 355185076 # Total number of references to valid blocks. system.cpu.icache.total_refs 355014725 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 8497 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.idleCycles 94965 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 126707080 # Number of branches executed system.cpu.iew.EXEC:branches 128778452 # Number of branches executed
system.cpu.iew.EXEC:nop 0 # number of nop insts executed system.cpu.iew.EXEC:nop 354384689 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.003361 # Inst execution rate system.cpu.iew.EXEC:rate 0.865881 # Inst execution rate
system.cpu.iew.EXEC:refs 760962527 # number of memory reference insts executed system.cpu.iew.EXEC:refs 753461994 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 208093186 # Number of stores executed system.cpu.iew.EXEC:stores 210026063 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 1493645383 # num instructions consuming a value system.cpu.iew.WB:consumers 1497813793 # num instructions consuming a value
system.cpu.iew.WB:count 2165444744 # cumulative count of insts written-back system.cpu.iew.WB:count 1867109874 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.962819 # average fanout of values written-back system.cpu.iew.WB:fanout 0.963032 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 1438109572 # num instructions producing a value system.cpu.iew.WB:producers 1442442170 # num instructions producing a value
system.cpu.iew.WB:rate 0.984381 # insts written-back per cycle system.cpu.iew.WB:rate 0.850638 # insts written-back per cycle
system.cpu.iew.WB:sent 2178310152 # cumulative count of insts sent to commit system.cpu.iew.WB:sent 1877161047 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 91514542 # Number of branch mispredicts detected at execute system.cpu.iew.branchMispredicts 91327681 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 458290 # Number of cycles IEW is blocking system.cpu.iew.iewBlockCycles 454443 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 745124340 # Number of dispatched load instructions system.cpu.iew.iewDispLoadInsts 745627925 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 21362312 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispNonSpecInsts 21367021 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 17090675 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispSquashedInsts 17089542 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 301027499 # Number of dispatched store instructions system.cpu.iew.iewDispStoreInsts 302069201 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 2876000922 # Number of instructions dispatched to IQ system.cpu.iew.iewDispatchedInsts 2889153048 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 552869341 # Number of load instructions executed system.cpu.iew.iewExecLoadInsts 543435931 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 140121943 # Number of squashed instructions skipped in execute system.cpu.iew.iewExecSquashedInsts 103575555 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 2207196457 # Number of executed instructions system.cpu.iew.iewExecutedInsts 1900567912 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 56098 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIQFullEvents 61243 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 8365 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 9772 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 242953531 # Number of cycles IEW is squashing system.cpu.iew.iewSquashCycles 239555254 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 87287 # Number of cycles IEW is unblocking system.cpu.iew.iewUnblockCycles 95884 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 119737756 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.forwLoads 119997179 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 85786 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.ignoredResponses 80650 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 10100571 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.memOrderViolation 5250080 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 31 # Number of loads that were rescheduled system.cpu.iew.lsq.thread.0.rescheduledLoads 6 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 342612652 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedLoads 343111839 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 134179531 # Number of stores squashed system.cpu.iew.lsq.thread.0.squashedStores 135211419 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 10100571 # Number of memory order violations system.cpu.iew.memOrderViolationEvents 5250080 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 1514083 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 1516982 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 90000459 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedTakenIncorrect 89810699 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.677113 # IPC: Instructions Per Cycle system.cpu.ipc 0.640383 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.677113 # IPC: Total IPC of All Threads system.cpu.ipc_total 0.640383 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 2347318400 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0 2004143467 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 351441317 14.97% # Type of FU issued No_OpClass 0 0.00% # Type of FU issued
IntAlu 1181231771 50.32% # Type of FU issued IntAlu 1186366605 59.20% # Type of FU issued
IntMult 0 0.00% # Type of FU issued IntMult 0 0.00% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued
FloatAdd 3000185 0.13% # Type of FU issued FloatAdd 3003253 0.15% # Type of FU issued
FloatCmp 0 0.00% # Type of FU issued FloatCmp 0 0.00% # Type of FU issued
FloatCvt 0 0.00% # Type of FU issued FloatCvt 0 0.00% # Type of FU issued
FloatMult 0 0.00% # Type of FU issued FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued
MemRead 586473179 24.98% # Type of FU issued MemRead 584611723 29.17% # Type of FU issued
MemWrite 225171948 9.59% # Type of FU issued MemWrite 230161886 11.48% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 3997880 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_cnt 6010355 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.001703 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_busy_rate 0.002999 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available No_OpClass 0 0.00% # attempts to use FU when none available
IntAlu 155579 3.89% # attempts to use FU when none available IntAlu 143340 2.38% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 244024 6.10% # attempts to use FU when none available FloatAdd 241345 4.02% # attempts to use FU when none available
FloatCmp 0 0.00% # attempts to use FU when none available FloatCmp 0 0.00% # attempts to use FU when none available
FloatCvt 0 0.00% # attempts to use FU when none available FloatCvt 0 0.00% # attempts to use FU when none available
FloatMult 0 0.00% # attempts to use FU when none available FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available
MemRead 3267233 81.72% # attempts to use FU when none available MemRead 5244225 87.25% # attempts to use FU when none available
MemWrite 331044 8.28% # attempts to use FU when none available MemWrite 381445 6.35% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples 2199803710 system.cpu.iq.ISSUE:issued_per_cycle.samples 2194953627
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 993478594 4516.21% 0 1076765226 4905.64%
1 570157916 2591.86% 1 582878371 2655.54%
2 321116547 1459.75% 2 298125643 1358.23%
3 178901320 813.26% 3 159003575 724.41%
4 92584833 420.88% 4 52530250 239.32%
5 34984610 159.04% 5 16707223 76.12%
6 7286511 33.12% 6 8404252 38.29%
7 1105050 5.02% 7 392238 1.79%
8 188329 0.86% 8 146849 0.67%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 1.067058 # Inst issue rate system.cpu.iq.ISSUE:rate 0.913069 # Inst issue rate
system.cpu.iq.iqInstsAdded 2854330173 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsAdded 2513084593 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 2347318400 # Number of instructions issued system.cpu.iq.iqInstsIssued 2004143467 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 21670749 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqNonSpecInstsAdded 21683766 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 1311892803 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsExamined 1087893079 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 993660 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsIssued 3817087 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 19427250 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedNonSpecRemoved 19440265 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 1293606933 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedOperandsExamined 1299740082 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 275979 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 275303 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 4897.575540 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency 4888.651776 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2897.575540 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2888.651776 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 1351628000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency 1345860500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 275979 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses 275303 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 799670000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency 795254500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 275979 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 275303 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 249421 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses 238559 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 4201.208939 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency 4206.099871 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2201.208939 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2206.099871 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 64300 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits 56424 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 777732000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency 766078000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.742203 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate 0.763480 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 185121 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses 182135 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 407490000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency 401808000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.742203 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate 0.763480 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 185121 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses 182135 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 73301 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses 71169 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4221.136137 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency 4205.419494 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2221.136137 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2205.419494 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 309413500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency 299295500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 73301 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses 71169 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 162811500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency 156957500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 73301 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses 71169 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 346070 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 343259 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 346070 # number of Writeback misses system.cpu.l2cache.Writeback_misses 343259 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 346070 # number of Writeback MSHR misses system.cpu.l2cache.Writeback_mshr_misses 343259 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 4.935065 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 4.652891 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 525400 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses 513862 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 4618.000434 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency 4616.884693 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2618.000434 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 2616.884693 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 64300 # number of demand (read+write) hits system.cpu.l2cache.demand_hits 56424 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 2129360000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency 2111938500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.877617 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate 0.890196 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 461100 # number of demand (read+write) misses system.cpu.l2cache.demand_misses 457438 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 1207160000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 1197062500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.877617 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate 0.890196 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 461100 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses 457438 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 525400 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses 513862 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 4618.000434 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency 4616.884693 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2618.000434 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 2616.884693 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 64300 # number of overall hits system.cpu.l2cache.overall_hits 56424 # number of overall hits
system.cpu.l2cache.overall_miss_latency 2129360000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency 2111938500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.877617 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate 0.890196 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 461100 # number of overall misses system.cpu.l2cache.overall_misses 457438 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 1207160000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency 1197062500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.877617 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate 0.890196 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 461100 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses 457438 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -411,31 +411,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 19390 # number of replacements system.cpu.l2cache.replacements 19390 # number of replacements
system.cpu.l2cache.sampled_refs 20790 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 20786 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 8555.838166 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 8527.413561 # Cycle average of tags in use
system.cpu.l2cache.total_refs 102600 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 96715 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.numCycles 2199803710 # number of cpu cycles simulated system.cpu.numCycles 2194953627 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 12980165 # Number of cycles rename is blocking system.cpu.rename.RENAME:BlockCycles 13000888 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1244762261 # Number of HB maps that are committed system.cpu.rename.RENAME:CommittedMaps 1244771057 # Number of HB maps that are committed
system.cpu.rename.RENAME:FullRegisterEvents 11 # Number of times there has been no free registers system.cpu.rename.RENAME:FullRegisterEvents 9 # Number of times there has been no free registers
system.cpu.rename.RENAME:IQFullEvents 40711 # Number of times rename has blocked due to IQ full system.cpu.rename.RENAME:IQFullEvents 47407 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 826156851 # Number of cycles rename is idle system.cpu.rename.RENAME:IdleCycles 822770114 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 20049545 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:LSQFullEvents 20101500 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 4942866473 # Number of register rename lookups that rename has made system.cpu.rename.RENAME:RenameLookups 4935577703 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 3108910588 # Number of instructions processed by rename system.cpu.rename.RENAME:RenamedInsts 3109070263 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 2431469653 # Number of destination operands rename has renamed system.cpu.rename.RENAME:RenamedOperands 2428488542 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 720639508 # Number of cycles rename is running system.cpu.rename.RENAME:RunCycles 723045080 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 242953531 # Number of cycles rename is squashing system.cpu.rename.RENAME:SquashCycles 239555254 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 28416809 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UnblockCycles 28402170 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 1186707392 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:UndoneMaps 1183717485 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 368656846 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializeStallCycles 368180121 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 21929426 # count of serializing insts renamed system.cpu.rename.RENAME:serializingInsts 21968418 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 159084902 # count of insts added to the skid buffer system.cpu.rename.RENAME:skidInsts 159248004 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 21683995 # count of temporary serializing insts renamed system.cpu.rename.RENAME:tempSerializingInsts 21723083 # count of temporary serializing insts renamed
system.cpu.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 35 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 19 # Number of system calls system.cpu.workload.PROG:num_syscalls 19 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

8
tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout
View file

@ -36,9 +36,9 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Aug 12 2007 12:23:15 M5 compiled Aug 14 2007 22:48:17
M5 started Sun Aug 12 12:23:18 2007 M5 started Tue Aug 14 22:51:35 2007
M5 executing on zeep M5 executing on nacho
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing tests/run.py long/00.gzip/sparc/linux/o3-timing command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing tests/run.py long/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
Exiting @ tick 1099901861500 because target called exit() Exiting @ tick 1097476890500 because target called exit()

18
tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
View file

@ -11,12 +11,14 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
children=workload children=dtb itb tracer workload
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false defer_registration=false
dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -25,11 +27,23 @@ phase=0
progress_interval=0 progress_interval=0
simulate_stalls=false simulate_stalls=false
system=system system=system
tracer=system.cpu.tracer
width=1 width=1
workload=system.cpu.workload workload=system.cpu.workload
dcache_port=system.membus.port[2] dcache_port=system.membus.port[2]
icache_port=system.membus.port[1] icache_port=system.membus.port[1]
[system.cpu.dtb]
type=SparcDTB
size=64
[system.cpu.itb]
type=SparcITB
size=64
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload] [system.cpu.workload]
type=LiveProcess type=LiveProcess
cmd=gzip input.log 1 cmd=gzip input.log 1
@ -53,7 +67,7 @@ bus_id=0
clock=1000 clock=1000
responder_set=false responder_set=false
width=64 width=64
port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem] [system.physmem]
type=PhysicalMemory type=PhysicalMemory

20
tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt
View file

@ -1,18 +1,18 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 723585 # Simulator instruction rate (inst/s) host_inst_rate 1870525 # Simulator instruction rate (inst/s)
host_mem_usage 149576 # Number of bytes of host memory used host_mem_usage 176480 # Number of bytes of host memory used
host_seconds 2058.52 # Real time elapsed on the host host_seconds 796.31 # Real time elapsed on the host
host_tick_rate 361792205 # Simulator tick rate (ticks/s) host_tick_rate 935265227 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1489514860 # Number of instructions simulated sim_insts 1489514761 # Number of instructions simulated
sim_seconds 0.744757 # Number of seconds simulated sim_seconds 0.744760 # Number of seconds simulated
sim_ticks 744757429500 # Number of ticks simulated sim_ticks 744759833500 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1489514860 # number of cpu cycles simulated system.cpu.numCycles 1489519668 # number of cpu cycles simulated
system.cpu.num_insts 1489514860 # Number of instructions executed system.cpu.num_insts 1489514761 # Number of instructions executed
system.cpu.num_refs 569359656 # Number of memory references system.cpu.num_refs 569364430 # Number of memory references
system.cpu.workload.PROG:num_syscalls 19 # Number of system calls system.cpu.workload.PROG:num_syscalls 19 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

8
tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout
View file

@ -36,9 +36,9 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled May 15 2007 13:02:31 M5 compiled Aug 14 2007 22:48:17
M5 started Tue May 15 13:02:33 2007 M5 started Tue Aug 14 22:51:35 2007
M5 executing on zizzer.eecs.umich.edu M5 executing on nacho
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic tests/run.py long/00.gzip/sparc/linux/simple-atomic command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic tests/run.py long/00.gzip/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
Exiting @ tick 744757429500 because target called exit() Exiting @ tick 744759833500 because target called exit()

12
tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
View file

@ -11,12 +11,14 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=TimingSimpleCPU type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus tracer workload children=dcache dtb icache itb l2cache toL2Bus tracer workload
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false defer_registration=false
dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -65,6 +67,10 @@ write_buffers=8
cpu_side=system.cpu.dcache_port cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1] mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=SparcDTB
size=64
[system.cpu.icache] [system.cpu.icache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615
@ -101,6 +107,10 @@ write_buffers=8
cpu_side=system.cpu.icache_port cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0] mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=SparcITB
size=64
[system.cpu.l2cache] [system.cpu.l2cache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615

44
tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 1190065 # Simulator instruction rate (inst/s) host_inst_rate 1120793 # Simulator instruction rate (inst/s)
host_mem_usage 201788 # Number of bytes of host memory used host_mem_usage 183848 # Number of bytes of host memory used
host_seconds 1251.63 # Real time elapsed on the host host_seconds 1328.98 # Real time elapsed on the host
host_tick_rate 1654548560 # Simulator tick rate (ticks/s) host_tick_rate 1558243449 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1489514860 # Number of instructions simulated sim_insts 1489514761 # Number of instructions simulated
sim_seconds 2.070875 # Number of seconds simulated sim_seconds 2.070880 # Number of seconds simulated
sim_ticks 2070875212000 # Number of ticks simulated sim_ticks 2070879986000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 402511688 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses 402511688 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 23237.213149 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency 23237.213149 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21237.213149 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21237.213149 # average ReadReq mshr miss latency
@ -86,14 +86,14 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 449136 # number of replacements system.cpu.dcache.replacements 449136 # number of replacements
system.cpu.dcache.sampled_refs 453232 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 453232 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4095.520244 # Cycle average of tags in use system.cpu.dcache.tagsinuse 4095.519446 # Cycle average of tags in use
system.cpu.dcache.total_refs 568906424 # Total number of references to valid blocks. system.cpu.dcache.total_refs 568906424 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 358125000 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 358580000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 316447 # number of writebacks system.cpu.dcache.writebacks 316447 # number of writebacks
system.cpu.icache.ReadReq_accesses 1489514861 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses 1489519635 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 24978.142077 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 24978.142077 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 22978.142077 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 22978.142077 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 1489513763 # number of ReadReq hits system.cpu.icache.ReadReq_hits 1489518537 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 27426000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency 27426000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 1098 # number of ReadReq misses system.cpu.icache.ReadReq_misses 1098 # number of ReadReq misses
@ -102,16 +102,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # ms
system.cpu.icache.ReadReq_mshr_misses 1098 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses 1098 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 1356569.911658 # Average number of references to valid blocks. system.cpu.icache.avg_refs 1356574.259563 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 1489514861 # number of demand (read+write) accesses system.cpu.icache.demand_accesses 1489519635 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 24978.142077 # average overall miss latency system.cpu.icache.demand_avg_miss_latency 24978.142077 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 22978.142077 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 22978.142077 # average overall mshr miss latency
system.cpu.icache.demand_hits 1489513763 # number of demand (read+write) hits system.cpu.icache.demand_hits 1489518537 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 27426000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency 27426000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
system.cpu.icache.demand_misses 1098 # number of demand (read+write) misses system.cpu.icache.demand_misses 1098 # number of demand (read+write) misses
@ -122,11 +122,11 @@ system.cpu.icache.demand_mshr_misses 1098 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 1489514861 # number of overall (read+write) accesses system.cpu.icache.overall_accesses 1489519635 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 24978.142077 # average overall miss latency system.cpu.icache.overall_avg_miss_latency 24978.142077 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 22978.142077 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 22978.142077 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 1489513763 # number of overall hits system.cpu.icache.overall_hits 1489518537 # number of overall hits
system.cpu.icache.overall_miss_latency 27426000 # number of overall miss cycles system.cpu.icache.overall_miss_latency 27426000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_misses 1098 # number of overall misses system.cpu.icache.overall_misses 1098 # number of overall misses
@ -148,8 +148,8 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 115 # number of replacements system.cpu.icache.replacements 115 # number of replacements
system.cpu.icache.sampled_refs 1098 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 1098 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 891.566276 # Cycle average of tags in use system.cpu.icache.tagsinuse 891.566024 # Cycle average of tags in use
system.cpu.icache.total_refs 1489513763 # Total number of references to valid blocks. system.cpu.icache.total_refs 1489518537 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
@ -234,14 +234,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 18201 # number of replacements system.cpu.l2cache.replacements 18201 # number of replacements
system.cpu.l2cache.sampled_refs 19574 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 19574 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 8449.172652 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 8449.165713 # Cycle average of tags in use
system.cpu.l2cache.total_refs 62289 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 62289 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 2070875212000 # number of cpu cycles simulated system.cpu.numCycles 2070879986000 # number of cpu cycles simulated
system.cpu.num_insts 1489514860 # Number of instructions executed system.cpu.num_insts 1489514761 # Number of instructions executed
system.cpu.num_refs 569359656 # Number of memory references system.cpu.num_refs 569364430 # Number of memory references
system.cpu.workload.PROG:num_syscalls 19 # Number of system calls system.cpu.workload.PROG:num_syscalls 19 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

8
tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout
View file

@ -36,9 +36,9 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Aug 12 2007 12:23:15 M5 compiled Aug 14 2007 22:48:17
M5 started Sun Aug 12 16:24:16 2007 M5 started Tue Aug 14 23:04:52 2007
M5 executing on zeep M5 executing on nacho
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing tests/run.py long/00.gzip/sparc/linux/simple-timing command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing tests/run.py long/00.gzip/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
Exiting @ tick 2070875212000 because target called exit() Exiting @ tick 2070879986000 because target called exit()

16
tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
View file

@ -11,12 +11,14 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
children=workload children=dtb itb tracer workload
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false defer_registration=false
dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -25,11 +27,23 @@ phase=0
progress_interval=0 progress_interval=0
simulate_stalls=false simulate_stalls=false
system=system system=system
tracer=system.cpu.tracer
width=1 width=1
workload=system.cpu.workload workload=system.cpu.workload
dcache_port=system.membus.port[2] dcache_port=system.membus.port[2]
icache_port=system.membus.port[1] icache_port=system.membus.port[1]
[system.cpu.dtb]
type=SparcDTB
size=64
[system.cpu.itb]
type=SparcITB
size=64
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload] [system.cpu.workload]
type=LiveProcess type=LiveProcess
cmd=mcf mcf.in cmd=mcf mcf.in

20
tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt
View file

@ -1,18 +1,18 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 1151751 # Simulator instruction rate (inst/s) host_inst_rate 1759086 # Simulator instruction rate (inst/s)
host_mem_usage 150484 # Number of bytes of host memory used host_mem_usage 176892 # Number of bytes of host memory used
host_seconds 211.71 # Real time elapsed on the host host_seconds 138.61 # Real time elapsed on the host
host_tick_rate 575874246 # Simulator tick rate (ticks/s) host_tick_rate 881692154 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 243840172 # Number of instructions simulated sim_insts 243829010 # Number of instructions simulated
sim_seconds 0.121920 # Number of seconds simulated sim_seconds 0.122213 # Number of seconds simulated
sim_ticks 121920085500 # Number of ticks simulated sim_ticks 122212687000 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 243840172 # number of cpu cycles simulated system.cpu.numCycles 244425375 # number of cpu cycles simulated
system.cpu.num_insts 243840172 # Number of instructions executed system.cpu.num_insts 243829010 # Number of instructions executed
system.cpu.num_refs 105125191 # Number of memory references system.cpu.num_refs 105710359 # Number of memory references
system.cpu.workload.PROG:num_syscalls 428 # Number of system calls system.cpu.workload.PROG:num_syscalls 428 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

8
tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout
View file

@ -21,9 +21,9 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Jun 21 2007 21:15:48 M5 compiled Aug 14 2007 22:48:17
M5 started Fri Jun 22 01:58:18 2007 M5 started Tue Aug 14 23:27:01 2007
M5 executing on zizzer.eecs.umich.edu M5 executing on nacho
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic tests/run.py long/10.mcf/sparc/linux/simple-atomic command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic tests/run.py long/10.mcf/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
Exiting @ tick 121920085500 because target called exit() Exiting @ tick 122212687000 because target called exit()

12
tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
View file

@ -11,12 +11,14 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=TimingSimpleCPU type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus tracer workload children=dcache dtb icache itb l2cache toL2Bus tracer workload
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false defer_registration=false
dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -65,6 +67,10 @@ write_buffers=8
cpu_side=system.cpu.dcache_port cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1] mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=SparcDTB
size=64
[system.cpu.icache] [system.cpu.icache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615
@ -101,6 +107,10 @@ write_buffers=8
cpu_side=system.cpu.icache_port cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0] mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=SparcITB
size=64
[system.cpu.l2cache] [system.cpu.l2cache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615

44
tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 1064489 # Simulator instruction rate (inst/s) host_inst_rate 1059302 # Simulator instruction rate (inst/s)
host_mem_usage 202188 # Number of bytes of host memory used host_mem_usage 184256 # Number of bytes of host memory used
host_seconds 229.07 # Real time elapsed on the host host_seconds 230.18 # Real time elapsed on the host
host_tick_rate 1583716497 # Simulator tick rate (ticks/s) host_tick_rate 1578613892 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 243840172 # Number of instructions simulated sim_insts 243829010 # Number of instructions simulated
sim_seconds 0.362779 # Number of seconds simulated sim_seconds 0.363364 # Number of seconds simulated
sim_ticks 362778959000 # Number of ticks simulated sim_ticks 363364127000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 82219469 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses 82219469 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 13897.517462 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency 13897.517462 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11897.517462 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11897.517462 # average ReadReq mshr miss latency
@ -86,14 +86,14 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 935407 # number of replacements system.cpu.dcache.replacements 935407 # number of replacements
system.cpu.dcache.sampled_refs 939503 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 939503 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 3565.606162 # Cycle average of tags in use system.cpu.dcache.tagsinuse 3566.459969 # Cycle average of tags in use
system.cpu.dcache.total_refs 104185688 # Total number of references to valid blocks. system.cpu.dcache.total_refs 104185688 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 134193588000 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 134193645000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 94807 # number of writebacks system.cpu.dcache.writebacks 94807 # number of writebacks
system.cpu.icache.ReadReq_accesses 243840173 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses 244425341 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 24972.696246 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 24972.696246 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 22972.696246 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 22972.696246 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 243839294 # number of ReadReq hits system.cpu.icache.ReadReq_hits 244424462 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 21951000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency 21951000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 879 # number of ReadReq misses system.cpu.icache.ReadReq_misses 879 # number of ReadReq misses
@ -102,16 +102,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # ms
system.cpu.icache.ReadReq_mshr_misses 879 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses 879 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 277405.340159 # Average number of references to valid blocks. system.cpu.icache.avg_refs 278071.060296 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 243840173 # number of demand (read+write) accesses system.cpu.icache.demand_accesses 244425341 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 24972.696246 # average overall miss latency system.cpu.icache.demand_avg_miss_latency 24972.696246 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 22972.696246 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 22972.696246 # average overall mshr miss latency
system.cpu.icache.demand_hits 243839294 # number of demand (read+write) hits system.cpu.icache.demand_hits 244424462 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 21951000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency 21951000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_misses 879 # number of demand (read+write) misses system.cpu.icache.demand_misses 879 # number of demand (read+write) misses
@ -122,11 +122,11 @@ system.cpu.icache.demand_mshr_misses 879 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 243840173 # number of overall (read+write) accesses system.cpu.icache.overall_accesses 244425341 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 24972.696246 # average overall miss latency system.cpu.icache.overall_avg_miss_latency 24972.696246 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 22972.696246 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 22972.696246 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 243839294 # number of overall hits system.cpu.icache.overall_hits 244424462 # number of overall hits
system.cpu.icache.overall_miss_latency 21951000 # number of overall miss cycles system.cpu.icache.overall_miss_latency 21951000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_misses 879 # number of overall misses system.cpu.icache.overall_misses 879 # number of overall misses
@ -148,8 +148,8 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 25 # number of replacements system.cpu.icache.replacements 25 # number of replacements
system.cpu.icache.sampled_refs 879 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 879 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 716.749422 # Cycle average of tags in use system.cpu.icache.tagsinuse 716.846544 # Cycle average of tags in use
system.cpu.icache.total_refs 243839294 # Total number of references to valid blocks. system.cpu.icache.total_refs 244424462 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
@ -234,14 +234,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 829 # number of replacements system.cpu.l2cache.replacements 829 # number of replacements
system.cpu.l2cache.sampled_refs 11345 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 11345 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 8098.685225 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 8106.936507 # Cycle average of tags in use
system.cpu.l2cache.total_refs 553407 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 553407 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 362778959000 # number of cpu cycles simulated system.cpu.numCycles 363364127000 # number of cpu cycles simulated
system.cpu.num_insts 243840172 # Number of instructions executed system.cpu.num_insts 243829010 # Number of instructions executed
system.cpu.num_refs 105125191 # Number of memory references system.cpu.num_refs 105710359 # Number of memory references
system.cpu.workload.PROG:num_syscalls 428 # Number of system calls system.cpu.workload.PROG:num_syscalls 428 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

8
tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout
View file

@ -21,9 +21,9 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Aug 12 2007 12:23:15 M5 compiled Aug 14 2007 22:48:17
M5 started Sun Aug 12 16:47:12 2007 M5 started Tue Aug 14 23:29:20 2007
M5 executing on zeep M5 executing on nacho
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing tests/run.py long/10.mcf/sparc/linux/simple-timing command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing tests/run.py long/10.mcf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
Exiting @ tick 362778959000 because target called exit() Exiting @ tick 363364127000 because target called exit()

12
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=DerivO3CPU type=DerivO3CPU
children=dcache fuPool icache l2cache toL2Bus tracer workload children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
BTBEntries=4096 BTBEntries=4096
BTBTagSize=16 BTBTagSize=16
LFSTSize=1024 LFSTSize=1024
@ -36,6 +36,7 @@ decodeToRenameDelay=1
decodeWidth=8 decodeWidth=8
defer_registration=false defer_registration=false
dispatchWidth=8 dispatchWidth=8
dtb=system.cpu.dtb
fetchToDecodeDelay=1 fetchToDecodeDelay=1
fetchTrapLatency=1 fetchTrapLatency=1
fetchWidth=8 fetchWidth=8
@ -53,6 +54,7 @@ iewToRenameDelay=1
instShiftAmt=2 instShiftAmt=2
issueToExecuteDelay=1 issueToExecuteDelay=1
issueWidth=8 issueWidth=8
itb=system.cpu.itb
localCtrBits=2 localCtrBits=2
localHistoryBits=11 localHistoryBits=11
localHistoryTableSize=2048 localHistoryTableSize=2048
@ -130,6 +132,10 @@ write_buffers=8
cpu_side=system.cpu.dcache_port cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1] mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=AlphaDTB
size=64
[system.cpu.fuPool] [system.cpu.fuPool]
type=FUPool type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
@ -303,6 +309,10 @@ write_buffers=8
cpu_side=system.cpu.icache_port cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0] mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=AlphaITB
size=48
[system.cpu.l2cache] [system.cpu.l2cache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615

566
tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt
View file

@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits 38073438 # Number of BTB hits global.BPredUnit.BTBHits 36861570 # Number of BTB hits
global.BPredUnit.BTBLookups 45542237 # Number of BTB lookups global.BPredUnit.BTBLookups 45954115 # Number of BTB lookups
global.BPredUnit.RASInCorrect 1066 # Number of incorrect RAS predictions. global.BPredUnit.RASInCorrect 1137 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 5897861 # Number of conditional branches incorrect global.BPredUnit.condIncorrect 5797485 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 35152227 # Number of conditional branches predicted global.BPredUnit.condPredicted 35586107 # Number of conditional branches predicted
global.BPredUnit.lookups 62262084 # Number of BP lookups global.BPredUnit.lookups 62816866 # Number of BP lookups
global.BPredUnit.usedRAS 12565322 # Number of times the RAS was used to get a target. global.BPredUnit.usedRAS 12584281 # Number of times the RAS was used to get a target.
host_inst_rate 169929 # Simulator instruction rate (inst/s) host_inst_rate 159982 # Simulator instruction rate (inst/s)
host_mem_usage 207944 # Number of bytes of host memory used host_mem_usage 190068 # Number of bytes of host memory used
host_seconds 2210.19 # Real time elapsed on the host host_seconds 2347.61 # Real time elapsed on the host
host_tick_rate 59827386 # Simulator tick rate (ticks/s) host_tick_rate 55593251 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 71764383 # Number of conflicting loads. memdepunit.memDep.conflictingLoads 72605768 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 51661369 # Number of conflicting stores. memdepunit.memDep.conflictingStores 52678550 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 124318593 # Number of loads inserted to the mem dependence unit. memdepunit.memDep.insertedLoads 125601766 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 91863744 # Number of stores inserted to the mem dependence unit. memdepunit.memDep.insertedStores 92855490 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 375574833 # Number of instructions simulated sim_insts 375574833 # Number of instructions simulated
sim_seconds 0.132230 # Number of seconds simulated sim_seconds 0.130511 # Number of seconds simulated
sim_ticks 132229900500 # Number of ticks simulated sim_ticks 130511349000 # Number of ticks simulated
system.cpu.commit.COM:branches 44587535 # Number of branches committed system.cpu.commit.COM:branches 44587535 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 12177812 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_lim_events 13042688 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 249309209 system.cpu.commit.COM:committed_per_cycle.samples 245378648
system.cpu.commit.COM:committed_per_cycle.min_value 0 system.cpu.commit.COM:committed_per_cycle.min_value 0
0 114305349 4584.88% 0 113059928 4607.57%
1 51380693 2060.92% 1 50147502 2043.68%
2 21363734 856.92% 2 19710557 803.27%
3 20883024 837.64% 3 20862995 850.24%
4 12699516 509.39% 4 12236933 498.70%
5 8486510 340.40% 5 8068065 328.80%
6 4833732 193.89% 6 4872414 198.57%
7 3178839 127.51% 7 3377566 137.65%
8 12177812 488.46% 8 13042688 531.53%
system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist system.cpu.commit.COM:committed_per_cycle.end_dist
@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 100651996 # Nu
system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 174183399 # Number of memory references committed system.cpu.commit.COM:refs 174183399 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 5893662 # The number of times a branch was mispredicted system.cpu.commit.branchMispredicts 5793282 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 398664608 # The number of committed instructions system.cpu.commit.commitCommittedInsts 398664608 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 93436434 # The number of squashed insts skipped by commit system.cpu.commit.commitSquashedInsts 97412298 # The number of squashed insts skipped by commit
system.cpu.committedInsts 375574833 # Number of Instructions Simulated system.cpu.committedInsts 375574833 # Number of Instructions Simulated
system.cpu.committedInsts_total 375574833 # Number of Instructions Simulated system.cpu.committedInsts_total 375574833 # Number of Instructions Simulated
system.cpu.cpi 0.704145 # CPI: Cycles Per Instruction system.cpu.cpi 0.694992 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.704145 # CPI: Total CPI of All Threads system.cpu.cpi_total 0.694992 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses 96516428 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses 96463931 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 11350.662589 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency 11260.913706 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5775.739042 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5745.177665 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 96515447 # number of ReadReq hits system.cpu.dcache.ReadReq_hits 96462946 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 11135000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency 11092000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 981 # number of ReadReq misses system.cpu.dcache.ReadReq_misses 985 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 512 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits 503 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 5666000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency 5659000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 981 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses 985 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 73513288 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 73513272 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 23676.737160 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency 23662.839879 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6083.836858 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6056.042296 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 73509978 # number of WriteReq hits system.cpu.dcache.WriteReq_hits 73509962 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 78370000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency 78324000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000045 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate 0.000045 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 3310 # number of WriteReq misses system.cpu.dcache.WriteReq_misses 3310 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 7442 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits 7458 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 20137500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency 20045500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 3310 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 3310 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 40714.928400 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 40702.353448 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 170029716 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses 169977203 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 20858.774179 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency 20818.626310 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 6013.400140 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 5984.749709 # average overall mshr miss latency
system.cpu.dcache.demand_hits 170025425 # number of demand (read+write) hits system.cpu.dcache.demand_hits 169972908 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 89505000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency 89416000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
system.cpu.dcache.demand_misses 4291 # number of demand (read+write) misses system.cpu.dcache.demand_misses 4295 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 7954 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits 7961 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 25803500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency 25704500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 4291 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses 4295 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 170029716 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses 169977203 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 20858.774179 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency 20818.626310 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 6013.400140 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 5984.749709 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 170025425 # number of overall hits system.cpu.dcache.overall_hits 169972908 # number of overall hits
system.cpu.dcache.overall_miss_latency 89505000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency 89416000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
system.cpu.dcache.overall_misses 4291 # number of overall misses system.cpu.dcache.overall_misses 4295 # number of overall misses
system.cpu.dcache.overall_mshr_hits 7954 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits 7961 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 25803500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency 25704500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 4291 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses 4295 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -123,89 +123,101 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 780 # number of replacements system.cpu.dcache.replacements 780 # number of replacements
system.cpu.dcache.sampled_refs 4176 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 4176 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 3294.806600 # Cycle average of tags in use system.cpu.dcache.tagsinuse 3295.577155 # Cycle average of tags in use
system.cpu.dcache.total_refs 170025541 # Total number of references to valid blocks. system.cpu.dcache.total_refs 169973028 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 635 # number of writebacks system.cpu.dcache.writebacks 635 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 14093330 # Number of cycles decode is blocked system.cpu.decode.DECODE:BlockedCycles 10379369 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 4329 # Number of times decode detected a branch misprediction system.cpu.decode.DECODE:BranchMispred 4333 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 11426166 # Number of times decode resolved a branch system.cpu.decode.DECODE:BranchResolved 11455632 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 530907169 # Number of instructions handled by decode system.cpu.decode.DECODE:DecodedInsts 536109933 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 132358480 # Number of cycles decode is idle system.cpu.decode.DECODE:IdleCycles 132797558 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 102072460 # Number of cycles decode is running system.cpu.decode.DECODE:RunCycles 101446828 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 15149848 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashCycles 15642913 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 12784 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:SquashedInsts 12797 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 784940 # Number of cycles decode is unblocking system.cpu.decode.DECODE:UnblockCycles 754894 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 62262084 # Number of branches that fetch encountered system.cpu.dtb.accesses 185890093 # DTB accesses
system.cpu.fetch.CacheLines 64149519 # Number of cache lines fetched system.cpu.dtb.acv 14625 # DTB access violations
system.cpu.fetch.Cycles 169628877 # Number of cycles fetch has run and was not squashing or blocked system.cpu.dtb.hits 185845750 # DTB hits
system.cpu.fetch.IcacheSquashes 1267942 # Number of outstanding Icache misses that were squashed system.cpu.dtb.misses 44343 # DTB misses
system.cpu.fetch.Insts 544672632 # Number of instructions fetch has processed system.cpu.dtb.read_accesses 105156938 # DTB read accesses
system.cpu.fetch.SquashCycles 6256256 # Number of cycles fetch has spent squashing system.cpu.dtb.read_acv 14625 # DTB read access violations
system.cpu.fetch.branchRate 0.235432 # Number of branch fetches per cycle system.cpu.dtb.read_hits 105114144 # DTB read hits
system.cpu.fetch.icacheStallCycles 64149519 # Number of cycles fetch is stalled on an Icache miss system.cpu.dtb.read_misses 42794 # DTB read misses
system.cpu.fetch.predictedBranches 50638760 # Number of branches that fetch has predicted taken system.cpu.dtb.write_accesses 80733155 # DTB write accesses
system.cpu.fetch.rate 2.059573 # Number of inst fetches per cycle system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 80731606 # DTB write hits
system.cpu.dtb.write_misses 1549 # DTB write misses
system.cpu.fetch.Branches 62816866 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 64526365 # Number of cache lines fetched
system.cpu.fetch.Cycles 169349894 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 1380085 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 550063393 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 6176073 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.240658 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 64526365 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 49445851 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.107348 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 264459058 system.cpu.fetch.rateDist.samples 261021562
system.cpu.fetch.rateDist.min_value 0 system.cpu.fetch.rateDist.min_value 0
0 158979701 6011.51% 0 156198329 5984.12%
1 11898103 449.90% 1 10474114 401.27%
2 12511338 473.09% 2 12009483 460.10%
3 6558243 247.99% 3 7031360 269.38%
4 15951093 603.16% 4 15051020 576.62%
5 8933216 337.79% 5 10018831 383.83%
6 6667977 252.14% 6 6809824 260.89%
7 4076286 154.14% 7 4109754 157.45%
8 38883101 1470.29% 8 39318847 1506.34%
system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 64149331 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses 64526174 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 7193.164363 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 7182.389131 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 5001.152074 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 4988.079979 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 64145425 # number of ReadReq hits system.cpu.icache.ReadReq_hits 64522273 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 28096500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency 28018500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000061 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate 0.000060 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 3906 # number of ReadReq misses system.cpu.icache.ReadReq_misses 3901 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 188 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits 191 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 19534500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency 19458500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000061 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate 0.000060 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 3906 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses 3901 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 16422.279826 # Average number of references to valid blocks. system.cpu.icache.avg_refs 16539.931556 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 64149331 # number of demand (read+write) accesses system.cpu.icache.demand_accesses 64526174 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 7193.164363 # average overall miss latency system.cpu.icache.demand_avg_miss_latency 7182.389131 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 5001.152074 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 4988.079979 # average overall mshr miss latency
system.cpu.icache.demand_hits 64145425 # number of demand (read+write) hits system.cpu.icache.demand_hits 64522273 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 28096500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency 28018500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000061 # miss rate for demand accesses system.cpu.icache.demand_miss_rate 0.000060 # miss rate for demand accesses
system.cpu.icache.demand_misses 3906 # number of demand (read+write) misses system.cpu.icache.demand_misses 3901 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 188 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits 191 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 19534500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency 19458500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000061 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate 0.000060 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 3906 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses 3901 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 64149331 # number of overall (read+write) accesses system.cpu.icache.overall_accesses 64526174 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 7193.164363 # average overall miss latency system.cpu.icache.overall_avg_miss_latency 7182.389131 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 5001.152074 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 4988.079979 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 64145425 # number of overall hits system.cpu.icache.overall_hits 64522273 # number of overall hits
system.cpu.icache.overall_miss_latency 28096500 # number of overall miss cycles system.cpu.icache.overall_miss_latency 28018500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000061 # miss rate for overall accesses system.cpu.icache.overall_miss_rate 0.000060 # miss rate for overall accesses
system.cpu.icache.overall_misses 3906 # number of overall misses system.cpu.icache.overall_misses 3901 # number of overall misses
system.cpu.icache.overall_mshr_hits 188 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits 191 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 19534500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency 19458500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000061 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate 0.000060 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 3906 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses 3901 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -217,144 +229,148 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 1984 # number of replacements system.cpu.icache.replacements 1979 # number of replacements
system.cpu.icache.sampled_refs 3906 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 3901 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1827.150129 # Cycle average of tags in use system.cpu.icache.tagsinuse 1827.041992 # Cycle average of tags in use
system.cpu.icache.total_refs 64145425 # Total number of references to valid blocks. system.cpu.icache.total_refs 64522273 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 557628 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.idleCycles 787561 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 51104102 # Number of branches executed system.cpu.iew.EXEC:branches 51184181 # Number of branches executed
system.cpu.iew.EXEC:nop 27319155 # number of nop insts executed system.cpu.iew.EXEC:nop 27521515 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.584545 # Inst execution rate system.cpu.iew.EXEC:rate 1.613810 # Inst execution rate
system.cpu.iew.EXEC:refs 191326029 # number of memory reference insts executed system.cpu.iew.EXEC:refs 192783461 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 79588041 # Number of stores executed system.cpu.iew.EXEC:stores 80743835 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 282498519 # num instructions consuming a value system.cpu.iew.WB:consumers 284447545 # num instructions consuming a value
system.cpu.iew.WB:count 414521159 # cumulative count of insts written-back system.cpu.iew.WB:count 417188655 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.706139 # average fanout of values written-back system.cpu.iew.WB:fanout 0.706015 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 199483248 # num instructions producing a value system.cpu.iew.WB:producers 200824371 # num instructions producing a value
system.cpu.iew.WB:rate 1.567430 # insts written-back per cycle system.cpu.iew.WB:rate 1.598292 # insts written-back per cycle
system.cpu.iew.WB:sent 415435713 # cumulative count of insts sent to commit system.cpu.iew.WB:sent 418096768 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 6236762 # Number of branch mispredicts detected at execute system.cpu.iew.branchMispredicts 6170690 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 2781988 # Number of cycles IEW is blocking system.cpu.iew.iewBlockCycles 1426561 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 124318593 # Number of dispatched load instructions system.cpu.iew.iewDispLoadInsts 125601766 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 240 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispNonSpecInsts 239 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 6814163 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispSquashedInsts 6545178 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 91863744 # Number of dispatched store instructions system.cpu.iew.iewDispStoreInsts 92855490 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 492099709 # Number of instructions dispatched to IQ system.cpu.iew.iewDispatchedInsts 496077841 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 111737988 # Number of load instructions executed system.cpu.iew.iewExecLoadInsts 112039626 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 8739319 # Number of squashed instructions skipped in execute system.cpu.iew.iewExecSquashedInsts 9995558 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 419047233 # Number of executed instructions system.cpu.iew.iewExecutedInsts 421239213 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 168412 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIQFullEvents 59610 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 50946 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 24612 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 15149848 # Number of cycles IEW is squashing system.cpu.iew.iewSquashCycles 15642913 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 506738 # Number of cycles IEW is unblocking system.cpu.iew.iewUnblockCycles 326804 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 8219638 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.forwLoads 8473702 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 31016 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.ignoredResponses 35459 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 502753 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.memOrderViolation 574238 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 178119 # Number of loads that were rescheduled system.cpu.iew.lsq.thread.0.rescheduledLoads 176007 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 23666597 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedLoads 24949770 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 18332341 # Number of stores squashed system.cpu.iew.lsq.thread.0.squashedStores 19324087 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 502753 # Number of memory order violations system.cpu.iew.memOrderViolationEvents 574238 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 955669 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 908757 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 5281093 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedTakenIncorrect 5261933 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.420162 # IPC: Instructions Per Cycle system.cpu.ipc 1.438865 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.420162 # IPC: Total IPC of All Threads system.cpu.ipc_total 1.438865 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 427786552 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0 431234771 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 33581 0.01% # Type of FU issued No_OpClass 33581 0.01% # Type of FU issued
IntAlu 166519693 38.93% # Type of FU issued IntAlu 167547165 38.85% # Type of FU issued
IntMult 2147905 0.50% # Type of FU issued IntMult 2148252 0.50% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued
FloatAdd 35254026 8.24% # Type of FU issued FloatAdd 34932915 8.10% # Type of FU issued
FloatCmp 7817685 1.83% # Type of FU issued FloatCmp 7864913 1.82% # Type of FU issued
FloatCvt 2969947 0.69% # Type of FU issued FloatCvt 2933513 0.68% # Type of FU issued
FloatMult 16787400 3.92% # Type of FU issued FloatMult 16766961 3.89% # Type of FU issued
FloatDiv 1570522 0.37% # Type of FU issued FloatDiv 1572145 0.36% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued
MemRead 113248293 26.47% # Type of FU issued MemRead 114624584 26.58% # Type of FU issued
MemWrite 81437500 19.04% # Type of FU issued MemWrite 82810742 19.20% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 9448608 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_cnt 10914524 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.022087 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_busy_rate 0.025310 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available No_OpClass 0 0.00% # attempts to use FU when none available
IntAlu 17181 0.18% # attempts to use FU when none available IntAlu 15305 0.14% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 604 0.01% # attempts to use FU when none available FloatAdd 41564 0.38% # attempts to use FU when none available
FloatCmp 32516 0.34% # attempts to use FU when none available FloatCmp 31641 0.29% # attempts to use FU when none available
FloatCvt 8012 0.08% # attempts to use FU when none available FloatCvt 9732 0.09% # attempts to use FU when none available
FloatMult 2137313 22.62% # attempts to use FU when none available FloatMult 2290427 20.99% # attempts to use FU when none available
FloatDiv 917798 9.71% # attempts to use FU when none available FloatDiv 1536693 14.08% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available
MemRead 5261958 55.69% # attempts to use FU when none available MemRead 5500856 50.40% # attempts to use FU when none available
MemWrite 1073226 11.36% # attempts to use FU when none available MemWrite 1488306 13.64% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples 264459058 system.cpu.iq.ISSUE:issued_per_cycle.samples 261021562
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 94473273 3572.32% 0 92982852 3562.27%
1 57538428 2175.70% 1 54227475 2077.51%
2 41283183 1561.04% 2 40411704 1548.21%
3 28951087 1094.73% 3 29929713 1146.64%
4 22152944 837.67% 4 23083699 884.36%
5 11939207 451.46% 5 11888091 455.44%
6 5137200 194.25% 6 5433351 208.16%
7 2172402 82.15% 7 2498024 95.70%
8 811334 30.68% 8 566653 21.71%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 1.617591 # Inst issue rate system.cpu.iq.ISSUE:rate 1.652104 # Inst issue rate
system.cpu.iq.iqInstsAdded 464780314 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsAdded 468556087 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 427786552 # Number of instructions issued system.cpu.iq.iqInstsIssued 431234771 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 240 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqNonSpecInstsAdded 239 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 88460147 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsExamined 92147793 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 742026 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsIssued 947116 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 25 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 67499517 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedOperandsExamined 68967166 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 3199 # number of ReadExReq accesses(hits+misses) system.cpu.itb.accesses 64526661 # ITB accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency 4646.764614 # average ReadExReq miss latency system.cpu.itb.acv 0 # ITB acv
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2646.764614 # average ReadExReq mshr miss latency system.cpu.itb.hits 64526365 # ITB hits
system.cpu.l2cache.ReadExReq_miss_latency 14865000 # number of ReadExReq miss cycles system.cpu.itb.misses 296 # ITB misses
system.cpu.l2cache.ReadExReq_accesses 3195 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 4623.317684 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2623.317684 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 14771500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 3199 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses 3195 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 8467000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency 8381500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 3199 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 3195 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 4883 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses 4882 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 4356.375525 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency 4343.436699 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2356.375525 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2343.436699 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 601 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits 593 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 18654000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency 18629000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.876920 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate 0.878533 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 4282 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses 4289 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 10090000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency 10051000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.876920 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate 0.878533 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 4282 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses 4289 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 117 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses 121 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4482.905983 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency 4487.603306 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2482.905983 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2487.603306 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 524500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency 543000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 117 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses 121 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 290500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency 301000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 117 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses 121 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 635 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 635 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 635 # number of Writeback misses system.cpu.l2cache.Writeback_misses 635 # number of Writeback misses
@ -362,38 +378,38 @@ system.cpu.l2cache.Writeback_mshr_miss_rate 1 #
system.cpu.l2cache.Writeback_mshr_misses 635 # number of Writeback MSHR misses system.cpu.l2cache.Writeback_mshr_misses 635 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.139496 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 0.137476 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 8082 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses 8077 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 4480.550729 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency 4462.920898 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2480.550729 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 2462.920898 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 601 # number of demand (read+write) hits system.cpu.l2cache.demand_hits 593 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 33519000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency 33400500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.925637 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate 0.926582 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 7481 # number of demand (read+write) misses system.cpu.l2cache.demand_misses 7484 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 18557000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 18432500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.925637 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate 0.926582 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 7481 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses 7484 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 8082 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses 8077 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 4480.550729 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency 4462.920898 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2480.550729 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 2462.920898 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 601 # number of overall hits system.cpu.l2cache.overall_hits 593 # number of overall hits
system.cpu.l2cache.overall_miss_latency 33519000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency 33400500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.925637 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate 0.926582 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 7481 # number of overall misses system.cpu.l2cache.overall_misses 7484 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 18557000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency 18432500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.925637 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate 0.926582 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 7481 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses 7484 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -406,30 +422,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 6 # number of replacements system.cpu.l2cache.replacements 6 # number of replacements
system.cpu.l2cache.sampled_refs 4165 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 4168 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 3521.188558 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 3522.085649 # Cycle average of tags in use
system.cpu.l2cache.total_refs 581 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 573 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.numCycles 264459058 # number of cpu cycles simulated system.cpu.numCycles 261021562 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 6942912 # Number of cycles rename is blocking system.cpu.rename.RENAME:BlockCycles 4632657 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 259532351 # Number of HB maps that are committed system.cpu.rename.RENAME:CommittedMaps 259532351 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 1128496 # Number of times rename has blocked due to IQ full system.cpu.rename.RENAME:IQFullEvents 371371 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 136398173 # Number of cycles rename is idle system.cpu.rename.RENAME:IdleCycles 136793870 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 4996172 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:LSQFullEvents 4480722 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 682131973 # Number of register rename lookups that rename has made system.cpu.rename.RENAME:RenameLookups 687103591 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 517993086 # Number of instructions processed by rename system.cpu.rename.RENAME:RenamedInsts 521769627 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 334891535 # Number of destination operands rename has renamed system.cpu.rename.RENAME:RenamedOperands 337207883 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 98637930 # Number of cycles rename is running system.cpu.rename.RENAME:RunCycles 98011455 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 15149848 # Number of cycles rename is squashing system.cpu.rename.RENAME:SquashCycles 15642913 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 6975590 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UnblockCycles 5589343 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 75359184 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:UndoneMaps 77675532 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 354605 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializeStallCycles 351324 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 37909 # count of serializing insts renamed system.cpu.rename.RENAME:serializingInsts 37944 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 15667924 # count of insts added to the skid buffer system.cpu.rename.RENAME:skidInsts 12960882 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 253 # count of temporary serializing insts renamed system.cpu.rename.RENAME:tempSerializingInsts 253 # count of temporary serializing insts renamed
system.cpu.timesIdled 375 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 442 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

18
tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -11,12 +11,14 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
children=workload children=dtb itb tracer workload
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false defer_registration=false
dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -25,11 +27,23 @@ phase=0
progress_interval=0 progress_interval=0
simulate_stalls=false simulate_stalls=false
system=system system=system
tracer=system.cpu.tracer
width=1 width=1
workload=system.cpu.workload workload=system.cpu.workload
dcache_port=system.membus.port[2] dcache_port=system.membus.port[2]
icache_port=system.membus.port[1] icache_port=system.membus.port[1]
[system.cpu.dtb]
type=AlphaDTB
size=64
[system.cpu.itb]
type=AlphaITB
size=48
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload] [system.cpu.workload]
type=LiveProcess type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
@ -53,7 +67,7 @@ bus_id=0
clock=1000 clock=1000
responder_set=false responder_set=false
width=64 width=64
port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem] [system.physmem]
type=PhysicalMemory type=PhysicalMemory

34
tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt
View file

@ -1,18 +1,34 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 828868 # Simulator instruction rate (inst/s) host_inst_rate 2526947 # Simulator instruction rate (inst/s)
host_mem_usage 151076 # Number of bytes of host memory used host_mem_usage 181828 # Number of bytes of host memory used
host_seconds 480.97 # Real time elapsed on the host host_seconds 157.77 # Real time elapsed on the host
host_tick_rate 414433819 # Simulator tick rate (ticks/s) host_tick_rate 1263471125 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 398664597 # Number of instructions simulated sim_insts 398664595 # Number of instructions simulated
sim_seconds 0.199332 # Number of seconds simulated sim_seconds 0.199332 # Number of seconds simulated
sim_ticks 199332298000 # Number of ticks simulated sim_ticks 199332411500 # Number of ticks simulated
system.cpu.dtb.accesses 168275274 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.dtb.hits 168275218 # DTB hits
system.cpu.dtb.misses 56 # DTB misses
system.cpu.dtb.read_accesses 94754510 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 94754489 # DTB read hits
system.cpu.dtb.read_misses 21 # DTB read misses
system.cpu.dtb.write_accesses 73520764 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 73520729 # DTB write hits
system.cpu.dtb.write_misses 35 # DTB write misses
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 398664824 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 398664651 # ITB hits
system.cpu.itb.misses 173 # ITB misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 398664597 # number of cpu cycles simulated system.cpu.numCycles 398664824 # number of cpu cycles simulated
system.cpu.num_insts 398664597 # Number of instructions executed system.cpu.num_insts 398664595 # Number of instructions executed
system.cpu.num_refs 174183399 # Number of memory references system.cpu.num_refs 174183453 # Number of memory references
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

12
tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
View file

@ -11,12 +11,14 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=TimingSimpleCPU type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus tracer workload children=dcache dtb icache itb l2cache toL2Bus tracer workload
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false defer_registration=false
dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -65,6 +67,10 @@ write_buffers=8
cpu_side=system.cpu.dcache_port cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1] mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=AlphaDTB
size=64
[system.cpu.icache] [system.cpu.icache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615
@ -101,6 +107,10 @@ write_buffers=8
cpu_side=system.cpu.icache_port cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0] mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=AlphaITB
size=48
[system.cpu.l2cache] [system.cpu.l2cache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615

56
tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 1477024 # Simulator instruction rate (inst/s) host_inst_rate 1404632 # Simulator instruction rate (inst/s)
host_mem_usage 207136 # Number of bytes of host memory used host_mem_usage 189192 # Number of bytes of host memory used
host_seconds 269.91 # Real time elapsed on the host host_seconds 283.82 # Real time elapsed on the host
host_tick_rate 2101151515 # Simulator tick rate (ticks/s) host_tick_rate 1998169503 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 398664611 # Number of instructions simulated sim_insts 398664609 # Number of instructions simulated
sim_seconds 0.567124 # Number of seconds simulated sim_seconds 0.567124 # Number of seconds simulated
sim_ticks 567123959000 # Number of ticks simulated sim_ticks 567124013000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 94754490 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses 94754490 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 24216.842105 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency 24216.842105 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22216.842105 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22216.842105 # average ReadReq mshr miss latency
@ -76,14 +76,26 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 764 # number of replacements system.cpu.dcache.replacements 764 # number of replacements
system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 3289.454030 # Cycle average of tags in use system.cpu.dcache.tagsinuse 3289.453852 # Cycle average of tags in use
system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks. system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 625 # number of writebacks system.cpu.dcache.writebacks 625 # number of writebacks
system.cpu.icache.ReadReq_accesses 398664612 # number of ReadReq accesses(hits+misses) system.cpu.dtb.accesses 168275276 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.dtb.hits 168275220 # DTB hits
system.cpu.dtb.misses 56 # DTB misses
system.cpu.dtb.read_accesses 94754511 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 94754490 # DTB read hits
system.cpu.dtb.read_misses 21 # DTB read misses
system.cpu.dtb.write_accesses 73520765 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 73520730 # DTB write hits
system.cpu.dtb.write_misses 35 # DTB write misses
system.cpu.icache.ReadReq_accesses 398664666 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 23471.004628 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 23471.004628 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 21471.004628 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 21471.004628 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 398660939 # number of ReadReq hits system.cpu.icache.ReadReq_hits 398660993 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 86209000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency 86209000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 3673 # number of ReadReq misses system.cpu.icache.ReadReq_misses 3673 # number of ReadReq misses
@ -92,16 +104,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # ms
system.cpu.icache.ReadReq_mshr_misses 3673 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses 3673 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 108538.235502 # Average number of references to valid blocks. system.cpu.icache.avg_refs 108538.250204 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 398664612 # number of demand (read+write) accesses system.cpu.icache.demand_accesses 398664666 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 23471.004628 # average overall miss latency system.cpu.icache.demand_avg_miss_latency 23471.004628 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 21471.004628 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 21471.004628 # average overall mshr miss latency
system.cpu.icache.demand_hits 398660939 # number of demand (read+write) hits system.cpu.icache.demand_hits 398660993 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 86209000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency 86209000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses
system.cpu.icache.demand_misses 3673 # number of demand (read+write) misses system.cpu.icache.demand_misses 3673 # number of demand (read+write) misses
@ -112,11 +124,11 @@ system.cpu.icache.demand_mshr_misses 3673 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 398664612 # number of overall (read+write) accesses system.cpu.icache.overall_accesses 398664666 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 23471.004628 # average overall miss latency system.cpu.icache.overall_avg_miss_latency 23471.004628 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 21471.004628 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 21471.004628 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 398660939 # number of overall hits system.cpu.icache.overall_hits 398660993 # number of overall hits
system.cpu.icache.overall_miss_latency 86209000 # number of overall miss cycles system.cpu.icache.overall_miss_latency 86209000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses
system.cpu.icache.overall_misses 3673 # number of overall misses system.cpu.icache.overall_misses 3673 # number of overall misses
@ -138,11 +150,15 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 1769 # number of replacements system.cpu.icache.replacements 1769 # number of replacements
system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1795.369888 # Cycle average of tags in use system.cpu.icache.tagsinuse 1795.369803 # Cycle average of tags in use
system.cpu.icache.total_refs 398660939 # Total number of references to valid blocks. system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 398664839 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 398664666 # ITB hits
system.cpu.itb.misses 173 # ITB misses
system.cpu.l2cache.ReadExReq_accesses 3202 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 3202 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
@ -224,14 +240,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 6 # number of replacements system.cpu.l2cache.replacements 6 # number of replacements
system.cpu.l2cache.sampled_refs 3981 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 3981 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 3355.056948 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 3355.056761 # Cycle average of tags in use
system.cpu.l2cache.total_refs 510 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 510 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 567123959000 # number of cpu cycles simulated system.cpu.numCycles 567124013000 # number of cpu cycles simulated
system.cpu.num_insts 398664611 # Number of instructions executed system.cpu.num_insts 398664609 # Number of instructions executed
system.cpu.num_refs 174183401 # Number of memory references system.cpu.num_refs 174183455 # Number of memory references
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

18
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -11,12 +11,14 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
children=workload children=dtb itb tracer workload
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false defer_registration=false
dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -25,11 +27,23 @@ phase=0
progress_interval=0 progress_interval=0
simulate_stalls=false simulate_stalls=false
system=system system=system
tracer=system.cpu.tracer
width=1 width=1
workload=system.cpu.workload workload=system.cpu.workload
dcache_port=system.membus.port[2] dcache_port=system.membus.port[2]
icache_port=system.membus.port[1] icache_port=system.membus.port[1]
[system.cpu.dtb]
type=AlphaDTB
size=64
[system.cpu.itb]
type=AlphaITB
size=48
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload] [system.cpu.workload]
type=LiveProcess type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl cmd=perlbmk -I. -I lib lgred.makerand.pl
@ -53,7 +67,7 @@ bus_id=0
clock=1000 clock=1000
responder_set=false responder_set=false
width=64 width=64
port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem] [system.physmem]
type=PhysicalMemory type=PhysicalMemory

36
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt
View file

@ -1,18 +1,34 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 855891 # Simulator instruction rate (inst/s) host_inst_rate 2579952 # Simulator instruction rate (inst/s)
host_mem_usage 151228 # Number of bytes of host memory used host_mem_usage 180972 # Number of bytes of host memory used
host_seconds 2347.25 # Real time elapsed on the host host_seconds 778.69 # Real time elapsed on the host
host_tick_rate 427945543 # Simulator tick rate (ticks/s) host_tick_rate 1290253991 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2008987607 # Number of instructions simulated sim_insts 2008987605 # Number of instructions simulated
sim_seconds 1.004494 # Number of seconds simulated sim_seconds 1.004711 # Number of seconds simulated
sim_ticks 1004493803000 # Number of ticks simulated sim_ticks 1004710587000 # Number of ticks simulated
system.cpu.dtb.accesses 722298387 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.dtb.hits 721864922 # DTB hits
system.cpu.dtb.misses 433465 # DTB misses
system.cpu.dtb.read_accesses 511488910 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 511070026 # DTB read hits
system.cpu.dtb.read_misses 418884 # DTB read misses
system.cpu.dtb.write_accesses 210809477 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 210794896 # DTB write hits
system.cpu.dtb.write_misses 14581 # DTB write misses
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 2009421175 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 2009421070 # ITB hits
system.cpu.itb.misses 105 # ITB misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 2008987607 # number of cpu cycles simulated system.cpu.numCycles 2009421175 # number of cpu cycles simulated
system.cpu.num_insts 2008987607 # Number of instructions executed system.cpu.num_insts 2008987605 # Number of instructions executed
system.cpu.num_refs 722390435 # Number of memory references system.cpu.num_refs 722823898 # Number of memory references
system.cpu.workload.PROG:num_syscalls 39 # Number of system calls system.cpu.workload.PROG:num_syscalls 39 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

12
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
View file

@ -11,12 +11,14 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=TimingSimpleCPU type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus tracer workload children=dcache dtb icache itb l2cache toL2Bus tracer workload
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false defer_registration=false
dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -65,6 +67,10 @@ write_buffers=8
cpu_side=system.cpu.dcache_port cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1] mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=AlphaDTB
size=64
[system.cpu.icache] [system.cpu.icache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615
@ -101,6 +107,10 @@ write_buffers=8
cpu_side=system.cpu.icache_port cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0] mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=AlphaITB
size=48
[system.cpu.l2cache] [system.cpu.l2cache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615

60
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 1536320 # Simulator instruction rate (inst/s) host_inst_rate 1524477 # Simulator instruction rate (inst/s)
host_mem_usage 206288 # Number of bytes of host memory used host_mem_usage 188336 # Number of bytes of host memory used
host_seconds 1307.66 # Real time elapsed on the host host_seconds 1317.82 # Real time elapsed on the host
host_tick_rate 2116487900 # Simulator tick rate (ticks/s) host_tick_rate 2100501698 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2008987607 # Number of instructions simulated sim_insts 2008987605 # Number of instructions simulated
sim_seconds 2.767652 # Number of seconds simulated sim_seconds 2.768086 # Number of seconds simulated
sim_ticks 2767652365000 # Number of ticks simulated sim_ticks 2768085828000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 24898.959808 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency 24898.959808 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22898.959808 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22898.959808 # average ReadReq mshr miss latency
@ -76,14 +76,26 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 1526048 # number of replacements system.cpu.dcache.replacements 1526048 # number of replacements
system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4095.361611 # Cycle average of tags in use system.cpu.dcache.tagsinuse 4095.361643 # Cycle average of tags in use
system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks. system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 795826000 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 795905000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 74589 # number of writebacks system.cpu.dcache.writebacks 74589 # number of writebacks
system.cpu.icache.ReadReq_accesses 2008987608 # number of ReadReq accesses(hits+misses) system.cpu.dtb.accesses 722298387 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.dtb.hits 721864922 # DTB hits
system.cpu.dtb.misses 433465 # DTB misses
system.cpu.dtb.read_accesses 511488910 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 511070026 # DTB read hits
system.cpu.dtb.read_misses 418884 # DTB read misses
system.cpu.dtb.write_accesses 210809477 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 210794896 # DTB write hits
system.cpu.dtb.write_misses 14581 # DTB write misses
system.cpu.icache.ReadReq_accesses 2009421071 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 15691.959230 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 15691.959230 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 13691.959230 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 13691.959230 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 2008977012 # number of ReadReq hits system.cpu.icache.ReadReq_hits 2009410475 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 166272000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency 166272000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 10596 # number of ReadReq misses system.cpu.icache.ReadReq_misses 10596 # number of ReadReq misses
@ -92,16 +104,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # ms
system.cpu.icache.ReadReq_mshr_misses 10596 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses 10596 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 189597.679502 # Average number of references to valid blocks. system.cpu.icache.avg_refs 189638.587675 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 2008987608 # number of demand (read+write) accesses system.cpu.icache.demand_accesses 2009421071 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 15691.959230 # average overall miss latency system.cpu.icache.demand_avg_miss_latency 15691.959230 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 13691.959230 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 13691.959230 # average overall mshr miss latency
system.cpu.icache.demand_hits 2008977012 # number of demand (read+write) hits system.cpu.icache.demand_hits 2009410475 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 166272000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency 166272000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses
system.cpu.icache.demand_misses 10596 # number of demand (read+write) misses system.cpu.icache.demand_misses 10596 # number of demand (read+write) misses
@ -112,11 +124,11 @@ system.cpu.icache.demand_mshr_misses 10596 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 2008987608 # number of overall (read+write) accesses system.cpu.icache.overall_accesses 2009421071 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 15691.959230 # average overall miss latency system.cpu.icache.overall_avg_miss_latency 15691.959230 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 13691.959230 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 13691.959230 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 2008977012 # number of overall hits system.cpu.icache.overall_hits 2009410475 # number of overall hits
system.cpu.icache.overall_miss_latency 166272000 # number of overall miss cycles system.cpu.icache.overall_miss_latency 166272000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses
system.cpu.icache.overall_misses 10596 # number of overall misses system.cpu.icache.overall_misses 10596 # number of overall misses
@ -138,11 +150,15 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 9046 # number of replacements system.cpu.icache.replacements 9046 # number of replacements
system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1478.559322 # Cycle average of tags in use system.cpu.icache.tagsinuse 1478.559335 # Cycle average of tags in use
system.cpu.icache.total_refs 2008977012 # Total number of references to valid blocks. system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 2009421176 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 2009421071 # ITB hits
system.cpu.itb.misses 105 # ITB misses
system.cpu.l2cache.ReadExReq_accesses 71952 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 71952 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
@ -224,14 +240,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 1412930 # number of replacements system.cpu.l2cache.replacements 1412930 # number of replacements
system.cpu.l2cache.sampled_refs 1445479 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 1445479 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 31165.183060 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 31165.186472 # Cycle average of tags in use
system.cpu.l2cache.total_refs 22612 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 22612 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 2767652365000 # number of cpu cycles simulated system.cpu.numCycles 2768085828000 # number of cpu cycles simulated
system.cpu.num_insts 2008987607 # Number of instructions executed system.cpu.num_insts 2008987605 # Number of instructions executed
system.cpu.num_refs 722390435 # Number of memory references system.cpu.num_refs 722823898 # Number of memory references
system.cpu.workload.PROG:num_syscalls 39 # Number of system calls system.cpu.workload.PROG:num_syscalls 39 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

12
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=DerivO3CPU type=DerivO3CPU
children=dcache fuPool icache l2cache toL2Bus tracer workload children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
BTBEntries=4096 BTBEntries=4096
BTBTagSize=16 BTBTagSize=16
LFSTSize=1024 LFSTSize=1024
@ -36,6 +36,7 @@ decodeToRenameDelay=1
decodeWidth=8 decodeWidth=8
defer_registration=false defer_registration=false
dispatchWidth=8 dispatchWidth=8
dtb=system.cpu.dtb
fetchToDecodeDelay=1 fetchToDecodeDelay=1
fetchTrapLatency=1 fetchTrapLatency=1
fetchWidth=8 fetchWidth=8
@ -53,6 +54,7 @@ iewToRenameDelay=1
instShiftAmt=2 instShiftAmt=2
issueToExecuteDelay=1 issueToExecuteDelay=1
issueWidth=8 issueWidth=8
itb=system.cpu.itb
localCtrBits=2 localCtrBits=2
localHistoryBits=11 localHistoryBits=11
localHistoryTableSize=2048 localHistoryTableSize=2048
@ -130,6 +132,10 @@ write_buffers=8
cpu_side=system.cpu.dcache_port cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1] mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=AlphaDTB
size=64
[system.cpu.fuPool] [system.cpu.fuPool]
type=FUPool type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
@ -303,6 +309,10 @@ write_buffers=8
cpu_side=system.cpu.icache_port cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0] mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=AlphaITB
size=48
[system.cpu.l2cache] [system.cpu.l2cache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615

588
tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt
View file

@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits 7542290 # Number of BTB hits global.BPredUnit.BTBHits 8001673 # Number of BTB hits
global.BPredUnit.BTBLookups 13308941 # Number of BTB lookups global.BPredUnit.BTBLookups 14256966 # Number of BTB lookups
global.BPredUnit.RASInCorrect 34250 # Number of incorrect RAS predictions. global.BPredUnit.RASInCorrect 35545 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 454073 # Number of conditional branches incorrect global.BPredUnit.condIncorrect 455902 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 9847799 # Number of conditional branches predicted global.BPredUnit.condPredicted 10551273 # Number of conditional branches predicted
global.BPredUnit.lookups 15155323 # Number of BP lookups global.BPredUnit.lookups 16246333 # Number of BP lookups
global.BPredUnit.usedRAS 1795531 # Number of times the RAS was used to get a target. global.BPredUnit.usedRAS 1941036 # Number of times the RAS was used to get a target.
host_inst_rate 196409 # Simulator instruction rate (inst/s) host_inst_rate 173213 # Simulator instruction rate (inst/s)
host_mem_usage 211144 # Number of bytes of host memory used host_mem_usage 193376 # Number of bytes of host memory used
host_seconds 405.24 # Real time elapsed on the host host_seconds 459.50 # Real time elapsed on the host
host_tick_rate 57107000 # Simulator tick rate (ticks/s) host_tick_rate 54150958 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 11563356 # Number of conflicting loads. memdepunit.memDep.conflictingLoads 12304370 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 10718994 # Number of conflicting stores. memdepunit.memDep.conflictingStores 10964244 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 21578903 # Number of loads inserted to the mem dependence unit. memdepunit.memDep.insertedLoads 22974359 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 15738647 # Number of stores inserted to the mem dependence unit. memdepunit.memDep.insertedStores 16298386 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 79591756 # Number of instructions simulated sim_insts 79591756 # Number of instructions simulated
sim_seconds 0.023142 # Number of seconds simulated sim_seconds 0.024882 # Number of seconds simulated
sim_ticks 23141799000 # Number of ticks simulated sim_ticks 24882469000 # Number of ticks simulated
system.cpu.commit.COM:branches 13754477 # Number of branches committed system.cpu.commit.COM:branches 13754477 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 3510282 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_lim_events 3430644 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 45393667 system.cpu.commit.COM:committed_per_cycle.samples 48501675
system.cpu.commit.COM:committed_per_cycle.min_value 0 system.cpu.commit.COM:committed_per_cycle.min_value 0
0 16854505 3712.96% 0 19715966 4065.01%
1 10816662 2382.86% 1 10943165 2256.24%
2 5010201 1103.72% 2 5093030 1050.07%
3 3353080 738.67% 3 3475751 716.62%
4 2515867 554.23% 4 2505421 516.56%
5 1511689 333.02% 5 1522534 313.91%
6 1009468 222.38% 6 1001460 206.48%
7 811913 178.86% 7 813704 167.77%
8 3510282 773.30% 8 3430644 707.32%
system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist system.cpu.commit.COM:committed_per_cycle.end_dist
@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 20379399 # Nu
system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 35224018 # Number of memory references committed system.cpu.commit.COM:refs 35224018 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 357583 # The number of times a branch was mispredicted system.cpu.commit.branchMispredicts 360143 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 5444219 # The number of squashed insts skipped by commit system.cpu.commit.commitSquashedInsts 8051078 # The number of squashed insts skipped by commit
system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedInsts 79591756 # Number of Instructions Simulated
system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
system.cpu.cpi 0.581499 # CPI: Cycles Per Instruction system.cpu.cpi 0.625230 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.581499 # CPI: Total CPI of All Threads system.cpu.cpi_total 0.625230 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses 44 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits 44 # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses 19849413 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses 20377695 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 15478.106634 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency 15251.726884 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4237.239017 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4211.460009 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 19787819 # number of ReadReq hits system.cpu.dcache.ReadReq_hits 20316168 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 953358500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency 938393000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.003103 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate 0.003019 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 61594 # number of ReadReq misses system.cpu.dcache.ReadReq_misses 61527 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 85223 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits 82932 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 260988500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency 259118500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003103 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate 0.003019 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 61594 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses 61527 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 13805554 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 13807431 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 30519.673214 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency 30521.435580 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5295.405245 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5307.053083 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 13655731 # number of WriteReq hits system.cpu.dcache.WriteReq_hits 13657610 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 4572549000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency 4572752000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.010852 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate 0.010851 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 149823 # number of WriteReq misses system.cpu.dcache.WriteReq_misses 149821 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 807823 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits 805946 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 793373500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency 795108000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010852 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.010851 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 149823 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 149821 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 163.116342 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 165.739033 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 33654967 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses 34185126 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 26137.479484 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency 26076.163484 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 4987.120241 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 4988.107292 # average overall mshr miss latency
system.cpu.dcache.demand_hits 33443550 # number of demand (read+write) hits system.cpu.dcache.demand_hits 33973778 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 5525907500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency 5511145000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.006282 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate 0.006182 # miss rate for demand accesses
system.cpu.dcache.demand_misses 211417 # number of demand (read+write) misses system.cpu.dcache.demand_misses 211348 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 893046 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits 888878 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 1054362000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency 1054226500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.006282 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate 0.006182 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 211417 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses 211348 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 33654967 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses 34185126 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 26137.479484 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency 26076.163484 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 4987.120241 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 4988.107292 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 33443550 # number of overall hits system.cpu.dcache.overall_hits 33973778 # number of overall hits
system.cpu.dcache.overall_miss_latency 5525907500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency 5511145000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.006282 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate 0.006182 # miss rate for overall accesses
system.cpu.dcache.overall_misses 211417 # number of overall misses system.cpu.dcache.overall_misses 211348 # number of overall misses
system.cpu.dcache.overall_mshr_hits 893046 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits 888878 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 1054362000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency 1054226500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.006282 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate 0.006182 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 211417 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses 211348 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -120,92 +120,104 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 200972 # number of replacements system.cpu.dcache.replacements 200926 # number of replacements
system.cpu.dcache.sampled_refs 205068 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 205022 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4079.963353 # Cycle average of tags in use system.cpu.dcache.tagsinuse 4080.923075 # Cycle average of tags in use
system.cpu.dcache.total_refs 33449942 # Total number of references to valid blocks. system.cpu.dcache.total_refs 33980148 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 119008000 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 120631000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 147761 # number of writebacks system.cpu.dcache.writebacks 147761 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 971695 # Number of cycles decode is blocked system.cpu.decode.DECODE:BlockedCycles 953936 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 97371 # Number of times decode detected a branch misprediction system.cpu.decode.DECODE:BranchMispred 96699 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 3417858 # Number of times decode resolved a branch system.cpu.decode.DECODE:BranchResolved 3650405 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 96162354 # Number of instructions handled by decode system.cpu.decode.DECODE:DecodedInsts 101647473 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 25952342 # Number of cycles decode is idle system.cpu.decode.DECODE:IdleCycles 27934130 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 18439987 # Number of cycles decode is running system.cpu.decode.DECODE:RunCycles 19589260 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 888885 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashCycles 1261472 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 288762 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:SquashedInsts 284553 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 29644 # Number of cycles decode is unblocking system.cpu.decode.DECODE:UnblockCycles 24350 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 15155323 # Number of branches that fetch encountered system.cpu.dtb.accesses 36627778 # DTB accesses
system.cpu.fetch.CacheLines 12535185 # Number of cache lines fetched system.cpu.dtb.acv 37 # DTB access violations
system.cpu.fetch.Cycles 31179449 # Number of cycles fetch has run and was not squashing or blocked system.cpu.dtb.hits 36455125 # DTB hits
system.cpu.fetch.IcacheSquashes 131701 # Number of outstanding Icache misses that were squashed system.cpu.dtb.misses 172653 # DTB misses
system.cpu.fetch.Insts 97686537 # Number of instructions fetch has processed system.cpu.dtb.read_accesses 21565019 # DTB read accesses
system.cpu.fetch.SquashCycles 470452 # Number of cycles fetch has spent squashing system.cpu.dtb.read_acv 35 # DTB read access violations
system.cpu.fetch.branchRate 0.327452 # Number of branch fetches per cycle system.cpu.dtb.read_hits 21407076 # DTB read hits
system.cpu.fetch.icacheStallCycles 12535185 # Number of cycles fetch is stalled on an Icache miss system.cpu.dtb.read_misses 157943 # DTB read misses
system.cpu.fetch.predictedBranches 9337821 # Number of branches that fetch has predicted taken system.cpu.dtb.write_accesses 15062759 # DTB write accesses
system.cpu.fetch.rate 2.110656 # Number of inst fetches per cycle system.cpu.dtb.write_acv 2 # DTB write access violations
system.cpu.dtb.write_hits 15048049 # DTB write hits
system.cpu.dtb.write_misses 14710 # DTB write misses
system.cpu.fetch.Branches 16246333 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 13375683 # Number of cache lines fetched
system.cpu.fetch.Cycles 33194597 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 152184 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 103251284 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 572846 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.326473 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 13375683 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 9942709 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.074854 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 46282553 system.cpu.fetch.rateDist.samples 49763148
system.cpu.fetch.rateDist.min_value 0 system.cpu.fetch.rateDist.min_value 0
0 27638291 5971.64% 0 29969634 6022.46%
1 1733920 374.64% 1 1857821 373.33%
2 1408099 304.24% 2 1524433 306.34%
3 1707036 368.83% 3 1786134 358.93%
4 3689148 797.09% 4 3977224 799.23%
5 1739866 375.92% 5 1866445 375.07%
6 655334 141.59% 6 698149 140.29%
7 1059487 228.92% 7 1110284 223.11%
8 6651372 1437.12% 8 6973024 1401.24%
system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 12534294 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses 13374854 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 4593.252212 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 4582.447586 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2552.911039 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 2544.287368 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 12448414 # number of ReadReq hits system.cpu.icache.ReadReq_hits 13289333 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 394468500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency 391895500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.006852 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate 0.006394 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 85880 # number of ReadReq misses system.cpu.icache.ReadReq_misses 85521 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 891 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits 829 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 219244000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency 217590000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.006852 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate 0.006394 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 85880 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses 85521 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 144.958009 # Average number of references to valid blocks. system.cpu.icache.avg_refs 155.392629 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 12534294 # number of demand (read+write) accesses system.cpu.icache.demand_accesses 13374854 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 4593.252212 # average overall miss latency system.cpu.icache.demand_avg_miss_latency 4582.447586 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 2552.911039 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 2544.287368 # average overall mshr miss latency
system.cpu.icache.demand_hits 12448414 # number of demand (read+write) hits system.cpu.icache.demand_hits 13289333 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 394468500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency 391895500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.006852 # miss rate for demand accesses system.cpu.icache.demand_miss_rate 0.006394 # miss rate for demand accesses
system.cpu.icache.demand_misses 85880 # number of demand (read+write) misses system.cpu.icache.demand_misses 85521 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 891 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits 829 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 219244000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency 217590000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.006852 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate 0.006394 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 85880 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses 85521 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 12534294 # number of overall (read+write) accesses system.cpu.icache.overall_accesses 13374854 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 4593.252212 # average overall miss latency system.cpu.icache.overall_avg_miss_latency 4582.447586 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 2552.911039 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 2544.287368 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 12448414 # number of overall hits system.cpu.icache.overall_hits 13289333 # number of overall hits
system.cpu.icache.overall_miss_latency 394468500 # number of overall miss cycles system.cpu.icache.overall_miss_latency 391895500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.006852 # miss rate for overall accesses system.cpu.icache.overall_miss_rate 0.006394 # miss rate for overall accesses
system.cpu.icache.overall_misses 85880 # number of overall misses system.cpu.icache.overall_misses 85521 # number of overall misses
system.cpu.icache.overall_mshr_hits 891 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits 829 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 219244000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency 217590000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.006852 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate 0.006394 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 85880 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses 85521 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -217,80 +229,80 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 83828 # number of replacements system.cpu.icache.replacements 83473 # number of replacements
system.cpu.icache.sampled_refs 85876 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 85521 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1919.939531 # Cycle average of tags in use system.cpu.icache.tagsinuse 1922.769682 # Cycle average of tags in use
system.cpu.icache.total_refs 12448414 # Total number of references to valid blocks. system.cpu.icache.total_refs 13289333 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 20180672000 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 21643859000 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 779486 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.idleCycles 1231826 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 14215317 # Number of branches executed system.cpu.iew.EXEC:branches 14739683 # Number of branches executed
system.cpu.iew.EXEC:nop 9054056 # number of nop insts executed system.cpu.iew.EXEC:nop 9380523 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.776804 # Inst execution rate system.cpu.iew.EXEC:rate 1.704450 # Inst execution rate
system.cpu.iew.EXEC:refs 36085022 # number of memory reference insts executed system.cpu.iew.EXEC:refs 36969776 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 15098216 # Number of stores executed system.cpu.iew.EXEC:stores 15295559 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 41423091 # num instructions consuming a value system.cpu.iew.WB:consumers 42405904 # num instructions consuming a value
system.cpu.iew.WB:count 81970056 # cumulative count of insts written-back system.cpu.iew.WB:count 84333016 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.763712 # average fanout of values written-back system.cpu.iew.WB:fanout 0.765386 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 31635305 # num instructions producing a value system.cpu.iew.WB:producers 32456867 # num instructions producing a value
system.cpu.iew.WB:rate 1.771079 # insts written-back per cycle system.cpu.iew.WB:rate 1.694688 # insts written-back per cycle
system.cpu.iew.WB:sent 82027383 # cumulative count of insts sent to commit system.cpu.iew.WB:sent 84566644 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 388269 # Number of branch mispredicts detected at execute system.cpu.iew.branchMispredicts 400717 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 17461 # Number of cycles IEW is blocking system.cpu.iew.iewBlockCycles 20492 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 21578903 # Number of dispatched load instructions system.cpu.iew.iewDispLoadInsts 22974359 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 4692 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispNonSpecInsts 4987 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 341214 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispSquashedInsts 359590 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 15738647 # Number of dispatched store instructions system.cpu.iew.iewDispStoreInsts 16298386 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 93782111 # Number of instructions dispatched to IQ system.cpu.iew.iewDispatchedInsts 98827714 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 20986806 # Number of load instructions executed system.cpu.iew.iewExecLoadInsts 21674217 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 455724 # Number of squashed instructions skipped in execute system.cpu.iew.iewExecSquashedInsts 545926 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 82235016 # Number of executed instructions system.cpu.iew.iewExecutedInsts 84818805 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 2252 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIQFullEvents 2571 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 122 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 174 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 888885 # Number of cycles IEW is squashing system.cpu.iew.iewSquashCycles 1261472 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 3197 # Number of cycles IEW is unblocking system.cpu.iew.iewUnblockCycles 3172 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 937737 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.forwLoads 945093 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 950 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.ignoredResponses 1085 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 19015 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.memOrderViolation 19531 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1226 # Number of loads that were rescheduled system.cpu.iew.lsq.thread.0.rescheduledLoads 1312 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 1199504 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedLoads 2594960 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 894028 # Number of stores squashed system.cpu.iew.lsq.thread.0.squashedStores 1453767 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 19015 # Number of memory order violations system.cpu.iew.memOrderViolationEvents 19531 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 105591 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 108348 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 282678 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedTakenIncorrect 292369 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.719692 # IPC: Instructions Per Cycle system.cpu.ipc 1.599412 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.719692 # IPC: Total IPC of All Threads system.cpu.ipc_total 1.599412 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 82690740 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0 85364731 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 0 0.00% # Type of FU issued No_OpClass 0 0.00% # Type of FU issued
IntAlu 46107608 55.76% # Type of FU issued IntAlu 47879047 56.09% # Type of FU issued
IntMult 43061 0.05% # Type of FU issued IntMult 43747 0.05% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued
FloatAdd 119602 0.14% # Type of FU issued FloatAdd 121378 0.14% # Type of FU issued
FloatCmp 87 0.00% # Type of FU issued FloatCmp 86 0.00% # Type of FU issued
FloatCvt 120853 0.15% # Type of FU issued FloatCvt 121979 0.14% # Type of FU issued
FloatMult 50 0.00% # Type of FU issued FloatMult 50 0.00% # Type of FU issued
FloatDiv 37774 0.05% # Type of FU issued FloatDiv 38527 0.05% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued
MemRead 21079728 25.49% # Type of FU issued MemRead 21782176 25.52% # Type of FU issued
MemWrite 15181977 18.36% # Type of FU issued MemWrite 15377741 18.01% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 974009 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_cnt 969096 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.011779 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_busy_rate 0.011352 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available No_OpClass 0 0.00% # attempts to use FU when none available
IntAlu 90058 9.25% # attempts to use FU when none available IntAlu 95806 9.89% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available
@ -299,62 +311,66 @@ system.cpu.iq.ISSUE:fu_full.start_dist
FloatMult 0 0.00% # attempts to use FU when none available FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available
MemRead 437339 44.90% # attempts to use FU when none available MemRead 442018 45.61% # attempts to use FU when none available
MemWrite 446612 45.85% # attempts to use FU when none available MemWrite 431272 44.50% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples 46282553 system.cpu.iq.ISSUE:issued_per_cycle.samples 49763148
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 12550048 2711.62% 0 14890253 2992.22%
1 12875827 2782.00% 1 13307982 2674.26%
2 7785024 1682.06% 2 8090593 1625.82%
3 4673558 1009.79% 3 4789845 962.53%
4 4500672 972.43% 4 4747984 954.12%
5 2074677 448.26% 5 2061711 414.30%
6 1137561 245.79% 6 1164817 234.07%
7 458736 99.12% 7 463069 93.05%
8 226450 48.93% 8 246894 49.61%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 1.786650 # Inst issue rate system.cpu.iq.ISSUE:rate 1.715421 # Inst issue rate
system.cpu.iq.iqInstsAdded 84723363 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsAdded 89442204 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 82690740 # Number of instructions issued system.cpu.iq.iqInstsIssued 85364731 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 4692 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqNonSpecInstsAdded 4987 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 4940751 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsExamined 9646731 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 53730 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsIssued 49535 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 109 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedNonSpecRemoved 404 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 3594449 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedOperandsExamined 6611614 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 143476 # number of ReadExReq accesses(hits+misses) system.cpu.itb.accesses 13401083 # ITB accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency 4086.446514 # average ReadExReq miss latency system.cpu.itb.acv 0 # ITB acv
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2086.446514 # average ReadExReq mshr miss latency system.cpu.itb.hits 13375683 # ITB hits
system.cpu.l2cache.ReadExReq_miss_latency 586307000 # number of ReadExReq miss cycles system.cpu.itb.misses 25400 # ITB misses
system.cpu.l2cache.ReadExReq_accesses 143495 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 4092.480574 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2092.480574 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 587250500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 143476 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses 143495 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 299355000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency 300260500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 143476 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 143495 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 147467 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses 147048 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 4144.894478 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency 4140.515824 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2144.894478 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2140.515824 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 98804 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits 98388 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 201703000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency 201477500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.329992 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate 0.330912 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 48663 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses 48660 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 104377000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency 104157500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.329992 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate 0.330912 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 48663 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses 48660 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 6368 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses 6344 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4226.366206 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency 4240.542245 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2231.626884 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2242.591425 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 26913500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency 26902000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 6368 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses 6344 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14211000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14227000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 6368 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses 6344 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 147761 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 147761 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 147761 # number of Writeback misses system.cpu.l2cache.Writeback_misses 147761 # number of Writeback misses
@ -362,38 +378,38 @@ system.cpu.l2cache.Writeback_mshr_miss_rate 1 #
system.cpu.l2cache.Writeback_mshr_misses 147761 # number of Writeback MSHR misses system.cpu.l2cache.Writeback_mshr_misses 147761 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 2.459748 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 2.449354 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 290943 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses 290543 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 4101.249616 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency 4104.644688 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2101.249616 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 2104.644688 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 98804 # number of demand (read+write) hits system.cpu.l2cache.demand_hits 98388 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 788010000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency 788728000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.660401 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate 0.661365 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 192139 # number of demand (read+write) misses system.cpu.l2cache.demand_misses 192155 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 403732000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 404418000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.660401 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate 0.661365 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 192139 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses 192155 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 290943 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses 290543 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 4101.249616 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency 4104.644688 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2101.249616 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 2104.644688 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 98804 # number of overall hits system.cpu.l2cache.overall_hits 98388 # number of overall hits
system.cpu.l2cache.overall_miss_latency 788010000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency 788728000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.660401 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate 0.661365 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 192139 # number of overall misses system.cpu.l2cache.overall_misses 192155 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 403732000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency 404418000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.660401 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate 0.661365 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 192139 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses 192155 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -405,31 +421,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 25941 # number of replacements system.cpu.l2cache.replacements 25943 # number of replacements
system.cpu.l2cache.sampled_refs 41849 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 41849 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 4585.524484 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 4581.530519 # Cycle average of tags in use
system.cpu.l2cache.total_refs 102938 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 102503 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.numCycles 46282553 # number of cpu cycles simulated system.cpu.numCycles 49763148 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 249890 # Number of cycles rename is blocking system.cpu.rename.RENAME:BlockCycles 263435 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 36341 # Number of times rename has blocked due to IQ full system.cpu.rename.RENAME:IQFullEvents 34724 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 26244762 # Number of cycles rename is idle system.cpu.rename.RENAME:IdleCycles 28245765 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 565515 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:LSQFullEvents 545942 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 115161809 # Number of register rename lookups that rename has made system.cpu.rename.RENAME:RenameLookups 121486902 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 95469817 # Number of instructions processed by rename system.cpu.rename.RENAME:RenamedInsts 100840274 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 57208765 # Number of destination operands rename has renamed system.cpu.rename.RENAME:RenamedOperands 60680951 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 18176186 # Number of cycles rename is running system.cpu.rename.RENAME:RunCycles 19296581 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 888885 # Number of cycles rename is squashing system.cpu.rename.RENAME:SquashCycles 1261472 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 649163 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UnblockCycles 621968 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 4661884 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:UndoneMaps 8134070 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 73667 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializeStallCycles 73927 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 4695 # count of serializing insts renamed system.cpu.rename.RENAME:serializingInsts 5255 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 1420326 # count of insts added to the skid buffer system.cpu.rename.RENAME:skidInsts 1395173 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 4693 # count of temporary serializing insts renamed system.cpu.rename.RENAME:tempSerializingInsts 5253 # count of temporary serializing insts renamed
system.cpu.timesIdled 518 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 678 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

18
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -11,12 +11,14 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
children=workload children=dtb itb tracer workload
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false defer_registration=false
dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -25,11 +27,23 @@ phase=0
progress_interval=0 progress_interval=0
simulate_stalls=false simulate_stalls=false
system=system system=system
tracer=system.cpu.tracer
width=1 width=1
workload=system.cpu.workload workload=system.cpu.workload
dcache_port=system.membus.port[2] dcache_port=system.membus.port[2]
icache_port=system.membus.port[1] icache_port=system.membus.port[1]
[system.cpu.dtb]
type=AlphaDTB
size=64
[system.cpu.itb]
type=AlphaITB
size=48
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload] [system.cpu.workload]
type=LiveProcess type=LiveProcess
cmd=vortex lendian.raw cmd=vortex lendian.raw
@ -53,7 +67,7 @@ bus_id=0
clock=1000 clock=1000
responder_set=false responder_set=false
width=64 width=64
port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem] [system.physmem]
type=PhysicalMemory type=PhysicalMemory

36
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt
View file

@ -1,18 +1,34 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 840697 # Simulator instruction rate (inst/s) host_inst_rate 2496642 # Simulator instruction rate (inst/s)
host_mem_usage 152968 # Number of bytes of host memory used host_mem_usage 184388 # Number of bytes of host memory used
host_seconds 105.08 # Real time elapsed on the host host_seconds 35.38 # Real time elapsed on the host
host_tick_rate 420346781 # Simulator tick rate (ticks/s) host_tick_rate 1249741953 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340674 # Number of instructions simulated sim_insts 88340673 # Number of instructions simulated
sim_seconds 0.044170 # Number of seconds simulated sim_seconds 0.044221 # Number of seconds simulated
sim_ticks 44170336500 # Number of ticks simulated sim_ticks 44221003000 # Number of ticks simulated
system.cpu.dtb.accesses 34987415 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.dtb.hits 34890015 # DTB hits
system.cpu.dtb.misses 97400 # DTB misses
system.cpu.dtb.read_accesses 20366786 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 20276638 # DTB read hits
system.cpu.dtb.read_misses 90148 # DTB read misses
system.cpu.dtb.write_accesses 14620629 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 14613377 # DTB write hits
system.cpu.dtb.write_misses 7252 # DTB write misses
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 88442007 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 88438073 # ITB hits
system.cpu.itb.misses 3934 # ITB misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 88340674 # number of cpu cycles simulated system.cpu.numCycles 88442007 # number of cpu cycles simulated
system.cpu.num_insts 88340674 # Number of instructions executed system.cpu.num_insts 88340673 # Number of instructions executed
system.cpu.num_refs 35224019 # Number of memory references system.cpu.num_refs 35321418 # Number of memory references
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

2
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg
View file

@ -134,7 +134,7 @@
DB Handle Chunk's StackPtr = 20797 DB Handle Chunk's StackPtr = 20797
DB[ 1] LOADED; Handles= 20797 DB[ 1] LOADED; Handles= 20797
KERNEL in CORE[ 1] Restored @ 40054800 KERNEL in CORE[ 1] Restored @ 4005c800
OPEN File ./input/lendian.wnv OPEN File ./input/lendian.wnv
*Status = 0 *Status = 0

12
tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
View file

@ -11,12 +11,14 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=TimingSimpleCPU type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus tracer workload children=dcache dtb icache itb l2cache toL2Bus tracer workload
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false defer_registration=false
dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -65,6 +67,10 @@ write_buffers=8
cpu_side=system.cpu.dcache_port cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1] mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=AlphaDTB
size=64
[system.cpu.icache] [system.cpu.icache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615
@ -101,6 +107,10 @@ write_buffers=8
cpu_side=system.cpu.icache_port cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0] mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=AlphaITB
size=48
[system.cpu.l2cache] [system.cpu.l2cache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615

72
tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 1495977 # Simulator instruction rate (inst/s) host_inst_rate 1453070 # Simulator instruction rate (inst/s)
host_mem_usage 209700 # Number of bytes of host memory used host_mem_usage 191752 # Number of bytes of host memory used
host_seconds 59.05 # Real time elapsed on the host host_seconds 60.80 # Real time elapsed on the host
host_tick_rate 2185213288 # Simulator tick rate (ticks/s) host_tick_rate 2124138006 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340674 # Number of instructions simulated sim_insts 88340673 # Number of instructions simulated
sim_seconds 0.129042 # Number of seconds simulated sim_seconds 0.129140 # Number of seconds simulated
sim_ticks 129042205000 # Number of ticks simulated sim_ticks 129139604000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 20958.331276 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency 20958.331276 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18958.331276 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18958.331276 # average ReadReq mshr miss latency
@ -76,53 +76,65 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 200247 # number of replacements system.cpu.dcache.replacements 200247 # number of replacements
system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4080.920336 # Cycle average of tags in use system.cpu.dcache.tagsinuse 4080.930479 # Cycle average of tags in use
system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks. system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 737102000 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 737173000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 147714 # number of writebacks system.cpu.dcache.writebacks 147714 # number of writebacks
system.cpu.icache.ReadReq_accesses 88340675 # number of ReadReq accesses(hits+misses) system.cpu.dtb.accesses 34987415 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.dtb.hits 34890015 # DTB hits
system.cpu.dtb.misses 97400 # DTB misses
system.cpu.dtb.read_accesses 20366786 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 20276638 # DTB read hits
system.cpu.dtb.read_misses 90148 # DTB read misses
system.cpu.dtb.write_accesses 14620629 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 14613377 # DTB write hits
system.cpu.dtb.write_misses 7252 # DTB write misses
system.cpu.icache.ReadReq_accesses 88438074 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 14131.456382 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 14131.456382 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12131.456382 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 12131.456382 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 88264239 # number of ReadReq hits system.cpu.icache.ReadReq_hits 88361638 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 1080152000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency 1080152000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000865 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate 0.000864 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 927280000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency 927280000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000865 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate 0.000864 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 1154.746965 # Average number of references to valid blocks. system.cpu.icache.avg_refs 1156.021220 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 88340675 # number of demand (read+write) accesses system.cpu.icache.demand_accesses 88438074 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 14131.456382 # average overall miss latency system.cpu.icache.demand_avg_miss_latency 14131.456382 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 12131.456382 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 12131.456382 # average overall mshr miss latency
system.cpu.icache.demand_hits 88264239 # number of demand (read+write) hits system.cpu.icache.demand_hits 88361638 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 1080152000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency 1080152000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000865 # miss rate for demand accesses system.cpu.icache.demand_miss_rate 0.000864 # miss rate for demand accesses
system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 927280000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency 927280000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000865 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate 0.000864 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 88340675 # number of overall (read+write) accesses system.cpu.icache.overall_accesses 88438074 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 14131.456382 # average overall miss latency system.cpu.icache.overall_avg_miss_latency 14131.456382 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 12131.456382 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 12131.456382 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 88264239 # number of overall hits system.cpu.icache.overall_hits 88361638 # number of overall hits
system.cpu.icache.overall_miss_latency 1080152000 # number of overall miss cycles system.cpu.icache.overall_miss_latency 1080152000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000865 # miss rate for overall accesses system.cpu.icache.overall_miss_rate 0.000864 # miss rate for overall accesses
system.cpu.icache.overall_misses 76436 # number of overall misses system.cpu.icache.overall_misses 76436 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 927280000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency 927280000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000865 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate 0.000864 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
@ -138,11 +150,15 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 74391 # number of replacements system.cpu.icache.replacements 74391 # number of replacements
system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1876.903920 # Cycle average of tags in use system.cpu.icache.tagsinuse 1876.941758 # Cycle average of tags in use
system.cpu.icache.total_refs 88264239 # Total number of references to valid blocks. system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 88442008 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 88438074 # ITB hits
system.cpu.itb.misses 3934 # ITB misses
system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
@ -224,14 +240,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 24953 # number of replacements system.cpu.l2cache.replacements 24953 # number of replacements
system.cpu.l2cache.sampled_refs 40841 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 40841 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 4393.051484 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 4393.054480 # Cycle average of tags in use
system.cpu.l2cache.total_refs 93692 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 93692 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 129042205000 # number of cpu cycles simulated system.cpu.numCycles 129139604000 # number of cpu cycles simulated
system.cpu.num_insts 88340674 # Number of instructions executed system.cpu.num_insts 88340673 # Number of instructions executed
system.cpu.num_refs 35224019 # Number of memory references system.cpu.num_refs 35321418 # Number of memory references
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

18
tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
View file

@ -11,12 +11,14 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
children=workload children=dtb itb tracer workload
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false defer_registration=false
dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -25,11 +27,23 @@ phase=0
progress_interval=0 progress_interval=0
simulate_stalls=false simulate_stalls=false
system=system system=system
tracer=system.cpu.tracer
width=1 width=1
workload=system.cpu.workload workload=system.cpu.workload
dcache_port=system.membus.port[2] dcache_port=system.membus.port[2]
icache_port=system.membus.port[1] icache_port=system.membus.port[1]
[system.cpu.dtb]
type=SparcDTB
size=64
[system.cpu.itb]
type=SparcITB
size=64
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload] [system.cpu.workload]
type=LiveProcess type=LiveProcess
cmd=vortex bendian.raw cmd=vortex bendian.raw
@ -53,7 +67,7 @@ bus_id=0
clock=1000 clock=1000
responder_set=false responder_set=false
width=64 width=64
port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem] [system.physmem]
type=PhysicalMemory type=PhysicalMemory

20
tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt
View file

@ -1,18 +1,18 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 672762 # Simulator instruction rate (inst/s) host_inst_rate 1682182 # Simulator instruction rate (inst/s)
host_mem_usage 151516 # Number of bytes of host memory used host_mem_usage 185356 # Number of bytes of host memory used
host_seconds 202.52 # Real time elapsed on the host host_seconds 80.93 # Real time elapsed on the host
host_tick_rate 336380340 # Simulator tick rate (ticks/s) host_tick_rate 842064489 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 136246936 # Number of instructions simulated sim_insts 136141055 # Number of instructions simulated
sim_seconds 0.068123 # Number of seconds simulated sim_seconds 0.068150 # Number of seconds simulated
sim_ticks 68123467500 # Number of ticks simulated sim_ticks 68149604500 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 136246936 # number of cpu cycles simulated system.cpu.numCycles 136299210 # number of cpu cycles simulated
system.cpu.num_insts 136246936 # Number of instructions executed system.cpu.num_insts 136141055 # Number of instructions executed
system.cpu.num_refs 58111522 # Number of memory references system.cpu.num_refs 58160249 # Number of memory references
system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

8
tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled May 15 2007 13:02:31 M5 compiled Aug 14 2007 22:48:17
M5 started Tue May 15 16:40:43 2007 M5 started Tue Aug 14 23:33:10 2007
M5 executing on zizzer.eecs.umich.edu M5 executing on nacho
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic tests/run.py long/50.vortex/sparc/linux/simple-atomic command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic tests/run.py long/50.vortex/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
Exiting @ tick 68123467500 because target called exit() Exiting @ tick 68149604500 because target called exit()

12
tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
View file

@ -11,12 +11,14 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=TimingSimpleCPU type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus tracer workload children=dcache dtb icache itb l2cache toL2Bus tracer workload
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false defer_registration=false
dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -65,6 +67,10 @@ write_buffers=8
cpu_side=system.cpu.dcache_port cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1] mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=SparcDTB
size=64
[system.cpu.icache] [system.cpu.icache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615
@ -101,6 +107,10 @@ write_buffers=8
cpu_side=system.cpu.icache_port cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0] mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=SparcITB
size=64
[system.cpu.l2cache] [system.cpu.l2cache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615

58
tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 1128502 # Simulator instruction rate (inst/s) host_inst_rate 960220 # Simulator instruction rate (inst/s)
host_mem_usage 210664 # Number of bytes of host memory used host_mem_usage 192724 # Number of bytes of host memory used
host_seconds 120.73 # Real time elapsed on the host host_seconds 141.78 # Real time elapsed on the host
host_tick_rate 1658768570 # Simulator tick rate (ticks/s) host_tick_rate 1412855280 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 136246936 # Number of instructions simulated sim_insts 136141055 # Number of instructions simulated
sim_seconds 0.200268 # Number of seconds simulated sim_seconds 0.200317 # Number of seconds simulated
sim_ticks 200267857000 # Number of ticks simulated sim_ticks 200316584000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 21199.169030 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency 21199.169030 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19199.169030 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19199.169030 # average ReadReq mshr miss latency
@ -86,53 +86,53 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 146582 # number of replacements system.cpu.dcache.replacements 146582 # number of replacements
system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4089.106244 # Cycle average of tags in use system.cpu.dcache.tagsinuse 4089.107113 # Cycle average of tags in use
system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks. system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 584597000 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 584680000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 107279 # number of writebacks system.cpu.dcache.writebacks 107279 # number of writebacks
system.cpu.icache.ReadReq_accesses 136246937 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses 136295664 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 13638.549063 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 13638.549063 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11638.549063 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 11638.549063 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 136059913 # number of ReadReq hits system.cpu.icache.ReadReq_hits 136108640 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 2550736000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency 2550736000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.001373 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate 0.001372 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 2176688000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency 2176688000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.001373 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate 0.001372 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 727.499749 # Average number of references to valid blocks. system.cpu.icache.avg_refs 727.760287 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 136246937 # number of demand (read+write) accesses system.cpu.icache.demand_accesses 136295664 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 13638.549063 # average overall miss latency system.cpu.icache.demand_avg_miss_latency 13638.549063 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11638.549063 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 11638.549063 # average overall mshr miss latency
system.cpu.icache.demand_hits 136059913 # number of demand (read+write) hits system.cpu.icache.demand_hits 136108640 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 2550736000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency 2550736000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.001373 # miss rate for demand accesses system.cpu.icache.demand_miss_rate 0.001372 # miss rate for demand accesses
system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 2176688000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency 2176688000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.001373 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate 0.001372 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 136246937 # number of overall (read+write) accesses system.cpu.icache.overall_accesses 136295664 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 13638.549063 # average overall miss latency system.cpu.icache.overall_avg_miss_latency 13638.549063 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11638.549063 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 11638.549063 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 136059913 # number of overall hits system.cpu.icache.overall_hits 136108640 # number of overall hits
system.cpu.icache.overall_miss_latency 2550736000 # number of overall miss cycles system.cpu.icache.overall_miss_latency 2550736000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.001373 # miss rate for overall accesses system.cpu.icache.overall_miss_rate 0.001372 # miss rate for overall accesses
system.cpu.icache.overall_misses 187024 # number of overall misses system.cpu.icache.overall_misses 187024 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 2176688000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency 2176688000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.001373 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate 0.001372 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
@ -148,9 +148,9 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 184976 # number of replacements system.cpu.icache.replacements 184976 # number of replacements
system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 2006.859894 # Cycle average of tags in use system.cpu.icache.tagsinuse 2006.864278 # Cycle average of tags in use
system.cpu.icache.total_refs 136059913 # Total number of references to valid blocks. system.cpu.icache.total_refs 136108640 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 142624255000 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 142656863000 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadExReq_accesses 105189 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 105189 # number of ReadExReq accesses(hits+misses)
@ -234,14 +234,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 22010 # number of replacements system.cpu.l2cache.replacements 22010 # number of replacements
system.cpu.l2cache.sampled_refs 36485 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 36485 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 6146.860431 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 6146.948797 # Cycle average of tags in use
system.cpu.l2cache.total_refs 193951 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 193951 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 200267857000 # number of cpu cycles simulated system.cpu.numCycles 200316584000 # number of cpu cycles simulated
system.cpu.num_insts 136246936 # Number of instructions executed system.cpu.num_insts 136141055 # Number of instructions executed
system.cpu.num_refs 58111522 # Number of memory references system.cpu.num_refs 58160249 # Number of memory references
system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

8
tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Aug 12 2007 12:23:15 M5 compiled Aug 14 2007 22:48:17
M5 started Sun Aug 12 16:52:13 2007 M5 started Tue Aug 14 23:34:32 2007
M5 executing on zeep M5 executing on nacho
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing tests/run.py long/50.vortex/sparc/linux/simple-timing command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing tests/run.py long/50.vortex/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
Exiting @ tick 200267857000 because target called exit() Exiting @ tick 200316584000 because target called exit()

82
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=DerivO3CPU type=DerivO3CPU
children=dcache fuPool icache l2cache toL2Bus workload children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
BTBEntries=4096 BTBEntries=4096
BTBTagSize=16 BTBTagSize=16
LFSTSize=1024 LFSTSize=1024
@ -21,6 +21,7 @@ SQEntries=32
SSITSize=1024 SSITSize=1024
activity=0 activity=0
backComSize=5 backComSize=5
cachePorts=200
choiceCtrBits=2 choiceCtrBits=2
choicePredictorSize=8192 choicePredictorSize=8192
clock=500 clock=500
@ -35,6 +36,7 @@ decodeToRenameDelay=1
decodeWidth=8 decodeWidth=8
defer_registration=false defer_registration=false
dispatchWidth=8 dispatchWidth=8
dtb=system.cpu.dtb
fetchToDecodeDelay=1 fetchToDecodeDelay=1
fetchTrapLatency=1 fetchTrapLatency=1
fetchWidth=8 fetchWidth=8
@ -52,6 +54,7 @@ iewToRenameDelay=1
instShiftAmt=2 instShiftAmt=2
issueToExecuteDelay=1 issueToExecuteDelay=1
issueWidth=8 issueWidth=8
itb=system.cpu.itb
localCtrBits=2 localCtrBits=2
localHistoryBits=11 localHistoryBits=11
localHistoryTableSize=2048 localHistoryTableSize=2048
@ -74,8 +77,18 @@ renameToFetchDelay=1
renameToIEWDelay=2 renameToIEWDelay=2
renameToROBDelay=1 renameToROBDelay=1
renameWidth=8 renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8 squashWidth=8
system=system system=system
tracer=system.cpu.tracer
trapLatency=13 trapLatency=13
wbDepth=1 wbDepth=1
wbWidth=8 wbWidth=8
@ -85,21 +98,21 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache] [system.cpu.dcache]
type=BaseCache type=BaseCache
adaptive_compression=false addr_range=0:18446744073709551615
assoc=2 assoc=2
block_size=64 block_size=64
compressed_bus=false cpu_side_filter_ranges=
compression_latency=0
hash_delay=1 hash_delay=1
latency=1000 latency=1000
lifo=false lifo=false
max_miss_count=0 max_miss_count=0
mem_side_filter_ranges=
mshrs=10 mshrs=10
prefetch_access=false prefetch_access=false
prefetch_cache_check_push=true prefetch_cache_check_push=true
prefetch_data_accesses_only=false prefetch_data_accesses_only=false
prefetch_degree=1 prefetch_degree=1
prefetch_latency=10 prefetch_latency=10000
prefetch_miss=false prefetch_miss=false
prefetch_past_page=false prefetch_past_page=false
prefetch_policy=none prefetch_policy=none
@ -107,12 +120,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true prefetch_use_cpu_id=true
prefetcher_size=100 prefetcher_size=100
prioritizeRequests=false prioritizeRequests=false
protocol=Null
repl=Null repl=Null
size=262144 size=262144
split=false split=false
split_size=0 split_size=0
store_compressed=false
subblock_size=0 subblock_size=0
tgts_per_mshr=20 tgts_per_mshr=20
trace_addr=0 trace_addr=0
@ -121,6 +132,10 @@ write_buffers=8
cpu_side=system.cpu.dcache_port cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1] mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=AlphaDTB
size=64
[system.cpu.fuPool] [system.cpu.fuPool]
type=FUPool type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
@ -128,11 +143,11 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL
[system.cpu.fuPool.FUList0] [system.cpu.fuPool.FUList0]
type=FUDesc type=FUDesc
children=opList0 children=opList
count=6 count=6
opList=system.cpu.fuPool.FUList0.opList0 opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList0] [system.cpu.fuPool.FUList0.opList]
type=OpDesc type=OpDesc
issueLat=1 issueLat=1
opClass=IntAlu opClass=IntAlu
@ -206,11 +221,11 @@ opLat=24
[system.cpu.fuPool.FUList4] [system.cpu.fuPool.FUList4]
type=FUDesc type=FUDesc
children=opList0 children=opList
count=0 count=0
opList=system.cpu.fuPool.FUList4.opList0 opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList0] [system.cpu.fuPool.FUList4.opList]
type=OpDesc type=OpDesc
issueLat=1 issueLat=1
opClass=MemRead opClass=MemRead
@ -218,11 +233,11 @@ opLat=1
[system.cpu.fuPool.FUList5] [system.cpu.fuPool.FUList5]
type=FUDesc type=FUDesc
children=opList0 children=opList
count=0 count=0
opList=system.cpu.fuPool.FUList5.opList0 opList=system.cpu.fuPool.FUList5.opList
[system.cpu.fuPool.FUList5.opList0] [system.cpu.fuPool.FUList5.opList]
type=OpDesc type=OpDesc
issueLat=1 issueLat=1
opClass=MemWrite opClass=MemWrite
@ -248,11 +263,11 @@ opLat=1
[system.cpu.fuPool.FUList7] [system.cpu.fuPool.FUList7]
type=FUDesc type=FUDesc
children=opList0 children=opList
count=1 count=1
opList=system.cpu.fuPool.FUList7.opList0 opList=system.cpu.fuPool.FUList7.opList
[system.cpu.fuPool.FUList7.opList0] [system.cpu.fuPool.FUList7.opList]
type=OpDesc type=OpDesc
issueLat=3 issueLat=3
opClass=IprAccess opClass=IprAccess
@ -260,21 +275,21 @@ opLat=3
[system.cpu.icache] [system.cpu.icache]
type=BaseCache type=BaseCache
adaptive_compression=false addr_range=0:18446744073709551615
assoc=2 assoc=2
block_size=64 block_size=64
compressed_bus=false cpu_side_filter_ranges=
compression_latency=0
hash_delay=1 hash_delay=1
latency=1000 latency=1000
lifo=false lifo=false
max_miss_count=0 max_miss_count=0
mem_side_filter_ranges=
mshrs=10 mshrs=10
prefetch_access=false prefetch_access=false
prefetch_cache_check_push=true prefetch_cache_check_push=true
prefetch_data_accesses_only=false prefetch_data_accesses_only=false
prefetch_degree=1 prefetch_degree=1
prefetch_latency=10 prefetch_latency=10000
prefetch_miss=false prefetch_miss=false
prefetch_past_page=false prefetch_past_page=false
prefetch_policy=none prefetch_policy=none
@ -282,12 +297,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true prefetch_use_cpu_id=true
prefetcher_size=100 prefetcher_size=100
prioritizeRequests=false prioritizeRequests=false
protocol=Null
repl=Null repl=Null
size=131072 size=131072
split=false split=false
split_size=0 split_size=0
store_compressed=false
subblock_size=0 subblock_size=0
tgts_per_mshr=20 tgts_per_mshr=20
trace_addr=0 trace_addr=0
@ -296,23 +309,27 @@ write_buffers=8
cpu_side=system.cpu.icache_port cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0] mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=AlphaITB
size=48
[system.cpu.l2cache] [system.cpu.l2cache]
type=BaseCache type=BaseCache
adaptive_compression=false addr_range=0:18446744073709551615
assoc=2 assoc=2
block_size=64 block_size=64
compressed_bus=false cpu_side_filter_ranges=
compression_latency=0
hash_delay=1 hash_delay=1
latency=1000 latency=1000
lifo=false lifo=false
max_miss_count=0 max_miss_count=0
mem_side_filter_ranges=
mshrs=10 mshrs=10
prefetch_access=false prefetch_access=false
prefetch_cache_check_push=true prefetch_cache_check_push=true
prefetch_data_accesses_only=false prefetch_data_accesses_only=false
prefetch_degree=1 prefetch_degree=1
prefetch_latency=10 prefetch_latency=10000
prefetch_miss=false prefetch_miss=false
prefetch_past_page=false prefetch_past_page=false
prefetch_policy=none prefetch_policy=none
@ -320,12 +337,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true prefetch_use_cpu_id=true
prefetcher_size=100 prefetcher_size=100
prioritizeRequests=false prioritizeRequests=false
protocol=Null
repl=Null repl=Null
size=2097152 size=2097152
split=false split=false
split_size=0 split_size=0
store_compressed=false
subblock_size=0 subblock_size=0
tgts_per_mshr=5 tgts_per_mshr=5
trace_addr=0 trace_addr=0
@ -343,6 +358,9 @@ responder_set=false
width=64 width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload] [system.cpu.workload]
type=LiveProcess type=LiveProcess
cmd=bzip2 input.source 1 cmd=bzip2 input.source 1
@ -366,7 +384,7 @@ bus_id=0
clock=1000 clock=1000
responder_set=false responder_set=false
width=64 width=64
port=system.physmem.port system.cpu.l2cache.mem_side port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem] [system.physmem]
type=PhysicalMemory type=PhysicalMemory

607
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt
View file

@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits 236329759 # Number of BTB hits global.BPredUnit.BTBHits 295839321 # Number of BTB hits
global.BPredUnit.BTBLookups 244099867 # Number of BTB lookups global.BPredUnit.BTBLookups 304173613 # Number of BTB lookups
global.BPredUnit.RASInCorrect 116 # Number of incorrect RAS predictions. global.BPredUnit.RASInCorrect 120 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 19342549 # Number of conditional branches incorrect global.BPredUnit.condIncorrect 19407214 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 203388054 # Number of conditional branches predicted global.BPredUnit.condPredicted 254124044 # Number of conditional branches predicted
global.BPredUnit.lookups 265702680 # Number of BP lookups global.BPredUnit.lookups 329654644 # Number of BP lookups
global.BPredUnit.usedRAS 19620183 # Number of times the RAS was used to get a target. global.BPredUnit.usedRAS 23321143 # Number of times the RAS was used to get a target.
host_inst_rate 104740 # Simulator instruction rate (inst/s) host_inst_rate 153530 # Simulator instruction rate (inst/s)
host_mem_usage 154596 # Number of bytes of host memory used host_mem_usage 182552 # Number of bytes of host memory used
host_seconds 16574.74 # Real time elapsed on the host host_seconds 11307.49 # Real time elapsed on the host
host_tick_rate 38540500 # Simulator tick rate (ticks/s) host_tick_rate 57851122 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 53067106 # Number of conflicting loads. memdepunit.memDep.conflictingLoads 71970991 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 26767467 # Number of conflicting stores. memdepunit.memDep.conflictingStores 36581423 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 497279728 # Number of loads inserted to the mem dependence unit. memdepunit.memDep.insertedLoads 594992654 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 174034666 # Number of stores inserted to the mem dependence unit. memdepunit.memDep.insertedStores 221743675 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1736043781 # Number of instructions simulated sim_insts 1736043781 # Number of instructions simulated
sim_seconds 0.638799 # Number of seconds simulated sim_seconds 0.654151 # Number of seconds simulated
sim_ticks 638798750000 # Number of ticks simulated sim_ticks 654151113500 # Number of ticks simulated
system.cpu.commit.COM:branches 214632552 # Number of branches committed system.cpu.commit.COM:branches 214632552 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 60317471 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_lim_events 63247574 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 1240430038 system.cpu.commit.COM:committed_per_cycle.samples 1235798441
system.cpu.commit.COM:committed_per_cycle.min_value 0 system.cpu.commit.COM:committed_per_cycle.min_value 0
0 616961832 4973.77% 0 591538606 4786.69%
1 236071207 1903.14% 1 262725137 2125.95%
2 130159070 1049.31% 2 125553765 1015.97%
3 77572840 625.37% 3 79229995 641.12%
4 40072787 323.06% 4 49991526 404.53%
5 42334502 341.29% 5 29482834 238.57%
6 22413470 180.69% 6 23306420 188.59%
7 14526859 117.11% 7 10722584 86.77%
8 60317471 486.26% 8 63247574 511.80%
system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist system.cpu.commit.COM:committed_per_cycle.end_dist
@ -43,70 +43,80 @@ system.cpu.commit.COM:loads 445666361 # Nu
system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 606571343 # Number of memory references committed system.cpu.commit.COM:refs 606571343 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 19342064 # The number of times a branch was mispredicted system.cpu.commit.branchMispredicts 19406708 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 213160886 # The number of squashed insts skipped by commit system.cpu.commit.commitSquashedInsts 476380119 # The number of squashed insts skipped by commit
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
system.cpu.cpi 0.735925 # CPI: Cycles Per Instruction system.cpu.cpi 0.753611 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.735925 # CPI: Total CPI of All Threads system.cpu.cpi_total 0.753611 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 460303357 # number of ReadReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 3955.169300 # average ReadReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 7500 # average LoadLockedReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2868.381634 # average ReadReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 5500 # average LoadLockedReq mshr miss latency
system.cpu.dcache.ReadReq_hits 451791924 # number of ReadReq hits system.cpu.dcache.LoadLockedReq_hits 2 # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_miss_latency 33664158500 # number of ReadReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 7500 # number of LoadLockedReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.018491 # miss rate for ReadReq accesses system.cpu.dcache.LoadLockedReq_miss_rate 0.333333 # miss rate for LoadLockedReq accesses
system.cpu.dcache.ReadReq_misses 8511433 # number of ReadReq misses system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses
system.cpu.dcache.ReadReq_mshr_hits 1219244 # number of ReadReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_miss_latency 5500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 20916781000 # number of ReadReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate 0.015842 # mshr miss rate for ReadReq accesses system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses 7292189 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_accesses 511433561 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 6211.231687 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 6699.535635 # average WriteReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3240.921493 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 8433.632873 # average WriteReq mshr miss latency system.cpu.dcache.ReadReq_hits 504159044 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 157310932 # number of WriteReq hits system.cpu.dcache.ReadReq_miss_latency 45183710500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 22896132000 # number of WriteReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.014224 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.021263 # miss rate for WriteReq accesses system.cpu.dcache.ReadReq_misses 7274517 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 3417570 # number of WriteReq misses system.cpu.dcache.ReadReq_mshr_hits 1442446 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 1533904 # number of WriteReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 23576138500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 15886147500 # number of WriteReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.014224 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.011720 # mshr miss rate for WriteReq accesses system.cpu.dcache.ReadReq_mshr_misses 7274517 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 1883666 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_accesses 158840549 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.avg_blocked_cycles_no_mshrs 1092.259997 # average number of cycles each access was blocked system.cpu.dcache.WriteReq_avg_miss_latency 13691.838043 # average WriteReq miss latency
system.cpu.dcache.avg_blocked_cycles_no_targets 571.397227 # average number of cycles each access was blocked system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7367.789283 # average WriteReq mshr miss latency
system.cpu.dcache.avg_refs 66.381046 # Average number of references to valid blocks. system.cpu.dcache.WriteReq_hits 156591934 # number of WriteReq hits
system.cpu.dcache.blocked_no_mshrs 62416 # number of cycles access was blocked system.cpu.dcache.WriteReq_miss_latency 30787672401 # number of WriteReq miss cycles
system.cpu.dcache.blocked_no_targets 56970 # number of cycles access was blocked system.cpu.dcache.WriteReq_miss_rate 0.014156 # miss rate for WriteReq accesses
system.cpu.dcache.blocked_cycles_no_mshrs 68174500 # number of cycles access was blocked system.cpu.dcache.WriteReq_misses 2248615 # number of WriteReq misses
system.cpu.dcache.blocked_cycles_no_targets 32552500 # number of cycles access was blocked system.cpu.dcache.WriteReq_mshr_hits 1887953 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 16567321498 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.014156 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 2248615 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs 1521.266534 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets 1667.900476 # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 72.179758 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 34791 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 65110 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 52926384 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 108597000 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 621031859 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses 670274110 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 4741.409697 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency 7977.562728 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 4010.844602 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 4215.363181 # average overall mshr miss latency
system.cpu.dcache.demand_hits 609102856 # number of demand (read+write) hits system.cpu.dcache.demand_hits 660750978 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 56560290500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency 75971382901 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.019208 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate 0.014208 # miss rate for demand accesses
system.cpu.dcache.demand_misses 11929003 # number of demand (read+write) misses system.cpu.dcache.demand_misses 9523132 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 2753148 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits 3330399 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 36802928500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency 40143459998 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.014775 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate 0.014208 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 9175855 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses 9523132 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 621031859 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses 670274110 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 4741.409697 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency 7977.562728 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 4010.844602 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 4215.363181 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 609102856 # number of overall hits system.cpu.dcache.overall_hits 660750978 # number of overall hits
system.cpu.dcache.overall_miss_latency 56560290500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency 75971382901 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.019208 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate 0.014208 # miss rate for overall accesses
system.cpu.dcache.overall_misses 11929003 # number of overall misses system.cpu.dcache.overall_misses 9523132 # number of overall misses
system.cpu.dcache.overall_mshr_hits 2753148 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits 3330399 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 36802928500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency 40143459998 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.014775 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate 0.014208 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 9175855 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses 9523132 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -118,92 +128,104 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 9171759 # number of replacements system.cpu.dcache.replacements 9155187 # number of replacements
system.cpu.dcache.sampled_refs 9175855 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 9159283 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4081.309726 # Cycle average of tags in use system.cpu.dcache.tagsinuse 4084.725965 # Cycle average of tags in use
system.cpu.dcache.total_refs 609102856 # Total number of references to valid blocks. system.cpu.dcache.total_refs 661114830 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 8881811000 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 6949550000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 2245633 # number of writebacks system.cpu.dcache.writebacks 2245528 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 27333658 # Number of cycles decode is blocked system.cpu.decode.DECODE:BlockedCycles 23691683 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 501 # Number of times decode detected a branch misprediction system.cpu.decode.DECODE:BranchMispred 575 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 42431183 # Number of times decode resolved a branch system.cpu.decode.DECODE:BranchResolved 51434078 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 2163062948 # Number of instructions handled by decode system.cpu.decode.DECODE:DecodedInsts 2685033161 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 823856490 # Number of cycles decode is idle system.cpu.decode.DECODE:IdleCycles 684622025 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 388659524 # Number of cycles decode is running system.cpu.decode.DECODE:RunCycles 525046007 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 37167487 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashCycles 72503589 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 1638 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:SquashedInsts 1687 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 580367 # Number of cycles decode is unblocking system.cpu.decode.DECODE:UnblockCycles 2438727 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 265702680 # Number of branches that fetch encountered system.cpu.dtb.accesses 758263361 # DTB accesses
system.cpu.fetch.CacheLines 277957843 # Number of cache lines fetched system.cpu.dtb.acv 0 # DTB access violations
system.cpu.fetch.Cycles 672748425 # Number of cycles fetch has run and was not squashing or blocked system.cpu.dtb.hits 743549453 # DTB hits
system.cpu.fetch.IcacheSquashes 10624598 # Number of outstanding Icache misses that were squashed system.cpu.dtb.misses 14713908 # DTB misses
system.cpu.fetch.Insts 2197044125 # Number of instructions fetch has processed system.cpu.dtb.read_accesses 558500359 # DTB read accesses
system.cpu.fetch.SquashCycles 19810424 # Number of cycles fetch has spent squashing system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.fetch.branchRate 0.207971 # Number of branch fetches per cycle system.cpu.dtb.read_hits 549711515 # DTB read hits
system.cpu.fetch.icacheStallCycles 277957843 # Number of cycles fetch is stalled on an Icache miss system.cpu.dtb.read_misses 8788844 # DTB read misses
system.cpu.fetch.predictedBranches 255949942 # Number of branches that fetch has predicted taken system.cpu.dtb.write_accesses 199763002 # DTB write accesses
system.cpu.fetch.rate 1.719668 # Number of inst fetches per cycle system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 193837938 # DTB write hits
system.cpu.dtb.write_misses 5925064 # DTB write misses
system.cpu.fetch.Branches 329654644 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 338459974 # Number of cache lines fetched
system.cpu.fetch.Cycles 875922763 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 8905677 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 2732615549 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 26330328 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.251971 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 338459974 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 319160464 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.088673 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 1277597526 system.cpu.fetch.rateDist.samples 1308302031
system.cpu.fetch.rateDist.min_value 0 system.cpu.fetch.rateDist.min_value 0
0 882806946 6909.90% 0 770839278 5891.91%
1 27356477 214.12% 1 46037022 351.88%
2 16416749 128.50% 2 31884256 243.71%
3 27123610 212.30% 3 48862894 373.48%
4 80197027 627.72% 4 119031598 909.82%
5 46838848 366.62% 5 67260927 514.11%
6 25144427 196.81% 6 45605029 348.58%
7 24073126 188.42% 7 40088084 306.41%
8 147640316 1155.61% 8 138692943 1060.10%
system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 277957843 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses 338459894 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 5447.729673 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 7804.756637 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4641.891892 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 5448.008850 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 277956896 # number of ReadReq hits system.cpu.icache.ReadReq_hits 338458990 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 5159000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency 7055500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 947 # number of ReadReq misses system.cpu.icache.ReadReq_misses 904 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 59 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits 80 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 4122000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency 4925000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 888 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses 904 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 313014.522523 # Average number of references to valid blocks. system.cpu.icache.avg_refs 374401.537611 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 277957843 # number of demand (read+write) accesses system.cpu.icache.demand_accesses 338459894 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 5447.729673 # average overall miss latency system.cpu.icache.demand_avg_miss_latency 7804.756637 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 4641.891892 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 5448.008850 # average overall mshr miss latency
system.cpu.icache.demand_hits 277956896 # number of demand (read+write) hits system.cpu.icache.demand_hits 338458990 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 5159000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency 7055500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
system.cpu.icache.demand_misses 947 # number of demand (read+write) misses system.cpu.icache.demand_misses 904 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 59 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits 80 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 4122000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency 4925000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 888 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses 904 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 277957843 # number of overall (read+write) accesses system.cpu.icache.overall_accesses 338459894 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 5447.729673 # average overall miss latency system.cpu.icache.overall_avg_miss_latency 7804.756637 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 4641.891892 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 5448.008850 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 277956896 # number of overall hits system.cpu.icache.overall_hits 338458990 # number of overall hits
system.cpu.icache.overall_miss_latency 5159000 # number of overall miss cycles system.cpu.icache.overall_miss_latency 7055500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
system.cpu.icache.overall_misses 947 # number of overall misses system.cpu.icache.overall_misses 904 # number of overall misses
system.cpu.icache.overall_mshr_hits 59 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits 80 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 4122000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency 4925000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 888 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses 904 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -216,79 +238,79 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 1 # number of replacements system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.sampled_refs 888 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 904 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 691.554117 # Cycle average of tags in use system.cpu.icache.tagsinuse 710.981871 # Cycle average of tags in use
system.cpu.icache.total_refs 277956896 # Total number of references to valid blocks. system.cpu.icache.total_refs 338458990 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 973 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.idleCycles 287621 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 231142223 # Number of branches executed system.cpu.iew.EXEC:branches 270496646 # Number of branches executed
system.cpu.iew.EXEC:nop 101615397 # number of nop insts executed system.cpu.iew.EXEC:nop 123104849 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.460942 # Inst execution rate system.cpu.iew.EXEC:rate 1.690527 # Inst execution rate
system.cpu.iew.EXEC:refs 650877785 # number of memory reference insts executed system.cpu.iew.EXEC:refs 759555990 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 168419462 # Number of stores executed system.cpu.iew.EXEC:stores 199980185 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 1210814193 # num instructions consuming a value system.cpu.iew.WB:consumers 1477074275 # num instructions consuming a value
system.cpu.iew.WB:count 1847797148 # cumulative count of insts written-back system.cpu.iew.WB:count 2172910283 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.819076 # average fanout of values written-back system.cpu.iew.WB:fanout 0.814315 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 991749121 # num instructions producing a value system.cpu.iew.WB:producers 1202803999 # num instructions producing a value
system.cpu.iew.WB:rate 1.446306 # insts written-back per cycle system.cpu.iew.WB:rate 1.660863 # insts written-back per cycle
system.cpu.iew.WB:sent 1849274792 # cumulative count of insts sent to commit system.cpu.iew.WB:sent 2193655848 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 20085867 # Number of branch mispredicts detected at execute system.cpu.iew.branchMispredicts 21011443 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 1985372 # Number of cycles IEW is blocking system.cpu.iew.iewBlockCycles 889547 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 497279728 # Number of dispatched load instructions system.cpu.iew.iewDispLoadInsts 594992654 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 38 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 27992821 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispSquashedInsts 23236593 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 174034666 # Number of dispatched store instructions system.cpu.iew.iewDispStoreInsts 221743675 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 2032941045 # Number of instructions dispatched to IQ system.cpu.iew.iewDispatchedInsts 2499789620 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 482458323 # Number of load instructions executed system.cpu.iew.iewExecLoadInsts 559575805 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 14098084 # Number of squashed instructions skipped in execute system.cpu.iew.iewExecSquashedInsts 40783059 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 1866495371 # Number of executed instructions system.cpu.iew.iewExecutedInsts 2211719338 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 77 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIQFullEvents 12131 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 1402 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 5627 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 37167487 # Number of cycles IEW is squashing system.cpu.iew.iewSquashCycles 72503589 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 36044 # Number of cycles IEW is unblocking system.cpu.iew.iewUnblockCycles 62383 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 409084 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.cacheBlocked 123404 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 20784106 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.forwLoads 36795200 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 401249 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.ignoredResponses 338162 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 306932 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.memOrderViolation 340968 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 3 # Number of loads that were rescheduled system.cpu.iew.lsq.thread.0.rescheduledLoads 5 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 51613367 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedLoads 149326293 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 13129684 # Number of stores squashed system.cpu.iew.lsq.thread.0.squashedStores 60838693 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 306932 # Number of memory order violations system.cpu.iew.memOrderViolationEvents 340968 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 672336 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 705259 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 19413531 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedTakenIncorrect 20306184 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.358835 # IPC: Instructions Per Cycle system.cpu.ipc 1.326944 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.358835 # IPC: Total IPC of All Threads system.cpu.ipc_total 1.326944 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 1880593455 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0 2252502397 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist system.cpu.iq.ISSUE:FU_type_0.start_dist
(null) 0 0.00% # Type of FU issued No_OpClass 0 0.00% # Type of FU issued
IntAlu 1224165146 65.09% # Type of FU issued IntAlu 1478322730 65.63% # Type of FU issued
IntMult 78 0.00% # Type of FU issued IntMult 88 0.00% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued
FloatAdd 199 0.00% # Type of FU issued FloatAdd 219 0.00% # Type of FU issued
FloatCmp 15 0.00% # Type of FU issued FloatCmp 16 0.00% # Type of FU issued
FloatCvt 141 0.00% # Type of FU issued FloatCvt 143 0.00% # Type of FU issued
FloatMult 13 0.00% # Type of FU issued FloatMult 14 0.00% # Type of FU issued
FloatDiv 24 0.00% # Type of FU issued FloatDiv 24 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued
MemRead 487297898 25.91% # Type of FU issued MemRead 570745758 25.34% # Type of FU issued
MemWrite 169129941 8.99% # Type of FU issued MemWrite 203433405 9.03% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 14841221 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_cnt 16701897 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.007892 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_busy_rate 0.007415 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist system.cpu.iq.ISSUE:fu_full.start_dist
(null) 0 0.00% # attempts to use FU when none available No_OpClass 0 0.00% # attempts to use FU when none available
IntAlu 753308 5.08% # attempts to use FU when none available IntAlu 2428134 14.54% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available
@ -297,84 +319,105 @@ system.cpu.iq.ISSUE:fu_full.start_dist
FloatMult 0 0.00% # attempts to use FU when none available FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available
MemRead 10126775 68.23% # attempts to use FU when none available MemRead 10594349 63.43% # attempts to use FU when none available
MemWrite 3961138 26.69% # attempts to use FU when none available MemWrite 3679414 22.03% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples 1277597526 system.cpu.iq.ISSUE:issued_per_cycle.samples 1308302031
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 550473495 4308.66% 0 464994121 3554.18%
1 242915598 1901.35% 1 246274545 1882.40%
2 174612702 1366.73% 2 221057021 1689.65%
3 111937959 876.16% 3 136661440 1044.57%
4 91216702 713.97% 4 111222535 850.13%
5 63235343 494.96% 5 73372650 560.82%
6 32411117 253.69% 6 42938124 328.20%
7 9228529 72.23% 7 9505404 72.65%
8 1566081 12.26% 8 2276191 17.40%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 1.471976 # Inst issue rate system.cpu.iq.ISSUE:rate 1.721699 # Inst issue rate
system.cpu.iq.iqInstsAdded 1931325610 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsAdded 2376684729 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 1880593455 # Number of instructions issued system.cpu.iq.iqInstsIssued 2252502397 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqNonSpecInstsAdded 42 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 179510503 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsExamined 628382514 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 87058 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsIssued 968135 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 101093002 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedOperandsExamined 253289566 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadReq_accesses 9176743 # number of ReadReq accesses(hits+misses) system.cpu.itb.accesses 338460010 # ITB accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 5323.405393 # average ReadReq miss latency system.cpu.itb.acv 0 # ITB acv
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2210.600583 # average ReadReq mshr miss latency system.cpu.itb.hits 338459974 # ITB hits
system.cpu.l2cache.ReadReq_hits 7008183 # number of ReadReq hits system.cpu.itb.misses 36 # ITB misses
system.cpu.l2cache.ReadReq_miss_latency 11544124000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_accesses 1884766 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_miss_rate 0.236310 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_avg_miss_latency 5021.667411 # average ReadExReq miss latency
system.cpu.l2cache.ReadReq_misses 2168560 # number of ReadReq misses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 3021.667411 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadReq_mshr_miss_latency 4793820000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_miss_latency 9464668000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.236310 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 2168560 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_misses 1884766 # number of ReadExReq misses
system.cpu.l2cache.Writeback_accesses 2245633 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_mshr_miss_latency 5695136000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.Writeback_hits 2216502 # number of Writeback hits system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.Writeback_miss_rate 0.012972 # miss rate for Writeback accesses system.cpu.l2cache.ReadExReq_mshr_misses 1884766 # number of ReadExReq MSHR misses
system.cpu.l2cache.Writeback_misses 29131 # number of Writeback misses system.cpu.l2cache.ReadReq_accesses 7275421 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_mshr_miss_rate 0.012972 # mshr miss rate for Writeback accesses system.cpu.l2cache.ReadReq_avg_miss_latency 4312.514661 # average ReadReq miss latency
system.cpu.l2cache.Writeback_mshr_misses 29131 # number of Writeback MSHR misses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2312.514661 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 5169531 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 9081681500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.289453 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 2105890 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 4869901500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.289453 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 2105890 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 363856 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4839.580768 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2839.786894 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 1760910500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 363856 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1033273500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 363856 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 2245528 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 2245528 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 2245528 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 4.253830 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 4.195595 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 9176743 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses 9160187 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 5323.405393 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency 4647.443804 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2210.600583 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 2647.443804 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 7008183 # number of demand (read+write) hits system.cpu.l2cache.demand_hits 5169531 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 11544124000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency 18546349500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.236310 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate 0.435652 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 2168560 # number of demand (read+write) misses system.cpu.l2cache.demand_misses 3990656 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 4793820000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 10565037500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.236310 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate 0.435652 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 2168560 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses 3990656 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 11422376 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses 9160187 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 5252.842188 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency 4647.443804 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2210.600583 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 2647.443804 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 9224685 # number of overall hits system.cpu.l2cache.overall_hits 5169531 # number of overall hits
system.cpu.l2cache.overall_miss_latency 11544124000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency 18546349500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.192402 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate 0.435652 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 2197691 # number of overall misses system.cpu.l2cache.overall_misses 3990656 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 4793820000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency 10565037500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.189852 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate 0.435652 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 2168560 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses 3990656 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -386,32 +429,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 2135792 # number of replacements system.cpu.l2cache.replacements 1375756 # number of replacements
system.cpu.l2cache.sampled_refs 2168560 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 1398753 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 31406.160078 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 18802.772660 # Cycle average of tags in use
system.cpu.l2cache.total_refs 9224685 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 5868601 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 53019662000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 505903232000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 1039396 # number of writebacks system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.numCycles 1277597526 # number of cpu cycles simulated system.cpu.numCycles 1308302031 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 16292159 # Number of cycles rename is blocking system.cpu.rename.RENAME:BlockCycles 9337867 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 4365074 # Number of times rename has blocked due to IQ full system.cpu.rename.RENAME:IQFullEvents 3445352 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 834284464 # Number of cycles rename is idle system.cpu.rename.RENAME:IdleCycles 700444810 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 6221923 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:LSQFullEvents 8719596 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 448 # Number of times rename has blocked due to ROB full system.cpu.rename.RENAME:ROBFullEvents 7541 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 2711841153 # Number of register rename lookups that rename has made system.cpu.rename.RENAME:RenameLookups 3393542048 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 2114466649 # Number of instructions processed by rename system.cpu.rename.RENAME:RenamedInsts 2622643652 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 1591248178 # Number of destination operands rename has renamed system.cpu.rename.RENAME:RenamedOperands 1968531188 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 378627043 # Number of cycles rename is running system.cpu.rename.RENAME:RunCycles 511623131 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 37167487 # Number of cycles rename is squashing system.cpu.rename.RENAME:SquashCycles 72503589 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 11225904 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UnblockCycles 14392125 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 215045215 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:UndoneMaps 592328225 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 469 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializeStallCycles 509 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 45 # count of serializing insts renamed system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 21611838 # count of insts added to the skid buffer system.cpu.rename.RENAME:skidInsts 29038158 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 43 # count of temporary serializing insts renamed system.cpu.rename.RENAME:tempSerializingInsts 46 # count of temporary serializing insts renamed
system.cpu.timesIdled 27 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 379 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

18
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -11,12 +11,14 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
children=workload children=dtb itb tracer workload
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false defer_registration=false
dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -25,11 +27,23 @@ phase=0
progress_interval=0 progress_interval=0
simulate_stalls=false simulate_stalls=false
system=system system=system
tracer=system.cpu.tracer
width=1 width=1
workload=system.cpu.workload workload=system.cpu.workload
dcache_port=system.membus.port[2] dcache_port=system.membus.port[2]
icache_port=system.membus.port[1] icache_port=system.membus.port[1]
[system.cpu.dtb]
type=AlphaDTB
size=64
[system.cpu.itb]
type=AlphaITB
size=48
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload] [system.cpu.workload]
type=LiveProcess type=LiveProcess
cmd=bzip2 input.source 1 cmd=bzip2 input.source 1
@ -53,7 +67,7 @@ bus_id=0
clock=1000 clock=1000
responder_set=false responder_set=false
width=64 width=64
port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem] [system.physmem]
type=PhysicalMemory type=PhysicalMemory

36
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt
View file

@ -1,18 +1,34 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 918892 # Simulator instruction rate (inst/s) host_inst_rate 2729023 # Simulator instruction rate (inst/s)
host_mem_usage 148632 # Number of bytes of host memory used host_mem_usage 174164 # Number of bytes of host memory used
host_seconds 1980.41 # Real time elapsed on the host host_seconds 666.82 # Real time elapsed on the host
host_tick_rate 459446111 # Simulator tick rate (ticks/s) host_tick_rate 1369458693 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1819780129 # Number of instructions simulated sim_insts 1819780127 # Number of instructions simulated
sim_seconds 0.909890 # Number of seconds simulated sim_seconds 0.913189 # Number of seconds simulated
sim_ticks 909890064000 # Number of ticks simulated sim_ticks 913189263000 # Number of ticks simulated
system.cpu.dtb.accesses 611922547 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.dtb.hits 605324165 # DTB hits
system.cpu.dtb.misses 6598382 # DTB misses
system.cpu.dtb.read_accesses 449492741 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 444595663 # DTB read hits
system.cpu.dtb.read_misses 4897078 # DTB read misses
system.cpu.dtb.write_accesses 162429806 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 160728502 # DTB write hits
system.cpu.dtb.write_misses 1701304 # DTB write misses
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 1826378527 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 1826378509 # ITB hits
system.cpu.itb.misses 18 # ITB misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1819780129 # number of cpu cycles simulated system.cpu.numCycles 1826378527 # number of cpu cycles simulated
system.cpu.num_insts 1819780129 # Number of instructions executed system.cpu.num_insts 1819780127 # Number of instructions executed
system.cpu.num_refs 606571345 # Number of memory references system.cpu.num_refs 613169725 # Number of memory references
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

12
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
View file

@ -11,12 +11,14 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=TimingSimpleCPU type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus tracer workload children=dcache dtb icache itb l2cache toL2Bus tracer workload
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false defer_registration=false
dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -65,6 +67,10 @@ write_buffers=8
cpu_side=system.cpu.dcache_port cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1] mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=AlphaDTB
size=64
[system.cpu.icache] [system.cpu.icache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615
@ -101,6 +107,10 @@ write_buffers=8
cpu_side=system.cpu.icache_port cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0] mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=AlphaITB
size=48
[system.cpu.l2cache] [system.cpu.l2cache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615

62
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 1593285 # Simulator instruction rate (inst/s) host_inst_rate 1514723 # Simulator instruction rate (inst/s)
host_mem_usage 199472 # Number of bytes of host memory used host_mem_usage 181532 # Number of bytes of host memory used
host_seconds 1142.16 # Real time elapsed on the host host_seconds 1201.39 # Real time elapsed on the host
host_tick_rate 2268225007 # Simulator tick rate (ticks/s) host_tick_rate 2161875158 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1819780129 # Number of instructions simulated sim_insts 1819780127 # Number of instructions simulated
sim_seconds 2.590667 # Number of seconds simulated sim_seconds 2.597265 # Number of seconds simulated
sim_ticks 2590666806000 # Number of ticks simulated sim_ticks 2597265186000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 16451.345769 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency 16451.345769 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 14451.345769 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 14451.345769 # average ReadReq mshr miss latency
@ -76,14 +76,26 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 9107638 # number of replacements system.cpu.dcache.replacements 9107638 # number of replacements
system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4079.283777 # Cycle average of tags in use system.cpu.dcache.tagsinuse 4079.325443 # Cycle average of tags in use
system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks. system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 40727264000 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 40727877000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 2244708 # number of writebacks system.cpu.dcache.writebacks 2244708 # number of writebacks
system.cpu.icache.ReadReq_accesses 1819780130 # number of ReadReq accesses(hits+misses) system.cpu.dtb.accesses 611922547 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.dtb.hits 605324165 # DTB hits
system.cpu.dtb.misses 6598382 # DTB misses
system.cpu.dtb.read_accesses 449492741 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 444595663 # DTB read hits
system.cpu.dtb.read_misses 4897078 # DTB read misses
system.cpu.dtb.write_accesses 162429806 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 160728502 # DTB write hits
system.cpu.dtb.write_misses 1701304 # DTB write misses
system.cpu.icache.ReadReq_accesses 1826378510 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 1819779328 # number of ReadReq hits system.cpu.icache.ReadReq_hits 1826377708 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 20050000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency 20050000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses
@ -92,16 +104,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # ms
system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 2269051.531172 # Average number of references to valid blocks. system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 1819780130 # number of demand (read+write) accesses system.cpu.icache.demand_accesses 1826378510 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 25000 # average overall miss latency system.cpu.icache.demand_avg_miss_latency 25000 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.icache.demand_hits 1819779328 # number of demand (read+write) hits system.cpu.icache.demand_hits 1826377708 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 20050000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency 20050000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
system.cpu.icache.demand_misses 802 # number of demand (read+write) misses system.cpu.icache.demand_misses 802 # number of demand (read+write) misses
@ -112,11 +124,11 @@ system.cpu.icache.demand_mshr_misses 802 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 1819780130 # number of overall (read+write) accesses system.cpu.icache.overall_accesses 1826378510 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 25000 # average overall miss latency system.cpu.icache.overall_avg_miss_latency 25000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 1819779328 # number of overall hits system.cpu.icache.overall_hits 1826377708 # number of overall hits
system.cpu.icache.overall_miss_latency 20050000 # number of overall miss cycles system.cpu.icache.overall_miss_latency 20050000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
system.cpu.icache.overall_misses 802 # number of overall misses system.cpu.icache.overall_misses 802 # number of overall misses
@ -138,11 +150,15 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 1 # number of replacements system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 611.417495 # Cycle average of tags in use system.cpu.icache.tagsinuse 611.506832 # Cycle average of tags in use
system.cpu.icache.total_refs 1819779328 # Total number of references to valid blocks. system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 1826378528 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 1826378510 # ITB hits
system.cpu.itb.misses 18 # ITB misses
system.cpu.l2cache.ReadExReq_accesses 1889320 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 1889320 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
@ -224,14 +240,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 1367767 # number of replacements system.cpu.l2cache.replacements 1367767 # number of replacements
system.cpu.l2cache.sampled_refs 1390767 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 1390767 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 18546.386002 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 18552.565433 # Cycle average of tags in use
system.cpu.l2cache.total_refs 5824390 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 5824390 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 2030116907000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 2034930554000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 2590666806000 # number of cpu cycles simulated system.cpu.numCycles 2597265186000 # number of cpu cycles simulated
system.cpu.num_insts 1819780129 # Number of instructions executed system.cpu.num_insts 1819780127 # Number of instructions executed
system.cpu.num_refs 606571345 # Number of memory references system.cpu.num_refs 613169725 # Number of memory references
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

12
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=DerivO3CPU type=DerivO3CPU
children=dcache fuPool icache l2cache toL2Bus tracer workload children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
BTBEntries=4096 BTBEntries=4096
BTBTagSize=16 BTBTagSize=16
LFSTSize=1024 LFSTSize=1024
@ -36,6 +36,7 @@ decodeToRenameDelay=1
decodeWidth=8 decodeWidth=8
defer_registration=false defer_registration=false
dispatchWidth=8 dispatchWidth=8
dtb=system.cpu.dtb
fetchToDecodeDelay=1 fetchToDecodeDelay=1
fetchTrapLatency=1 fetchTrapLatency=1
fetchWidth=8 fetchWidth=8
@ -53,6 +54,7 @@ iewToRenameDelay=1
instShiftAmt=2 instShiftAmt=2
issueToExecuteDelay=1 issueToExecuteDelay=1
issueWidth=8 issueWidth=8
itb=system.cpu.itb
localCtrBits=2 localCtrBits=2
localHistoryBits=11 localHistoryBits=11
localHistoryTableSize=2048 localHistoryTableSize=2048
@ -130,6 +132,10 @@ write_buffers=8
cpu_side=system.cpu.dcache_port cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1] mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=AlphaDTB
size=64
[system.cpu.fuPool] [system.cpu.fuPool]
type=FUPool type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
@ -303,6 +309,10 @@ write_buffers=8
cpu_side=system.cpu.icache_port cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0] mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=AlphaITB
size=48
[system.cpu.l2cache] [system.cpu.l2cache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615

568
tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt
View file

@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits 13022932 # Number of BTB hits global.BPredUnit.BTBHits 13010658 # Number of BTB hits
global.BPredUnit.BTBLookups 16938031 # Number of BTB lookups global.BPredUnit.BTBLookups 16925459 # Number of BTB lookups
global.BPredUnit.RASInCorrect 1193 # Number of incorrect RAS predictions. global.BPredUnit.RASInCorrect 1191 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 1944645 # Number of conditional branches incorrect global.BPredUnit.condIncorrect 1944478 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 14588431 # Number of conditional branches predicted global.BPredUnit.condPredicted 14575632 # Number of conditional branches predicted
global.BPredUnit.lookups 19441115 # Number of BP lookups global.BPredUnit.lookups 19422613 # Number of BP lookups
global.BPredUnit.usedRAS 1715741 # Number of times the RAS was used to get a target. global.BPredUnit.usedRAS 1713685 # Number of times the RAS was used to get a target.
host_inst_rate 140839 # Simulator instruction rate (inst/s) host_inst_rate 134486 # Simulator instruction rate (inst/s)
host_mem_usage 205524 # Number of bytes of host memory used host_mem_usage 187512 # Number of bytes of host memory used
host_seconds 597.70 # Real time elapsed on the host host_seconds 625.94 # Real time elapsed on the host
host_tick_rate 68085854 # Simulator tick rate (ticks/s) host_tick_rate 64866574 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 17320747 # Number of conflicting loads. memdepunit.memDep.conflictingLoads 17216912 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 5158870 # Number of conflicting stores. memdepunit.memDep.conflictingStores 5017487 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 33916617 # Number of loads inserted to the mem dependence unit. memdepunit.memDep.insertedLoads 33831723 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 10592327 # Number of stores inserted to the mem dependence unit. memdepunit.memDep.insertedStores 10556967 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 84179709 # Number of instructions simulated sim_insts 84179709 # Number of instructions simulated
sim_seconds 0.040695 # Number of seconds simulated sim_seconds 0.040602 # Number of seconds simulated
sim_ticks 40694900000 # Number of ticks simulated sim_ticks 40602361500 # Number of ticks simulated
system.cpu.commit.COM:branches 10240685 # Number of branches committed system.cpu.commit.COM:branches 10240685 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 2814383 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_lim_events 2830089 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 73372540 system.cpu.commit.COM:committed_per_cycle.samples 73220545
system.cpu.commit.COM:committed_per_cycle.min_value 0 system.cpu.commit.COM:committed_per_cycle.min_value 0
0 36054158 4913.85% 0 35958705 4911.01%
1 18224800 2483.87% 1 18165534 2480.93%
2 7501822 1022.43% 2 7495163 1023.64%
3 3901009 531.67% 3 3905368 533.37%
4 2128189 290.05% 4 2115499 288.92%
5 1274528 173.71% 5 1290804 176.29%
6 744433 101.46% 6 741318 101.24%
7 729218 99.39% 7 718065 98.07%
8 2814383 383.57% 8 2830089 386.52%
system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist system.cpu.commit.COM:committed_per_cycle.end_dist
@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 20034413 # Nu
system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 26537108 # Number of memory references committed system.cpu.commit.COM:refs 26537108 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 1932230 # The number of times a branch was mispredicted system.cpu.commit.branchMispredicts 1932029 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 55717434 # The number of squashed insts skipped by commit system.cpu.commit.commitSquashedInsts 55442802 # The number of squashed insts skipped by commit
system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedInsts 84179709 # Number of Instructions Simulated
system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
system.cpu.cpi 0.966851 # CPI: Cycles Per Instruction system.cpu.cpi 0.964650 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.966851 # CPI: Total CPI of All Threads system.cpu.cpi_total 0.964650 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses 23356209 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses 23305151 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 9066 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency 8854.743083 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5569 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5500 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 23355709 # number of ReadReq hits system.cpu.dcache.ReadReq_hits 23304645 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 4533000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency 4480500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000021 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate 0.000022 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 500 # number of ReadReq misses system.cpu.dcache.ReadReq_misses 506 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 123 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits 115 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 2784500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency 2783000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000021 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 500 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses 506 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 6495002 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 6494991 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 24564.959569 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency 24985.167206 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5850.134771 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5885.922330 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 6493147 # number of WriteReq hits system.cpu.dcache.WriteReq_hits 6493137 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 45568000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency 46322500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000286 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate 0.000285 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1855 # number of WriteReq misses system.cpu.dcache.WriteReq_misses 1854 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 6101 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits 6112 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 10852000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency 10912500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000285 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1855 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 1854 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 13325.436607 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 13302.637946 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 29851211 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses 29800142 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 21274.309979 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency 21526.694915 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 5790.445860 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 5803.177966 # average overall mshr miss latency
system.cpu.dcache.demand_hits 29848856 # number of demand (read+write) hits system.cpu.dcache.demand_hits 29797782 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 50101000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency 50803000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000079 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate 0.000079 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2355 # number of demand (read+write) misses system.cpu.dcache.demand_misses 2360 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 6224 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits 6227 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 13636500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency 13695500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2355 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses 2360 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 29851211 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses 29800142 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 21274.309979 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency 21526.694915 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 5790.445860 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 5803.177966 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 29848856 # number of overall hits system.cpu.dcache.overall_hits 29797782 # number of overall hits
system.cpu.dcache.overall_miss_latency 50101000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency 50803000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000079 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate 0.000079 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2355 # number of overall misses system.cpu.dcache.overall_misses 2360 # number of overall misses
system.cpu.dcache.overall_mshr_hits 6224 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits 6227 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 13636500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency 13695500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2355 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses 2360 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -120,92 +120,104 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 160 # number of replacements system.cpu.dcache.replacements 159 # number of replacements
system.cpu.dcache.sampled_refs 2240 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 2240 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 1458.130010 # Cycle average of tags in use system.cpu.dcache.tagsinuse 1459.011880 # Cycle average of tags in use
system.cpu.dcache.total_refs 29848978 # Total number of references to valid blocks. system.cpu.dcache.total_refs 29797909 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 106 # number of writebacks system.cpu.dcache.writebacks 105 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 3820626 # Number of cycles decode is blocked system.cpu.decode.DECODE:BlockedCycles 3766232 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 12575 # Number of times decode detected a branch misprediction system.cpu.decode.DECODE:BranchMispred 12611 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 3037417 # Number of times decode resolved a branch system.cpu.decode.DECODE:BranchResolved 3034294 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 162462210 # Number of instructions handled by decode system.cpu.decode.DECODE:DecodedInsts 162205348 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 39463165 # Number of cycles decode is idle system.cpu.decode.DECODE:IdleCycles 39405972 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 29936850 # Number of cycles decode is running system.cpu.decode.DECODE:RunCycles 29900475 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 8016661 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashCycles 7983383 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 44953 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:SquashedInsts 45169 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 151900 # Number of cycles decode is unblocking system.cpu.decode.DECODE:UnblockCycles 147867 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 19441115 # Number of branches that fetch encountered system.cpu.dtb.accesses 31800987 # DTB accesses
system.cpu.fetch.CacheLines 19217268 # Number of cache lines fetched system.cpu.dtb.acv 0 # DTB access violations
system.cpu.fetch.Cycles 50163624 # Number of cycles fetch has run and was not squashing or blocked system.cpu.dtb.hits 31340580 # DTB hits
system.cpu.fetch.IcacheSquashes 510483 # Number of outstanding Icache misses that were squashed system.cpu.dtb.misses 460407 # DTB misses
system.cpu.fetch.Insts 167309935 # Number of instructions fetch has processed system.cpu.dtb.read_accesses 24617799 # DTB read accesses
system.cpu.fetch.SquashCycles 2078673 # Number of cycles fetch has spent squashing system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.fetch.branchRate 0.238866 # Number of branch fetches per cycle system.cpu.dtb.read_hits 24158583 # DTB read hits
system.cpu.fetch.icacheStallCycles 19217268 # Number of cycles fetch is stalled on an Icache miss system.cpu.dtb.read_misses 459216 # DTB read misses
system.cpu.fetch.predictedBranches 14738673 # Number of branches that fetch has predicted taken system.cpu.dtb.write_accesses 7183188 # DTB write accesses
system.cpu.fetch.rate 2.055677 # Number of inst fetches per cycle system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 7181997 # DTB write hits
system.cpu.dtb.write_misses 1191 # DTB write misses
system.cpu.fetch.Branches 19422613 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 19195045 # Number of cache lines fetched
system.cpu.fetch.Cycles 50102609 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 509210 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 167066208 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 2080138 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.239183 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 19195045 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 14724343 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.057366 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 81389202 system.cpu.fetch.rateDist.samples 81203929
system.cpu.fetch.rateDist.min_value 0 system.cpu.fetch.rateDist.min_value 0
0 50442849 6197.73% 0 50296438 6193.84%
1 3127409 384.25% 1 3127485 385.14%
2 2013333 247.37% 2 2009190 247.43%
3 3501649 430.24% 3 3499443 430.95%
4 4585592 563.42% 4 4580392 564.06%
5 1499931 184.29% 5 1498651 184.55%
6 2042041 250.90% 6 2040206 251.24%
7 1854540 227.86% 7 1851037 227.95%
8 12321858 1513.94% 8 12301087 1514.84%
system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 19216915 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses 19194697 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 5291.898608 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 5285.401314 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3156.958250 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 3152.011551 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 19206855 # number of ReadReq hits system.cpu.icache.ReadReq_hits 19184655 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 53236500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency 53076000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000523 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate 0.000523 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 10060 # number of ReadReq misses system.cpu.icache.ReadReq_misses 10042 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 353 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits 348 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 31759000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency 31652500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000523 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate 0.000523 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 10060 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses 10042 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 1909.230119 # Average number of references to valid blocks. system.cpu.icache.avg_refs 1910.441645 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 19216915 # number of demand (read+write) accesses system.cpu.icache.demand_accesses 19194697 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 5291.898608 # average overall miss latency system.cpu.icache.demand_avg_miss_latency 5285.401314 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 3156.958250 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 3152.011551 # average overall mshr miss latency
system.cpu.icache.demand_hits 19206855 # number of demand (read+write) hits system.cpu.icache.demand_hits 19184655 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 53236500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency 53076000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000523 # miss rate for demand accesses system.cpu.icache.demand_miss_rate 0.000523 # miss rate for demand accesses
system.cpu.icache.demand_misses 10060 # number of demand (read+write) misses system.cpu.icache.demand_misses 10042 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 353 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits 348 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 31759000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency 31652500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000523 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate 0.000523 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 10060 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses 10042 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 19216915 # number of overall (read+write) accesses system.cpu.icache.overall_accesses 19194697 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 5291.898608 # average overall miss latency system.cpu.icache.overall_avg_miss_latency 5285.401314 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 3156.958250 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 3152.011551 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 19206855 # number of overall hits system.cpu.icache.overall_hits 19184655 # number of overall hits
system.cpu.icache.overall_miss_latency 53236500 # number of overall miss cycles system.cpu.icache.overall_miss_latency 53076000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000523 # miss rate for overall accesses system.cpu.icache.overall_miss_rate 0.000523 # miss rate for overall accesses
system.cpu.icache.overall_misses 10060 # number of overall misses system.cpu.icache.overall_misses 10042 # number of overall misses
system.cpu.icache.overall_mshr_hits 353 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits 348 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 31759000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency 31652500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000523 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate 0.000523 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 10060 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses 10042 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -217,183 +229,187 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 8146 # number of replacements system.cpu.icache.replacements 8129 # number of replacements
system.cpu.icache.sampled_refs 10060 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 10042 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1551.624399 # Cycle average of tags in use system.cpu.icache.tagsinuse 1547.586704 # Cycle average of tags in use
system.cpu.icache.total_refs 19206855 # Total number of references to valid blocks. system.cpu.icache.total_refs 19184655 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 435727 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.idleCycles 554685 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 12761226 # Number of branches executed system.cpu.iew.EXEC:branches 12760718 # Number of branches executed
system.cpu.iew.EXEC:nop 12552336 # number of nop insts executed system.cpu.iew.EXEC:nop 12520368 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.247935 # Inst execution rate system.cpu.iew.EXEC:rate 1.249722 # Inst execution rate
system.cpu.iew.EXEC:refs 31899012 # number of memory reference insts executed system.cpu.iew.EXEC:refs 31851627 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 7188094 # Number of stores executed system.cpu.iew.EXEC:stores 7184817 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 90808493 # num instructions consuming a value system.cpu.iew.WB:consumers 90693698 # num instructions consuming a value
system.cpu.iew.WB:count 99646578 # cumulative count of insts written-back system.cpu.iew.WB:count 99568419 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.722903 # average fanout of values written-back system.cpu.iew.WB:fanout 0.723301 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 65645732 # num instructions producing a value system.cpu.iew.WB:producers 65598879 # num instructions producing a value
system.cpu.iew.WB:rate 1.224322 # insts written-back per cycle system.cpu.iew.WB:rate 1.226153 # insts written-back per cycle
system.cpu.iew.WB:sent 100573545 # cumulative count of insts sent to commit system.cpu.iew.WB:sent 100495413 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 2105709 # Number of branch mispredicts detected at execute system.cpu.iew.branchMispredicts 2106580 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 285403 # Number of cycles IEW is blocking system.cpu.iew.iewBlockCycles 285272 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 33916617 # Number of dispatched load instructions system.cpu.iew.iewDispLoadInsts 33831723 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 429 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispNonSpecInsts 429 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 1714541 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispSquashedInsts 1731846 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 10592327 # Number of dispatched store instructions system.cpu.iew.iewDispStoreInsts 10556967 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 147619094 # Number of instructions dispatched to IQ system.cpu.iew.iewDispatchedInsts 147344437 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 24710918 # Number of load instructions executed system.cpu.iew.iewExecLoadInsts 24666810 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 2203361 # Number of squashed instructions skipped in execute system.cpu.iew.iewExecSquashedInsts 2188087 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 101568426 # Number of executed instructions system.cpu.iew.iewExecutedInsts 101482299 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 132795 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIQFullEvents 133099 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 9 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 12 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 8016661 # Number of cycles IEW is squashing system.cpu.iew.iewSquashCycles 7983383 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 165683 # Number of cycles IEW is unblocking system.cpu.iew.iewUnblockCycles 165893 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 838013 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.forwLoads 843499 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 1487 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.ignoredResponses 1537 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 249026 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.memOrderViolation 250644 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 9801 # Number of loads that were rescheduled system.cpu.iew.lsq.thread.0.rescheduledLoads 9811 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 13882204 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedLoads 13797310 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 4089632 # Number of stores squashed system.cpu.iew.lsq.thread.0.squashedStores 4054272 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 249026 # Number of memory order violations system.cpu.iew.memOrderViolationEvents 250644 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 202527 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 202889 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 1903182 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedTakenIncorrect 1903691 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.034286 # IPC: Instructions Per Cycle system.cpu.ipc 1.036646 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.034286 # IPC: Total IPC of All Threads system.cpu.ipc_total 1.036646 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 103771787 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0 103670386 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 7 0.00% # Type of FU issued No_OpClass 7 0.00% # Type of FU issued
IntAlu 64228940 61.89% # Type of FU issued IntAlu 64195239 61.92% # Type of FU issued
IntMult 473017 0.46% # Type of FU issued IntMult 473046 0.46% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued
FloatAdd 2790055 2.69% # Type of FU issued FloatAdd 2788829 2.69% # Type of FU issued
FloatCmp 115633 0.11% # Type of FU issued FloatCmp 115617 0.11% # Type of FU issued
FloatCvt 2376207 2.29% # Type of FU issued FloatCvt 2372095 2.29% # Type of FU issued
FloatMult 305676 0.29% # Type of FU issued FloatMult 305683 0.29% # Type of FU issued
FloatDiv 755062 0.73% # Type of FU issued FloatDiv 755148 0.73% # Type of FU issued
FloatSqrt 323 0.00% # Type of FU issued FloatSqrt 322 0.00% # Type of FU issued
MemRead 25409003 24.49% # Type of FU issued MemRead 25353594 24.46% # Type of FU issued
MemWrite 7317864 7.05% # Type of FU issued MemWrite 7310806 7.05% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 1978136 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_cnt 1973729 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.019062 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_busy_rate 0.019039 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available No_OpClass 0 0.00% # attempts to use FU when none available
IntAlu 311313 15.74% # attempts to use FU when none available IntAlu 311847 15.80% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 546 0.03% # attempts to use FU when none available FloatAdd 478 0.02% # attempts to use FU when none available
FloatCmp 0 0.00% # attempts to use FU when none available FloatCmp 0 0.00% # attempts to use FU when none available
FloatCvt 3483 0.18% # attempts to use FU when none available FloatCvt 2917 0.15% # attempts to use FU when none available
FloatMult 2460 0.12% # attempts to use FU when none available FloatMult 2390 0.12% # attempts to use FU when none available
FloatDiv 833660 42.14% # attempts to use FU when none available FloatDiv 832522 42.18% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available
MemRead 753551 38.09% # attempts to use FU when none available MemRead 750992 38.05% # attempts to use FU when none available
MemWrite 73123 3.70% # attempts to use FU when none available MemWrite 72583 3.68% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples 81389202 system.cpu.iq.ISSUE:issued_per_cycle.samples 81203929
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 35308856 4338.27% 0 35188418 4333.34%
1 18677963 2294.89% 1 18662979 2298.29%
2 11652538 1431.71% 2 11625415 1431.63%
3 6999702 860.03% 3 6937118 854.28%
4 4887440 600.50% 4 4927347 606.79%
5 2229546 273.94% 5 2234432 275.16%
6 1377818 169.29% 6 1373348 169.12%
7 217468 26.72% 7 215389 26.52%
8 37871 4.65% 8 39483 4.86%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 1.275007 # Inst issue rate system.cpu.iq.ISSUE:rate 1.276667 # Inst issue rate
system.cpu.iq.iqInstsAdded 135066329 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsAdded 134823640 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 103771787 # Number of instructions issued system.cpu.iq.iqInstsIssued 103670386 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 429 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqNonSpecInstsAdded 429 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 50270340 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsExamined 50027749 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 231965 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsIssued 225448 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 47066497 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedOperandsExamined 46827412 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 1741 # number of ReadExReq accesses(hits+misses) system.cpu.itb.accesses 19195118 # ITB accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency 4485.353245 # average ReadExReq miss latency system.cpu.itb.acv 0 # ITB acv
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2485.353245 # average ReadExReq mshr miss latency system.cpu.itb.hits 19195045 # ITB hits
system.cpu.l2cache.ReadExReq_miss_latency 7809000 # number of ReadExReq miss cycles system.cpu.itb.misses 73 # ITB misses
system.cpu.l2cache.ReadExReq_accesses 1735 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 4523.342939 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2523.342939 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 7848000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1741 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses 1735 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4327000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency 4378000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1741 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 1735 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 10559 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses 10547 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 4274.193548 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency 4263.929619 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2274.193548 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2263.929619 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 7149 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits 7137 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 14575000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency 14540000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.322947 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate 0.323315 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 3410 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses 3410 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 7755000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency 7720000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.322947 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate 0.323315 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 3410 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses 3410 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 118 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses 123 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4500 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency 4430.894309 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2500 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2430.894309 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 531000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency 545000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 118 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses 123 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 295000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency 299000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 118 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses 123 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 106 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 105 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 106 # number of Writeback misses system.cpu.l2cache.Writeback_misses 105 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 106 # number of Writeback MSHR misses system.cpu.l2cache.Writeback_mshr_misses 105 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 2.172948 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 2.172603 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 12300 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses 12282 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 4345.563968 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency 4351.409135 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2345.563968 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 2351.409135 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 7149 # number of demand (read+write) hits system.cpu.l2cache.demand_hits 7137 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 22384000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency 22388000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.418780 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate 0.418906 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 5151 # number of demand (read+write) misses system.cpu.l2cache.demand_misses 5145 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 12082000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 12098000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.418780 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate 0.418906 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 5151 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses 5145 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 12300 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses 12282 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 4345.563968 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency 4351.409135 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2345.563968 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 2351.409135 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 7149 # number of overall hits system.cpu.l2cache.overall_hits 7137 # number of overall hits
system.cpu.l2cache.overall_miss_latency 22384000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency 22388000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.418780 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate 0.418906 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 5151 # number of overall misses system.cpu.l2cache.overall_misses 5145 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 12082000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency 12098000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.418780 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate 0.418906 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 5151 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses 5145 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -406,30 +422,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 3290 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 3285 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 2252.890734 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 2248.754865 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7149 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 7137 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.numCycles 81389202 # number of cpu cycles simulated system.cpu.numCycles 81203929 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 1683934 # Number of cycles rename is blocking system.cpu.rename.RENAME:BlockCycles 1670922 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 1032549 # Number of times rename has blocked due to IQ full system.cpu.rename.RENAME:IQFullEvents 1021107 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 40751116 # Number of cycles rename is idle system.cpu.rename.RENAME:IdleCycles 40689840 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 970163 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:LSQFullEvents 938076 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 202965992 # Number of register rename lookups that rename has made system.cpu.rename.RENAME:RenameLookups 202669964 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 157380306 # Number of instructions processed by rename system.cpu.rename.RENAME:RenamedInsts 157140698 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 115963922 # Number of destination operands rename has renamed system.cpu.rename.RENAME:RenamedOperands 115798524 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 28805465 # Number of cycles rename is running system.cpu.rename.RENAME:RunCycles 28770212 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 8016661 # Number of cycles rename is squashing system.cpu.rename.RENAME:SquashCycles 7983383 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 2127274 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UnblockCycles 2084846 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 47536561 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:UndoneMaps 47371163 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 4752 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializeStallCycles 4726 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 464 # count of serializing insts renamed system.cpu.rename.RENAME:serializingInsts 465 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 4689522 # count of insts added to the skid buffer system.cpu.rename.RENAME:skidInsts 4645791 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 453 # count of temporary serializing insts renamed system.cpu.rename.RENAME:tempSerializingInsts 454 # count of temporary serializing insts renamed
system.cpu.timesIdled 283 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 325 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

18
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -11,12 +11,14 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
children=workload children=dtb itb tracer workload
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false defer_registration=false
dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -25,11 +27,23 @@ phase=0
progress_interval=0 progress_interval=0
simulate_stalls=false simulate_stalls=false
system=system system=system
tracer=system.cpu.tracer
width=1 width=1
workload=system.cpu.workload workload=system.cpu.workload
dcache_port=system.membus.port[2] dcache_port=system.membus.port[2]
icache_port=system.membus.port[1] icache_port=system.membus.port[1]
[system.cpu.dtb]
type=AlphaDTB
size=64
[system.cpu.itb]
type=AlphaITB
size=48
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload] [system.cpu.workload]
type=LiveProcess type=LiveProcess
cmd=twolf smred cmd=twolf smred
@ -53,7 +67,7 @@ bus_id=0
clock=1000 clock=1000
responder_set=false responder_set=false
width=64 width=64
port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem] [system.physmem]
type=PhysicalMemory type=PhysicalMemory

34
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt
View file

@ -1,18 +1,34 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 935813 # Simulator instruction rate (inst/s) host_inst_rate 2451408 # Simulator instruction rate (inst/s)
host_mem_usage 150648 # Number of bytes of host memory used host_mem_usage 179100 # Number of bytes of host memory used
host_seconds 98.21 # Real time elapsed on the host host_seconds 37.49 # Real time elapsed on the host
host_tick_rate 467904361 # Simulator tick rate (ticks/s) host_tick_rate 1225693454 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91903057 # Number of instructions simulated sim_insts 91903056 # Number of instructions simulated
sim_seconds 0.045952 # Number of seconds simulated sim_seconds 0.045952 # Number of seconds simulated
sim_ticks 45951528000 # Number of ticks simulated sim_ticks 45951567500 # Number of ticks simulated
system.cpu.dtb.accesses 26497334 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.dtb.hits 26497301 # DTB hits
system.cpu.dtb.misses 33 # DTB misses
system.cpu.dtb.read_accesses 19996208 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 19996198 # DTB read hits
system.cpu.dtb.read_misses 10 # DTB read misses
system.cpu.dtb.write_accesses 6501126 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 6501103 # DTB write hits
system.cpu.dtb.write_misses 23 # DTB write misses
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 91903136 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 91903089 # ITB hits
system.cpu.itb.misses 47 # ITB misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 91903057 # number of cpu cycles simulated system.cpu.numCycles 91903136 # number of cpu cycles simulated
system.cpu.num_insts 91903057 # Number of instructions executed system.cpu.num_insts 91903056 # Number of instructions executed
system.cpu.num_refs 26537109 # Number of memory references system.cpu.num_refs 26537141 # Number of memory references
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

12
tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
View file

@ -11,12 +11,14 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=TimingSimpleCPU type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus tracer workload children=dcache dtb icache itb l2cache toL2Bus tracer workload
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false defer_registration=false
dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -65,6 +67,10 @@ write_buffers=8
cpu_side=system.cpu.dcache_port cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1] mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=AlphaDTB
size=64
[system.cpu.icache] [system.cpu.icache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615
@ -101,6 +107,10 @@ write_buffers=8
cpu_side=system.cpu.icache_port cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0] mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=AlphaITB
size=48
[system.cpu.l2cache] [system.cpu.l2cache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615

56
tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 1713530 # Simulator instruction rate (inst/s) host_inst_rate 1574277 # Simulator instruction rate (inst/s)
host_mem_usage 204416 # Number of bytes of host memory used host_mem_usage 186464 # Number of bytes of host memory used
host_seconds 53.63 # Real time elapsed on the host host_seconds 58.38 # Real time elapsed on the host
host_tick_rate 2211088665 # Simulator tick rate (ticks/s) host_tick_rate 2031398471 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91903057 # Number of instructions simulated sim_insts 91903056 # Number of instructions simulated
sim_seconds 0.118590 # Number of seconds simulated sim_seconds 0.118590 # Number of seconds simulated
sim_ticks 118589598000 # Number of ticks simulated sim_ticks 118589630000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 24316.455696 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency 24316.455696 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22316.455696 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22316.455696 # average ReadReq mshr miss latency
@ -76,14 +76,26 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.replacements 157 # number of replacements
system.cpu.dcache.sampled_refs 2222 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 2222 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 1441.457790 # Cycle average of tags in use system.cpu.dcache.tagsinuse 1441.457531 # Cycle average of tags in use
system.cpu.dcache.total_refs 26495079 # Total number of references to valid blocks. system.cpu.dcache.total_refs 26495079 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 104 # number of writebacks system.cpu.dcache.writebacks 104 # number of writebacks
system.cpu.icache.ReadReq_accesses 91903058 # number of ReadReq accesses(hits+misses) system.cpu.dtb.accesses 26497334 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.dtb.hits 26497301 # DTB hits
system.cpu.dtb.misses 33 # DTB misses
system.cpu.dtb.read_accesses 19996208 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 19996198 # DTB read hits
system.cpu.dtb.read_misses 10 # DTB read misses
system.cpu.dtb.write_accesses 6501126 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 6501103 # DTB write hits
system.cpu.dtb.write_misses 23 # DTB write misses
system.cpu.icache.ReadReq_accesses 91903090 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 16695.887192 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 16695.887192 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 14695.887192 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 14695.887192 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 91894548 # number of ReadReq hits system.cpu.icache.ReadReq_hits 91894580 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 142082000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency 142082000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses
@ -92,16 +104,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # ms
system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 10798.419271 # Average number of references to valid blocks. system.cpu.icache.avg_refs 10798.423032 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 91903058 # number of demand (read+write) accesses system.cpu.icache.demand_accesses 91903090 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 16695.887192 # average overall miss latency system.cpu.icache.demand_avg_miss_latency 16695.887192 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 14695.887192 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 14695.887192 # average overall mshr miss latency
system.cpu.icache.demand_hits 91894548 # number of demand (read+write) hits system.cpu.icache.demand_hits 91894580 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 142082000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency 142082000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses
system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses
@ -112,11 +124,11 @@ system.cpu.icache.demand_mshr_misses 8510 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 91903058 # number of overall (read+write) accesses system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 16695.887192 # average overall miss latency system.cpu.icache.overall_avg_miss_latency 16695.887192 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 14695.887192 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 14695.887192 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 91894548 # number of overall hits system.cpu.icache.overall_hits 91894580 # number of overall hits
system.cpu.icache.overall_miss_latency 142082000 # number of overall miss cycles system.cpu.icache.overall_miss_latency 142082000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses
system.cpu.icache.overall_misses 8510 # number of overall misses system.cpu.icache.overall_misses 8510 # number of overall misses
@ -138,11 +150,15 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 6681 # number of replacements system.cpu.icache.replacements 6681 # number of replacements
system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1418.474486 # Cycle average of tags in use system.cpu.icache.tagsinuse 1418.474247 # Cycle average of tags in use
system.cpu.icache.total_refs 91894548 # Total number of references to valid blocks. system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 91903137 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 91903090 # ITB hits
system.cpu.itb.misses 47 # ITB misses
system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
@ -224,14 +240,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 2955 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 2955 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 2014.752255 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 2014.751911 # Cycle average of tags in use
system.cpu.l2cache.total_refs 5916 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 5916 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 118589598000 # number of cpu cycles simulated system.cpu.numCycles 118589630000 # number of cpu cycles simulated
system.cpu.num_insts 91903057 # Number of instructions executed system.cpu.num_insts 91903056 # Number of instructions executed
system.cpu.num_refs 26537109 # Number of memory references system.cpu.num_refs 26537141 # Number of memory references
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

18
tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
View file

@ -11,12 +11,14 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
children=workload children=dtb itb tracer workload
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false defer_registration=false
dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -25,11 +27,23 @@ phase=0
progress_interval=0 progress_interval=0
simulate_stalls=false simulate_stalls=false
system=system system=system
tracer=system.cpu.tracer
width=1 width=1
workload=system.cpu.workload workload=system.cpu.workload
dcache_port=system.membus.port[2] dcache_port=system.membus.port[2]
icache_port=system.membus.port[1] icache_port=system.membus.port[1]
[system.cpu.dtb]
type=SparcDTB
size=64
[system.cpu.itb]
type=SparcITB
size=64
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload] [system.cpu.workload]
type=LiveProcess type=LiveProcess
cmd=twolf smred cmd=twolf smred
@ -53,7 +67,7 @@ bus_id=0
clock=1000 clock=1000
responder_set=false responder_set=false
width=64 width=64
port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem] [system.physmem]
type=PhysicalMemory type=PhysicalMemory

18
tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt
View file

@ -1,18 +1,18 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 673586 # Simulator instruction rate (inst/s) host_inst_rate 1618953 # Simulator instruction rate (inst/s)
host_mem_usage 150548 # Number of bytes of host memory used host_mem_usage 181044 # Number of bytes of host memory used
host_seconds 287.17 # Real time elapsed on the host host_seconds 119.48 # Real time elapsed on the host
host_tick_rate 336792536 # Simulator tick rate (ticks/s) host_tick_rate 809478979 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 193435973 # Number of instructions simulated sim_insts 193435005 # Number of instructions simulated
sim_seconds 0.096718 # Number of seconds simulated sim_seconds 0.096718 # Number of seconds simulated
sim_ticks 96717986000 # Number of ticks simulated sim_ticks 96718067000 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 193435973 # number of cpu cycles simulated system.cpu.numCycles 193436135 # number of cpu cycles simulated
system.cpu.num_insts 193435973 # Number of instructions executed system.cpu.num_insts 193435005 # Number of instructions executed
system.cpu.num_refs 76732959 # Number of memory references system.cpu.num_refs 76733003 # Number of memory references
system.cpu.workload.PROG:num_syscalls 396 # Number of system calls system.cpu.workload.PROG:num_syscalls 396 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

8
tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout
View file

@ -18,11 +18,11 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled May 15 2007 13:02:31 M5 compiled Aug 14 2007 22:48:17
M5 started Tue May 15 16:48:51 2007 M5 started Tue Aug 14 23:36:54 2007
M5 executing on zizzer.eecs.umich.edu M5 executing on nacho
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic tests/run.py long/70.twolf/sparc/linux/simple-atomic command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic tests/run.py long/70.twolf/sparc/linux/simple-atomic
Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav
Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2 Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
Exiting @ tick 96717986000 because target called exit() Exiting @ tick 96718067000 because target called exit()

12
tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
View file

@ -11,12 +11,14 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=TimingSimpleCPU type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus tracer workload children=dcache dtb icache itb l2cache toL2Bus tracer workload
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false defer_registration=false
dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -65,6 +67,10 @@ write_buffers=8
cpu_side=system.cpu.dcache_port cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1] mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=SparcDTB
size=64
[system.cpu.icache] [system.cpu.icache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615
@ -101,6 +107,10 @@ write_buffers=8
cpu_side=system.cpu.icache_port cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0] mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=SparcITB
size=64
[system.cpu.l2cache] [system.cpu.l2cache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615

40
tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 1154889 # Simulator instruction rate (inst/s) host_inst_rate 1002711 # Simulator instruction rate (inst/s)
host_mem_usage 206344 # Number of bytes of host memory used host_mem_usage 188412 # Number of bytes of host memory used
host_seconds 167.49 # Real time elapsed on the host host_seconds 192.91 # Real time elapsed on the host
host_tick_rate 1614378740 # Simulator tick rate (ticks/s) host_tick_rate 1401662479 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 193435973 # Number of instructions simulated sim_insts 193435005 # Number of instructions simulated
sim_seconds 0.270398 # Number of seconds simulated sim_seconds 0.270398 # Number of seconds simulated
sim_ticks 270397855000 # Number of ticks simulated sim_ticks 270397899000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 57734138 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses 57734138 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency
@ -86,14 +86,14 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 26 # number of replacements system.cpu.dcache.replacements 26 # number of replacements
system.cpu.dcache.sampled_refs 1585 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 1585 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 1237.402461 # Cycle average of tags in use system.cpu.dcache.tagsinuse 1237.402352 # Cycle average of tags in use
system.cpu.dcache.total_refs 76731373 # Total number of references to valid blocks. system.cpu.dcache.total_refs 76731373 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 23 # number of writebacks system.cpu.dcache.writebacks 23 # number of writebacks
system.cpu.icache.ReadReq_accesses 193435974 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses 193436018 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 16510.596674 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 16510.596674 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 14510.596674 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 14510.596674 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 193423706 # number of ReadReq hits system.cpu.icache.ReadReq_hits 193423750 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 202552000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency 202552000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000063 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate 0.000063 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 12268 # number of ReadReq misses system.cpu.icache.ReadReq_misses 12268 # number of ReadReq misses
@ -102,16 +102,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000063 # ms
system.cpu.icache.ReadReq_mshr_misses 12268 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses 12268 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 15766.523150 # Average number of references to valid blocks. system.cpu.icache.avg_refs 15766.526736 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 193435974 # number of demand (read+write) accesses system.cpu.icache.demand_accesses 193436018 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 16510.596674 # average overall miss latency system.cpu.icache.demand_avg_miss_latency 16510.596674 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 14510.596674 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 14510.596674 # average overall mshr miss latency
system.cpu.icache.demand_hits 193423706 # number of demand (read+write) hits system.cpu.icache.demand_hits 193423750 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 202552000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency 202552000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000063 # miss rate for demand accesses system.cpu.icache.demand_miss_rate 0.000063 # miss rate for demand accesses
system.cpu.icache.demand_misses 12268 # number of demand (read+write) misses system.cpu.icache.demand_misses 12268 # number of demand (read+write) misses
@ -122,11 +122,11 @@ system.cpu.icache.demand_mshr_misses 12268 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 193435974 # number of overall (read+write) accesses system.cpu.icache.overall_accesses 193436018 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 16510.596674 # average overall miss latency system.cpu.icache.overall_avg_miss_latency 16510.596674 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 14510.596674 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 14510.596674 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 193423706 # number of overall hits system.cpu.icache.overall_hits 193423750 # number of overall hits
system.cpu.icache.overall_miss_latency 202552000 # number of overall miss cycles system.cpu.icache.overall_miss_latency 202552000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000063 # miss rate for overall accesses system.cpu.icache.overall_miss_rate 0.000063 # miss rate for overall accesses
system.cpu.icache.overall_misses 12268 # number of overall misses system.cpu.icache.overall_misses 12268 # number of overall misses
@ -148,8 +148,8 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 10342 # number of replacements system.cpu.icache.replacements 10342 # number of replacements
system.cpu.icache.sampled_refs 12268 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 12268 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1591.726914 # Cycle average of tags in use system.cpu.icache.tagsinuse 1591.726789 # Cycle average of tags in use
system.cpu.icache.total_refs 193423706 # Total number of references to valid blocks. system.cpu.icache.total_refs 193423750 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
@ -234,14 +234,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 4062 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 4062 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 2649.703709 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 2649.703495 # Cycle average of tags in use
system.cpu.l2cache.total_refs 8679 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 8679 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 270397855000 # number of cpu cycles simulated system.cpu.numCycles 270397899000 # number of cpu cycles simulated
system.cpu.num_insts 193435973 # Number of instructions executed system.cpu.num_insts 193435005 # Number of instructions executed
system.cpu.num_refs 76732959 # Number of memory references system.cpu.num_refs 76733003 # Number of memory references
system.cpu.workload.PROG:num_syscalls 396 # Number of system calls system.cpu.workload.PROG:num_syscalls 396 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

8
tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout
View file

@ -18,11 +18,11 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Aug 12 2007 12:23:15 M5 compiled Aug 14 2007 22:48:17
M5 started Sun Aug 12 16:55:52 2007 M5 started Tue Aug 14 23:38:54 2007
M5 executing on zeep M5 executing on nacho
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing tests/run.py long/70.twolf/sparc/linux/simple-timing command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing tests/run.py long/70.twolf/sparc/linux/simple-timing
Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav
Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2 Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
Exiting @ tick 270397855000 because target called exit() Exiting @ tick 270397899000 because target called exit()

14
tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
View file

@ -34,8 +34,8 @@ symbolfile=
[system.bridge] [system.bridge]
type=Bridge type=Bridge
delay=100 delay=100
fix_partial_write_a=false filter_ranges_a=
fix_partial_write_b=true filter_ranges_b=
nack_delay=8 nack_delay=8
req_size_a=16 req_size_a=16
req_size_b=16 req_size_b=16
@ -47,7 +47,7 @@ side_b=system.membus.port[2]
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
children=dtb itb children=dtb itb tracer
clock=1 clock=1
cpu_id=0 cpu_id=0
defer_registration=false defer_registration=false
@ -67,6 +67,7 @@ profile=0
progress_interval=0 progress_interval=0
simulate_stalls=false simulate_stalls=false
system=system system=system
tracer=system.cpu.tracer
width=1 width=1
dcache_port=system.membus.port[10] dcache_port=system.membus.port[10]
icache_port=system.membus.port[9] icache_port=system.membus.port[9]
@ -79,6 +80,9 @@ size=64
type=SparcITB type=SparcITB
size=64 size=64
[system.cpu.tracer]
type=ExeTracer
[system.disk0] [system.disk0]
type=MmDisk type=MmDisk
children=image children=image
@ -149,7 +153,7 @@ clock=2
responder_set=false responder_set=false
width=64 width=64
default=system.membus.responder.pio default=system.membus.responder.pio
port=system.t1000.iob.pio system.t1000.htod.pio system.bridge.side_b system.physmem.port system.physmem2.port system.rom.port system.nvram.port system.hypervisor_desc.port system.partition_desc.port system.cpu.icache_port system.cpu.dcache_port port=system.t1000.iob.pio system.t1000.htod.pio system.bridge.side_b system.physmem.port[0] system.physmem2.port[0] system.rom.port[0] system.nvram.port[0] system.hypervisor_desc.port[0] system.partition_desc.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.membus.responder] [system.membus.responder]
type=IsaFake type=IsaFake
@ -419,7 +423,7 @@ pio_addr=1099255906296
pio_latency=2 pio_latency=2
platform=system.t1000 platform=system.t1000
system=system system=system
time=2009 1 1 0 0 0 3 1 time=Thu Jan 1 00:00:00 2009
pio=system.membus.port[1] pio=system.membus.port[1]
[system.t1000.hvuart] [system.t1000.hvuart]

96
tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/console.system.t1000.pconsole
View file

@ -1,48 +1,48 @@
cpu cpu
Sun Fire T2000, No Keyboard Sun Fire T2000, No Keyboard
Copyright 2006 Sun Microsystems, Inc. All rights reserved. Copyright 2006 Sun Microsystems, Inc. All rights reserved.
OpenBoot 4.23.0, 256 MB memory available, Serial #1122867. OpenBoot 4.23.0, 256 MB memory available, Serial #1122867.
[saidi obp #30] [saidi obp #30]
Ethernet address 0:80:3:de:ad:3, Host ID: 80112233. Ethernet address 0:80:3:de:ad:3, Host ID: 80112233.
Boot device: /virtual-devices/disk@0 File and args: -vV Boot device: /virtual-devices/disk@0 File and args: -vV
Loading ufs-file-system package 1.4 04 Aug 1995 13:02:54. Loading ufs-file-system package 1.4 04 Aug 1995 13:02:54.
FCode UFS Reader 1.12 00/07/17 15:48:16. FCode UFS Reader 1.12 00/07/17 15:48:16.
Loading: /platform/SUNW,Sun-Fire-T2000/ufsboot Loading: /platform/SUNW,Sun-Fire-T2000/ufsboot
Loading: /platform/sun4v/ufsboot Loading: /platform/sun4v/ufsboot
device path '/virtual-devices@100/disk@0:a' device path '/virtual-devices@100/disk@0:a'
The boot filesystem is logging. The boot filesystem is logging.
The ufs log is empty and will not be used. The ufs log is empty and will not be used.
standalone = `kernel/sparcv9/unix', args = `-v' standalone = `kernel/sparcv9/unix', args = `-v'
|Elf64 client |Elf64 client
Size: /-\|/-\|0x76e40+/-\|/-\|/-\|/-\0x1c872+|/-\0x3123a Bytes Size: /-\|/-\|0x76e40+/-\|/-\|/-\|/-\0x1c872+|/-\0x3123a Bytes
modpath: /platform/sun4v/kernel /kernel /usr/kernel modpath: /platform/sun4v/kernel /kernel /usr/kernel
|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-module /platform/sun4v/kernel/sparcv9/unix: text at [0x1000000, 0x1076e3f] data at 0x1800000 |/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-module /platform/sun4v/kernel/sparcv9/unix: text at [0x1000000, 0x1076e3f] data at 0x1800000
module misc/sparcv9/krtld: text at [0x1076e40, 0x108f737] data at 0x184dab0 module misc/sparcv9/krtld: text at [0x1076e40, 0x108f737] data at 0x184dab0
module /platform/sun4v/kernel/sparcv9/genunix: text at [0x108f738, 0x11dd437] data at 0x18531c0 module /platform/sun4v/kernel/sparcv9/genunix: text at [0x108f738, 0x11dd437] data at 0x18531c0
module /platform/sun4v/kernel/misc/sparcv9/platmod: text at [0x11dd438, 0x11dd43f] data at 0x18a4be0 module /platform/sun4v/kernel/misc/sparcv9/platmod: text at [0x11dd438, 0x11dd43f] data at 0x18a4be0
module /platform/sun4v/kernel/cpu/sparcv9/SUNW,UltraSPARC-T1: text at [0x11dd440, 0x11e06ff] data at 0x18a5300 module /platform/sun4v/kernel/cpu/sparcv9/SUNW,UltraSPARC-T1: text at [0x11dd440, 0x11e06ff] data at 0x18a5300
\ SunOS Release 5.10 Version Generic_118822-23 64-bit \ SunOS Release 5.10 Version Generic_118822-23 64-bit
Copyright 1983-2005 Sun Microsystems, Inc. All rights reserved. Copyright 1983-2005 Sun Microsystems, Inc. All rights reserved.
Use is subject to license terms. Use is subject to license terms.
|/-\|/-\|/-\|/-\|/-Ethernet address = 0:80:3:de:ad:3 |/-\|/-\|/-\|/-\|/-Ethernet address = 0:80:3:de:ad:3
\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/mem = 262144K (0x10000000) \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/mem = 262144K (0x10000000)
avail mem = 237879296 avail mem = 237879296
root nexus = Sun Fire T2000 root nexus = Sun Fire T2000
pseudo0 at root pseudo0 at root
pseudo0 is /pseudo pseudo0 is /pseudo
scsi_vhci0 at root scsi_vhci0 at root
scsi_vhci0 is /scsi_vhci scsi_vhci0 is /scsi_vhci
virtual-device: hsimd0 virtual-device: hsimd0
hsimd0 is /virtual-devices@100/disk@0 hsimd0 is /virtual-devices@100/disk@0
root on /virtual-devices@100/disk@0:a fstype ufs root on /virtual-devices@100/disk@0:a fstype ufs
pseudo-device: dld0 pseudo-device: dld0
dld0 is /pseudo/dld@0 dld0 is /pseudo/dld@0
cpu0: UltraSPARC-T1 (cpuid 0 clock 5 MHz) cpu0: UltraSPARC-T1 (cpuid 0 clock 5 MHz)
iscsi0 at root iscsi0 at root
iscsi0 is /iscsi iscsi0 is /iscsi
Hostname: unknown Hostname: unknown
Loading M5 readfile script... Loading M5 readfile script...

12
tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt
View file

@ -1,11 +1,11 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 584673 # Simulator instruction rate (inst/s) host_inst_rate 1839897 # Simulator instruction rate (inst/s)
host_mem_usage 374168 # Number of bytes of host memory used host_mem_usage 481416 # Number of bytes of host memory used
host_seconds 3820.23 # Real time elapsed on the host host_seconds 1211.57 # Real time elapsed on the host
host_tick_rate 584723 # Simulator tick rate (ticks/s) host_tick_rate 1843707 # Simulator tick rate (ticks/s)
sim_freq 2000000000 # Frequency of simulated ticks sim_freq 2000000000 # Frequency of simulated ticks
sim_insts 2233583679 # Number of instructions simulated sim_insts 2229160714 # Number of instructions simulated
sim_seconds 1.116889 # Number of seconds simulated sim_seconds 1.116889 # Number of seconds simulated
sim_ticks 2233777512 # Number of ticks simulated sim_ticks 2233777512 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
@ -13,7 +13,7 @@ system.cpu.kern.inst.arm 0 # nu
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 2233777513 # number of cpu cycles simulated system.cpu.numCycles 2233777513 # number of cpu cycles simulated
system.cpu.num_insts 2233583679 # Number of instructions executed system.cpu.num_insts 2229160714 # Number of instructions executed
system.cpu.num_refs 547951940 # Number of memory references system.cpu.num_refs 547951940 # Number of memory references
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

4
tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr
View file

@ -3,8 +3,12 @@ Warning: rounding error > tolerance
Warning: rounding error > tolerance Warning: rounding error > tolerance
0.002000 rounded to 0 0.002000 rounded to 0
warn: No kernel set for full system simulation. Assuming you know what you're doing... warn: No kernel set for full system simulation. Assuming you know what you're doing...
Warning: rounding error > tolerance
0.002000 rounded to 0
Listening for t1000 connection on port 3456 Listening for t1000 connection on port 3456
Listening for t1000 connection on port 3457 Listening for t1000 connection on port 3457
Warning: rounding error > tolerance
0.002000 rounded to 0
0: system.remote_gdb.listener: listening for remote gdb on port 7000 0: system.remote_gdb.listener: listening for remote gdb on port 7000
warn: Entering event queue @ 0. Starting simulation... warn: Entering event queue @ 0. Starting simulation...
warn: Ignoring write to SPARC ERROR regsiter warn: Ignoring write to SPARC ERROR regsiter

6
tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled May 15 2007 17:08:10 M5 compiled Aug 21 2007 14:42:25
M5 started Tue May 15 17:08:12 2007 M5 started Tue Aug 21 14:44:56 2007
M5 executing on zizzer.eecs.umich.edu M5 executing on nacho
command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic tests/run.py long/80.solaris-boot/sparc/solaris/t1000-simple-atomic command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic tests/run.py long/80.solaris-boot/sparc/solaris/t1000-simple-atomic
Global frequency set at 2000000000 ticks per second Global frequency set at 2000000000 ticks per second
Exiting @ tick 2233777512 because m5_exit instruction encountered Exiting @ tick 2233777512 because m5_exit instruction encountered

12
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=DerivO3CPU type=DerivO3CPU
children=dcache fuPool icache l2cache toL2Bus tracer workload children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
BTBEntries=4096 BTBEntries=4096
BTBTagSize=16 BTBTagSize=16
LFSTSize=1024 LFSTSize=1024
@ -36,6 +36,7 @@ decodeToRenameDelay=1
decodeWidth=8 decodeWidth=8
defer_registration=false defer_registration=false
dispatchWidth=8 dispatchWidth=8
dtb=system.cpu.dtb
fetchToDecodeDelay=1 fetchToDecodeDelay=1
fetchTrapLatency=1 fetchTrapLatency=1
fetchWidth=8 fetchWidth=8
@ -53,6 +54,7 @@ iewToRenameDelay=1
instShiftAmt=2 instShiftAmt=2
issueToExecuteDelay=1 issueToExecuteDelay=1
issueWidth=8 issueWidth=8
itb=system.cpu.itb
localCtrBits=2 localCtrBits=2
localHistoryBits=11 localHistoryBits=11
localHistoryTableSize=2048 localHistoryTableSize=2048
@ -130,6 +132,10 @@ write_buffers=8
cpu_side=system.cpu.dcache_port cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1] mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=AlphaDTB
size=64
[system.cpu.fuPool] [system.cpu.fuPool]
type=FUPool type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
@ -303,6 +309,10 @@ write_buffers=8
cpu_side=system.cpu.icache_port cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0] mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=AlphaITB
size=48
[system.cpu.l2cache] [system.cpu.l2cache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615

510
tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
View file

@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits 538 # Number of BTB hits global.BPredUnit.BTBHits 562 # Number of BTB hits
global.BPredUnit.BTBLookups 1681 # Number of BTB lookups global.BPredUnit.BTBLookups 1725 # Number of BTB lookups
global.BPredUnit.RASInCorrect 51 # Number of incorrect RAS predictions. global.BPredUnit.RASInCorrect 51 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 412 # Number of conditional branches incorrect global.BPredUnit.condIncorrect 409 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 1149 # Number of conditional branches predicted global.BPredUnit.condPredicted 1184 # Number of conditional branches predicted
global.BPredUnit.lookups 1984 # Number of BP lookups global.BPredUnit.lookups 2029 # Number of BP lookups
global.BPredUnit.usedRAS 275 # Number of times the RAS was used to get a target. global.BPredUnit.usedRAS 277 # Number of times the RAS was used to get a target.
host_inst_rate 62494 # Simulator instruction rate (inst/s) host_inst_rate 9351 # Simulator instruction rate (inst/s)
host_mem_usage 196896 # Number of bytes of host memory used host_mem_usage 180452 # Number of bytes of host memory used
host_seconds 0.09 # Real time elapsed on the host host_seconds 0.60 # Real time elapsed on the host
host_tick_rate 50069310 # Simulator tick rate (ticks/s) host_tick_rate 7988790 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 10 # Number of conflicting loads. memdepunit.memDep.conflictingLoads 23 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 121 # Number of conflicting stores. memdepunit.memDep.conflictingStores 124 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 1979 # Number of loads inserted to the mem dependence unit. memdepunit.memDep.insertedLoads 2030 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 1190 # Number of stores inserted to the mem dependence unit. memdepunit.memDep.insertedStores 1236 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5623 # Number of instructions simulated sim_insts 5623 # Number of instructions simulated
sim_seconds 0.000005 # Number of seconds simulated sim_seconds 0.000005 # Number of seconds simulated
sim_ticks 4515000 # Number of ticks simulated sim_ticks 4806000 # Number of ticks simulated
system.cpu.commit.COM:branches 862 # Number of branches committed system.cpu.commit.COM:branches 862 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 81 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_lim_events 85 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 8177 system.cpu.commit.COM:committed_per_cycle.samples 8660
system.cpu.commit.COM:committed_per_cycle.min_value 0 system.cpu.commit.COM:committed_per_cycle.min_value 0
0 5854 7159.10% 0 6353 7336.03%
1 1205 1473.65% 1 1192 1376.44%
2 403 492.85% 2 402 464.20%
3 188 229.91% 3 185 213.63%
4 133 162.65% 4 132 152.42%
5 98 119.85% 5 93 107.39%
6 110 134.52% 6 110 127.02%
7 105 128.41% 7 108 124.71%
8 81 99.06% 8 85 98.15%
system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist system.cpu.commit.COM:committed_per_cycle.end_dist
@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 979 # Nu
system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 1791 # Number of memory references committed system.cpu.commit.COM:refs 1791 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 339 # The number of times a branch was mispredicted system.cpu.commit.branchMispredicts 336 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 4015 # The number of squashed insts skipped by commit system.cpu.commit.commitSquashedInsts 4234 # The number of squashed insts skipped by commit
system.cpu.committedInsts 5623 # Number of Instructions Simulated system.cpu.committedInsts 5623 # Number of Instructions Simulated
system.cpu.committedInsts_total 5623 # Number of Instructions Simulated system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
system.cpu.cpi 1.584030 # CPI: Cycles Per Instruction system.cpu.cpi 1.680420 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.584030 # CPI: Total CPI of All Threads system.cpu.cpi_total 1.680420 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 1516 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses 1535 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 10550 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency 10443.877551 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6350 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6357.142857 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 1416 # number of ReadReq hits system.cpu.dcache.ReadReq_hits 1437 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 1055000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency 1023500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.065963 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate 0.063844 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 100 # number of ReadReq misses system.cpu.dcache.ReadReq_misses 98 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 32 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits 31 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 635000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency 623000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.065963 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate 0.063844 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses 98 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 533 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 529 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 26660.919540 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency 27385.057471 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5781.609195 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5839.080460 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 446 # number of WriteReq hits system.cpu.dcache.WriteReq_hits 442 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 2319500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency 2382500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.163227 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate 0.164461 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 279 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 503000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency 508000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.163227 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.164461 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 10.843931 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 11.141176 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 2049 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses 2064 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 18045.454545 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency 18410.810811 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 6085.561497 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 6113.513514 # average overall mshr miss latency
system.cpu.dcache.demand_hits 1862 # number of demand (read+write) hits system.cpu.dcache.demand_hits 1879 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 3374500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency 3406000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.091264 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate 0.089632 # miss rate for demand accesses
system.cpu.dcache.demand_misses 187 # number of demand (read+write) misses system.cpu.dcache.demand_misses 185 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 311 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits 314 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 1138000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency 1131000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.091264 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate 0.089632 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 187 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses 185 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 2049 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses 2064 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 18045.454545 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency 18410.810811 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 6085.561497 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 6113.513514 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 1862 # number of overall hits system.cpu.dcache.overall_hits 1879 # number of overall hits
system.cpu.dcache.overall_miss_latency 3374500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency 3406000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.091264 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate 0.089632 # miss rate for overall accesses
system.cpu.dcache.overall_misses 187 # number of overall misses system.cpu.dcache.overall_misses 185 # number of overall misses
system.cpu.dcache.overall_mshr_hits 311 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits 314 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 1138000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency 1131000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.091264 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate 0.089632 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 187 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses 185 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -119,91 +119,103 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 170 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 111.683956 # Cycle average of tags in use system.cpu.dcache.tagsinuse 109.245747 # Cycle average of tags in use
system.cpu.dcache.total_refs 1876 # Total number of references to valid blocks. system.cpu.dcache.total_refs 1894 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 428 # Number of cycles decode is blocked system.cpu.decode.DECODE:BlockedCycles 428 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 81 # Number of times decode detected a branch misprediction system.cpu.decode.DECODE:BranchMispred 80 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 164 # Number of times decode resolved a branch system.cpu.decode.DECODE:BranchResolved 168 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 11204 # Number of instructions handled by decode system.cpu.decode.DECODE:DecodedInsts 11542 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 5725 # Number of cycles decode is idle system.cpu.decode.DECODE:IdleCycles 6127 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 1989 # Number of cycles decode is running system.cpu.decode.DECODE:RunCycles 2070 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 729 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashCycles 788 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 235 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:SquashedInsts 235 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 36 # Number of cycles decode is unblocking system.cpu.decode.DECODE:UnblockCycles 36 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 1984 # Number of branches that fetch encountered system.cpu.dtb.accesses 2656 # DTB accesses
system.cpu.fetch.CacheLines 1520 # Number of cache lines fetched system.cpu.dtb.acv 0 # DTB access violations
system.cpu.fetch.Cycles 3641 # Number of cycles fetch has run and was not squashing or blocked system.cpu.dtb.hits 2596 # DTB hits
system.cpu.fetch.IcacheSquashes 230 # Number of outstanding Icache misses that were squashed system.cpu.dtb.misses 60 # DTB misses
system.cpu.fetch.Insts 12195 # Number of instructions fetch has processed system.cpu.dtb.read_accesses 1652 # DTB read accesses
system.cpu.fetch.SquashCycles 444 # Number of cycles fetch has spent squashing system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.fetch.branchRate 0.222746 # Number of branch fetches per cycle system.cpu.dtb.read_hits 1615 # DTB read hits
system.cpu.fetch.icacheStallCycles 1520 # Number of cycles fetch is stalled on an Icache miss system.cpu.dtb.read_misses 37 # DTB read misses
system.cpu.fetch.predictedBranches 813 # Number of branches that fetch has predicted taken system.cpu.dtb.write_accesses 1004 # DTB write accesses
system.cpu.fetch.rate 1.369148 # Number of inst fetches per cycle system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 981 # DTB write hits
system.cpu.dtb.write_misses 23 # DTB write misses
system.cpu.fetch.Branches 2029 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 1542 # Number of cache lines fetched
system.cpu.fetch.Cycles 3746 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 226 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 12519 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 469 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.214732 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 1542 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 839 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.324902 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 8907 system.cpu.fetch.rateDist.samples 9449
system.cpu.fetch.rateDist.min_value 0 system.cpu.fetch.rateDist.min_value 0
0 6787 7619.85% 0 7275 7699.23%
1 178 199.84% 1 181 191.55%
2 167 187.49% 2 174 184.15%
3 149 167.28% 3 146 154.51%
4 210 235.77% 4 219 231.77%
5 157 176.27% 5 159 168.27%
6 180 202.09% 6 189 200.02%
7 101 113.39% 7 101 106.89%
8 978 1098.01% 8 1005 1063.60%
system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 1497 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses 1520 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 7812.101911 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 7745.954693 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 5500 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 5443.365696 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 1183 # number of ReadReq hits system.cpu.icache.ReadReq_hits 1211 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 2453000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency 2393500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.209753 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate 0.203289 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 314 # number of ReadReq misses system.cpu.icache.ReadReq_misses 309 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 23 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits 22 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 1727000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency 1682000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.209753 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate 0.203289 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 314 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses 309 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 3.767516 # Average number of references to valid blocks. system.cpu.icache.avg_refs 3.919094 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 1497 # number of demand (read+write) accesses system.cpu.icache.demand_accesses 1520 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 7812.101911 # average overall miss latency system.cpu.icache.demand_avg_miss_latency 7745.954693 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 5500 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 5443.365696 # average overall mshr miss latency
system.cpu.icache.demand_hits 1183 # number of demand (read+write) hits system.cpu.icache.demand_hits 1211 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 2453000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency 2393500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.209753 # miss rate for demand accesses system.cpu.icache.demand_miss_rate 0.203289 # miss rate for demand accesses
system.cpu.icache.demand_misses 314 # number of demand (read+write) misses system.cpu.icache.demand_misses 309 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 23 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits 22 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 1727000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency 1682000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.209753 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate 0.203289 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 314 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses 309 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 1497 # number of overall (read+write) accesses system.cpu.icache.overall_accesses 1520 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 7812.101911 # average overall miss latency system.cpu.icache.overall_avg_miss_latency 7745.954693 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 5500 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 5443.365696 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 1183 # number of overall hits system.cpu.icache.overall_hits 1211 # number of overall hits
system.cpu.icache.overall_miss_latency 2453000 # number of overall miss cycles system.cpu.icache.overall_miss_latency 2393500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.209753 # miss rate for overall accesses system.cpu.icache.overall_miss_rate 0.203289 # miss rate for overall accesses
system.cpu.icache.overall_misses 314 # number of overall misses system.cpu.icache.overall_misses 309 # number of overall misses
system.cpu.icache.overall_mshr_hits 23 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits 22 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 1727000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency 1682000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.209753 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate 0.203289 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 314 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses 309 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -216,61 +228,61 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 309 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 165.376334 # Cycle average of tags in use system.cpu.icache.tagsinuse 164.253671 # Cycle average of tags in use
system.cpu.icache.total_refs 1183 # Total number of references to valid blocks. system.cpu.icache.total_refs 1211 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 88946 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.idleCycles 110443 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 1172 # Number of branches executed system.cpu.iew.EXEC:branches 1199 # Number of branches executed
system.cpu.iew.EXEC:nop 45 # number of nop insts executed system.cpu.iew.EXEC:nop 72 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.880207 # Inst execution rate system.cpu.iew.EXEC:rate 0.848450 # Inst execution rate
system.cpu.iew.EXEC:refs 2591 # number of memory reference insts executed system.cpu.iew.EXEC:refs 2660 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 974 # Number of stores executed system.cpu.iew.EXEC:stores 1006 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 5292 # num instructions consuming a value system.cpu.iew.WB:consumers 5426 # num instructions consuming a value
system.cpu.iew.WB:count 7505 # cumulative count of insts written-back system.cpu.iew.WB:count 7664 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.745276 # average fanout of values written-back system.cpu.iew.WB:fanout 0.742905 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 3944 # num instructions producing a value system.cpu.iew.WB:producers 4031 # num instructions producing a value
system.cpu.iew.WB:rate 0.842596 # insts written-back per cycle system.cpu.iew.WB:rate 0.811091 # insts written-back per cycle
system.cpu.iew.WB:sent 7591 # cumulative count of insts sent to commit system.cpu.iew.WB:sent 7781 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 401 # Number of branch mispredicts detected at execute system.cpu.iew.branchMispredicts 401 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 1979 # Number of dispatched load instructions system.cpu.iew.iewDispLoadInsts 2030 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 194 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispSquashedInsts 173 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 1190 # Number of dispatched store instructions system.cpu.iew.iewDispStoreInsts 1236 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 9672 # Number of instructions dispatched to IQ system.cpu.iew.iewDispatchedInsts 9996 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 1617 # Number of load instructions executed system.cpu.iew.iewExecLoadInsts 1654 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 358 # Number of squashed instructions skipped in execute system.cpu.iew.iewExecSquashedInsts 366 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 7840 # Number of executed instructions system.cpu.iew.iewExecutedInsts 8017 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 729 # Number of cycles IEW is squashing system.cpu.iew.iewSquashCycles 788 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 47 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.forwLoads 48 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 66 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.memOrderViolation 68 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 1000 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedLoads 1051 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 378 # Number of stores squashed system.cpu.iew.lsq.thread.0.squashedStores 424 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 66 # Number of memory order violations system.cpu.iew.memOrderViolationEvents 68 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 295 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedTakenIncorrect 106 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.631301 # IPC: Instructions Per Cycle system.cpu.ipc 0.595089 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.631301 # IPC: Total IPC of All Threads system.cpu.ipc_total 0.595089 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 8198 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0 8383 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 2 0.02% # Type of FU issued No_OpClass 2 0.02% # Type of FU issued
IntAlu 5452 66.50% # Type of FU issued IntAlu 5559 66.31% # Type of FU issued
IntMult 1 0.01% # Type of FU issued IntMult 1 0.01% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued
FloatAdd 2 0.02% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued
@ -279,16 +291,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist
FloatMult 0 0.00% # Type of FU issued FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued
MemRead 1744 21.27% # Type of FU issued MemRead 1786 21.31% # Type of FU issued
MemWrite 997 12.16% # Type of FU issued MemWrite 1033 12.32% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 102 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_cnt 102 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.012442 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_busy_rate 0.012167 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available No_OpClass 0 0.00% # attempts to use FU when none available
IntAlu 0 0.00% # attempts to use FU when none available IntAlu 1 0.98% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available
@ -297,96 +309,100 @@ system.cpu.iq.ISSUE:fu_full.start_dist
FloatMult 0 0.00% # attempts to use FU when none available FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available
MemRead 67 65.69% # attempts to use FU when none available MemRead 66 64.71% # attempts to use FU when none available
MemWrite 35 34.31% # attempts to use FU when none available MemWrite 35 34.31% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples 8907 system.cpu.iq.ISSUE:issued_per_cycle.samples 9449
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 5630 6320.87% 0 6104 6459.94%
1 1096 1230.49% 1 1119 1184.25%
2 792 889.19% 2 811 858.29%
3 582 653.42% 3 592 626.52%
4 464 520.94% 4 460 486.82%
5 200 224.54% 5 212 224.36%
6 99 111.15% 6 105 111.12%
7 30 33.68% 7 32 33.87%
8 14 15.72% 8 14 14.82%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 0.920400 # Inst issue rate system.cpu.iq.ISSUE:rate 0.887184 # Inst issue rate
system.cpu.iq.iqInstsAdded 9604 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsAdded 9901 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 8198 # Number of instructions issued system.cpu.iq.iqInstsIssued 8383 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 3664 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsExamined 3948 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 22 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 2365 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedOperandsExamined 2574 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) system.cpu.itb.accesses 1572 # ITB accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency 4486.301370 # average ReadExReq miss latency system.cpu.itb.acv 0 # ITB acv
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2486.301370 # average ReadExReq mshr miss latency system.cpu.itb.hits 1542 # ITB hits
system.cpu.itb.misses 30 # ITB misses
system.cpu.l2cache.ReadExReq_accesses 72 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 4548.611111 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2548.611111 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 327500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency 327500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses 72 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 181500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency 183500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 72 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 414 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses 407 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 4450.242718 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency 4400.246305 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2450.242718 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2400.246305 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1833500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency 1786500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.995169 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate 0.997543 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 412 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses 406 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1009500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency 974500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995169 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997543 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 412 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses 406 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4214.285714 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency 4266.666667 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2214.285714 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2266.666667 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 59000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency 64000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency 34000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.005025 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 0.002558 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 487 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses 479 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 4455.670103 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency 4422.594142 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2455.670103 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 2422.594142 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 2161000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency 2114000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.995893 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate 0.997912 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 485 # number of demand (read+write) misses system.cpu.l2cache.demand_misses 478 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 1191000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 1158000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.995893 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate 0.997912 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 485 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses 478 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 487 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses 479 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 4455.670103 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency 4422.594142 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2455.670103 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 2422.594142 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 2 # number of overall hits system.cpu.l2cache.overall_hits 1 # number of overall hits
system.cpu.l2cache.overall_miss_latency 2161000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency 2114000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.995893 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate 0.997912 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 485 # number of overall misses system.cpu.l2cache.overall_misses 478 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 1191000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency 1158000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.995893 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate 0.997912 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 485 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses 478 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -399,29 +415,29 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 398 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 391 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 221.319862 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 218.025629 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.numCycles 8907 # number of cpu cycles simulated system.cpu.numCycles 9449 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 50 # Number of cycles rename is blocking system.cpu.rename.RENAME:BlockCycles 50 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
system.cpu.rename.RENAME:IdleCycles 5884 # Number of cycles rename is idle system.cpu.rename.RENAME:IdleCycles 6291 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 71 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:LSQFullEvents 71 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 13715 # Number of register rename lookups that rename has made system.cpu.rename.RENAME:RenameLookups 14101 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 10735 # Number of instructions processed by rename system.cpu.rename.RENAME:RenamedInsts 11035 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 8030 # Number of destination operands rename has renamed system.cpu.rename.RENAME:RenamedOperands 8205 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 1846 # Number of cycles rename is running system.cpu.rename.RENAME:RunCycles 1922 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 729 # Number of cycles rename is squashing system.cpu.rename.RENAME:SquashCycles 788 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 122 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UnblockCycles 122 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 3979 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:UndoneMaps 4154 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 276 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializeStallCycles 276 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 532 # count of insts added to the skid buffer system.cpu.rename.RENAME:skidInsts 532 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed
system.cpu.timesIdled 54 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 57 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

8
tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
View file

@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Aug 12 2007 00:26:55 M5 compiled Aug 13 2007 17:39:24
M5 started Sun Aug 12 00:29:40 2007 M5 started Mon Aug 13 17:39:25 2007
M5 executing on zeep M5 executing on nacho
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
Exiting @ tick 4515000 because target called exit() Exiting @ tick 4806000 because target called exit()

14
tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
View file

@ -11,12 +11,14 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
children=tracer workload children=dtb itb tracer workload
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false defer_registration=false
dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -31,6 +33,14 @@ workload=system.cpu.workload
dcache_port=system.membus.port[2] dcache_port=system.membus.port[2]
icache_port=system.membus.port[1] icache_port=system.membus.port[1]
[system.cpu.dtb]
type=AlphaDTB
size=64
[system.cpu.itb]
type=AlphaITB
size=48
[system.cpu.tracer] [system.cpu.tracer]
type=ExeTracer type=ExeTracer
@ -41,7 +51,7 @@ cwd=
egid=100 egid=100
env= env=
euid=100 euid=100
executable=tests/test-progs/hello/bin/alpha/linux/hello executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100 gid=100
input=cin input=cin
output=cout output=cout

34
tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt
View file

@ -1,18 +1,34 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 109073 # Simulator instruction rate (inst/s) host_inst_rate 274181 # Simulator instruction rate (inst/s)
host_mem_usage 148564 # Number of bytes of host memory used host_mem_usage 172576 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host host_seconds 0.02 # Real time elapsed on the host
host_tick_rate 54123810 # Simulator tick rate (ticks/s) host_tick_rate 135418658 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5642 # Number of instructions simulated sim_insts 5641 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated sim_seconds 0.000003 # Number of seconds simulated
sim_ticks 2820500 # Number of ticks simulated sim_ticks 2833500 # Number of ticks simulated
system.cpu.dtb.accesses 1801 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.dtb.hits 1791 # DTB hits
system.cpu.dtb.misses 10 # DTB misses
system.cpu.dtb.read_accesses 986 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 979 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.write_accesses 815 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 812 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 5668 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 5651 # ITB hits
system.cpu.itb.misses 17 # ITB misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 5642 # number of cpu cycles simulated system.cpu.numCycles 5668 # number of cpu cycles simulated
system.cpu.num_insts 5642 # Number of instructions executed system.cpu.num_insts 5641 # Number of instructions executed
system.cpu.num_refs 1792 # Number of memory references system.cpu.num_refs 1801 # Number of memory references
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

8
tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout
View file

@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Aug 3 2007 03:56:47 M5 compiled Aug 14 2007 17:36:58
M5 started Fri Aug 3 04:17:12 2007 M5 started Tue Aug 14 17:40:03 2007
M5 executing on zizzer.eecs.umich.edu M5 executing on nacho
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
Exiting @ tick 2820500 because target called exit() Exiting @ tick 2833500 because target called exit()

14
tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
View file

@ -11,12 +11,14 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=TimingSimpleCPU type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus tracer workload children=dcache dtb icache itb l2cache toL2Bus tracer workload
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false defer_registration=false
dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -65,6 +67,10 @@ write_buffers=8
cpu_side=system.cpu.dcache_port cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1] mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=AlphaDTB
size=64
[system.cpu.icache] [system.cpu.icache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615
@ -101,6 +107,10 @@ write_buffers=8
cpu_side=system.cpu.icache_port cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0] mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=AlphaITB
size=48
[system.cpu.l2cache] [system.cpu.l2cache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615
@ -156,7 +166,7 @@ cwd=
egid=100 egid=100
env= env=
euid=100 euid=100
executable=tests/test-progs/hello/bin/alpha/linux/hello executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100 gid=100
input=cin input=cin
output=cout output=cout

66
tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 334797 # Simulator instruction rate (inst/s) host_inst_rate 243703 # Simulator instruction rate (inst/s)
host_mem_usage 196348 # Number of bytes of host memory used host_mem_usage 179944 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host host_seconds 0.02 # Real time elapsed on the host
host_tick_rate 1064082508 # Simulator tick rate (ticks/s) host_tick_rate 781539770 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5642 # Number of instructions simulated sim_insts 5641 # Number of instructions simulated
sim_seconds 0.000018 # Number of seconds simulated sim_seconds 0.000018 # Number of seconds simulated
sim_ticks 18365000 # Number of ticks simulated sim_ticks 18374000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 979 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses 979 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency
@ -76,53 +76,65 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 102.396682 # Cycle average of tags in use system.cpu.dcache.tagsinuse 102.386256 # Cycle average of tags in use
system.cpu.dcache.total_refs 1626 # Total number of references to valid blocks. system.cpu.dcache.total_refs 1626 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_accesses 5643 # number of ReadReq accesses(hits+misses) system.cpu.dtb.accesses 1801 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.dtb.hits 1791 # DTB hits
system.cpu.dtb.misses 10 # DTB misses
system.cpu.dtb.read_accesses 986 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 979 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.write_accesses 815 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 812 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.icache.ReadReq_accesses 5652 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 24956.678700 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 24956.678700 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 22956.678700 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 22956.678700 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 5366 # number of ReadReq hits system.cpu.icache.ReadReq_hits 5375 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 6913000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency 6913000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.049087 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate 0.049009 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 277 # number of ReadReq misses system.cpu.icache.ReadReq_misses 277 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 6359000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency 6359000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.049087 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate 0.049009 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 277 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses 277 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 19.371841 # Average number of references to valid blocks. system.cpu.icache.avg_refs 19.404332 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 5643 # number of demand (read+write) accesses system.cpu.icache.demand_accesses 5652 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 24956.678700 # average overall miss latency system.cpu.icache.demand_avg_miss_latency 24956.678700 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 22956.678700 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 22956.678700 # average overall mshr miss latency
system.cpu.icache.demand_hits 5366 # number of demand (read+write) hits system.cpu.icache.demand_hits 5375 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 6913000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency 6913000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.049087 # miss rate for demand accesses system.cpu.icache.demand_miss_rate 0.049009 # miss rate for demand accesses
system.cpu.icache.demand_misses 277 # number of demand (read+write) misses system.cpu.icache.demand_misses 277 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 6359000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency 6359000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.049087 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate 0.049009 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 277 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses 277 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 5643 # number of overall (read+write) accesses system.cpu.icache.overall_accesses 5652 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 24956.678700 # average overall miss latency system.cpu.icache.overall_avg_miss_latency 24956.678700 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 22956.678700 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 22956.678700 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 5366 # number of overall hits system.cpu.icache.overall_hits 5375 # number of overall hits
system.cpu.icache.overall_miss_latency 6913000 # number of overall miss cycles system.cpu.icache.overall_miss_latency 6913000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.049087 # miss rate for overall accesses system.cpu.icache.overall_miss_rate 0.049009 # miss rate for overall accesses
system.cpu.icache.overall_misses 277 # number of overall misses system.cpu.icache.overall_misses 277 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 6359000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency 6359000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.049087 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate 0.049009 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 277 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses 277 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
@ -138,11 +150,15 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 277 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 277 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 128.096333 # Cycle average of tags in use system.cpu.icache.tagsinuse 128.084203 # Cycle average of tags in use
system.cpu.icache.total_refs 5366 # Total number of references to valid blocks. system.cpu.icache.total_refs 5375 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 5669 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 5652 # ITB hits
system.cpu.itb.misses 17 # ITB misses
system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
@ -219,14 +235,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 354 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 354 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 177.517189 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 177.499846 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 18365000 # number of cpu cycles simulated system.cpu.numCycles 18374000 # number of cpu cycles simulated
system.cpu.num_insts 5642 # Number of instructions executed system.cpu.num_insts 5641 # Number of instructions executed
system.cpu.num_refs 1792 # Number of memory references system.cpu.num_refs 1801 # Number of memory references
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

8
tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
View file

@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Aug 12 2007 00:26:55 M5 compiled Aug 14 2007 17:58:14
M5 started Sun Aug 12 00:29:41 2007 M5 started Tue Aug 14 17:59:07 2007
M5 executing on zeep M5 executing on nacho
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
Exiting @ tick 18365000 because target called exit() Exiting @ tick 18374000 because target called exit()

12
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=DerivO3CPU type=DerivO3CPU
children=dcache fuPool icache l2cache toL2Bus tracer workload children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
BTBEntries=4096 BTBEntries=4096
BTBTagSize=16 BTBTagSize=16
LFSTSize=1024 LFSTSize=1024
@ -36,6 +36,7 @@ decodeToRenameDelay=1
decodeWidth=8 decodeWidth=8
defer_registration=false defer_registration=false
dispatchWidth=8 dispatchWidth=8
dtb=system.cpu.dtb
fetchToDecodeDelay=1 fetchToDecodeDelay=1
fetchTrapLatency=1 fetchTrapLatency=1
fetchWidth=8 fetchWidth=8
@ -53,6 +54,7 @@ iewToRenameDelay=1
instShiftAmt=2 instShiftAmt=2
issueToExecuteDelay=1 issueToExecuteDelay=1
issueWidth=8 issueWidth=8
itb=system.cpu.itb
localCtrBits=2 localCtrBits=2
localHistoryBits=11 localHistoryBits=11
localHistoryTableSize=2048 localHistoryTableSize=2048
@ -130,6 +132,10 @@ write_buffers=8
cpu_side=system.cpu.dcache_port cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1] mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=AlphaDTB
size=64
[system.cpu.fuPool] [system.cpu.fuPool]
type=FUPool type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
@ -303,6 +309,10 @@ write_buffers=8
cpu_side=system.cpu.icache_port cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0] mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=AlphaITB
size=48
[system.cpu.l2cache] [system.cpu.l2cache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615

460
tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
View file

@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits 143 # Number of BTB hits global.BPredUnit.BTBHits 156 # Number of BTB hits
global.BPredUnit.BTBLookups 610 # Number of BTB lookups global.BPredUnit.BTBLookups 642 # Number of BTB lookups
global.BPredUnit.RASInCorrect 32 # Number of incorrect RAS predictions. global.BPredUnit.RASInCorrect 35 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 212 # Number of conditional branches incorrect global.BPredUnit.condIncorrect 213 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 394 # Number of conditional branches predicted global.BPredUnit.condPredicted 401 # Number of conditional branches predicted
global.BPredUnit.lookups 779 # Number of BP lookups global.BPredUnit.lookups 824 # Number of BP lookups
global.BPredUnit.usedRAS 155 # Number of times the RAS was used to get a target. global.BPredUnit.usedRAS 163 # Number of times the RAS was used to get a target.
host_inst_rate 72558 # Simulator instruction rate (inst/s) host_inst_rate 31893 # Simulator instruction rate (inst/s)
host_mem_usage 196048 # Number of bytes of host memory used host_mem_usage 179460 # Number of bytes of host memory used
host_seconds 0.03 # Real time elapsed on the host host_seconds 0.08 # Real time elapsed on the host
host_tick_rate 63572637 # Simulator tick rate (ticks/s) host_tick_rate 32096529 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 8 # Number of conflicting loads. memdepunit.memDep.conflictingLoads 7 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. memdepunit.memDep.conflictingStores 7 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 636 # Number of loads inserted to the mem dependence unit. memdepunit.memDep.insertedLoads 698 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 369 # Number of stores inserted to the mem dependence unit. memdepunit.memDep.insertedStores 412 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2387 # Number of instructions simulated sim_insts 2387 # Number of instructions simulated
sim_seconds 0.000002 # Number of seconds simulated sim_seconds 0.000002 # Number of seconds simulated
sim_ticks 2104000 # Number of ticks simulated sim_ticks 2410000 # Number of ticks simulated
system.cpu.commit.COM:branches 396 # Number of branches committed system.cpu.commit.COM:branches 396 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 35 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_lim_events 32 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 3945 system.cpu.commit.COM:committed_per_cycle.samples 4452
system.cpu.commit.COM:committed_per_cycle.min_value 0 system.cpu.commit.COM:committed_per_cycle.min_value 0
0 2992 7584.28% 0 3490 7839.17%
1 255 646.39% 1 258 579.51%
2 335 849.18% 2 340 763.70%
3 139 352.34% 3 140 314.47%
4 66 167.30% 4 70 157.23%
5 69 174.90% 5 70 157.23%
6 33 83.65% 6 32 71.88%
7 21 53.23% 7 20 44.92%
8 35 88.72% 8 32 71.88%
system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist system.cpu.commit.COM:committed_per_cycle.end_dist
@ -43,69 +43,69 @@ system.cpu.commit.COM:loads 415 # Nu
system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 709 # Number of memory references committed system.cpu.commit.COM:refs 709 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 131 # The number of times a branch was mispredicted system.cpu.commit.branchMispredicts 132 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 1134 # The number of squashed insts skipped by commit system.cpu.commit.commitSquashedInsts 1380 # The number of squashed insts skipped by commit
system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts 2387 # Number of Instructions Simulated
system.cpu.committedInsts_total 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
system.cpu.cpi 1.747382 # CPI: Cycles Per Instruction system.cpu.cpi 1.984080 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.747382 # CPI: Total CPI of All Threads system.cpu.cpi_total 1.984080 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 519 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses 528 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 8729.508197 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency 8639.344262 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5745.901639 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5655.737705 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 458 # number of ReadReq hits system.cpu.dcache.ReadReq_hits 467 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 532500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency 527000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.117534 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate 0.115530 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 61 # number of ReadReq misses system.cpu.dcache.ReadReq_misses 61 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 350500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency 345000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.117534 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate 0.115530 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 240 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 240 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 18810.810811 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency 18297.297297 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6202.702703 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5986.486486 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 203 # number of WriteReq hits system.cpu.dcache.WriteReq_hits 203 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 696000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency 677000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.154167 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate 0.154167 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 37 # number of WriteReq misses system.cpu.dcache.WriteReq_misses 37 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 54 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits 54 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 229500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency 221500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.154167 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.154167 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 37 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 37 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 7.929412 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 8.035294 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 759 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses 768 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 12535.714286 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency 12285.714286 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 5918.367347 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 5780.612245 # average overall mshr miss latency
system.cpu.dcache.demand_hits 661 # number of demand (read+write) hits system.cpu.dcache.demand_hits 670 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 1228500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency 1204000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.129117 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate 0.127604 # miss rate for demand accesses
system.cpu.dcache.demand_misses 98 # number of demand (read+write) misses system.cpu.dcache.demand_misses 98 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 64 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits 64 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 580000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency 566500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.129117 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate 0.127604 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 98 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses 98 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 759 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses 768 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 12535.714286 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency 12285.714286 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 5918.367347 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 5780.612245 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 661 # number of overall hits system.cpu.dcache.overall_hits 670 # number of overall hits
system.cpu.dcache.overall_miss_latency 1228500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency 1204000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.129117 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate 0.127604 # miss rate for overall accesses
system.cpu.dcache.overall_misses 98 # number of overall misses system.cpu.dcache.overall_misses 98 # number of overall misses
system.cpu.dcache.overall_mshr_hits 64 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits 64 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 580000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency 566500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.129117 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate 0.127604 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 98 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses 98 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
@ -121,89 +121,101 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 50.690606 # Cycle average of tags in use system.cpu.dcache.tagsinuse 47.072215 # Cycle average of tags in use
system.cpu.dcache.total_refs 674 # Total number of references to valid blocks. system.cpu.dcache.total_refs 683 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 91 # Number of cycles decode is blocked system.cpu.decode.DECODE:BlockedCycles 93 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 83 # Number of times decode detected a branch misprediction system.cpu.decode.DECODE:BranchMispred 83 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 126 # Number of times decode resolved a branch system.cpu.decode.DECODE:BranchResolved 135 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 4236 # Number of instructions handled by decode system.cpu.decode.DECODE:DecodedInsts 4564 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 3045 # Number of cycles decode is idle system.cpu.decode.DECODE:IdleCycles 3475 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 809 # Number of cycles decode is running system.cpu.decode.DECODE:RunCycles 884 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 225 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashCycles 283 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 304 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:SquashedInsts 303 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 779 # Number of branches that fetch encountered system.cpu.dtb.accesses 931 # DTB accesses
system.cpu.fetch.CacheLines 691 # Number of cache lines fetched system.cpu.dtb.acv 1 # DTB access violations
system.cpu.fetch.Cycles 1534 # Number of cycles fetch has run and was not squashing or blocked system.cpu.dtb.hits 904 # DTB hits
system.cpu.fetch.IcacheSquashes 112 # Number of outstanding Icache misses that were squashed system.cpu.dtb.misses 27 # DTB misses
system.cpu.fetch.Insts 4961 # Number of instructions fetch has processed system.cpu.dtb.read_accesses 575 # DTB read accesses
system.cpu.fetch.SquashCycles 223 # Number of cycles fetch has spent squashing system.cpu.dtb.read_acv 1 # DTB read access violations
system.cpu.fetch.branchRate 0.186766 # Number of branch fetches per cycle system.cpu.dtb.read_hits 563 # DTB read hits
system.cpu.fetch.icacheStallCycles 691 # Number of cycles fetch is stalled on an Icache miss system.cpu.dtb.read_misses 12 # DTB read misses
system.cpu.fetch.predictedBranches 298 # Number of branches that fetch has predicted taken system.cpu.dtb.write_accesses 356 # DTB write accesses
system.cpu.fetch.rate 1.189403 # Number of inst fetches per cycle system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 341 # DTB write hits
system.cpu.dtb.write_misses 15 # DTB write misses
system.cpu.fetch.Branches 824 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 707 # Number of cache lines fetched
system.cpu.fetch.Cycles 1626 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 101 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 5268 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 242 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.173986 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 707 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 319 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.112331 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 4171 system.cpu.fetch.rateDist.samples 4736
system.cpu.fetch.rateDist.min_value 0 system.cpu.fetch.rateDist.min_value 0
0 3330 7983.70% 0 3845 8118.67%
1 36 86.31% 1 38 80.24%
2 85 203.79% 2 85 179.48%
3 57 136.66% 3 63 133.02%
4 109 261.33% 4 118 249.16%
5 54 129.47% 5 55 116.13%
6 40 95.90% 6 42 88.68%
7 42 100.70% 7 48 101.35%
8 418 1002.16% 8 442 933.28%
system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 674 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses 692 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 7774.193548 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 7648.351648 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 5451.612903 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 5370.879121 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 488 # number of ReadReq hits system.cpu.icache.ReadReq_hits 510 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 1446000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency 1392000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.275964 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate 0.263006 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 186 # number of ReadReq misses system.cpu.icache.ReadReq_misses 182 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 17 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 1014000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency 977500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.275964 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate 0.263006 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 186 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses 182 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 2.623656 # Average number of references to valid blocks. system.cpu.icache.avg_refs 2.802198 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 674 # number of demand (read+write) accesses system.cpu.icache.demand_accesses 692 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 7774.193548 # average overall miss latency system.cpu.icache.demand_avg_miss_latency 7648.351648 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 5451.612903 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 5370.879121 # average overall mshr miss latency
system.cpu.icache.demand_hits 488 # number of demand (read+write) hits system.cpu.icache.demand_hits 510 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 1446000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency 1392000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.275964 # miss rate for demand accesses system.cpu.icache.demand_miss_rate 0.263006 # miss rate for demand accesses
system.cpu.icache.demand_misses 186 # number of demand (read+write) misses system.cpu.icache.demand_misses 182 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 17 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits 15 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 1014000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency 977500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.275964 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate 0.263006 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 186 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 674 # number of overall (read+write) accesses system.cpu.icache.overall_accesses 692 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 7774.193548 # average overall miss latency system.cpu.icache.overall_avg_miss_latency 7648.351648 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 5451.612903 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 5370.879121 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 488 # number of overall hits system.cpu.icache.overall_hits 510 # number of overall hits
system.cpu.icache.overall_miss_latency 1446000 # number of overall miss cycles system.cpu.icache.overall_miss_latency 1392000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.275964 # miss rate for overall accesses system.cpu.icache.overall_miss_rate 0.263006 # miss rate for overall accesses
system.cpu.icache.overall_misses 186 # number of overall misses system.cpu.icache.overall_misses 182 # number of overall misses
system.cpu.icache.overall_mshr_hits 17 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits 15 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 1014000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency 977500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.275964 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate 0.263006 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 186 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses 182 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -216,61 +228,61 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 186 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 182 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 102.643576 # Cycle average of tags in use system.cpu.icache.tagsinuse 92.900452 # Cycle average of tags in use
system.cpu.icache.total_refs 488 # Total number of references to valid blocks. system.cpu.icache.total_refs 510 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 26984 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.idleCycles 56472 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 522 # Number of branches executed system.cpu.iew.EXEC:branches 538 # Number of branches executed
system.cpu.iew.EXEC:nop 242 # number of nop insts executed system.cpu.iew.EXEC:nop 274 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.736514 # Inst execution rate system.cpu.iew.EXEC:rate 0.670608 # Inst execution rate
system.cpu.iew.EXEC:refs 896 # number of memory reference insts executed system.cpu.iew.EXEC:refs 934 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 333 # Number of stores executed system.cpu.iew.EXEC:stores 356 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 1736 # num instructions consuming a value system.cpu.iew.WB:consumers 1781 # num instructions consuming a value
system.cpu.iew.WB:count 3002 # cumulative count of insts written-back system.cpu.iew.WB:count 3084 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.793779 # average fanout of values written-back system.cpu.iew.WB:fanout 0.794497 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 1378 # num instructions producing a value system.cpu.iew.WB:producers 1415 # num instructions producing a value
system.cpu.iew.WB:rate 0.719731 # insts written-back per cycle system.cpu.iew.WB:rate 0.651182 # insts written-back per cycle
system.cpu.iew.WB:sent 3020 # cumulative count of insts sent to commit system.cpu.iew.WB:sent 3123 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 147 # Number of branch mispredicts detected at execute system.cpu.iew.branchMispredicts 149 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 636 # Number of dispatched load instructions system.cpu.iew.iewDispLoadInsts 698 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 85 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispSquashedInsts 83 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 369 # Number of dispatched store instructions system.cpu.iew.iewDispStoreInsts 412 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 3727 # Number of instructions dispatched to IQ system.cpu.iew.iewDispatchedInsts 4056 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 563 # Number of load instructions executed system.cpu.iew.iewExecLoadInsts 578 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 108 # Number of squashed instructions skipped in execute system.cpu.iew.iewExecSquashedInsts 105 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 3072 # Number of executed instructions system.cpu.iew.iewExecutedInsts 3176 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 225 # Number of cycles IEW is squashing system.cpu.iew.iewSquashCycles 283 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 25 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.forwLoads 25 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 13 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.memOrderViolation 11 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 221 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedLoads 283 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 75 # Number of stores squashed system.cpu.iew.lsq.thread.0.squashedStores 118 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 99 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 97 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 48 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedTakenIncorrect 52 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.572285 # IPC: Instructions Per Cycle system.cpu.ipc 0.504012 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.572285 # IPC: Total IPC of All Threads system.cpu.ipc_total 0.504012 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 3180 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0 3281 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 0 0.00% # Type of FU issued No_OpClass 0 0.00% # Type of FU issued
IntAlu 2258 71.01% # Type of FU issued IntAlu 2319 70.68% # Type of FU issued
IntMult 1 0.03% # Type of FU issued IntMult 1 0.03% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued
FloatAdd 0 0.00% # Type of FU issued FloatAdd 0 0.00% # Type of FU issued
@ -279,16 +291,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist
FloatMult 0 0.00% # Type of FU issued FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued
MemRead 581 18.27% # Type of FU issued MemRead 597 18.20% # Type of FU issued
MemWrite 340 10.69% # Type of FU issued MemWrite 364 11.09% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 36 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.011321 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_busy_rate 0.010667 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available No_OpClass 0 0.00% # attempts to use FU when none available
IntAlu 2 5.56% # attempts to use FU when none available IntAlu 1 2.86% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available
@ -297,59 +309,63 @@ system.cpu.iq.ISSUE:fu_full.start_dist
FloatMult 0 0.00% # attempts to use FU when none available FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available
MemRead 12 33.33% # attempts to use FU when none available MemRead 12 34.29% # attempts to use FU when none available
MemWrite 22 61.11% # attempts to use FU when none available MemWrite 22 62.86% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples 4171 system.cpu.iq.ISSUE:issued_per_cycle.samples 4736
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 2877 6897.63% 0 3384 7145.27%
1 465 1114.84% 1 494 1043.07%
2 300 719.25% 2 314 663.01%
3 228 546.63% 3 237 500.42%
4 154 369.22% 4 163 344.17%
5 89 213.38% 5 88 185.81%
6 40 95.90% 6 40 84.46%
7 14 33.57% 7 12 25.34%
8 4 9.59% 8 4 8.45%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 0.762407 # Inst issue rate system.cpu.iq.ISSUE:rate 0.692779 # Inst issue rate
system.cpu.iq.iqInstsAdded 3479 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsAdded 3776 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 3180 # Number of instructions issued system.cpu.iq.iqInstsIssued 3281 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 944 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsExamined 1238 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 473 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedOperandsExamined 742 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses 735 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 707 # ITB hits
system.cpu.itb.misses 28 # ITB misses
system.cpu.l2cache.ReadExReq_accesses 24 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 24 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 4750 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency 4604.166667 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2750 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2604.166667 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 114000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency 110500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 24 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses 24 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 66000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency 62500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 247 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses 243 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 4354.251012 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency 4304.526749 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2354.251012 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2304.526749 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_miss_latency 1075500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency 1046000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 247 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses 243 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 581500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency 560000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 247 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses 243 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4250 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency 4178.571429 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2250 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2178.571429 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 59500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency 58500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency 30500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -360,32 +376,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 271 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses 267 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 4389.298893 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency 4331.460674 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2389.298893 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 2331.460674 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 1189500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency 1156500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 271 # number of demand (read+write) misses system.cpu.l2cache.demand_misses 267 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 647500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 622500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 271 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses 267 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 271 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses 267 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 4389.298893 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency 4331.460674 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2389.298893 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 2331.460674 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 0 # number of overall hits system.cpu.l2cache.overall_hits 0 # number of overall hits
system.cpu.l2cache.overall_miss_latency 1189500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency 1156500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 271 # number of overall misses system.cpu.l2cache.overall_misses 267 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 647500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency 622500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 271 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses 267 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -398,28 +414,28 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 233 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 229 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 127.304233 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 115.687599 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.numCycles 4171 # number of cpu cycles simulated system.cpu.numCycles 4736 # number of cpu cycles simulated
system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed
system.cpu.rename.RENAME:IdleCycles 3117 # Number of cycles rename is idle system.cpu.rename.RENAME:IdleCycles 3552 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:LSQFullEvents 2 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 4657 # Number of register rename lookups that rename has made system.cpu.rename.RENAME:RenameLookups 4989 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 4106 # Number of instructions processed by rename system.cpu.rename.RENAME:RenamedInsts 4410 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 2936 # Number of destination operands rename has renamed system.cpu.rename.RENAME:RenamedOperands 3154 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 738 # Number of cycles rename is running system.cpu.rename.RENAME:RunCycles 808 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 225 # Number of cycles rename is squashing system.cpu.rename.RENAME:SquashCycles 283 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 7 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UnblockCycles 9 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 1168 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:UndoneMaps 1386 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 84 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializeStallCycles 84 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 50 # count of insts added to the skid buffer system.cpu.rename.RENAME:skidInsts 60 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed
system.cpu.timesIdled 16 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 28 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

8
tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
View file

@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Aug 12 2007 00:26:55 M5 compiled Aug 13 2007 17:39:24
M5 started Sun Aug 12 00:29:41 2007 M5 started Mon Aug 13 17:39:27 2007
M5 executing on zeep M5 executing on nacho
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
Exiting @ tick 2104000 because target called exit() Exiting @ tick 2410000 because target called exit()

14
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -11,12 +11,14 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
children=tracer workload children=dtb itb tracer workload
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false defer_registration=false
dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -31,6 +33,14 @@ workload=system.cpu.workload
dcache_port=system.membus.port[2] dcache_port=system.membus.port[2]
icache_port=system.membus.port[1] icache_port=system.membus.port[1]
[system.cpu.dtb]
type=AlphaDTB
size=64
[system.cpu.itb]
type=AlphaITB
size=48
[system.cpu.tracer] [system.cpu.tracer]
type=ExeTracer type=ExeTracer
@ -41,7 +51,7 @@ cwd=
egid=100 egid=100
env= env=
euid=100 euid=100
executable=tests/test-progs/hello/bin/alpha/tru64/hello executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100 gid=100
input=cin input=cin
output=cout output=cout

34
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt
View file

@ -1,18 +1,34 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 34280 # Simulator instruction rate (inst/s) host_inst_rate 124133 # Simulator instruction rate (inst/s)
host_mem_usage 147884 # Number of bytes of host memory used host_mem_usage 171628 # Number of bytes of host memory used
host_seconds 0.08 # Real time elapsed on the host host_seconds 0.02 # Real time elapsed on the host
host_tick_rate 17043200 # Simulator tick rate (ticks/s) host_tick_rate 61574601 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2578 # Number of instructions simulated sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000001 # Number of seconds simulated sim_seconds 0.000001 # Number of seconds simulated
sim_ticks 1288500 # Number of ticks simulated sim_ticks 1297500 # Number of ticks simulated
system.cpu.dtb.accesses 717 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.dtb.hits 709 # DTB hits
system.cpu.dtb.misses 8 # DTB misses
system.cpu.dtb.read_accesses 419 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 415 # DTB read hits
system.cpu.dtb.read_misses 4 # DTB read misses
system.cpu.dtb.write_accesses 298 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 294 # DTB write hits
system.cpu.dtb.write_misses 4 # DTB write misses
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 2596 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 2585 # ITB hits
system.cpu.itb.misses 11 # ITB misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 2578 # number of cpu cycles simulated system.cpu.numCycles 2596 # number of cpu cycles simulated
system.cpu.num_insts 2578 # Number of instructions executed system.cpu.num_insts 2577 # Number of instructions executed
system.cpu.num_refs 710 # Number of memory references system.cpu.num_refs 717 # Number of memory references
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

8
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout
View file

@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Aug 3 2007 03:56:47 M5 compiled Aug 14 2007 17:36:58
M5 started Fri Aug 3 04:17:14 2007 M5 started Tue Aug 14 17:40:04 2007
M5 executing on zizzer.eecs.umich.edu M5 executing on nacho
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
Exiting @ tick 1288500 because target called exit() Exiting @ tick 1297500 because target called exit()

14
tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
View file

@ -11,12 +11,14 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=TimingSimpleCPU type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus tracer workload children=dcache dtb icache itb l2cache toL2Bus tracer workload
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false defer_registration=false
dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -65,6 +67,10 @@ write_buffers=8
cpu_side=system.cpu.dcache_port cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1] mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=AlphaDTB
size=64
[system.cpu.icache] [system.cpu.icache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615
@ -101,6 +107,10 @@ write_buffers=8
cpu_side=system.cpu.icache_port cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0] mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=AlphaITB
size=48
[system.cpu.l2cache] [system.cpu.l2cache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615
@ -156,7 +166,7 @@ cwd=
egid=100 egid=100
env= env=
euid=100 euid=100
executable=tests/test-progs/hello/bin/alpha/tru64/hello executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100 gid=100
input=cin input=cin
output=cout output=cout

68
tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 196854 # Simulator instruction rate (inst/s) host_inst_rate 123219 # Simulator instruction rate (inst/s)
host_mem_usage 195480 # Number of bytes of host memory used host_mem_usage 178996 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host host_seconds 0.02 # Real time elapsed on the host
host_tick_rate 706389035 # Simulator tick rate (ticks/s) host_tick_rate 443932267 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2578 # Number of instructions simulated sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000009 # Number of seconds simulated sim_seconds 0.000009 # Number of seconds simulated
sim_ticks 9431000 # Number of ticks simulated sim_ticks 9438000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency
@ -76,53 +76,65 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 48.863963 # Cycle average of tags in use system.cpu.dcache.tagsinuse 48.838317 # Cycle average of tags in use
system.cpu.dcache.total_refs 627 # Total number of references to valid blocks. system.cpu.dcache.total_refs 627 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_accesses 2579 # number of ReadReq accesses(hits+misses) system.cpu.dtb.accesses 717 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.dtb.hits 709 # DTB hits
system.cpu.dtb.misses 8 # DTB misses
system.cpu.dtb.read_accesses 419 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 415 # DTB read hits
system.cpu.dtb.read_misses 4 # DTB read misses
system.cpu.dtb.write_accesses 298 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 294 # DTB write hits
system.cpu.dtb.write_misses 4 # DTB write misses
system.cpu.icache.ReadReq_accesses 2586 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 2416 # number of ReadReq hits system.cpu.icache.ReadReq_hits 2423 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 4075000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency 4075000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.063203 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate 0.063032 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 3749000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency 3749000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.063203 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate 0.063032 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 14.822086 # Average number of references to valid blocks. system.cpu.icache.avg_refs 14.865031 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 2579 # number of demand (read+write) accesses system.cpu.icache.demand_accesses 2586 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 25000 # average overall miss latency system.cpu.icache.demand_avg_miss_latency 25000 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.icache.demand_hits 2416 # number of demand (read+write) hits system.cpu.icache.demand_hits 2423 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 4075000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency 4075000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.063203 # miss rate for demand accesses system.cpu.icache.demand_miss_rate 0.063032 # miss rate for demand accesses
system.cpu.icache.demand_misses 163 # number of demand (read+write) misses system.cpu.icache.demand_misses 163 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 3749000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency 3749000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.063203 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate 0.063032 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 2579 # number of overall (read+write) accesses system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 25000 # average overall miss latency system.cpu.icache.overall_avg_miss_latency 25000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 2416 # number of overall hits system.cpu.icache.overall_hits 2423 # number of overall hits
system.cpu.icache.overall_miss_latency 4075000 # number of overall miss cycles system.cpu.icache.overall_miss_latency 4075000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.063203 # miss rate for overall accesses system.cpu.icache.overall_miss_rate 0.063032 # miss rate for overall accesses
system.cpu.icache.overall_misses 163 # number of overall misses system.cpu.icache.overall_misses 163 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 3749000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency 3749000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.063203 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate 0.063032 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
@ -138,11 +150,15 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 83.443652 # Cycle average of tags in use system.cpu.icache.tagsinuse 83.395749 # Cycle average of tags in use
system.cpu.icache.total_refs 2416 # Total number of references to valid blocks. system.cpu.icache.total_refs 2423 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 2597 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 2586 # ITB hits
system.cpu.itb.misses 11 # ITB misses
system.cpu.l2cache.ReadExReq_accesses 27 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 27 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
@ -218,14 +234,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 207 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 207 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 106.620093 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 106.559981 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 9431000 # number of cpu cycles simulated system.cpu.numCycles 9438000 # number of cpu cycles simulated
system.cpu.num_insts 2578 # Number of instructions executed system.cpu.num_insts 2577 # Number of instructions executed
system.cpu.num_refs 710 # Number of memory references system.cpu.num_refs 717 # Number of memory references
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

8
tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
View file

@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Aug 12 2007 00:26:55 M5 compiled Aug 14 2007 17:58:14
M5 started Sun Aug 12 00:29:42 2007 M5 started Tue Aug 14 17:59:08 2007
M5 executing on zeep M5 executing on nacho
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
Exiting @ tick 9431000 because target called exit() Exiting @ tick 9438000 because target called exit()

12
tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
View file

@ -11,12 +11,14 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
children=tracer workload children=dtb itb tracer workload
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false defer_registration=false
dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -31,6 +33,12 @@ workload=system.cpu.workload
dcache_port=system.membus.port[2] dcache_port=system.membus.port[2]
icache_port=system.membus.port[1] icache_port=system.membus.port[1]
[system.cpu.dtb]
type=MipsDTB
[system.cpu.itb]
type=MipsITB
[system.cpu.tracer] [system.cpu.tracer]
type=ExeTracer type=ExeTracer
@ -41,7 +49,7 @@ cwd=
egid=100 egid=100
env= env=
euid=100 euid=100
executable=tests/test-progs/hello/bin/mips/linux/hello executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
gid=100 gid=100
input=cin input=cin
output=cout output=cout

12
tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt
View file

@ -1,17 +1,17 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 25511 # Simulator instruction rate (inst/s) host_inst_rate 9753 # Simulator instruction rate (inst/s)
host_mem_usage 149560 # Number of bytes of host memory used host_mem_usage 173424 # Number of bytes of host memory used
host_seconds 0.22 # Real time elapsed on the host host_seconds 0.58 # Real time elapsed on the host
host_tick_rate 12728361 # Simulator tick rate (ticks/s) host_tick_rate 4872477 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5657 # Number of instructions simulated sim_insts 5656 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated sim_seconds 0.000003 # Number of seconds simulated
sim_ticks 2828000 # Number of ticks simulated sim_ticks 2828000 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 5657 # number of cpu cycles simulated system.cpu.numCycles 5657 # number of cpu cycles simulated
system.cpu.num_insts 5657 # Number of instructions executed system.cpu.num_insts 5656 # Number of instructions executed
system.cpu.num_refs 2055 # Number of memory references system.cpu.num_refs 2055 # Number of memory references
system.cpu.workload.PROG:num_syscalls 13 # Number of system calls system.cpu.workload.PROG:num_syscalls 13 # Number of system calls

6
tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout
View file

@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Aug 3 2007 04:06:41 M5 compiled Aug 14 2007 22:02:23
M5 started Fri Aug 3 04:31:09 2007 M5 started Tue Aug 14 22:02:24 2007
M5 executing on zizzer.eecs.umich.edu M5 executing on nacho
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
Exiting @ tick 2828000 because target called exit() Exiting @ tick 2828000 because target called exit()

12
tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
View file

@ -11,12 +11,14 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=TimingSimpleCPU type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus tracer workload children=dcache dtb icache itb l2cache toL2Bus tracer workload
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false defer_registration=false
dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -65,6 +67,9 @@ write_buffers=8
cpu_side=system.cpu.dcache_port cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1] mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=MipsDTB
[system.cpu.icache] [system.cpu.icache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615
@ -101,6 +106,9 @@ write_buffers=8
cpu_side=system.cpu.icache_port cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0] mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=MipsITB
[system.cpu.l2cache] [system.cpu.l2cache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615
@ -156,7 +164,7 @@ cwd=
egid=100 egid=100
env= env=
euid=100 euid=100
executable=tests/test-progs/hello/bin/mips/linux/hello executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
gid=100 gid=100
input=cin input=cin
output=cout output=cout

12
tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
View file

@ -1,11 +1,11 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 269189 # Simulator instruction rate (inst/s) host_inst_rate 186969 # Simulator instruction rate (inst/s)
host_mem_usage 197500 # Number of bytes of host memory used host_mem_usage 180780 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host host_seconds 0.03 # Real time elapsed on the host
host_tick_rate 866482072 # Simulator tick rate (ticks/s) host_tick_rate 602814418 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5657 # Number of instructions simulated sim_insts 5656 # Number of instructions simulated
sim_seconds 0.000018 # Number of seconds simulated sim_seconds 0.000018 # Number of seconds simulated
sim_ticks 18463000 # Number of ticks simulated sim_ticks 18463000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses)
@ -225,7 +225,7 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 18463000 # number of cpu cycles simulated system.cpu.numCycles 18463000 # number of cpu cycles simulated
system.cpu.num_insts 5657 # Number of instructions executed system.cpu.num_insts 5656 # Number of instructions executed
system.cpu.num_refs 2055 # Number of memory references system.cpu.num_refs 2055 # Number of memory references
system.cpu.workload.PROG:num_syscalls 13 # Number of system calls system.cpu.workload.PROG:num_syscalls 13 # Number of system calls

6
tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
View file

@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Aug 12 2007 17:11:48 M5 compiled Aug 14 2007 22:02:23
M5 started Sun Aug 12 17:11:50 2007 M5 started Tue Aug 14 22:02:25 2007
M5 executing on zeep M5 executing on nacho
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
Exiting @ tick 18463000 because target called exit() Exiting @ tick 18463000 because target called exit()

14
tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
View file

@ -11,12 +11,14 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
children=tracer workload children=dtb itb tracer workload
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false defer_registration=false
dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -31,6 +33,14 @@ workload=system.cpu.workload
dcache_port=system.membus.port[2] dcache_port=system.membus.port[2]
icache_port=system.membus.port[1] icache_port=system.membus.port[1]
[system.cpu.dtb]
type=SparcDTB
size=64
[system.cpu.itb]
type=SparcITB
size=64
[system.cpu.tracer] [system.cpu.tracer]
type=ExeTracer type=ExeTracer
@ -41,7 +51,7 @@ cwd=
egid=100 egid=100
env= env=
euid=100 euid=100
executable=tests/test-progs/hello/bin/sparc/linux/hello executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
gid=100 gid=100
input=cin input=cin
output=cout output=cout

18
tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt
View file

@ -1,18 +1,18 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 15625 # Simulator instruction rate (inst/s) host_inst_rate 5187 # Simulator instruction rate (inst/s)
host_mem_usage 149968 # Number of bytes of host memory used host_mem_usage 173740 # Number of bytes of host memory used
host_seconds 0.31 # Real time elapsed on the host host_seconds 0.93 # Real time elapsed on the host
host_tick_rate 7799892 # Simulator tick rate (ticks/s) host_tick_rate 2625893 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 4863 # Number of instructions simulated sim_insts 4833 # Number of instructions simulated
sim_seconds 0.000002 # Number of seconds simulated sim_seconds 0.000002 # Number of seconds simulated
sim_ticks 2431000 # Number of ticks simulated sim_ticks 2447500 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 4863 # number of cpu cycles simulated system.cpu.numCycles 4896 # number of cpu cycles simulated
system.cpu.num_insts 4863 # Number of instructions executed system.cpu.num_insts 4833 # Number of instructions executed
system.cpu.num_refs 1269 # Number of memory references system.cpu.num_refs 1282 # Number of memory references
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

8
tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Aug 3 2007 04:11:25 M5 compiled Aug 14 2007 22:08:21
M5 started Fri Aug 3 04:31:18 2007 M5 started Tue Aug 14 22:08:22 2007
M5 executing on zizzer.eecs.umich.edu M5 executing on nacho
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
Exiting @ tick 2431000 because target called exit() Exiting @ tick 2447500 because target called exit()

14
tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
View file

@ -11,12 +11,14 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=TimingSimpleCPU type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus tracer workload children=dcache dtb icache itb l2cache toL2Bus tracer workload
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false defer_registration=false
dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -65,6 +67,10 @@ write_buffers=8
cpu_side=system.cpu.dcache_port cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1] mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=SparcDTB
size=64
[system.cpu.icache] [system.cpu.icache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615
@ -101,6 +107,10 @@ write_buffers=8
cpu_side=system.cpu.icache_port cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0] mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=SparcITB
size=64
[system.cpu.l2cache] [system.cpu.l2cache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615
@ -156,7 +166,7 @@ cwd=
egid=100 egid=100
env= env=
euid=100 euid=100
executable=tests/test-progs/hello/bin/sparc/linux/hello executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
gid=100 gid=100
input=cin input=cin
output=cout output=cout

50
tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 277220 # Simulator instruction rate (inst/s) host_inst_rate 198489 # Simulator instruction rate (inst/s)
host_mem_usage 197684 # Number of bytes of host memory used host_mem_usage 181156 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host host_seconds 0.02 # Real time elapsed on the host
host_tick_rate 892278360 # Simulator tick rate (ticks/s) host_tick_rate 645076356 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 4863 # Number of instructions simulated sim_insts 4833 # Number of instructions simulated
sim_seconds 0.000016 # Number of seconds simulated sim_seconds 0.000016 # Number of seconds simulated
sim_ticks 15912000 # Number of ticks simulated sim_ticks 15925000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 608 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses 608 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 24777.777778 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency 24777.777778 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22777.777778 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22777.777778 # average ReadReq mshr miss latency
@ -76,53 +76,53 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 83.464621 # Cycle average of tags in use system.cpu.dcache.tagsinuse 83.440192 # Cycle average of tags in use
system.cpu.dcache.total_refs 1131 # Total number of references to valid blocks. system.cpu.dcache.total_refs 1131 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_accesses 4864 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses 4877 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 24906.250000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 24906.250000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 22906.250000 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 22906.250000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 4608 # number of ReadReq hits system.cpu.icache.ReadReq_hits 4621 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 6376000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency 6376000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.052632 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate 0.052491 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 256 # number of ReadReq misses system.cpu.icache.ReadReq_misses 256 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 5864000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency 5864000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.052632 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate 0.052491 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 256 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses 256 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 18 # Average number of references to valid blocks. system.cpu.icache.avg_refs 18.050781 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 4864 # number of demand (read+write) accesses system.cpu.icache.demand_accesses 4877 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 24906.250000 # average overall miss latency system.cpu.icache.demand_avg_miss_latency 24906.250000 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 22906.250000 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 22906.250000 # average overall mshr miss latency
system.cpu.icache.demand_hits 4608 # number of demand (read+write) hits system.cpu.icache.demand_hits 4621 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 6376000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency 6376000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.052632 # miss rate for demand accesses system.cpu.icache.demand_miss_rate 0.052491 # miss rate for demand accesses
system.cpu.icache.demand_misses 256 # number of demand (read+write) misses system.cpu.icache.demand_misses 256 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 5864000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency 5864000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.052632 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate 0.052491 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 256 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses 256 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 4864 # number of overall (read+write) accesses system.cpu.icache.overall_accesses 4877 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 24906.250000 # average overall miss latency system.cpu.icache.overall_avg_miss_latency 24906.250000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 22906.250000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 22906.250000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 4608 # number of overall hits system.cpu.icache.overall_hits 4621 # number of overall hits
system.cpu.icache.overall_miss_latency 6376000 # number of overall miss cycles system.cpu.icache.overall_miss_latency 6376000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.052632 # miss rate for overall accesses system.cpu.icache.overall_miss_rate 0.052491 # miss rate for overall accesses
system.cpu.icache.overall_misses 256 # number of overall misses system.cpu.icache.overall_misses 256 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 5864000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency 5864000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.052632 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate 0.052491 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 256 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses 256 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
@ -138,8 +138,8 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 256 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 256 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 114.953503 # Cycle average of tags in use system.cpu.icache.tagsinuse 114.921642 # Cycle average of tags in use
system.cpu.icache.total_refs 4608 # Total number of references to valid blocks. system.cpu.icache.total_refs 4621 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
@ -219,14 +219,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 292 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 292 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 133.743977 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 133.706132 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 15912000 # number of cpu cycles simulated system.cpu.numCycles 15925000 # number of cpu cycles simulated
system.cpu.num_insts 4863 # Number of instructions executed system.cpu.num_insts 4833 # Number of instructions executed
system.cpu.num_refs 1269 # Number of memory references system.cpu.num_refs 1282 # Number of memory references
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

8
tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Aug 12 2007 12:23:15 M5 compiled Aug 14 2007 22:08:21
M5 started Sun Aug 12 16:58:40 2007 M5 started Tue Aug 14 22:08:24 2007
M5 executing on zeep M5 executing on nacho
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
Exiting @ tick 15912000 because target called exit() Exiting @ tick 15925000 because target called exit()

12
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu] [system.cpu]
type=DerivO3CPU type=DerivO3CPU
children=dcache fuPool icache l2cache toL2Bus tracer workload0 workload1 children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload0 workload1
BTBEntries=4096 BTBEntries=4096
BTBTagSize=16 BTBTagSize=16
LFSTSize=1024 LFSTSize=1024
@ -36,6 +36,7 @@ decodeToRenameDelay=1
decodeWidth=8 decodeWidth=8
defer_registration=false defer_registration=false
dispatchWidth=8 dispatchWidth=8
dtb=system.cpu.dtb
fetchToDecodeDelay=1 fetchToDecodeDelay=1
fetchTrapLatency=1 fetchTrapLatency=1
fetchWidth=8 fetchWidth=8
@ -53,6 +54,7 @@ iewToRenameDelay=1
instShiftAmt=2 instShiftAmt=2
issueToExecuteDelay=1 issueToExecuteDelay=1
issueWidth=8 issueWidth=8
itb=system.cpu.itb
localCtrBits=2 localCtrBits=2
localHistoryBits=11 localHistoryBits=11
localHistoryTableSize=2048 localHistoryTableSize=2048
@ -130,6 +132,10 @@ write_buffers=8
cpu_side=system.cpu.dcache_port cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1] mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
type=AlphaDTB
size=64
[system.cpu.fuPool] [system.cpu.fuPool]
type=FUPool type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
@ -303,6 +309,10 @@ write_buffers=8
cpu_side=system.cpu.icache_port cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0] mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
type=AlphaITB
size=48
[system.cpu.l2cache] [system.cpu.l2cache]
type=BaseCache type=BaseCache
addr_range=0:18446744073709551615 addr_range=0:18446744073709551615

800
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt
View file

File diff suppressed because it is too large Load diff

8
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout
View file

@ -7,9 +7,9 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Aug 12 2007 00:26:55 M5 compiled Aug 14 2007 15:45:23
M5 started Sun Aug 12 00:29:42 2007 M5 started Tue Aug 14 15:45:27 2007
M5 executing on zeep M5 executing on nacho
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
Exiting @ tick 5506000 because target called exit() Exiting @ tick 5727000 because target called exit()

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