Registers: Eliminate the ISA defined integer register file.
This commit is contained in:
parent
0cb180ea0d
commit
a480ba00b9
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@ -30,11 +30,7 @@
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* Kevin Lim
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* Kevin Lim
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*/
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*/
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#include <cstring>
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#include "arch/alpha/isa_traits.hh"
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#include "arch/alpha/intregfile.hh"
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#include "arch/alpha/intregfile.hh"
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#include "sim/serialize.hh"
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namespace AlphaISA {
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namespace AlphaISA {
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@ -52,23 +48,5 @@ const int reg_redir[NumIntRegs] = {
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/* 24 */ 24, 25, 26, 27, 28, 29, 30, 31 };
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/* 24 */ 24, 25, 26, 27, 28, 29, 30, 31 };
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#endif
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#endif
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void
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IntRegFile::clear()
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{
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std::memset(regs, 0, sizeof(regs));
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}
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void
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IntRegFile::serialize(std::ostream &os)
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{
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SERIALIZE_ARRAY(regs, NumIntRegs);
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}
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void
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IntRegFile::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_ARRAY(regs, NumIntRegs);
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}
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} // namespace AlphaISA
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} // namespace AlphaISA
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@ -32,42 +32,13 @@
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#ifndef __ARCH_ALPHA_INTREGFILE_HH__
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#ifndef __ARCH_ALPHA_INTREGFILE_HH__
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#define __ARCH_ALPHA_INTREGFILE_HH__
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#define __ARCH_ALPHA_INTREGFILE_HH__
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#include <iosfwd>
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#include "arch/alpha/isa_traits.hh"
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#include <string>
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#include "arch/alpha/types.hh"
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class Checkpoint;
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namespace AlphaISA {
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namespace AlphaISA {
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// redirected register map, really only used for the full system case.
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// redirected register map, really only used for the full system case.
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extern const int reg_redir[NumIntRegs];
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extern const int reg_redir[NumIntRegs];
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class IntRegFile
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{
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protected:
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IntReg regs[NumIntRegs];
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public:
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IntReg
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readReg(int intReg)
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{
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return regs[intReg];
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}
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void
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setReg(int intReg, const IntReg &val)
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{
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regs[intReg] = val;
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}
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void clear();
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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};
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} // namespace AlphaISA
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} // namespace AlphaISA
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#endif // __ARCH_ALPHA_INTREGFILE_HH__
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#endif // __ARCH_ALPHA_INTREGFILE_HH__
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@ -41,7 +41,6 @@ namespace AlphaISA {
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void
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void
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RegFile::serialize(EventManager *em, ostream &os)
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RegFile::serialize(EventManager *em, ostream &os)
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{
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{
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intRegFile.serialize(os);
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SERIALIZE_SCALAR(pc);
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SERIALIZE_SCALAR(pc);
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SERIALIZE_SCALAR(npc);
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SERIALIZE_SCALAR(npc);
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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@ -52,7 +51,6 @@ RegFile::serialize(EventManager *em, ostream &os)
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void
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void
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RegFile::unserialize(EventManager *em, Checkpoint *cp, const string §ion)
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RegFile::unserialize(EventManager *em, Checkpoint *cp, const string §ion)
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{
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{
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intRegFile.unserialize(cp, section);
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UNSERIALIZE_SCALAR(pc);
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UNSERIALIZE_SCALAR(pc);
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UNSERIALIZE_SCALAR(npc);
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UNSERIALIZE_SCALAR(npc);
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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@ -89,9 +89,6 @@ class RegFile {
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setNextNPC(Addr val)
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setNextNPC(Addr val)
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{ }
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{ }
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protected:
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IntRegFile intRegFile; // (signed) integer register file
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public:
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public:
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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int intrflag; // interrupt flag
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int intrflag; // interrupt flag
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@ -100,19 +97,6 @@ class RegFile {
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void
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void
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clear()
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clear()
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{
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{
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intRegFile.clear();
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}
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IntReg
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readIntReg(int intReg)
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{
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return intRegFile.readReg(intReg);
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}
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void
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setIntReg(int intReg, const IntReg &val)
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{
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intRegFile.setReg(intReg, val);
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}
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}
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void serialize(EventManager *em, std::ostream &os);
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void serialize(EventManager *em, std::ostream &os);
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@ -43,11 +43,6 @@ class ThreadContext;
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namespace ArmISA
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namespace ArmISA
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{
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{
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static inline std::string getIntRegName(RegIndex)
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{
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return "";
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}
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enum MiscIntRegNums {
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enum MiscIntRegNums {
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zero_reg = NumIntArchRegs,
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zero_reg = NumIntArchRegs,
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addr_reg,
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addr_reg,
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@ -77,42 +72,6 @@ namespace ArmISA
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r14_abt
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r14_abt
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};
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};
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class IntRegFile
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{
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protected:
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IntReg regs[NumIntRegs];
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public:
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IntReg readReg(int intReg)
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{
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DPRINTF(IntRegs, "Reading int reg %d as %#x.\n",
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intReg, regs[intReg]);
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return regs[intReg];
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}
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void clear()
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{
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bzero(regs, sizeof(regs));
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}
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Fault setReg(int intReg, const IntReg &val)
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{
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DPRINTF(IntRegs, "Setting int reg %d to %#x.\n", intReg, val);
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regs[intReg] = val;
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return NoFault;
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}
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void serialize(std::ostream &os)
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{
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SERIALIZE_ARRAY(regs, NumIntRegs);
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}
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void unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_ARRAY(regs, NumIntRegs);
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}
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};
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} // namespace ArmISA
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} // namespace ArmISA
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#endif
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#endif
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@ -57,7 +57,6 @@ MiscRegFile::copyMiscRegs(ThreadContext *tc)
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void
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void
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RegFile::serialize(EventManager *em, ostream &os)
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RegFile::serialize(EventManager *em, ostream &os)
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{
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{
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intRegFile.serialize(os);
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SERIALIZE_SCALAR(npc);
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SERIALIZE_SCALAR(npc);
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SERIALIZE_SCALAR(nnpc);
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SERIALIZE_SCALAR(nnpc);
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}
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}
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@ -65,7 +64,6 @@ RegFile::serialize(EventManager *em, ostream &os)
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void
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void
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RegFile::unserialize(EventManager *em, Checkpoint *cp, const string §ion)
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RegFile::unserialize(EventManager *em, Checkpoint *cp, const string §ion)
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{
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{
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intRegFile.unserialize(cp, section);
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UNSERIALIZE_SCALAR(npc);
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UNSERIALIZE_SCALAR(npc);
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UNSERIALIZE_SCALAR(nnpc);
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UNSERIALIZE_SCALAR(nnpc);
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}
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}
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@ -67,25 +67,10 @@ namespace ArmISA
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class RegFile
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class RegFile
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{
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{
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protected:
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IntRegFile intRegFile; // (signed) integer register file
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public:
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public:
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void clear()
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void clear()
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{
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{}
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intRegFile.clear();
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}
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IntReg readIntReg(int intReg)
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{
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return intRegFile.readReg(intReg);
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}
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void setIntReg(int intReg, const IntReg &val)
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{
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intRegFile.setReg(intReg, val);
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}
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protected:
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protected:
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Addr pc; // program counter
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Addr pc; // program counter
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public:
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public:
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Addr readPC()
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Addr readPC()
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{
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{
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return intRegFile.readReg(PCReg);
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return pc;
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//return pc;
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}
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}
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void setPC(Addr val)
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void setPC(Addr val)
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{
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{
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intRegFile.setReg(PCReg, val);
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pc = val;
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//pc = val;
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}
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}
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Addr readNextPC()
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Addr readNextPC()
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if env['TARGET_ISA'] == 'mips':
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if env['TARGET_ISA'] == 'mips':
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Source('faults.cc')
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Source('faults.cc')
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Source('isa.cc')
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Source('isa.cc')
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Source('regfile/int_regfile.cc')
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Source('regfile/misc_regfile.cc')
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Source('regfile/misc_regfile.cc')
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Source('regfile/regfile.cc')
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Source('regfile/regfile.cc')
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Source('tlb.cc')
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Source('tlb.cc')
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void RegFile::clear()
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void RegFile::clear()
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{
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{
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intRegFile.clear();
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miscRegFile.clear();
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miscRegFile.clear();
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}
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}
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RegFile::reset(std::string core_name, ThreadID num_threads,
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RegFile::reset(std::string core_name, ThreadID num_threads,
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unsigned num_vpes)
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unsigned num_vpes)
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{
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{
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bzero(&intRegFile, sizeof(intRegFile));
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miscRegFile.reset(core_name, num_threads, num_vpes);
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miscRegFile.reset(core_name, num_threads, num_vpes);
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}
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}
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IntReg RegFile::readIntReg(int intReg)
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{
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return intRegFile.readReg(intReg);
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}
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Fault RegFile::setIntReg(int intReg, const IntReg &val)
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{
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return intRegFile.setReg(intReg, val);
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}
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MiscReg
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MiscReg
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RegFile::readMiscRegNoEffect(int miscReg, ThreadID tid = 0)
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RegFile::readMiscRegNoEffect(int miscReg, ThreadID tid = 0)
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{
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{
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void
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void
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RegFile::serialize(std::ostream &os)
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RegFile::serialize(std::ostream &os)
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{
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{
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intRegFile.serialize(os);
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miscRegFile.serialize(os);
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miscRegFile.serialize(os);
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SERIALIZE_SCALAR(pc);
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SERIALIZE_SCALAR(pc);
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void
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void
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RegFile::unserialize(Checkpoint *cp, const std::string §ion)
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RegFile::unserialize(Checkpoint *cp, const std::string §ion)
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{
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{
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intRegFile.unserialize(cp, section);
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miscRegFile.unserialize(cp, section);
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miscRegFile.unserialize(cp, section);
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UNSERIALIZE_SCALAR(pc);
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UNSERIALIZE_SCALAR(pc);
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UNSERIALIZE_SCALAR(npc);
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UNSERIALIZE_SCALAR(npc);
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@ -1,103 +0,0 @@
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/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Korey Sewell
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* Jaidev Patwardhan
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*/
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#include "arch/mips/regfile/int_regfile.hh"
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#include "sim/serialize.hh"
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using namespace MipsISA;
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using namespace std;
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void
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IntRegFile::clear()
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{
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bzero(®s, sizeof(regs));
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currShadowSet=0;
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}
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int
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IntRegFile::readShadowSet()
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{
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return currShadowSet;
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}
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void
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IntRegFile::setShadowSet(int css)
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{
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DPRINTF(MipsPRA, "Setting Shadow Set to :%d (%s)\n", css, currShadowSet);
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currShadowSet = css;
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}
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IntReg
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IntRegFile::readReg(int intReg)
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{
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if (intReg < NumIntArchRegs) {
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// Regular GPR Read
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DPRINTF(MipsPRA, "Reading Reg: %d, CurrShadowSet: %d\n", intReg,
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currShadowSet);
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return regs[intReg + NumIntArchRegs * currShadowSet];
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} else {
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unsigned special_reg_num = intReg - NumIntArchRegs;
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// Read A Special Reg
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return regs[TotalArchRegs + special_reg_num];
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}
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}
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Fault
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IntRegFile::setReg(int intReg, const IntReg &val)
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{
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if (intReg != ZeroReg) {
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if (intReg < NumIntArchRegs) {
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regs[intReg + NumIntArchRegs * currShadowSet] = val;
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} else {
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unsigned special_reg_num = intReg - NumIntArchRegs;
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||||||
regs[TotalArchRegs + special_reg_num] = val;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
return NoFault;
|
|
||||||
}
|
|
||||||
|
|
||||||
void
|
|
||||||
IntRegFile::serialize(std::ostream &os)
|
|
||||||
{
|
|
||||||
SERIALIZE_ARRAY(regs, NumIntRegs);
|
|
||||||
}
|
|
||||||
|
|
||||||
void
|
|
||||||
IntRegFile::unserialize(Checkpoint *cp, const std::string §ion)
|
|
||||||
{
|
|
||||||
UNSERIALIZE_ARRAY(regs, NumIntRegs);
|
|
||||||
}
|
|
|
@ -65,23 +65,6 @@ namespace MipsISA
|
||||||
//TotalArchRegs = NumIntArchRegs * ShadowSets
|
//TotalArchRegs = NumIntArchRegs * ShadowSets
|
||||||
const int TotalArchRegs = NumIntArchRegs;
|
const int TotalArchRegs = NumIntArchRegs;
|
||||||
|
|
||||||
class IntRegFile
|
|
||||||
{
|
|
||||||
protected:
|
|
||||||
IntReg regs[NumIntRegs];
|
|
||||||
int currShadowSet;
|
|
||||||
public:
|
|
||||||
void clear();
|
|
||||||
int readShadowSet();
|
|
||||||
void setShadowSet(int css);
|
|
||||||
IntReg readReg(int intReg);
|
|
||||||
Fault setReg(int intReg, const IntReg &val);
|
|
||||||
|
|
||||||
void serialize(std::ostream &os);
|
|
||||||
void unserialize(Checkpoint *cp, const std::string §ion);
|
|
||||||
|
|
||||||
};
|
|
||||||
|
|
||||||
} // namespace MipsISA
|
} // namespace MipsISA
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -40,31 +40,16 @@ namespace MipsISA
|
||||||
void
|
void
|
||||||
RegFile::clear()
|
RegFile::clear()
|
||||||
{
|
{
|
||||||
intRegFile.clear();
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
RegFile::reset(std::string core_name, ThreadID num_threads, unsigned num_vpes,
|
RegFile::reset(std::string core_name, ThreadID num_threads, unsigned num_vpes,
|
||||||
BaseCPU *_cpu)
|
BaseCPU *_cpu)
|
||||||
{
|
{
|
||||||
bzero(&intRegFile, sizeof(intRegFile));
|
|
||||||
}
|
|
||||||
|
|
||||||
IntReg
|
|
||||||
RegFile::readIntReg(int intReg)
|
|
||||||
{
|
|
||||||
return intRegFile.readReg(intReg);
|
|
||||||
}
|
|
||||||
|
|
||||||
Fault
|
|
||||||
RegFile::setIntReg(int intReg, const IntReg &val)
|
|
||||||
{
|
|
||||||
return intRegFile.setReg(intReg, val);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
RegFile::setShadowSet(int css){
|
RegFile::setShadowSet(int css){
|
||||||
intRegFile.setShadowSet(css);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
@ -107,7 +92,6 @@ RegFile::setNextNPC(Addr val)
|
||||||
void
|
void
|
||||||
RegFile::serialize(EventManager *em, std::ostream &os)
|
RegFile::serialize(EventManager *em, std::ostream &os)
|
||||||
{
|
{
|
||||||
intRegFile.serialize(os);
|
|
||||||
SERIALIZE_SCALAR(pc);
|
SERIALIZE_SCALAR(pc);
|
||||||
SERIALIZE_SCALAR(npc);
|
SERIALIZE_SCALAR(npc);
|
||||||
SERIALIZE_SCALAR(nnpc);
|
SERIALIZE_SCALAR(nnpc);
|
||||||
|
@ -117,7 +101,6 @@ void
|
||||||
RegFile::unserialize(EventManager *em, Checkpoint *cp,
|
RegFile::unserialize(EventManager *em, Checkpoint *cp,
|
||||||
const std::string §ion)
|
const std::string §ion)
|
||||||
{
|
{
|
||||||
intRegFile.unserialize(cp, section);
|
|
||||||
UNSERIALIZE_SCALAR(pc);
|
UNSERIALIZE_SCALAR(pc);
|
||||||
UNSERIALIZE_SCALAR(npc);
|
UNSERIALIZE_SCALAR(npc);
|
||||||
UNSERIALIZE_SCALAR(nnpc);
|
UNSERIALIZE_SCALAR(nnpc);
|
||||||
|
|
|
@ -79,16 +79,11 @@ namespace MipsISA
|
||||||
// used to implement branch delay slot
|
// used to implement branch delay slot
|
||||||
// not real register
|
// not real register
|
||||||
|
|
||||||
IntRegFile intRegFile; // (signed) integer register file
|
|
||||||
|
|
||||||
public:
|
public:
|
||||||
void clear();
|
void clear();
|
||||||
void reset(std::string core_name, ThreadID num_threads,
|
void reset(std::string core_name, ThreadID num_threads,
|
||||||
unsigned num_vpes, BaseCPU *_cpu);
|
unsigned num_vpes, BaseCPU *_cpu);
|
||||||
|
|
||||||
IntReg readIntReg(int intReg);
|
|
||||||
Fault setIntReg(int intReg, const IntReg &val);
|
|
||||||
|
|
||||||
void setShadowSet(int css);
|
void setShadowSet(int css);
|
||||||
|
|
||||||
public:
|
public:
|
||||||
|
|
|
@ -34,7 +34,6 @@ Import('*')
|
||||||
if env['TARGET_ISA'] == 'sparc':
|
if env['TARGET_ISA'] == 'sparc':
|
||||||
Source('asi.cc')
|
Source('asi.cc')
|
||||||
Source('faults.cc')
|
Source('faults.cc')
|
||||||
Source('intregfile.cc')
|
|
||||||
Source('isa.cc')
|
Source('isa.cc')
|
||||||
Source('miscregfile.cc')
|
Source('miscregfile.cc')
|
||||||
Source('pagetable.cc')
|
Source('pagetable.cc')
|
||||||
|
|
|
@ -1,80 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2003-2005 The Regents of The University of Michigan
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are
|
|
||||||
* met: redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer;
|
|
||||||
* redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution;
|
|
||||||
* neither the name of the copyright holders nor the names of its
|
|
||||||
* contributors may be used to endorse or promote products derived from
|
|
||||||
* this software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
||||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
||||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
||||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
||||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
||||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
||||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
||||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
||||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
* Authors: Gabe Black
|
|
||||||
* Ali Saidi
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "arch/sparc/intregfile.hh"
|
|
||||||
#include "base/trace.hh"
|
|
||||||
#include "base/misc.hh"
|
|
||||||
#include "sim/serialize.hh"
|
|
||||||
|
|
||||||
#include <string.h>
|
|
||||||
|
|
||||||
using namespace SparcISA;
|
|
||||||
using namespace std;
|
|
||||||
|
|
||||||
class Checkpoint;
|
|
||||||
|
|
||||||
void IntRegFile::clear()
|
|
||||||
{
|
|
||||||
memset(regs, 0, sizeof(IntReg) * NumIntRegs);
|
|
||||||
}
|
|
||||||
|
|
||||||
IntRegFile::IntRegFile()
|
|
||||||
{
|
|
||||||
clear();
|
|
||||||
}
|
|
||||||
|
|
||||||
IntReg IntRegFile::readReg(int intReg)
|
|
||||||
{
|
|
||||||
DPRINTF(IntRegs, "Read register %d = 0x%x\n", intReg, regs[intReg]);
|
|
||||||
return regs[intReg];
|
|
||||||
}
|
|
||||||
|
|
||||||
void IntRegFile::setReg(int intReg, const IntReg &val)
|
|
||||||
{
|
|
||||||
if(intReg)
|
|
||||||
{
|
|
||||||
DPRINTF(IntRegs, "Wrote register %d = 0x%x\n", intReg, val);
|
|
||||||
regs[intReg] = val;
|
|
||||||
}
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
void IntRegFile::serialize(std::ostream &os)
|
|
||||||
{
|
|
||||||
SERIALIZE_ARRAY(regs, NumIntRegs);
|
|
||||||
SERIALIZE_ARRAY(microRegs, NumMicroIntRegs);
|
|
||||||
}
|
|
||||||
|
|
||||||
void IntRegFile::unserialize(Checkpoint *cp, const std::string §ion)
|
|
||||||
{
|
|
||||||
UNSERIALIZE_ARRAY(regs, NumIntRegs);
|
|
||||||
UNSERIALIZE_ARRAY(microRegs, NumMicroIntRegs);
|
|
||||||
}
|
|
|
@ -32,39 +32,12 @@
|
||||||
#ifndef __ARCH_SPARC_INTREGFILE_HH__
|
#ifndef __ARCH_SPARC_INTREGFILE_HH__
|
||||||
#define __ARCH_SPARC_INTREGFILE_HH__
|
#define __ARCH_SPARC_INTREGFILE_HH__
|
||||||
|
|
||||||
#include "arch/sparc/isa_traits.hh"
|
#include "arch/sparc/sparc_traits.hh"
|
||||||
#include "arch/sparc/types.hh"
|
|
||||||
#include "base/bitfield.hh"
|
|
||||||
|
|
||||||
#include <string>
|
|
||||||
|
|
||||||
class Checkpoint;
|
|
||||||
|
|
||||||
namespace SparcISA
|
namespace SparcISA
|
||||||
{
|
{
|
||||||
const int NumIntArchRegs = 32;
|
const int NumIntArchRegs = 32;
|
||||||
const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs;
|
const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs;
|
||||||
|
|
||||||
class IntRegFile
|
|
||||||
{
|
|
||||||
protected:
|
|
||||||
IntReg microRegs[NumMicroIntRegs];
|
|
||||||
IntReg regs[NumIntRegs];
|
|
||||||
|
|
||||||
public:
|
|
||||||
|
|
||||||
void clear();
|
|
||||||
|
|
||||||
IntRegFile();
|
|
||||||
|
|
||||||
IntReg readReg(int intReg);
|
|
||||||
|
|
||||||
void setReg(int intReg, const IntReg &val);
|
|
||||||
|
|
||||||
void serialize(std::ostream &os);
|
|
||||||
|
|
||||||
void unserialize(Checkpoint *cp, const std::string §ion);
|
|
||||||
};
|
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -32,6 +32,7 @@
|
||||||
#define __ARCH_SPARC_PREDECODER_HH__
|
#define __ARCH_SPARC_PREDECODER_HH__
|
||||||
|
|
||||||
#include "arch/sparc/types.hh"
|
#include "arch/sparc/types.hh"
|
||||||
|
#include "base/bitfield.hh"
|
||||||
#include "base/misc.hh"
|
#include "base/misc.hh"
|
||||||
#include "base/types.hh"
|
#include "base/types.hh"
|
||||||
#include "cpu/thread_context.hh"
|
#include "cpu/thread_context.hh"
|
||||||
|
|
|
@ -68,25 +68,9 @@ void RegFile::setNextNPC(Addr val)
|
||||||
nnpc = val;
|
nnpc = val;
|
||||||
}
|
}
|
||||||
|
|
||||||
void RegFile::clear()
|
|
||||||
{
|
|
||||||
intRegFile.clear();
|
|
||||||
}
|
|
||||||
|
|
||||||
IntReg RegFile::readIntReg(int intReg)
|
|
||||||
{
|
|
||||||
return intRegFile.readReg(intReg);
|
|
||||||
}
|
|
||||||
|
|
||||||
void RegFile::setIntReg(int intReg, const IntReg &val)
|
|
||||||
{
|
|
||||||
intRegFile.setReg(intReg, val);
|
|
||||||
}
|
|
||||||
|
|
||||||
void
|
void
|
||||||
RegFile::serialize(EventManager *em, ostream &os)
|
RegFile::serialize(EventManager *em, ostream &os)
|
||||||
{
|
{
|
||||||
intRegFile.serialize(os);
|
|
||||||
SERIALIZE_SCALAR(pc);
|
SERIALIZE_SCALAR(pc);
|
||||||
SERIALIZE_SCALAR(npc);
|
SERIALIZE_SCALAR(npc);
|
||||||
SERIALIZE_SCALAR(nnpc);
|
SERIALIZE_SCALAR(nnpc);
|
||||||
|
@ -95,7 +79,6 @@ RegFile::serialize(EventManager *em, ostream &os)
|
||||||
void
|
void
|
||||||
RegFile::unserialize(EventManager *em, Checkpoint *cp, const string §ion)
|
RegFile::unserialize(EventManager *em, Checkpoint *cp, const string §ion)
|
||||||
{
|
{
|
||||||
intRegFile.unserialize(cp, section);
|
|
||||||
UNSERIALIZE_SCALAR(pc);
|
UNSERIALIZE_SCALAR(pc);
|
||||||
UNSERIALIZE_SCALAR(npc);
|
UNSERIALIZE_SCALAR(npc);
|
||||||
UNSERIALIZE_SCALAR(nnpc);
|
UNSERIALIZE_SCALAR(nnpc);
|
||||||
|
|
|
@ -61,16 +61,10 @@ namespace SparcISA
|
||||||
Addr readNextNPC();
|
Addr readNextNPC();
|
||||||
void setNextNPC(Addr val);
|
void setNextNPC(Addr val);
|
||||||
|
|
||||||
protected:
|
|
||||||
IntRegFile intRegFile; // integer register file
|
|
||||||
|
|
||||||
public:
|
public:
|
||||||
|
|
||||||
void clear();
|
void clear()
|
||||||
|
{}
|
||||||
IntReg readIntReg(int intReg);
|
|
||||||
|
|
||||||
void setIntReg(int intReg, const IntReg &val);
|
|
||||||
|
|
||||||
void serialize(EventManager *em, std::ostream &os);
|
void serialize(EventManager *em, std::ostream &os);
|
||||||
void unserialize(EventManager *em, Checkpoint *cp,
|
void unserialize(EventManager *em, Checkpoint *cp,
|
||||||
|
|
|
@ -94,7 +94,6 @@ if env['TARGET_ISA'] == 'x86':
|
||||||
Source('insts/microop.cc')
|
Source('insts/microop.cc')
|
||||||
Source('insts/microregop.cc')
|
Source('insts/microregop.cc')
|
||||||
Source('insts/static_inst.cc')
|
Source('insts/static_inst.cc')
|
||||||
Source('intregfile.cc')
|
|
||||||
Source('isa.cc')
|
Source('isa.cc')
|
||||||
Source('miscregfile.cc')
|
Source('miscregfile.cc')
|
||||||
Source('pagetable.cc')
|
Source('pagetable.cc')
|
||||||
|
|
|
@ -1,132 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2003-2007 The Regents of The University of Michigan
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are
|
|
||||||
* met: redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer;
|
|
||||||
* redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution;
|
|
||||||
* neither the name of the copyright holders nor the names of its
|
|
||||||
* contributors may be used to endorse or promote products derived from
|
|
||||||
* this software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
||||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
||||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
||||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
||||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
||||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
||||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
||||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
||||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
* Authors: Gabe Black
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Copyright (c) 2007 The Hewlett-Packard Development Company
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use of this software in source and binary forms,
|
|
||||||
* with or without modification, are permitted provided that the
|
|
||||||
* following conditions are met:
|
|
||||||
*
|
|
||||||
* The software must be used only for Non-Commercial Use which means any
|
|
||||||
* use which is NOT directed to receiving any direct monetary
|
|
||||||
* compensation for, or commercial advantage from such use. Illustrative
|
|
||||||
* examples of non-commercial use are academic research, personal study,
|
|
||||||
* teaching, education and corporate research & development.
|
|
||||||
* Illustrative examples of commercial use are distributing products for
|
|
||||||
* commercial advantage and providing services using the software for
|
|
||||||
* commercial advantage.
|
|
||||||
*
|
|
||||||
* If you wish to use this software or functionality therein that may be
|
|
||||||
* covered by patents for commercial use, please contact:
|
|
||||||
* Director of Intellectual Property Licensing
|
|
||||||
* Office of Strategy and Technology
|
|
||||||
* Hewlett-Packard Company
|
|
||||||
* 1501 Page Mill Road
|
|
||||||
* Palo Alto, California 94304
|
|
||||||
*
|
|
||||||
* Redistributions of source code must retain the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer. Redistributions
|
|
||||||
* in binary form must reproduce the above copyright notice, this list of
|
|
||||||
* conditions and the following disclaimer in the documentation and/or
|
|
||||||
* other materials provided with the distribution. Neither the name of
|
|
||||||
* the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
|
|
||||||
* contributors may be used to endorse or promote products derived from
|
|
||||||
* this software without specific prior written permission. No right of
|
|
||||||
* sublicense is granted herewith. Derivatives of the software and
|
|
||||||
* output created using the software may be prepared, but only for
|
|
||||||
* Non-Commercial Uses. Derivatives of the software may be shared with
|
|
||||||
* others provided: (i) the others agree to abide by the list of
|
|
||||||
* conditions herein which includes the Non-Commercial Use restrictions;
|
|
||||||
* and (ii) such Derivatives of the software include the above copyright
|
|
||||||
* notice to acknowledge the contribution from this software where
|
|
||||||
* applicable, this list of conditions and the disclaimer below.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
||||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
||||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
||||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
||||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
||||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
||||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
||||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
||||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
* Authors: Gabe Black
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "arch/x86/intregfile.hh"
|
|
||||||
#include "base/misc.hh"
|
|
||||||
#include "base/trace.hh"
|
|
||||||
#include "sim/serialize.hh"
|
|
||||||
|
|
||||||
#include <string.h>
|
|
||||||
|
|
||||||
using namespace X86ISA;
|
|
||||||
using namespace std;
|
|
||||||
|
|
||||||
class Checkpoint;
|
|
||||||
|
|
||||||
int IntRegFile::flattenIndex(int reg)
|
|
||||||
{
|
|
||||||
return reg;
|
|
||||||
}
|
|
||||||
|
|
||||||
void IntRegFile::clear()
|
|
||||||
{
|
|
||||||
memset(regs, 0, sizeof(IntReg) * NumIntRegs);
|
|
||||||
}
|
|
||||||
|
|
||||||
IntReg IntRegFile::readReg(int intReg)
|
|
||||||
{
|
|
||||||
DPRINTF(IntRegs, "Read int reg %d and got value %#x\n",
|
|
||||||
intReg, regs[intReg]);
|
|
||||||
return regs[intReg];
|
|
||||||
}
|
|
||||||
|
|
||||||
void IntRegFile::setReg(int intReg, const IntReg &val)
|
|
||||||
{
|
|
||||||
DPRINTF(IntRegs, "Setting int reg %d to value %#x\n",
|
|
||||||
intReg, val);
|
|
||||||
regs[intReg] = val;
|
|
||||||
}
|
|
||||||
|
|
||||||
void IntRegFile::serialize(std::ostream &os)
|
|
||||||
{
|
|
||||||
SERIALIZE_ARRAY(regs, NumIntRegs);
|
|
||||||
}
|
|
||||||
|
|
||||||
void IntRegFile::unserialize(Checkpoint *cp, const std::string §ion)
|
|
||||||
{
|
|
||||||
UNSERIALIZE_ARRAY(regs, NumIntRegs);
|
|
||||||
}
|
|
|
@ -89,41 +89,14 @@
|
||||||
#define __ARCH_X86_INTREGFILE_HH__
|
#define __ARCH_X86_INTREGFILE_HH__
|
||||||
|
|
||||||
#include "arch/x86/intregs.hh"
|
#include "arch/x86/intregs.hh"
|
||||||
#include "arch/x86/types.hh"
|
|
||||||
#include "arch/x86/x86_traits.hh"
|
#include "arch/x86/x86_traits.hh"
|
||||||
|
|
||||||
#include <string>
|
|
||||||
|
|
||||||
class Checkpoint;
|
|
||||||
|
|
||||||
namespace X86ISA
|
namespace X86ISA
|
||||||
{
|
{
|
||||||
class Regfile;
|
|
||||||
|
|
||||||
const int NumIntArchRegs = NUM_INTREGS;
|
const int NumIntArchRegs = NUM_INTREGS;
|
||||||
const int NumIntRegs =
|
const int NumIntRegs =
|
||||||
NumIntArchRegs + NumMicroIntRegs +
|
NumIntArchRegs + NumMicroIntRegs +
|
||||||
NumPseudoIntRegs + NumImplicitIntRegs;
|
NumPseudoIntRegs + NumImplicitIntRegs;
|
||||||
|
|
||||||
class IntRegFile
|
|
||||||
{
|
|
||||||
protected:
|
|
||||||
IntReg regs[NumIntRegs];
|
|
||||||
|
|
||||||
public:
|
|
||||||
|
|
||||||
int flattenIndex(int reg);
|
|
||||||
|
|
||||||
void clear();
|
|
||||||
|
|
||||||
IntReg readReg(int intReg);
|
|
||||||
|
|
||||||
void setReg(int intReg, const IntReg &val);
|
|
||||||
|
|
||||||
void serialize(std::ostream &os);
|
|
||||||
|
|
||||||
void unserialize(Checkpoint *cp, const std::string §ion);
|
|
||||||
};
|
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif //__ARCH_X86_INTREGFILE__
|
#endif //__ARCH_X86_INTREGFILE__
|
||||||
|
|
|
@ -127,21 +127,6 @@ Addr RegFile::readNextNPC()
|
||||||
void RegFile::setNextNPC(Addr val)
|
void RegFile::setNextNPC(Addr val)
|
||||||
{ }
|
{ }
|
||||||
|
|
||||||
void RegFile::clear()
|
|
||||||
{
|
|
||||||
intRegFile.clear();
|
|
||||||
}
|
|
||||||
|
|
||||||
IntReg RegFile::readIntReg(int intReg)
|
|
||||||
{
|
|
||||||
return intRegFile.readReg(intReg);
|
|
||||||
}
|
|
||||||
|
|
||||||
void RegFile::setIntReg(int intReg, const IntReg &val)
|
|
||||||
{
|
|
||||||
intRegFile.setReg(intReg, val);
|
|
||||||
}
|
|
||||||
|
|
||||||
void
|
void
|
||||||
X86ISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
|
X86ISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
|
||||||
{
|
{
|
||||||
|
@ -167,15 +152,3 @@ X86ISA::copyRegs(ThreadContext *src, ThreadContext *dest)
|
||||||
dest->setPC(src->readPC());
|
dest->setPC(src->readPC());
|
||||||
dest->setNextPC(src->readNextPC());
|
dest->setNextPC(src->readNextPC());
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
|
||||||
RegFile::serialize(EventManager *em, std::ostream &os)
|
|
||||||
{
|
|
||||||
intRegFile.serialize(os);
|
|
||||||
}
|
|
||||||
|
|
||||||
void
|
|
||||||
RegFile::unserialize(EventManager *em, Checkpoint *cp, const string §ion)
|
|
||||||
{
|
|
||||||
intRegFile.unserialize(cp, section);
|
|
||||||
}
|
|
||||||
|
|
|
@ -97,20 +97,17 @@ namespace X86ISA
|
||||||
Addr readNextNPC();
|
Addr readNextNPC();
|
||||||
void setNextNPC(Addr val);
|
void setNextNPC(Addr val);
|
||||||
|
|
||||||
protected:
|
|
||||||
IntRegFile intRegFile; // integer register file
|
|
||||||
|
|
||||||
public:
|
public:
|
||||||
|
|
||||||
void clear();
|
void clear()
|
||||||
|
{}
|
||||||
|
|
||||||
IntReg readIntReg(int intReg);
|
void serialize(EventManager *em, std::ostream &os)
|
||||||
|
{}
|
||||||
|
|
||||||
void setIntReg(int intReg, const IntReg &val);
|
|
||||||
|
|
||||||
void serialize(EventManager *em, std::ostream &os);
|
|
||||||
void unserialize(EventManager *em, Checkpoint *cp,
|
void unserialize(EventManager *em, Checkpoint *cp,
|
||||||
const std::string §ion);
|
const std::string §ion)
|
||||||
|
{}
|
||||||
};
|
};
|
||||||
|
|
||||||
void copyRegs(ThreadContext *src, ThreadContext *dest);
|
void copyRegs(ThreadContext *src, ThreadContext *dest);
|
||||||
|
|
|
@ -264,7 +264,7 @@ InOrderCPU::InOrderCPU(Params *params)
|
||||||
squashSeqNum[tid] = MaxAddr;
|
squashSeqNum[tid] = MaxAddr;
|
||||||
lastSquashCycle[tid] = 0;
|
lastSquashCycle[tid] = 0;
|
||||||
|
|
||||||
intRegFile[tid].clear();
|
memset(intRegs[tid], 0, sizeof(intRegs[tid]));
|
||||||
memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid]));
|
memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid]));
|
||||||
isa[tid].clear();
|
isa[tid].clear();
|
||||||
|
|
||||||
|
@ -886,7 +886,7 @@ InOrderCPU::setNextNPC(uint64_t new_NNPC, ThreadID tid)
|
||||||
uint64_t
|
uint64_t
|
||||||
InOrderCPU::readIntReg(int reg_idx, ThreadID tid)
|
InOrderCPU::readIntReg(int reg_idx, ThreadID tid)
|
||||||
{
|
{
|
||||||
return intRegFile[tid].readReg(reg_idx);
|
return intRegs[tid][reg_idx];
|
||||||
}
|
}
|
||||||
|
|
||||||
FloatReg
|
FloatReg
|
||||||
|
@ -904,7 +904,7 @@ InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid)
|
||||||
void
|
void
|
||||||
InOrderCPU::setIntReg(int reg_idx, uint64_t val, ThreadID tid)
|
InOrderCPU::setIntReg(int reg_idx, uint64_t val, ThreadID tid)
|
||||||
{
|
{
|
||||||
intRegFile[tid].setReg(reg_idx, val);
|
intRegs[tid][reg_idx] = val;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
|
@ -258,11 +258,11 @@ class InOrderCPU : public BaseCPU
|
||||||
TheISA::IntReg nextNPC[ThePipeline::MaxThreads];
|
TheISA::IntReg nextNPC[ThePipeline::MaxThreads];
|
||||||
|
|
||||||
/** The Register File for the CPU */
|
/** The Register File for the CPU */
|
||||||
TheISA::IntRegFile intRegFile[ThePipeline::MaxThreads];;
|
|
||||||
union {
|
union {
|
||||||
FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
|
FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
|
||||||
FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
|
FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
|
||||||
} floatRegs;
|
} floatRegs;
|
||||||
|
TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
|
||||||
|
|
||||||
/** ISA state */
|
/** ISA state */
|
||||||
TheISA::ISA isa[ThePipeline::MaxThreads];
|
TheISA::ISA isa[ThePipeline::MaxThreads];
|
||||||
|
|
|
@ -71,7 +71,7 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
|
||||||
|
|
||||||
quiesceEvent = new EndQuiesceEvent(tc);
|
quiesceEvent = new EndQuiesceEvent(tc);
|
||||||
|
|
||||||
regs.clear();
|
clearArchRegs();
|
||||||
|
|
||||||
if (cpu->params()->profile) {
|
if (cpu->params()->profile) {
|
||||||
profile = new FunctionProfile(system->kernelSymtab);
|
profile = new FunctionProfile(system->kernelSymtab);
|
||||||
|
@ -96,7 +96,7 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
|
||||||
: ThreadState(_cpu, _thread_num, _process, _asid),
|
: ThreadState(_cpu, _thread_num, _process, _asid),
|
||||||
cpu(_cpu), itb(_itb), dtb(_dtb)
|
cpu(_cpu), itb(_itb), dtb(_dtb)
|
||||||
{
|
{
|
||||||
regs.clear();
|
clearArchRegs();
|
||||||
tc = new ProxyThreadContext<SimpleThread>(this);
|
tc = new ProxyThreadContext<SimpleThread>(this);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -193,6 +193,7 @@ SimpleThread::serialize(ostream &os)
|
||||||
ThreadState::serialize(os);
|
ThreadState::serialize(os);
|
||||||
regs.serialize(cpu, os);
|
regs.serialize(cpu, os);
|
||||||
SERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
|
SERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
|
||||||
|
SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
|
||||||
// thread_num and cpu_id are deterministic from the config
|
// thread_num and cpu_id are deterministic from the config
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -203,6 +204,7 @@ SimpleThread::unserialize(Checkpoint *cp, const std::string §ion)
|
||||||
ThreadState::unserialize(cp, section);
|
ThreadState::unserialize(cp, section);
|
||||||
regs.unserialize(cpu, cp, section);
|
regs.unserialize(cpu, cp, section);
|
||||||
UNSERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
|
UNSERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
|
||||||
|
UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
|
||||||
// thread_num and cpu_id are deterministic from the config
|
// thread_num and cpu_id are deterministic from the config
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -36,6 +36,7 @@
|
||||||
#include "arch/isa_traits.hh"
|
#include "arch/isa_traits.hh"
|
||||||
#include "arch/regfile.hh"
|
#include "arch/regfile.hh"
|
||||||
#include "arch/tlb.hh"
|
#include "arch/tlb.hh"
|
||||||
|
#include "arch/types.hh"
|
||||||
#include "base/types.hh"
|
#include "base/types.hh"
|
||||||
#include "config/full_system.hh"
|
#include "config/full_system.hh"
|
||||||
#include "cpu/thread_context.hh"
|
#include "cpu/thread_context.hh"
|
||||||
|
@ -103,6 +104,7 @@ class SimpleThread : public ThreadState
|
||||||
FloatReg f[TheISA::NumFloatRegs];
|
FloatReg f[TheISA::NumFloatRegs];
|
||||||
FloatRegBits i[TheISA::NumFloatRegs];
|
FloatRegBits i[TheISA::NumFloatRegs];
|
||||||
} floatRegs;
|
} floatRegs;
|
||||||
|
TheISA::IntReg intRegs[TheISA::NumIntRegs];
|
||||||
TheISA::ISA isa; // one "instance" of the current ISA.
|
TheISA::ISA isa; // one "instance" of the current ISA.
|
||||||
|
|
||||||
public:
|
public:
|
||||||
|
@ -230,6 +232,7 @@ class SimpleThread : public ThreadState
|
||||||
void clearArchRegs()
|
void clearArchRegs()
|
||||||
{
|
{
|
||||||
regs.clear();
|
regs.clear();
|
||||||
|
memset(intRegs, 0, sizeof(intRegs));
|
||||||
memset(floatRegs.i, 0, sizeof(floatRegs.i));
|
memset(floatRegs.i, 0, sizeof(floatRegs.i));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -239,7 +242,7 @@ class SimpleThread : public ThreadState
|
||||||
uint64_t readIntReg(int reg_idx)
|
uint64_t readIntReg(int reg_idx)
|
||||||
{
|
{
|
||||||
int flatIndex = isa.flattenIntIndex(reg_idx);
|
int flatIndex = isa.flattenIntIndex(reg_idx);
|
||||||
return regs.readIntReg(flatIndex);
|
return intRegs[flatIndex];
|
||||||
}
|
}
|
||||||
|
|
||||||
FloatReg readFloatReg(int reg_idx)
|
FloatReg readFloatReg(int reg_idx)
|
||||||
|
@ -257,7 +260,7 @@ class SimpleThread : public ThreadState
|
||||||
void setIntReg(int reg_idx, uint64_t val)
|
void setIntReg(int reg_idx, uint64_t val)
|
||||||
{
|
{
|
||||||
int flatIndex = isa.flattenIntIndex(reg_idx);
|
int flatIndex = isa.flattenIntIndex(reg_idx);
|
||||||
regs.setIntReg(flatIndex, val);
|
intRegs[flatIndex] = val;
|
||||||
}
|
}
|
||||||
|
|
||||||
void setFloatReg(int reg_idx, FloatReg val)
|
void setFloatReg(int reg_idx, FloatReg val)
|
||||||
|
|
Loading…
Reference in a new issue