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arm: enable DCZVA by default in SE mode

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This commit is contained in:
Giacomo Gabrielli 2015-05-05 03:22:42 -04:00
parent 80cd107e51
commit a3f23894eb
1 changed files with 5 additions and 2 deletions
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7
src/arch/arm/miscregs.cc
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2010-2013 ARM Limited
* Copyright (c) 2010-2013, 2015 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@ -43,6 +43,7 @@
#include "arch/arm/miscregs.hh"
#include "base/misc.hh"
#include "cpu/thread_context.hh"
#include "sim/full_system.hh"
namespace ArmISA
{
@ -2138,7 +2139,9 @@ canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
if (el == EL0 && !sctlr.uma)
return false;
}
if (reg == MISCREG_DC_ZVA_Xt) {
if (FullSystem && reg == MISCREG_DC_ZVA_Xt) {
// In syscall-emulation mode, this test is skipped and DCZVA is always
// allowed at EL0
SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
if (el == EL0 && !sctlr.dze)
return false;