mem: Add a WideIO DRAM configuration
This patch adds a WideIO 200 MHz configuration that can be used as a baseline to compare with DDRx and LPDDRx. Note that it is a single channel and that it should be replicated 4 times. It is based on publically available information and attempts to capture an envisioned 8 Gbit single-die part (i.e. without TSVs).
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@ -239,3 +239,39 @@ class SimpleLPDDR2_S4(SimpleDRAM):
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# Irrespective of size, tFAW is 50 ns
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tXAW = '50ns'
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activation_limit = 4
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# High-level model of a single WideIO x128 interface (one command and
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# address bus), with default timings based on an estimated WIO-200 8
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# Gbit part.
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class SimpleWideIO(SimpleDRAM):
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# Assuming 64 byte cache lines, use a 4kbyte page size, this
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# depends on the memory density
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lines_per_rowbuffer = 64
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# Use one rank for a one-high die stack
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ranks_per_channel = 1
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# WideIO has 4 banks in all configurations
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banks_per_rank = 4
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# WIO-200
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tRCD = '18ns'
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tCL = '18ns'
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tRP = '18ns'
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# Assuming 64 byte cache lines, across an x128 SDR interface,
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# translates to BL4, 4 clocks @ 200 MHz
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tBURST = '20ns'
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# WIO 8 Gb
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tRFC = '210ns'
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# WIO 8 Gb, <=85C, half for >85C
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tREFI = '3.9us'
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# Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
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tWTR = '15ns'
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# Two instead of four activation window
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tXAW = '50ns'
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activation_limit = 2
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