Merge zizzer:/bk/m5 into isabel.reinhardt.house:/z/stever/bk/m5
--HG-- extra : convert_revision : c74b502bf44ac300e44c9aa7d6d6e3c55a511893
This commit is contained in:
commit
a1dcdeb3d8
6 changed files with 1648 additions and 1439 deletions
1216
base/statistics.cc
1216
base/statistics.cc
File diff suppressed because it is too large
Load diff
1737
base/statistics.hh
1737
base/statistics.hh
File diff suppressed because it is too large
Load diff
|
@ -216,6 +216,63 @@ SimpleCPU::execCtxStatusChg(int thread_num) {
|
|||
setStatus(Idle);
|
||||
}
|
||||
|
||||
void
|
||||
SimpleCPU::setStatus(Status new_status)
|
||||
{
|
||||
Status old_status = status();
|
||||
|
||||
// We should never even get here if the CPU has been switched out.
|
||||
assert(old_status != SwitchedOut);
|
||||
|
||||
_status = new_status;
|
||||
|
||||
switch (status()) {
|
||||
case IcacheMissStall:
|
||||
assert(old_status == Running);
|
||||
lastIcacheStall = curTick;
|
||||
if (tickEvent.scheduled())
|
||||
tickEvent.squash();
|
||||
break;
|
||||
|
||||
case IcacheMissComplete:
|
||||
assert(old_status == IcacheMissStall);
|
||||
if (tickEvent.squashed())
|
||||
tickEvent.reschedule(curTick + 1);
|
||||
else if (!tickEvent.scheduled())
|
||||
tickEvent.schedule(curTick + 1);
|
||||
break;
|
||||
|
||||
case DcacheMissStall:
|
||||
assert(old_status == Running);
|
||||
lastDcacheStall = curTick;
|
||||
if (tickEvent.scheduled())
|
||||
tickEvent.squash();
|
||||
break;
|
||||
|
||||
case Idle:
|
||||
assert(old_status == Running);
|
||||
notIdleFraction--;
|
||||
if (tickEvent.scheduled())
|
||||
tickEvent.squash();
|
||||
break;
|
||||
|
||||
case Running:
|
||||
assert(old_status == Idle ||
|
||||
old_status == DcacheMissStall ||
|
||||
old_status == IcacheMissComplete);
|
||||
if (old_status == Idle)
|
||||
notIdleFraction++;
|
||||
|
||||
if (tickEvent.squashed())
|
||||
tickEvent.reschedule(curTick + 1);
|
||||
else if (!tickEvent.scheduled())
|
||||
tickEvent.schedule(curTick + 1);
|
||||
break;
|
||||
|
||||
default:
|
||||
panic("can't get here");
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
SimpleCPU::regStats()
|
||||
|
@ -251,6 +308,7 @@ SimpleCPU::regStats()
|
|||
.prereq(dcacheStallCycles)
|
||||
;
|
||||
|
||||
idleFraction = constant(1.0) - notIdleFraction;
|
||||
numInsts = Statistics::scalar(numInst) - Statistics::scalar(startNumInst);
|
||||
simInsts += numInsts;
|
||||
}
|
||||
|
@ -259,6 +317,7 @@ void
|
|||
SimpleCPU::resetStats()
|
||||
{
|
||||
startNumInst = numInst;
|
||||
notIdleFraction = (_status != Idle);
|
||||
}
|
||||
|
||||
void
|
||||
|
|
|
@ -174,61 +174,7 @@ class SimpleCPU : public BaseCPU
|
|||
|
||||
virtual void execCtxStatusChg(int thread_num);
|
||||
|
||||
void setStatus(Status new_status) {
|
||||
Status old_status = status();
|
||||
|
||||
// We should never even get here if the CPU has been switched out.
|
||||
assert(old_status != SwitchedOut);
|
||||
|
||||
_status = new_status;
|
||||
|
||||
switch (status()) {
|
||||
case IcacheMissStall:
|
||||
assert(old_status == Running);
|
||||
lastIcacheStall = curTick;
|
||||
if (tickEvent.scheduled())
|
||||
tickEvent.squash();
|
||||
break;
|
||||
|
||||
case IcacheMissComplete:
|
||||
assert(old_status == IcacheMissStall);
|
||||
if (tickEvent.squashed())
|
||||
tickEvent.reschedule(curTick + 1);
|
||||
else if (!tickEvent.scheduled())
|
||||
tickEvent.schedule(curTick + 1);
|
||||
break;
|
||||
|
||||
case DcacheMissStall:
|
||||
assert(old_status == Running);
|
||||
lastDcacheStall = curTick;
|
||||
if (tickEvent.scheduled())
|
||||
tickEvent.squash();
|
||||
break;
|
||||
|
||||
case Idle:
|
||||
assert(old_status == Running);
|
||||
idleFraction++;
|
||||
if (tickEvent.scheduled())
|
||||
tickEvent.squash();
|
||||
break;
|
||||
|
||||
case Running:
|
||||
assert(old_status == Idle ||
|
||||
old_status == DcacheMissStall ||
|
||||
old_status == IcacheMissComplete);
|
||||
if (old_status == Idle && curTick != 0)
|
||||
idleFraction--;
|
||||
|
||||
if (tickEvent.squashed())
|
||||
tickEvent.reschedule(curTick + 1);
|
||||
else if (!tickEvent.scheduled())
|
||||
tickEvent.schedule(curTick + 1);
|
||||
break;
|
||||
|
||||
default:
|
||||
panic("can't get here");
|
||||
}
|
||||
}
|
||||
void setStatus(Status new_status);
|
||||
|
||||
// statistics
|
||||
virtual void regStats();
|
||||
|
@ -247,7 +193,8 @@ class SimpleCPU : public BaseCPU
|
|||
Counter startNumLoad;
|
||||
|
||||
// number of idle cycles
|
||||
Statistics::Average<> idleFraction;
|
||||
Statistics::Average<> notIdleFraction;
|
||||
Statistics::Formula idleFraction;
|
||||
|
||||
// number of cycles stalled for I-cache misses
|
||||
Statistics::Scalar<> icacheStallCycles;
|
||||
|
|
|
@ -52,8 +52,7 @@ offtest: offtest.o
|
|||
rangetest: rangetest.o str.o
|
||||
$(CXX) $(LFLAGS) -o $@ $^
|
||||
|
||||
stattest: cprintf.o hostinfo.o misc.o sim_stats.o sim_time.o \
|
||||
statistics.o stattest.o str.o
|
||||
stattest: cprintf.o hostinfo.o misc.o sim_time.o statistics.o stattest.o str.o
|
||||
$(CXX) $(LFLAGS) -o $@ $^
|
||||
|
||||
strnumtest: strnumtest.o str.o
|
||||
|
|
|
@ -35,7 +35,6 @@
|
|||
#include "base/misc.hh"
|
||||
#include "base/statistics.hh"
|
||||
#include "sim/host.hh"
|
||||
#include "sim/sim_stats.hh"
|
||||
|
||||
using namespace std;
|
||||
using namespace Statistics;
|
||||
|
@ -67,8 +66,8 @@ Formula f4;
|
|||
Formula f5;
|
||||
Formula f6;
|
||||
|
||||
MainBin bin1;
|
||||
MainBin bin2;
|
||||
MainBin bin1("bin1");
|
||||
MainBin bin2("bin2");
|
||||
|
||||
double
|
||||
testfunc()
|
||||
|
@ -256,7 +255,7 @@ main(int argc, char *argv[])
|
|||
|
||||
check();
|
||||
|
||||
MainBin::activate(bin1);
|
||||
bin1.activate();
|
||||
|
||||
f1 = s1 + s2;
|
||||
f2 = (-s1) / (-s2) * -s3 + ULL(100) + s4;
|
||||
|
@ -452,7 +451,7 @@ main(int argc, char *argv[])
|
|||
s6.sample(8);
|
||||
s6.sample(9);
|
||||
|
||||
MainBin::activate(bin2);
|
||||
bin2.activate();
|
||||
s6.sample(10);
|
||||
s6.sample(10);
|
||||
s6.sample(10);
|
||||
|
@ -493,12 +492,12 @@ main(int argc, char *argv[])
|
|||
|
||||
s12.sample(100);
|
||||
|
||||
MainBin::activate(bin1);
|
||||
bin1.activate();
|
||||
cout << "dump 1" << endl;
|
||||
dump(cout);
|
||||
cout << endl << endl;
|
||||
|
||||
MainBin::activate(bin2);
|
||||
bin2.activate();
|
||||
cout << "dump 2" << endl;
|
||||
dump(cout);
|
||||
cout << endl << endl;
|
||||
|
|
Loading…
Reference in a new issue