From e72f1e63f0b17ab3701d955235a478d7b34a13fb Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 11 Apr 2007 12:25:00 +0000 Subject: [PATCH 01/68] Create a filter and a union to translate the SPARC instruction implementations from using doubles to using concatenated singles. --HG-- extra : convert_revision : 609ba35bbb13cbd1998e93957cb051461442d1f9 --- src/arch/sparc/isa/base.isa | 70 +++++++++++++++++++++ src/arch/sparc/isa/formats/basic.isa | 2 + src/arch/sparc/isa/formats/mem/basicmem.isa | 4 ++ src/arch/sparc/isa/formats/mem/blockmem.isa | 2 + src/arch/sparc/isa/operands.isa | 54 ++++++++++++---- 5 files changed, 121 insertions(+), 11 deletions(-) diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa index bba63f407..4339003e0 100644 --- a/src/arch/sparc/isa/base.isa +++ b/src/arch/sparc/isa/base.isa @@ -154,6 +154,76 @@ def template ROrImmDecode {{ } }}; +output header {{ + union DoubleSingle + { + double d; + uint64_t ui; + uint32_t s[2]; + DoubleSingle(double _d) : d(_d) + {} + DoubleSingle(uint64_t _ui) : ui(_ui) + {} + DoubleSingle(uint32_t _s0, uint32_t _s1) + { + s[0] = _s0; + s[1] = _s1; + } + }; +}}; + +let {{ + def filterDoubles(code): + assignRE = re.compile(r'\s*=(?!=)', re.MULTILINE) + for opName in ("Frd", "Frs1", "Frs2", "Frd_N"): + next_pos = 0 + operandsREString = (r''' + (?\d)_or_imm(?P\d+)(?P\.\w+)?') diff --git a/src/arch/sparc/isa/formats/basic.isa b/src/arch/sparc/isa/formats/basic.isa index 017f43780..7665d2d4f 100644 --- a/src/arch/sparc/isa/formats/basic.isa +++ b/src/arch/sparc/isa/formats/basic.isa @@ -97,6 +97,7 @@ def template BasicDecodeWithMnemonic {{ // The most basic instruction format... used only for a few misc. insts def format BasicOperate(code, *flags) {{ + code = filterDoubles(code) iop = InstObjParams(name, Name, 'SparcStaticInst', code, flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) @@ -140,6 +141,7 @@ def format FpBasic(code, *flags) {{ fesetround(oldrnd); #endif """ + fp_code = filterDoubles(fp_code) iop = InstObjParams(name, Name, 'SparcStaticInst', fp_code, flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) diff --git a/src/arch/sparc/isa/formats/mem/basicmem.isa b/src/arch/sparc/isa/formats/mem/basicmem.isa index 751262811..2f62c7bef 100644 --- a/src/arch/sparc/isa/formats/mem/basicmem.isa +++ b/src/arch/sparc/isa/formats/mem/basicmem.isa @@ -71,6 +71,7 @@ let {{ }}; def format LoadAlt(code, asi, *opt_flags) {{ + code = filterDoubles(code) (header_output, decoder_output, exec_output, @@ -79,6 +80,7 @@ def format LoadAlt(code, asi, *opt_flags) {{ }}; def format StoreAlt(code, asi, *opt_flags) {{ + code = filterDoubles(code) (header_output, decoder_output, exec_output, @@ -87,6 +89,7 @@ def format StoreAlt(code, asi, *opt_flags) {{ }}; def format Load(code, *opt_flags) {{ + code = filterDoubles(code) (header_output, decoder_output, exec_output, @@ -95,6 +98,7 @@ def format Load(code, *opt_flags) {{ }}; def format Store(code, *opt_flags) {{ + code = filterDoubles(code) (header_output, decoder_output, exec_output, diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa index 499685a5c..e19016bd0 100644 --- a/src/arch/sparc/isa/formats/mem/blockmem.isa +++ b/src/arch/sparc/isa/formats/mem/blockmem.isa @@ -317,6 +317,7 @@ let {{ }}; def format BlockLoad(code, asi, *opt_flags) {{ + code = filterDoubles(code) # We need to make sure to check the highest priority fault last. # That way, if other faults have been detected, they'll be overwritten # rather than the other way around. @@ -329,6 +330,7 @@ def format BlockLoad(code, asi, *opt_flags) {{ }}; def format BlockStore(code, asi, *opt_flags) {{ + code = filterDoubles(code) # We need to make sure to check the highest priority fault last. # That way, if other faults have been detected, they'll be overwritten # rather than the other way around. diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index 038919bd1..58d616a7a 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -52,6 +52,16 @@ output header {{ { return (regNum & (~1)) | ((regNum & 1) << 5); } + + static inline unsigned int dfprl(unsigned int regNum) + { + return dfpr(regNum) & (~0x1); + } + + static inline unsigned int dfprh(unsigned int regNum) + { + return dfpr(regNum) | 0x1; + } }}; def operands {{ @@ -79,21 +89,43 @@ def operands {{ # differently, they get different operands. The single precision versions # have an s post pended to their name. 'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10), - 'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), + #'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), + 'Frd_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10), + 'Frd_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10), # Each Frd_N refers to the Nth double precision register from Frd. # Note that this adds twice N to the register number. - 'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), - 'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10), - 'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10), - 'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10), - 'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10), - 'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10), - 'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10), - 'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10), + #'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), + 'Frd_0_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10), + 'Frd_0_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10), + #'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10), + 'Frd_1_low': ('FloatReg', 'uw', 'dfprl(RD) + 2', 'IsFloating', 10), + 'Frd_1_high': ('FloatReg', 'uw', 'dfprh(RD) + 2', 'IsFloating', 10), + #'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10), + 'Frd_2_low': ('FloatReg', 'uw', 'dfprl(RD) + 4', 'IsFloating', 10), + 'Frd_2_high': ('FloatReg', 'uw', 'dfprh(RD) + 4', 'IsFloating', 10), + #'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10), + 'Frd_3_low': ('FloatReg', 'uw', 'dfprl(RD) + 6', 'IsFloating', 10), + 'Frd_3_high': ('FloatReg', 'uw', 'dfprh(RD) + 6', 'IsFloating', 10), + #'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10), + 'Frd_4_low': ('FloatReg', 'uw', 'dfprl(RD) + 8', 'IsFloating', 10), + 'Frd_4_high': ('FloatReg', 'uw', 'dfprh(RD) + 8', 'IsFloating', 10), + #'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10), + 'Frd_5_low': ('FloatReg', 'uw', 'dfprl(RD) + 10', 'IsFloating', 10), + 'Frd_5_high': ('FloatReg', 'uw', 'dfprh(RD) + 10', 'IsFloating', 10), + #'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10), + 'Frd_6_low': ('FloatReg', 'uw', 'dfprl(RD) + 12', 'IsFloating', 10), + 'Frd_6_high': ('FloatReg', 'uw', 'dfprh(RD) + 12', 'IsFloating', 10), + #'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10), + 'Frd_7_low': ('FloatReg', 'uw', 'dfprl(RD) + 14', 'IsFloating', 10), + 'Frd_7_high': ('FloatReg', 'uw', 'dfprh(RD) + 14', 'IsFloating', 10), 'Frs1s': ('FloatReg', 'sf', 'RS1', 'IsFloating', 11), - 'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11), + #'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11), + 'Frs1_low': ('FloatReg', 'uw', 'dfprl(RS1)', 'IsFloating', 11), + 'Frs1_high': ('FloatReg', 'uw', 'dfprh(RS1)', 'IsFloating', 11), 'Frs2s': ('FloatReg', 'sf', 'RS2', 'IsFloating', 12), - 'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12), + #'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12), + 'Frs2_low': ('FloatReg', 'uw', 'dfprl(RS2)', 'IsFloating', 12), + 'Frs2_high': ('FloatReg', 'uw', 'dfprh(RS2)', 'IsFloating', 12), 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31), 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32), # Registers which are used explicitly in instructions From 121a5438a512ec26728a73ea8b4e5677bed4b94e Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 11 Apr 2007 12:26:23 +0000 Subject: [PATCH 02/68] Make trying to execute macroops fail with a better error message. --HG-- extra : convert_revision : e81c0337d6db4b5a33381ed19686750bbb9d9178 --- src/arch/sparc/isa/formats/micro.isa | 33 ++++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/src/arch/sparc/isa/formats/micro.isa b/src/arch/sparc/isa/formats/micro.isa index 82d7fb4cb..da0f97d1b 100644 --- a/src/arch/sparc/isa/formats/micro.isa +++ b/src/arch/sparc/isa/formats/micro.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2006 The Regents of The University of Michigan +// Copyright (c) 2006-2007 The Regents of The University of Michigan // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -26,6 +26,33 @@ // // Authors: Gabe Black +//This delcares the initiateAcc function in memory operations +def template MacroInitiateAcc {{ + Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const + { + panic("Tried to execute a macroop directly!\n"); + return NoFault; + } +}}; + +def template MacroCompleteAcc {{ + Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, + Trace::InstRecord *) const + { + panic("Tried to execute a macroop directly!\n"); + return NoFault; + } +}}; + +//This template provides the execute functions for a store +def template MacroExecute {{ + Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const + { + panic("Tried to execute a macroop directly!\n"); + return NoFault; + } +}}; + output header {{ class SparcMacroInst : public SparcStaticInst @@ -60,7 +87,9 @@ output header {{ return microOps[microPC]; } - %(BasicExecPanic)s + %(MacroExecute)s + %(MacroInitiateAcc)s + %(MacroCompleteAcc)s }; class SparcMicroInst : public SparcStaticInst From fa2a93a236f42d5b70061f3f8b2b65457eb5f836 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Thu, 12 Apr 2007 08:35:19 -0700 Subject: [PATCH 03/68] Add a scons hack to force symlinks to the swig .i files to be created --HG-- extra : convert_revision : 826cc692614528f987c80c3410cb025190f0a4e0 --- src/python/SConscript | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/python/SConscript b/src/python/SConscript index 6662c8a45..fc0b12f85 100644 --- a/src/python/SConscript +++ b/src/python/SConscript @@ -101,8 +101,11 @@ pyzip_files.append(join(env['ROOT'], 'src/base/traceflags.py')) swig_modules = [] def swig_it(module): - env.Command(['swig/%s_wrap.cc' % module, 'm5/internal/%s.py' % module], - 'swig/%s.i' % module, + cc_file = 'swig/%s_wrap.cc' % module + py_file = 'm5/internal/%s.py' % module + source = File('swig/%s.i' % module) + source.rfile() # Hack to cause the symlink to the .i file to be created + env.Command([cc_file, py_file], source, '$SWIG $SWIGFLAGS -outdir ${TARGETS[1].dir} ' '-o ${TARGETS[0]} $SOURCES') swig_modules.append(module) From e04208f046237c74a2350d98a74a2fdc0ad838fa Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Thu, 12 Apr 2007 08:37:55 -0700 Subject: [PATCH 04/68] Fix NextEthernetAddr. unproxy() needs to return a new object otherwise all instances will use the same value. This fix is more or less unique to NextEthernetAddr because its use of the proxy stuff is a bit different than everything else. --HG-- extra : convert_revision : 2ce452e37d00b9ba76b6abfaec0ad2e0073920d7 --- src/python/m5/params.py | 25 ++++++++++--------------- 1 file changed, 10 insertions(+), 15 deletions(-) diff --git a/src/python/m5/params.py b/src/python/m5/params.py index 9892df97c..da7ddd65e 100644 --- a/src/python/m5/params.py +++ b/src/python/m5/params.py @@ -51,6 +51,7 @@ import sys import time import convert +import proxy import ticks from util import * @@ -477,12 +478,13 @@ def IncEthernetAddr(addr, val = 1): assert(bytes[0] <= 255) return ':'.join(map(lambda x: '%02x' % x, bytes)) -class NextEthernetAddr(object): - addr = "00:90:00:00:00:01" +_NextEthernetAddr = "00:90:00:00:00:01" +def NextEthernetAddr(): + global _NextEthernetAddr - def __init__(self, inc = 1): - self.value = NextEthernetAddr.addr - NextEthernetAddr.addr = IncEthernetAddr(NextEthernetAddr.addr, inc) + value = _NextEthernetAddr + _NextEthernetAddr = IncEthernetAddr(_NextEthernetAddr, 1) + return value class EthernetAddr(ParamValue): cxx_type = 'Net::EthAddr' @@ -508,17 +510,11 @@ class EthernetAddr(ParamValue): def unproxy(self, base): if self.value == NextEthernetAddr: - self.addr = self.value().value + return EthernetAddr(self.value()) return self - def __str__(self): - if self.value == NextEthernetAddr: - if hasattr(self, 'addr'): - return self.addr - else: - return "NextEthernetAddr (unresolved)" - else: - return self.value + def ini_str(self): + return self.value time_formats = [ "%a %b %d %H:%M:%S %Z %Y", "%a %b %d %H:%M:%S %Z %Y", @@ -1028,6 +1024,5 @@ __all__ = ['Param', 'VectorParam', # see comment on imports at end of __init__.py. from SimObject import isSimObject, isSimObjectSequence, isSimObjectClass -import proxy import objects import internal From eefbda7f7c54735791dab70626a40a7d29aa8a80 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Thu, 12 Apr 2007 09:07:59 -0700 Subject: [PATCH 05/68] Don't allow Source to accept multiple arguments, lists, or automatically do Split(). It isn't used anywhere, and isn't very consistent with the python features that are about to be added. Do accept SCons.Node.FS.File arguments though. --HG-- extra : convert_revision : 0f3bb0e9e6806490330eea59a104013042b4dd49 --- src/SConscript | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/src/SConscript b/src/SConscript index 5efd2f794..da940c97a 100644 --- a/src/SConscript +++ b/src/SConscript @@ -33,21 +33,19 @@ import sys from os.path import join as joinpath +import SCons + # This file defines how to build a particular configuration of M5 # based on variable settings in the 'env' build environment. Import('*') sources = [] -def Source(*args): - for arg in args: - if isinstance(arg, (list, tuple)): - # Recurse to load a list - Source(*arg) - elif isinstance(arg, str): - sources.extend([ File(f) for f in Split(arg) ]) - else: - sources.append(File(arg)) +def Source(source): + if isinstance(source, SCons.Node.FS.File): + sources.append(source) + else: + sources.append(File(source)) Export('env') Export('Source') From a575fbd4aaa45af90535f67d5100b95b3c610f93 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Thu, 12 Apr 2007 21:20:04 -0700 Subject: [PATCH 06/68] Completely re-work how the scons framework incorporates swig and python code into m5 to allow swig an python code to easily added by any SConscript instead of just the one in src/python. This provides SwigSource and PySource for adding new files to m5 (similar to Source for C++). Also provides SimObject for including files that contain SimObject information and build the m5.objects __init__.py file. --HG-- extra : convert_revision : 38b50a0629846ef451ed02f96fe3633947df23eb --- src/SConscript | 187 +++++++++++++++++++++++++-- src/base/SConscript | 2 + src/python/SConscript | 197 ++++++++++++----------------- src/python/m5/internal/__init__.py | 35 +++++ 4 files changed, 290 insertions(+), 131 deletions(-) create mode 100644 src/python/m5/internal/__init__.py diff --git a/src/SConscript b/src/SConscript index da940c97a..34c5453b7 100644 --- a/src/SConscript +++ b/src/SConscript @@ -30,7 +30,9 @@ import os import sys +import zipfile +from os.path import basename from os.path import join as joinpath import SCons @@ -40,6 +42,12 @@ import SCons Import('*') +# Children need to see the environment +Export('env') + +######################################################################## +# Code for adding source files +# sources = [] def Source(source): if isinstance(source, SCons.Node.FS.File): @@ -47,9 +55,46 @@ def Source(source): else: sources.append(File(source)) -Export('env') +# Children should have access Export('Source') +######################################################################## +# Code for adding python objects +# +py_sources = [] +py_source_packages = {} +def PySource(package, source): + if not isinstance(source, SCons.Node.FS.File): + source = File(source) + py_source_packages[source] = package + py_sources.append(source) + +sim_objects = [] +def SimObject(source): + if not isinstance(source, SCons.Node.FS.File): + source = File(source) + PySource('m5.objects', source) + modname = basename(str(source)) + sim_objects.append(modname) + +swig_sources = [] +swig_source_packages = {} +def SwigSource(package, source): + if not isinstance(source, SCons.Node.FS.File): + source = File(source) + swig_source_packages[source] = package + swig_sources.append(source) + +# Children should have access +Export('PySource') +Export('SimObject') +Export('SwigSource') + +######################################################################## +# +# Set some compiler variables +# + # Include file paths are rooted in this directory. SCons will # automatically expand '.' to refer to both the source directory and # the corresponding build directory to pick up generated include @@ -59,7 +104,9 @@ env.Append(CPPPATH=Dir('.')) # Add a flag defining what THE_ISA should be for all compilation env.Append(CPPDEFINES=[('THE_ISA','%s_ISA' % env['TARGET_ISA'].upper())]) +######################################################################## # Walk the tree and execute all SConscripts +# scripts = [] srcdir = env['SRCDIR'] for root, dirs, files in os.walk(srcdir, topdown=True): @@ -76,6 +123,132 @@ for root, dirs, files in os.walk(srcdir, topdown=True): for opt in env.ExportOptions: env.ConfigFile(opt) +######################################################################## +# +# Deal with python/swig, object code. Collect .py files and +# generating a zip archive that is appended to the m5 binary. +# + +# Generate Python file that contains a dict specifying the current +# build_env flags. +def MakeDefinesPyFile(target, source, env): + f = file(str(target[0]), 'w') + print >>f, "m5_build_env = ", source[0] + f.close() + +optionDict = dict([(opt, env[opt]) for opt in env.ExportOptions]) +env.Command('python/m5/defines.py', Value(optionDict), MakeDefinesPyFile) +PySource('m5', 'python/m5/defines.py') + +def MakeInfoPyFile(target, source, env): + f = file(str(target[0]), 'w') + for src in source: + data = ''.join(file(src.srcnode().abspath, 'r').xreadlines()) + print >>f, "%s = %s" % (src, repr(data)) + f.close() + +env.Command('python/m5/info.py', + [ '#/AUTHORS', '#/LICENSE', '#/README', '#/RELEASE_NOTES' ], + MakeInfoPyFile) +PySource('m5', 'python/m5/info.py') + +def MakeObjectsInitFile(target, source, env): + f = file(str(target[0]), 'w') + print >>f, 'from m5.SimObject import *' + for src_path in source: + src_file = basename(src_path.get_contents()) + assert(src_file.endswith('.py')) + src_module = src_file[:-3] + print >>f, 'from %s import *' % src_module + f.close() + +env.Command('python/m5/objects/__init__.py', + [ Value(o) for o in sim_objects], + MakeObjectsInitFile) +PySource('m5.objects', 'python/m5/objects/__init__.py') + +swig_modules = [] +for source in swig_sources: + source.rfile() # Hack to cause the symlink to the .i file to be created + package = swig_source_packages[source] + filename = str(source) + module = basename(filename) + + assert(module.endswith('.i')) + module = module[:-2] + cc_file = 'swig/%s_wrap.cc' % module + py_file = 'm5/internal/%s.py' % module + + env.Command([cc_file, py_file], source, + '$SWIG $SWIGFLAGS -outdir ${TARGETS[1].dir} ' + '-o ${TARGETS[0]} $SOURCES') + env.Depends(py_file, source) + env.Depends(cc_file, source) + + swig_modules.append(Value(module)) + Source(cc_file) + PySource(package, py_file) + +def MakeSwigInit(target, source, env): + f = file(str(target[0]), 'w') + print >>f, 'extern "C" {' + for module in source: + print >>f, ' void init_%s();' % module.get_contents() + print >>f, '}' + print >>f, 'void init_swig() {' + for module in source: + print >>f, ' init_%s();' % module.get_contents() + print >>f, '}' + f.close() +env.Command('python/swig/init.cc', swig_modules, MakeSwigInit) + +def CompilePyFile(target, source, env): + import py_compile + py_compile.compile(str(source[0]), str(target[0])) + +py_compiled = [] +py_arcname = {} +py_zip_depends = [] +for source in py_sources: + filename = str(source) + package = py_source_packages[source] + arc_path = package.split('.') + [ basename(filename) + 'c' ] + zip_path = [ 'zip' ] + arc_path + arcname = joinpath(*arc_path) + zipname = joinpath(*zip_path) + f = File(zipname) + + env.Command(f, source, CompilePyFile) + py_compiled.append(f) + py_arcname[f] = arcname + + # make the zipfile depend on the archive name so that the archive + # is rebuilt if the name changes + py_zip_depends.append(Value(arcname)) + +# Action function to build the zip archive. Uses the PyZipFile module +# included in the standard Python library. +def buildPyZip(target, source, env): + zf = zipfile.ZipFile(str(target[0]), 'w') + for s in source: + arcname = py_arcname[s] + zipname = str(s) + zf.write(zipname, arcname) + zf.close() + +# Add the zip file target to the environment. +env.Command('m5py.zip', py_compiled, buildPyZip) +env.Depends('m5py.zip', py_zip_depends) + +######################################################################## +# +# Define binaries. Each different build type (debug, opt, etc.) gets +# a slightly different build environment. +# + +# List of constructed environments to pass back to SConstruct +envList = [] + # This function adds the specified sources to the given build # environment, and returns a list of all the corresponding SCons # Object nodes (including an extra one for date.cc). We explicitly @@ -90,16 +263,6 @@ def make_objs(sources, env): objs.append(date_obj) return objs -################################################### -# -# Define binaries. Each different build type (debug, opt, etc.) gets -# a slightly different build environment. -# -################################################### - -# List of constructed environments to pass back to SConstruct -envList = [] - # Function to create a new build environment as clone of current # environment 'env' with modified object suffix and optional stripped # binary. Additional keyword arguments are appended to corresponding @@ -118,7 +281,7 @@ def makeEnv(label, objsfx, strip = False, **kwargs): else: newEnv.Command(stripped_bin, bin, 'strip $SOURCE -o $TARGET') bin = stripped_bin - targets = newEnv.Concat(exe, [bin, 'python/m5py.zip']) + targets = newEnv.Concat(exe, [bin, 'm5py.zip']) newEnv.M5Binary = targets[0] envList.append(newEnv) diff --git a/src/base/SConscript b/src/base/SConscript index 6fc140145..5e4aaafc2 100644 --- a/src/base/SConscript +++ b/src/base/SConscript @@ -97,3 +97,5 @@ Source('stats/visit.cc') if env['USE_MYSQL']: Source('mysql.cc') Source('stats/mysql.cc') + +PySource('m5', 'traceflags.py') diff --git a/src/python/SConscript b/src/python/SConscript index fc0b12f85..e1095eabe 100644 --- a/src/python/SConscript +++ b/src/python/SConscript @@ -30,132 +30,91 @@ # Nathan Binkert import os -import zipfile - -# handy function for path joins -def join(*args): - return os.path.normpath(os.path.join(*args)) - Import('*') -# This SConscript is in charge of collecting .py files and generating -# a zip archive that is appended to the m5 binary. - -# List of files & directories to include in the zip file. To include -# a package, list only the root directory of the package, not any -# internal .py files (else they will get the path stripped off when -# they are imported into the zip file). -pyzip_files = [] - -# List of additional files on which the zip archive depends, but which -# are not included in pyzip_files... i.e. individual .py files within -# a package. -pyzip_dep_files = [] - -# Add the specified package to the zip archive. Adds the directory to -# pyzip_files and all included .py files to pyzip_dep_files. -def addPkg(pkgdir): - pyzip_files.append(pkgdir) - origdir = os.getcwd() - srcdir = join(Dir('.').srcnode().abspath, pkgdir) - os.chdir(srcdir) - for path, dirs, files in os.walk('.'): - for i,dir in enumerate(dirs): - if dir == 'SCCS': - del dirs[i] - break - - for f in files: - if f.endswith('.py'): - pyzip_dep_files.append(join(pkgdir, path, f)) - - os.chdir(origdir) - -# Generate Python file that contains a dict specifying the current -# build_env flags. -def MakeDefinesPyFile(target, source, env): - f = file(str(target[0]), 'w') - print >>f, "m5_build_env = ", source[0] - f.close() - -optionDict = dict([(opt, env[opt]) for opt in env.ExportOptions]) -env.Command('m5/defines.py', Value(optionDict), MakeDefinesPyFile) - -def MakeInfoPyFile(target, source, env): - f = file(str(target[0]), 'w') - for src in source: - data = ''.join(file(src.srcnode().abspath, 'r').xreadlines()) - print >>f, "%s = %s" % (src, repr(data)) - f.close() - -env.Command('m5/info.py', - [ '#/AUTHORS', '#/LICENSE', '#/README', '#/RELEASE_NOTES' ], - MakeInfoPyFile) - -# Now specify the packages & files for the zip archive. -addPkg('m5') -pyzip_files.append('m5/defines.py') -pyzip_files.append('m5/info.py') -pyzip_files.append(join(env['ROOT'], 'util/pbs/jobfile.py')) -pyzip_files.append(join(env['ROOT'], 'src/base/traceflags.py')) - -swig_modules = [] -def swig_it(module): - cc_file = 'swig/%s_wrap.cc' % module - py_file = 'm5/internal/%s.py' % module - source = File('swig/%s.i' % module) - source.rfile() # Hack to cause the symlink to the .i file to be created - env.Command([cc_file, py_file], source, - '$SWIG $SWIGFLAGS -outdir ${TARGETS[1].dir} ' - '-o ${TARGETS[0]} $SOURCES') - swig_modules.append(module) - Source('swig/%s_wrap.cc' % module) - Source('swig/init.cc') Source('swig/pyevent.cc') Source('swig/pyobject.cc') -swig_it('core') -swig_it('debug') -swig_it('event') -swig_it('random') -swig_it('sim_object') -swig_it('stats') -swig_it('trace') +PySource('m5', 'm5/__init__.py') +PySource('m5', 'm5/SimObject.py') +PySource('m5', 'm5/attrdict.py') +PySource('m5', 'm5/convert.py') +PySource('m5', 'm5/event.py') +PySource('m5', 'm5/main.py') +PySource('m5', 'm5/multidict.py') +PySource('m5', 'm5/params.py') +PySource('m5', 'm5/proxy.py') +PySource('m5', 'm5/smartdict.py') +PySource('m5', 'm5/stats.py') +PySource('m5', 'm5/ticks.py') +PySource('m5', 'm5/util.py') -# Automatically generate m5/internals/__init__.py -def MakeInternalsInit(target, source, env): - f = file(str(target[0]), 'w') - for m in swig_modules: - print >>f, 'import %s' % m - f.close() +PySource('m5', os.path.join(env['ROOT'], 'util/pbs/jobfile.py')) -swig_py_files = [ 'm5/internal/%s.py' % m for m in swig_modules ] -env.Command('m5/internal/__init__.py', swig_py_files, MakeInternalsInit) -pyzip_dep_files.append('m5/internal/__init__.py') +SwigSource('m5.internal', 'swig/core.i') +SwigSource('m5.internal', 'swig/debug.i') +SwigSource('m5.internal', 'swig/event.i') +SwigSource('m5.internal', 'swig/random.i') +SwigSource('m5.internal', 'swig/sim_object.i') +SwigSource('m5.internal', 'swig/stats.i') +SwigSource('m5.internal', 'swig/trace.i') +PySource('m5.internal', 'm5/internal/__init__.py') -def MakeSwigInit(target, source, env): - f = file(str(target[0]), 'w') - print >>f, 'extern "C" {' - for m in swig_modules: - print >>f, ' void init_%s();' % m - print >>f, '}' - print >>f, 'void init_swig() {' - for m in swig_modules: - print >>f, ' init_%s();' % m - print >>f, '}' - f.close() +SimObject('m5/objects/AlphaConsole.py') +SimObject('m5/objects/AlphaTLB.py') +SimObject('m5/objects/BadDevice.py') +SimObject('m5/objects/BaseCPU.py') +SimObject('m5/objects/BaseCache.py') +SimObject('m5/objects/BaseHier.py') +SimObject('m5/objects/BaseMem.py') +SimObject('m5/objects/BaseMemory.py') +SimObject('m5/objects/BranchPred.py') +SimObject('m5/objects/Bridge.py') +SimObject('m5/objects/Bus.py') +SimObject('m5/objects/Checker.py') +SimObject('m5/objects/CoherenceProtocol.py') +SimObject('m5/objects/DRAMMemory.py') +SimObject('m5/objects/Device.py') +SimObject('m5/objects/DiskImage.py') +SimObject('m5/objects/Ethernet.py') +SimObject('m5/objects/FUPool.py') +SimObject('m5/objects/FastCPU.py') +#SimObject('m5/objects/FreebsdSystem.py') +SimObject('m5/objects/FullCPU.py') +SimObject('m5/objects/FuncUnit.py') +SimObject('m5/objects/FuncUnitConfig.py') +SimObject('m5/objects/FunctionalMemory.py') +SimObject('m5/objects/HierParams.py') +SimObject('m5/objects/Ide.py') +SimObject('m5/objects/IntrControl.py') +SimObject('m5/objects/LinuxSystem.py') +SimObject('m5/objects/MainMemory.py') +SimObject('m5/objects/MemObject.py') +SimObject('m5/objects/MemTest.py') +SimObject('m5/objects/MemoryController.py') +SimObject('m5/objects/O3CPU.py') +SimObject('m5/objects/OzoneCPU.py') +SimObject('m5/objects/Pci.py') +SimObject('m5/objects/PhysicalMemory.py') +SimObject('m5/objects/PipeTrace.py') +SimObject('m5/objects/Platform.py') +SimObject('m5/objects/Process.py') +SimObject('m5/objects/Repl.py') +SimObject('m5/objects/Root.py') +SimObject('m5/objects/Sampler.py') +SimObject('m5/objects/Scsi.py') +SimObject('m5/objects/SimConsole.py') +SimObject('m5/objects/SimpleCPU.py') +SimObject('m5/objects/SimpleDisk.py') +#SimObject('m5/objects/SimpleOzoneCPU.py') +SimObject('m5/objects/SparcTLB.py') +SimObject('m5/objects/System.py') +SimObject('m5/objects/T1000.py') +#SimObject('m5/objects/Tru64System.py') +SimObject('m5/objects/Tsunami.py') +SimObject('m5/objects/Uart.py') -swig_cc_files = [ 'swig/%s_wrap.cc' % m for m in swig_modules ] -env.Command('swig/init.cc', swig_cc_files, MakeSwigInit) - -# Action function to build the zip archive. Uses the PyZipFile module -# included in the standard Python library. -def buildPyZip(target, source, env): - pzf = zipfile.PyZipFile(str(target[0]), 'w') - for s in source: - pzf.writepy(str(s)) - -# Add the zip file target to the environment. -env.Command('m5py.zip', pyzip_files, buildPyZip) -env.Depends('m5py.zip', pyzip_dep_files) +if env['ALPHA_TLASER']: + SimObject('m5/objects/DmaEngine.py') + SimObject('m5/objects/Turbolaser.py') diff --git a/src/python/m5/internal/__init__.py b/src/python/m5/internal/__init__.py new file mode 100644 index 000000000..6b7859cd7 --- /dev/null +++ b/src/python/m5/internal/__init__.py @@ -0,0 +1,35 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +import core +import debug +import event +import random +import sim_object +import stats +import trace From 2778458eb5c089cfa120f290acae010df424bbdc Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 13 Apr 2007 13:33:32 -0400 Subject: [PATCH 07/68] take a first stab at the release notes AUTHORS: add sparc full system support to my list of accolades --HG-- extra : convert_revision : 1d3afaae2502306e44cd7fb251e763931a7e3ae9 --- AUTHORS | 2 +- RELEASE_NOTES | 18 +++++++++++++++++- 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/AUTHORS b/AUTHORS index a7ee88c4b..848e3e1df 100644 --- a/AUTHORS +++ b/AUTHORS @@ -29,13 +29,13 @@ Steven K. Reinhardt Ali G. Saidi ----------------------- +* SPARC Full System Support * Alpha Linux support * Alpha (Tsunami) platform and devices * I/O <-> memory interface * PCI device interface * Multiple ISA support * Memory bridge, bus, packet, port interfaces -* SPARC IPRs Kevin T. Lim ----------------------- diff --git a/RELEASE_NOTES b/RELEASE_NOTES index 03eec3aab..eebe0eb57 100644 --- a/RELEASE_NOTES +++ b/RELEASE_NOTES @@ -1,3 +1,19 @@ +Apr. XX, 2007: m5_2.0_beta3 +-------------------- +New Features +1. Some support for SPARC full-system simulation + +Bug fixes since beta 2: +1. Many SPARC linux syscall emulation support fixes +2. Multiprocessor linux boot using the detailed O3 CPU module +3. Simulator performance and memory leak fixes +4. Fix issues with remote debugging +5. Many other minor fixes and enhancements + +Outstanding issues for 2.0 release: +-------------------- +1. ??? + Nov. 28, 2006: m5_2.0_beta2 -------------------- Bug fixes since beta 1: @@ -7,7 +23,7 @@ Bug fixes since beta 1: 4. Draining/Switchover 5. Functional Accesses 6. Bus now has real timing -7. Single config file fro all SpecCPU2000 benchmarks +7. Single config file for all SpecCPU2000 benchmarks 8. Several other minor bug fixes and enhancements Outstading issues for 2.0 release: From 733a57d45a6a99a6259bff979ac7e40e5231f84f Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Sun, 15 Apr 2007 22:29:37 -0400 Subject: [PATCH 08/68] Update long test refs. tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini: tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out: tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr: tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini: tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out: tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr: tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini: tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out: tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr: tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini: tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out: tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr: tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini: tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out: tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.out: tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr: Update refs. --HG-- extra : convert_revision : 19483a5a18e76338a3208a58d7460a922377acd3 --- .../ref/alpha/tru64/o3-timing/config.ini | 50 +- .../ref/alpha/tru64/o3-timing/config.out | 48 +- .../ref/alpha/tru64/o3-timing/m5stats.txt | 552 ++++++++-------- .../00.gzip/ref/alpha/tru64/o3-timing/stderr | 2 +- .../ref/alpha/tru64/o3-timing/config.ini | 59 +- .../ref/alpha/tru64/o3-timing/config.out | 60 +- .../ref/alpha/tru64/o3-timing/m5stats.txt | 570 ++++++++--------- .../30.eon/ref/alpha/tru64/o3-timing/stderr | 3 +- .../ref/alpha/tru64/o3-timing/config.ini | 50 +- .../ref/alpha/tru64/o3-timing/config.out | 48 +- .../ref/alpha/tru64/o3-timing/m5stats.txt | 574 ++++++++--------- .../ref/alpha/tru64/o3-timing/stderr | 2 +- .../ref/alpha/tru64/o3-timing/config.ini | 50 +- .../ref/alpha/tru64/o3-timing/config.out | 48 +- .../ref/alpha/tru64/o3-timing/m5stats.txt | 564 ++++++++--------- .../60.bzip2/ref/alpha/tru64/o3-timing/stderr | 3 +- .../ref/alpha/tru64/o3-timing/config.ini | 15 +- .../ref/alpha/tru64/o3-timing/config.out | 14 +- .../ref/alpha/tru64/o3-timing/m5stats.txt | 598 +++++++++--------- .../ref/alpha/tru64/o3-timing/smred.out | 4 +- .../70.twolf/ref/alpha/tru64/o3-timing/stderr | 2 +- 21 files changed, 1490 insertions(+), 1826 deletions(-) diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index fa5ac1725..853e93096 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -1,48 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -70,6 +29,7 @@ commitToFetchDelay=1 commitToIEWDelay=1 commitToRenameDelay=1 commitWidth=8 +cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 @@ -155,7 +115,7 @@ split=false split_size=0 store_compressed=false subblock_size=0 -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -331,7 +291,7 @@ split=false split_size=0 store_compressed=false subblock_size=0 -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -388,7 +348,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing egid=100 env= euid=100 diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out index 8744b6907..e04428224 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -31,7 +28,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip input=cin output=cout env= -cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing system=system uid=100 euid=100 @@ -173,6 +170,7 @@ type=DerivO3CPU clock=1 phase=0 numThreads=1 +cpu_id=0 activity=0 workload=system.cpu.workload checker=null @@ -253,7 +251,7 @@ assoc=2 block_size=64 latency=1 mshrs=10 -tgts_per_mshr=5 +tgts_per_mshr=20 write_buffers=8 prioritizeRequests=false protocol=null @@ -291,7 +289,7 @@ assoc=2 block_size=64 latency=1 mshrs=10 -tgts_per_mshr=5 +tgts_per_mshr=20 write_buffers=8 prioritizeRequests=false protocol=null @@ -367,39 +365,3 @@ clock=1000 width=64 responder_set=false -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt index 8303336ed..78a2b3f52 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 97621780 # Number of BTB hits -global.BPredUnit.BTBLookups 104888901 # Number of BTB lookups -global.BPredUnit.RASInCorrect 203 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 4270829 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 101462576 # Number of conditional branches predicted -global.BPredUnit.lookups 108029652 # Number of BP lookups -global.BPredUnit.usedRAS 1765818 # Number of times the RAS was used to get a target. -host_inst_rate 64442 # Simulator instruction rate (inst/s) -host_mem_usage 296420 # Number of bytes of host memory used -host_seconds 8776.17 # Real time elapsed on the host -host_tick_rate 192322 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 20975706 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 18042230 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 207074480 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 57063120 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 71631614 # Number of BTB hits +global.BPredUnit.BTBLookups 80215513 # Number of BTB lookups +global.BPredUnit.RASInCorrect 194 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 4366377 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 76991765 # Number of conditional branches predicted +global.BPredUnit.lookups 83232960 # Number of BP lookups +global.BPredUnit.usedRAS 1776050 # Number of times the RAS was used to get a target. +host_inst_rate 91613 # Simulator instruction rate (inst/s) +host_mem_usage 151676 # Number of bytes of host memory used +host_seconds 6173.25 # Real time elapsed on the host +host_tick_rate 271486 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 26015543 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 23632204 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 134244919 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 44983310 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated -sim_seconds 0.001688 # Number of seconds simulated -sim_ticks 1687849017 # Number of ticks simulated +sim_seconds 0.001676 # Number of seconds simulated +sim_ticks 1675949017 # Number of ticks simulated system.cpu.commit.COM:branches 62547159 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 17132854 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 16353031 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 701581491 +system.cpu.commit.COM:committed_per_cycle.samples 801372491 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 480309675 6846.10% - 1 104094392 1483.71% - 2 40244499 573.63% - 3 11990473 170.91% - 4 15113210 215.42% - 5 17360338 247.45% - 6 10367558 147.77% - 7 4968492 70.82% - 8 17132854 244.20% + 0 580782547 7247.35% + 1 101892793 1271.48% + 2 41339172 515.85% + 3 11939444 148.99% + 4 15719123 196.15% + 5 17754998 221.56% + 6 10147917 126.63% + 7 5443466 67.93% + 8 16353031 204.06% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 115049510 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 154862033 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 4270194 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 4365734 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 331156834 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 90079827 # The number of squashed insts skipped by commit system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 2.984425 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.984425 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 114919015 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3573.284961 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3259.194046 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 114199728 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2570217420 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.006259 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 719287 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 495902 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 728055062 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001944 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 223385 # number of ReadReq MSHR misses +system.cpu.cpi 2.963384 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.963384 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 120253770 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3927.286441 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3434.366579 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 119156440 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4309529230 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.009125 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1097330 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 872988 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 770472667 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001866 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 224342 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3753.412851 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3080.837357 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 38221364 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4616536410 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.031177 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1229957 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 972712 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 792530006 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006521 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 257245 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 329.539233 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 2285.588257 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 317.127712 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 3492 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 327032 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 1150751 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 747460499 # number of cycles access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 9089.303046 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 9344.661839 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 37503702 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 17702499310 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.049368 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1947619 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1690762 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2400241806 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006511 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 256857 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 327.941025 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 3498.764706 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 325.562069 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 3493 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 17 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 1145498 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 59479 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 154370336 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3686.944185 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3163.733159 # average overall mshr miss latency -system.cpu.dcache.demand_hits 152421092 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 7186753830 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.012627 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1949244 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 1468614 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1520585068 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003113 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 480630 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 159705091 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 7229.030286 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 6589.195890 # average overall mshr miss latency +system.cpu.dcache.demand_hits 156660142 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 22012028540 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.019066 # miss rate for demand accesses +system.cpu.dcache.demand_misses 3044949 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2563750 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 3170714473 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.003013 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 481199 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 154370336 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3686.944185 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3163.733159 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 159705091 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 7229.030286 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 6589.195890 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 152421092 # number of overall hits -system.cpu.dcache.overall_miss_latency 7186753830 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.012627 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1949244 # number of overall misses -system.cpu.dcache.overall_mshr_hits 1468614 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1520585068 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003113 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 480630 # number of overall MSHR misses +system.cpu.dcache.overall_hits 156660142 # number of overall hits +system.cpu.dcache.overall_miss_latency 22012028540 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.019066 # miss rate for overall accesses +system.cpu.dcache.overall_misses 3044949 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2563750 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 3170714473 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.003013 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 481199 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 476534 # number of replacements -system.cpu.dcache.sampled_refs 480630 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 477103 # number of replacements +system.cpu.dcache.sampled_refs 481199 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4061.534340 # Cycle average of tags in use -system.cpu.dcache.total_refs 152421092 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 22778000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 337990 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 113629190 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 667 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 4610173 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 1474333999 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 347767079 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 231043933 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 53597030 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 1980 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 9141290 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 108029652 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 167528188 # Number of cache lines fetched -system.cpu.fetch.Cycles 410392582 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 7840605 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 1486495774 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 39151172 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.143052 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 167528188 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 99387598 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.968403 # Number of inst fetches per cycle +system.cpu.dcache.tagsinuse 4063.174314 # Cycle average of tags in use +system.cpu.dcache.total_refs 156660142 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 20910000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 338217 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 515310439 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 681 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 4340917 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 740208637 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 161139948 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 116871564 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 14453620 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 2001 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 8050541 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 83232960 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 72135284 # Number of cache lines fetched +system.cpu.fetch.Cycles 198811102 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1485258 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 751818937 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 5990379 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.102023 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 72135284 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 73407664 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.921543 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 755178522 +system.cpu.fetch.rateDist.samples 815826112 system.cpu.fetch.rateDist.min_value 0 - 0 512314112 6784.01% - 1 11453310 151.66% - 2 16801464 222.48% - 3 16318450 216.09% - 4 18767749 248.52% - 5 15201778 201.30% - 6 32935567 436.13% - 7 7297838 96.64% - 8 124088254 1643.16% + 0 689150299 8447.27% + 1 10579353 129.68% + 2 12110332 148.44% + 3 11560507 141.70% + 4 9007686 110.41% + 5 3425511 41.99% + 6 3768928 46.20% + 7 3222436 39.50% + 8 73001060 894.81% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 167528184 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 5600.855285 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 4703.251892 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 167526954 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 6889052 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000007 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1230 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 305 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 4350508 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 925 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 72135284 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5699.600162 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4917.297556 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 72134046 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 7056105 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000017 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 1238 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 297 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 4627177 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000013 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 941 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets 5880.941176 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 181110.220541 # Average number of references to valid blocks. +system.cpu.icache.avg_blocked_cycles_no_targets 3783 # average number of cycles each access was blocked +system.cpu.icache.avg_refs 76656.797024 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 17 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 1 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 99976 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 3783 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 167528184 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 5600.855285 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 4703.251892 # average overall mshr miss latency -system.cpu.icache.demand_hits 167526954 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 6889052 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000007 # miss rate for demand accesses -system.cpu.icache.demand_misses 1230 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 305 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 4350508 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000006 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 925 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 72135284 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5699.600162 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4917.297556 # average overall mshr miss latency +system.cpu.icache.demand_hits 72134046 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 7056105 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000017 # miss rate for demand accesses +system.cpu.icache.demand_misses 1238 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 297 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 4627177 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000013 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 941 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 167528184 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 5600.855285 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 4703.251892 # average overall mshr miss latency +system.cpu.icache.overall_accesses 72135284 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5699.600162 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4917.297556 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 167526954 # number of overall hits -system.cpu.icache.overall_miss_latency 6889052 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000007 # miss rate for overall accesses -system.cpu.icache.overall_misses 1230 # number of overall misses -system.cpu.icache.overall_mshr_hits 305 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 4350508 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000006 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 925 # number of overall MSHR misses +system.cpu.icache.overall_hits 72134046 # number of overall hits +system.cpu.icache.overall_miss_latency 7056105 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000017 # miss rate for overall accesses +system.cpu.icache.overall_misses 1238 # number of overall misses +system.cpu.icache.overall_mshr_hits 297 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 4627177 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000013 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 941 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,63 +215,63 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 47 # number of replacements -system.cpu.icache.sampled_refs 925 # Sample count of references to valid blocks. +system.cpu.icache.replacements 44 # number of replacements +system.cpu.icache.sampled_refs 941 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 739.927243 # Cycle average of tags in use -system.cpu.icache.total_refs 167526954 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 749.515669 # Cycle average of tags in use +system.cpu.icache.total_refs 72134046 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 932670496 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 92484798 # Number of branches executed -system.cpu.iew.EXEC:nop 154927960 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.987080 # Inst execution rate -system.cpu.iew.EXEC:refs 253735466 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 51400640 # Number of stores executed +system.cpu.idleCycles 860122906 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 67691806 # Number of branches executed +system.cpu.iew.EXEC:nop 43795429 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.748142 # Inst execution rate +system.cpu.iew.EXEC:refs 168635664 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 41396142 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 486804101 # num instructions consuming a value -system.cpu.iew.WB:count 671280122 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.809385 # average fanout of values written-back +system.cpu.iew.WB:consumers 508232399 # num instructions consuming a value +system.cpu.iew.WB:count 603225060 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.792920 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 394011709 # num instructions producing a value -system.cpu.iew.WB:rate 0.888903 # insts written-back per cycle -system.cpu.iew.WB:sent 673021204 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 4738518 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 26824121 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 207074480 # Number of dispatched load instructions +system.cpu.iew.WB:producers 402987686 # num instructions producing a value +system.cpu.iew.WB:rate 0.739404 # insts written-back per cycle +system.cpu.iew.WB:sent 604785539 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 4695315 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 442855270 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 134244919 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 169524029 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 57063120 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 933012139 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 202334826 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7294318 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 745421559 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 36474 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 5961708 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 44983310 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 691933738 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 127239522 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6754480 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 610353566 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 42801 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 1439 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 53597030 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 214253 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 5548 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 70837719 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 7377596 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 20150 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.iewLSQFullEvents 120734 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 14453620 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 431168 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 1871526 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 4575118 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 24838 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 1892 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 5548 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 92024970 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 17250597 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 1892 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 530187 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 4208331 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.335073 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.335073 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 752715877 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 1001889 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 5578 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 19195409 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 5170787 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 1001889 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 542024 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 4153291 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.337452 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.337452 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 617108046 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 0 0.00% # Type of FU issued - IntAlu 496182294 65.92% # Type of FU issued - IntMult 8208 0.00% # Type of FU issued + IntAlu 445691749 72.22% # Type of FU issued + IntMult 6563 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 33 0.00% # Type of FU issued FloatCmp 6 0.00% # Type of FU issued @@ -279,16 +279,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 5 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 204178453 27.13% # Type of FU issued - MemWrite 52346873 6.95% # Type of FU issued + MemRead 129192933 20.94% # Type of FU issued + MemWrite 42216752 6.84% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 3466320 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.004605 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 3402065 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.005513 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 2723724 78.58% # attempts to use FU when none available + IntAlu 2626203 77.19% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -297,80 +297,80 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 683243 19.71% # attempts to use FU when none available - MemWrite 59353 1.71% # attempts to use FU when none available + MemRead 644339 18.94% # attempts to use FU when none available + MemWrite 131523 3.87% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 755178522 +system.cpu.iq.ISSUE:issued_per_cycle.samples 815826112 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 450030250 5959.26% - 1 91846319 1216.22% - 2 83470092 1105.30% - 3 53962116 714.56% - 4 57175468 757.11% - 5 10089384 133.60% - 6 7448894 98.64% - 7 1047122 13.87% - 8 108877 1.44% + 0 553114491 6779.81% + 1 85371128 1046.44% + 2 77782451 953.42% + 3 52154516 639.28% + 4 28098332 344.42% + 5 10103046 123.84% + 6 7930576 97.21% + 7 956122 11.72% + 8 315450 3.87% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.996739 # Inst issue rate -system.cpu.iq.iqInstsAdded 778084154 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 752715877 # Number of instructions issued +system.cpu.iq.ISSUE:rate 0.756421 # Inst issue rate +system.cpu.iq.iqInstsAdded 648138284 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 617108046 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 210836257 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 250496 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 80438129 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 1088392 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 119170992 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 481555 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 6806.870170 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2221.284395 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 455236 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 179150016 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.054654 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 26319 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 58461984 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054654 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 26319 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 337990 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 337990 # number of Writeback hits +system.cpu.iq.iqSquashedOperandsExamined 57507029 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 482140 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 8078.944187 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2363.998861 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 455802 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 212783232 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.054627 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 26338 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 62263002 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054627 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 26338 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 338217 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 338217 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 30.138911 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 30.147278 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 481555 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 6806.870170 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2221.284395 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 455236 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 179150016 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.054654 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 26319 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 482140 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 8078.944187 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2363.998861 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 455802 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 212783232 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.054627 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 26338 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 58461984 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.054654 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 26319 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 62263002 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.054627 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 26338 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 819545 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 6806.870170 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2221.284395 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 820357 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 8078.944187 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2363.998861 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 793226 # number of overall hits -system.cpu.l2cache.overall_miss_latency 179150016 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.032114 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 26319 # number of overall misses +system.cpu.l2cache.overall_hits 794019 # number of overall hits +system.cpu.l2cache.overall_miss_latency 212783232 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.032106 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 26338 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 58461984 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.032114 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 26319 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 62263002 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.032106 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 26338 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -382,32 +382,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 934 # number of replacements -system.cpu.l2cache.sampled_refs 26319 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 935 # number of replacements +system.cpu.l2cache.sampled_refs 26338 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 24352.046438 # Cycle average of tags in use -system.cpu.l2cache.total_refs 793226 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 24391.955858 # Cycle average of tags in use +system.cpu.l2cache.total_refs 794019 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 907 # number of writebacks -system.cpu.numCycles 755178522 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 71954881 # Number of cycles rename is blocking +system.cpu.l2cache.writebacks 908 # number of writebacks +system.cpu.numCycles 815826112 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 467231804 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 32102756 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 363513131 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 18414484 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 164520 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 1301215151 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 1374424300 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 698904999 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 224329578 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 53597030 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 41747264 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 235050110 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 36638 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:IQFullEvents 38638370 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 170863189 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 8553533 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 36121 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 961623776 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 729244091 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 554812455 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 115192044 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 14453620 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 48042805 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 90957566 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 42650 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 30 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 105666858 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 77555696 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 28 # count of temporary serializing insts renamed -system.cpu.timesIdled 349047 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 308219 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr index eb1796ead..f33d007a7 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini index 915a6967f..7d8c8259e 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -1,48 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -70,6 +29,7 @@ commitToFetchDelay=1 commitToIEWDelay=1 commitToRenameDelay=1 commitWidth=8 +cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 @@ -155,7 +115,7 @@ split=false split_size=0 store_compressed=false subblock_size=0 -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -331,7 +291,7 @@ split=false split_size=0 store_compressed=false subblock_size=0 -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -388,7 +348,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing egid=100 env= euid=100 @@ -417,12 +377,3 @@ range=0:134217727 zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out index 80e067401..96829f8a9 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -31,7 +28,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon input=cin output=cout env= -cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing system=system uid=100 euid=100 @@ -173,6 +170,7 @@ type=DerivO3CPU clock=1 phase=0 numThreads=1 +cpu_id=0 activity=0 workload=system.cpu.workload checker=null @@ -253,7 +251,7 @@ assoc=2 block_size=64 latency=1 mshrs=10 -tgts_per_mshr=5 +tgts_per_mshr=20 write_buffers=8 prioritizeRequests=false protocol=null @@ -291,7 +289,7 @@ assoc=2 block_size=64 latency=1 mshrs=10 -tgts_per_mshr=5 +tgts_per_mshr=20 write_buffers=8 prioritizeRequests=false protocol=null @@ -367,51 +365,3 @@ clock=1000 width=64 responder_set=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt index 9d00cb146..bca3fa536 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 38046005 # Number of BTB hits -global.BPredUnit.BTBLookups 46765160 # Number of BTB lookups -global.BPredUnit.RASInCorrect 1072 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 5897447 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 36345249 # Number of conditional branches predicted -global.BPredUnit.lookups 64275681 # Number of BP lookups -global.BPredUnit.usedRAS 12928446 # Number of times the RAS was used to get a target. -host_inst_rate 88491 # Simulator instruction rate (inst/s) -host_mem_usage 183984 # Number of bytes of host memory used -host_seconds 4244.22 # Real time elapsed on the host -host_tick_rate 69460 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 64217134 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 49870920 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 126084683 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 92646936 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 36573856 # Number of BTB hits +global.BPredUnit.BTBLookups 48300104 # Number of BTB lookups +global.BPredUnit.RASInCorrect 1110 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 6040473 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 37489973 # Number of conditional branches predicted +global.BPredUnit.lookups 66376995 # Number of BP lookups +global.BPredUnit.usedRAS 13616030 # Number of times the RAS was used to get a target. +host_inst_rate 78938 # Simulator instruction rate (inst/s) +host_mem_usage 153528 # Number of bytes of host memory used +host_seconds 4757.83 # Real time elapsed on the host +host_tick_rate 66128 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 89962751 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 64024234 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 131935591 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 95765344 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 375574675 # Number of instructions simulated -sim_seconds 0.000295 # Number of seconds simulated -sim_ticks 294803028 # Number of ticks simulated +sim_seconds 0.000315 # Number of seconds simulated +sim_ticks 314625027 # Number of ticks simulated system.cpu.commit.COM:branches 44587523 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 16167573 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 13381546 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 260352657 +system.cpu.commit.COM:committed_per_cycle.samples 276331431 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 139362663 5352.84% - 1 37755491 1450.17% - 2 23927219 919.03% - 3 17243764 662.32% - 4 9550787 366.84% - 5 7718539 296.46% - 6 5199548 199.71% - 7 3427073 131.63% - 8 16167573 620.99% + 0 148231465 5364.26% + 1 40756250 1474.90% + 2 28135615 1018.18% + 3 18140880 656.49% + 4 10622787 384.42% + 5 8112500 293.58% + 6 5544405 200.64% + 7 3405983 123.26% + 8 13381546 484.26% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 100651988 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 174183388 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 5893264 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 6036288 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 398664447 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 98024957 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 118579541 # The number of squashed insts skipped by commit system.cpu.committedInsts 375574675 # Number of Instructions Simulated system.cpu.committedInsts_total 375574675 # Number of Instructions Simulated -system.cpu.cpi 0.784939 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.784939 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 94465294 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 5573.350269 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5155.812183 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 94463621 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 9324215 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1673 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 688 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 5078475 # number of ReadReq MSHR miss cycles +system.cpu.cpi 0.837716 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.837716 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 96374626 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5603.456853 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5219.612576 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 96372656 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 11038810 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000020 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1970 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 984 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 5146538 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 985 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 986 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 73520727 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 5442.694460 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5169.706416 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 73508218 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 68082665 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000170 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 12509 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 9314 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 16517212 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 6647.641993 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6867.316020 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 73501543 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 127528364 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000261 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 19184 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 15988 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 21947942 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 3195 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 2708.631579 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 3690.984252 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 40184.650478 # Average number of references to valid blocks. +system.cpu.dcache.WriteReq_mshr_misses 3196 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 2800 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 40620.324964 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 19 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 2032 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 51464 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 7500080 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 53200 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 167986021 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 5458.107460 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 5166.432297 # average overall mshr miss latency -system.cpu.dcache.demand_hits 167971839 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 77406880 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses -system.cpu.dcache.demand_misses 14182 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 10002 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 21595687 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_accesses 169895353 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 6550.400586 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 6478.833094 # average overall mshr miss latency +system.cpu.dcache.demand_hits 169874199 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 138567174 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000125 # miss rate for demand accesses +system.cpu.dcache.demand_misses 21154 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 16972 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 27094480 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 4180 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 4182 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 167986021 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 5458.107460 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 5166.432297 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 169895353 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 6550.400586 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 6478.833094 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 167971839 # number of overall hits -system.cpu.dcache.overall_miss_latency 77406880 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses -system.cpu.dcache.overall_misses 14182 # number of overall misses -system.cpu.dcache.overall_mshr_hits 10002 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 21595687 # number of overall MSHR miss cycles +system.cpu.dcache.overall_hits 169874199 # number of overall hits +system.cpu.dcache.overall_miss_latency 138567174 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000125 # miss rate for overall accesses +system.cpu.dcache.overall_misses 21154 # number of overall misses +system.cpu.dcache.overall_mshr_hits 16972 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 27094480 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 4180 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 4182 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 784 # number of replacements -system.cpu.dcache.sampled_refs 4180 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 786 # number of replacements +system.cpu.dcache.sampled_refs 4182 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3190.140908 # Cycle average of tags in use -system.cpu.dcache.total_refs 167971839 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3211.654167 # Cycle average of tags in use +system.cpu.dcache.total_refs 169874199 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 637 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 19324711 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 4274 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 11555430 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 538406721 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 137426232 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 102617017 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 16124012 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 12594 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 984698 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 64275681 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 66044385 # Number of cache lines fetched -system.cpu.fetch.Cycles 172472243 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1233740 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 552850318 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 6527825 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.232481 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 66044385 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 50974451 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.999627 # Number of inst fetches per cycle +system.cpu.dcache.writebacks 639 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 32658535 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 4257 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 11810746 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 562730439 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 143183566 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 99541453 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 18560140 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 12611 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 947878 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 66376995 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 68531131 # Number of cache lines fetched +system.cpu.fetch.Cycles 171584130 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1722712 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 577337575 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 6483468 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.225089 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 68531131 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 50189886 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.957796 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 276476670 +system.cpu.fetch.rateDist.samples 294891572 system.cpu.fetch.rateDist.min_value 0 - 0 170048750 6150.56% - 1 11707777 423.46% - 2 11563595 418.25% - 3 7250668 262.25% - 4 16393688 592.95% - 5 9178756 331.99% - 6 6871715 248.55% - 7 4129243 149.35% - 8 39332478 1422.63% + 0 191838575 6505.39% + 1 8000057 271.29% + 2 8353997 283.29% + 3 6793291 230.37% + 4 15387795 521.81% + 5 8442060 286.28% + 6 8794810 298.24% + 7 2528585 85.75% + 8 44752402 1517.59% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 66044384 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4697.455355 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3736.572860 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 66039333 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 23726847 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000076 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 5051 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 1160 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 14539005 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000059 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 3891 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets 5023.260870 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 16972.329221 # Average number of references to valid blocks. +system.cpu.icache.ReadReq_accesses 68531131 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 4689.224645 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 3850.973049 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 68526132 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 23441434 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000073 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 4999 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 1103 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 15003391 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000057 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 3896 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 17588.842916 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 69 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 346605 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 66044384 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4697.455355 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3736.572860 # average overall mshr miss latency -system.cpu.icache.demand_hits 66039333 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 23726847 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000076 # miss rate for demand accesses -system.cpu.icache.demand_misses 5051 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 1160 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 14539005 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000059 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 3891 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 68531131 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 4689.224645 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 3850.973049 # average overall mshr miss latency +system.cpu.icache.demand_hits 68526132 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 23441434 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000073 # miss rate for demand accesses +system.cpu.icache.demand_misses 4999 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 1103 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 15003391 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000057 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 3896 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 66044384 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4697.455355 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3736.572860 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 66039333 # number of overall hits -system.cpu.icache.overall_miss_latency 23726847 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000076 # miss rate for overall accesses -system.cpu.icache.overall_misses 5051 # number of overall misses -system.cpu.icache.overall_mshr_hits 1160 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 14539005 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000059 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 3891 # number of overall MSHR misses +system.cpu.icache.overall_accesses 68531131 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 4689.224645 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 3850.973049 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 68526132 # number of overall hits +system.cpu.icache.overall_miss_latency 23441434 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000073 # miss rate for overall accesses +system.cpu.icache.overall_misses 4999 # number of overall misses +system.cpu.icache.overall_mshr_hits 1103 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 15003391 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000057 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 3896 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,162 +215,162 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 1971 # number of replacements -system.cpu.icache.sampled_refs 3891 # Sample count of references to valid blocks. +system.cpu.icache.replacements 1976 # number of replacements +system.cpu.icache.sampled_refs 3896 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1776.887115 # Cycle average of tags in use -system.cpu.icache.total_refs 66039333 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1786.777118 # Cycle average of tags in use +system.cpu.icache.total_refs 68526132 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 18326359 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 51280930 # Number of branches executed -system.cpu.iew.EXEC:nop 27455299 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.521589 # Inst execution rate -system.cpu.iew.EXEC:refs 191354897 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 79285920 # Number of stores executed +system.cpu.idleCycles 19733456 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 52475714 # Number of branches executed +system.cpu.iew.EXEC:nop 28200659 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.439607 # Inst execution rate +system.cpu.iew.EXEC:refs 190729803 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 78992420 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 293982680 # num instructions consuming a value -system.cpu.iew.WB:count 415403944 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.694108 # average fanout of values written-back +system.cpu.iew.WB:consumers 302582293 # num instructions consuming a value +system.cpu.iew.WB:count 419651187 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.683002 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 204055700 # num instructions producing a value -system.cpu.iew.WB:rate 1.502492 # insts written-back per cycle -system.cpu.iew.WB:sent 416259284 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 6316593 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 2856011 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 126084683 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 240 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 7411275 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 92646936 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 496689311 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 112068977 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 8996952 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 420683841 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 114816 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 206664160 # num instructions producing a value +system.cpu.iew.WB:rate 1.423069 # insts written-back per cycle +system.cpu.iew.WB:sent 420984328 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 6525670 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 4581779 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 131935591 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 243 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 8433935 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 95765344 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 517242480 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 111737383 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7591261 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 424527920 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 366722 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 1986 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 16124012 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 416926 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 183286 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 727659 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 9888553 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 47660 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.iewLSQFullEvents 32377 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 18560140 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 737234 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 8882 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 8984961 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 39727 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 81366 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 183286 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 25432695 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 19115536 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 81366 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 996952 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 5319641 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.273985 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.273985 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 429680793 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 675434 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 175954 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 31283603 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 22233944 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 675434 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1009222 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 5516448 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.193722 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.193722 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 432119181 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 33581 0.01% # Type of FU issued - IntAlu 167723328 39.03% # Type of FU issued - IntMult 2137299 0.50% # Type of FU issued + IntAlu 171100299 39.60% # Type of FU issued + IntMult 2148839 0.50% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 34928239 8.13% # Type of FU issued - FloatCmp 8071357 1.88% # Type of FU issued - FloatCvt 3141242 0.73% # Type of FU issued - FloatMult 16626981 3.87% # Type of FU issued - FloatDiv 1577676 0.37% # Type of FU issued + FloatAdd 35472672 8.21% # Type of FU issued + FloatCmp 7906658 1.83% # Type of FU issued + FloatCvt 2966336 0.69% # Type of FU issued + FloatMult 16725823 3.87% # Type of FU issued + FloatDiv 1566508 0.36% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 114426564 26.63% # Type of FU issued - MemWrite 81014526 18.85% # Type of FU issued + MemRead 113251606 26.21% # Type of FU issued + MemWrite 80946859 18.73% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 9055324 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.021075 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 9237965 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.021378 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 66610 0.74% # attempts to use FU when none available + IntAlu 31984 0.35% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 110487 1.22% # attempts to use FU when none available - FloatCmp 35273 0.39% # attempts to use FU when none available - FloatCvt 2828 0.03% # attempts to use FU when none available - FloatMult 2149754 23.74% # attempts to use FU when none available - FloatDiv 664669 7.34% # attempts to use FU when none available + FloatAdd 74124 0.80% # attempts to use FU when none available + FloatCmp 35886 0.39% # attempts to use FU when none available + FloatCvt 5384 0.06% # attempts to use FU when none available + FloatMult 1393766 15.09% # attempts to use FU when none available + FloatDiv 1142138 12.36% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 4545406 50.20% # attempts to use FU when none available - MemWrite 1480297 16.35% # attempts to use FU when none available + MemRead 5413419 58.60% # attempts to use FU when none available + MemWrite 1141264 12.35% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 276476670 +system.cpu.iq.ISSUE:issued_per_cycle.samples 294891572 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 105552217 3817.76% - 1 55104063 1993.08% - 2 43517427 1574.00% - 3 31483356 1138.73% - 4 21726208 785.82% - 5 11633875 420.79% - 6 4624667 167.27% - 7 2409257 87.14% - 8 425600 15.39% + 0 116554693 3952.46% + 1 58404803 1980.55% + 2 49059967 1663.66% + 3 31805455 1078.55% + 4 23494336 796.71% + 5 9548381 323.79% + 6 4038173 136.94% + 7 1656320 56.17% + 8 329444 11.17% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.554130 # Inst issue rate -system.cpu.iq.iqInstsAdded 469233772 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 429680793 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 240 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 93305351 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 1513608 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 25 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 71392848 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 8070 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4399.297838 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2193.473956 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 717 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 32348037 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.911152 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 7353 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 16128614 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.911152 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 7353 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 637 # number of WriteReqNoAck|Writeback accesses(hits+misses) -system.cpu.l2cache.WriteReqNoAck|Writeback_hits 637 # number of WriteReqNoAck|Writeback hits +system.cpu.iq.ISSUE:rate 1.465349 # Inst issue rate +system.cpu.iq.iqInstsAdded 489041578 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 432119181 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 243 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 113088119 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 1629891 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 97430194 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 8078 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4922.926872 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2406.841240 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 721 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 36217973 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.910745 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 7357 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 17707131 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.910745 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 7357 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 639 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 639 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.184143 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.184858 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 8070 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4399.297838 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2193.473956 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 717 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 32348037 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.911152 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 7353 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 8078 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4922.926872 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2406.841240 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 721 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 36217973 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.910745 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 7357 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 16128614 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.911152 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 7353 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 17707131 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.910745 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 7357 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 8707 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4399.297838 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2193.473956 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 8717 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4922.926872 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2406.841240 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1354 # number of overall hits -system.cpu.l2cache.overall_miss_latency 32348037 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.844493 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 7353 # number of overall misses +system.cpu.l2cache.overall_hits 1360 # number of overall hits +system.cpu.l2cache.overall_miss_latency 36217973 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.843983 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 7357 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 16128614 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.844493 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 7353 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 17707131 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.843983 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 7357 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -383,31 +383,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 7353 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 7357 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 6415.706550 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1354 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 6462.850486 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1360 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 276476670 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 8743693 # Number of cycles rename is blocking +system.cpu.numCycles 294891572 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 14686909 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 259532206 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 653030 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 142074266 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 8196045 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 109 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 687565953 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 524563034 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 338654872 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 98656303 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 16124012 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 9950983 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 79122666 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 927413 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 40317 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 23109451 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 249 # count of temporary serializing insts renamed -system.cpu.timesIdled 6216 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 2446116 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 148616326 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 11769281 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 32 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 721460314 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 549210935 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 355537016 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 94743971 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 18560140 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 15563294 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 96004810 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 2720932 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 38133 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 34543353 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 264 # count of temporary serializing insts renamed +system.cpu.timesIdled 6492 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr index d414f5cfe..4bb0d9bbe 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr @@ -1,10 +1,11 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7002 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera opening surfaces file chair.surfaces reading data +warn: Increasing stack size by one page. processing 8parts Grid measure is 6 by 3.0001 by 6 cell dimension is 0.863065 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini index cf4e15676..d565e945f 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -1,48 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -70,6 +29,7 @@ commitToFetchDelay=1 commitToIEWDelay=1 commitToRenameDelay=1 commitWidth=8 +cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 @@ -155,7 +115,7 @@ split=false split_size=0 store_compressed=false subblock_size=0 -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -331,7 +291,7 @@ split=false split_size=0 store_compressed=false subblock_size=0 -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -388,7 +348,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing egid=100 env= euid=100 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out index 52c225902..85be70a92 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -31,7 +28,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex input=cin output=cout env= -cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing system=system uid=100 euid=100 @@ -173,6 +170,7 @@ type=DerivO3CPU clock=1 phase=0 numThreads=1 +cpu_id=0 activity=0 workload=system.cpu.workload checker=null @@ -253,7 +251,7 @@ assoc=2 block_size=64 latency=1 mshrs=10 -tgts_per_mshr=5 +tgts_per_mshr=20 write_buffers=8 prioritizeRequests=false protocol=null @@ -291,7 +289,7 @@ assoc=2 block_size=64 latency=1 mshrs=10 -tgts_per_mshr=5 +tgts_per_mshr=20 write_buffers=8 prioritizeRequests=false protocol=null @@ -367,39 +365,3 @@ clock=1000 width=64 responder_set=false -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt index 3069385f0..00598f40d 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 13202034 # Number of BTB hits -global.BPredUnit.BTBLookups 22107115 # Number of BTB lookups -global.BPredUnit.RASInCorrect 30370 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 454360 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 16498204 # Number of conditional branches predicted -global.BPredUnit.lookups 27047110 # Number of BP lookups -global.BPredUnit.usedRAS 4878193 # Number of times the RAS was used to get a target. -host_inst_rate 69520 # Simulator instruction rate (inst/s) -host_mem_usage 239908 # Number of bytes of host memory used -host_seconds 1144.87 # Real time elapsed on the host -host_tick_rate 987535 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 14725847 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 11490673 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 28863760 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 16312214 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 7945230 # Number of BTB hits +global.BPredUnit.BTBLookups 13714223 # Number of BTB lookups +global.BPredUnit.RASInCorrect 29001 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 454297 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 10141226 # Number of conditional branches predicted +global.BPredUnit.lookups 15617287 # Number of BP lookups +global.BPredUnit.usedRAS 1851141 # Number of times the RAS was used to get a target. +host_inst_rate 91600 # Simulator instruction rate (inst/s) +host_mem_usage 155864 # Number of bytes of host memory used +host_seconds 868.91 # Real time elapsed on the host +host_tick_rate 1051887 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 16262618 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 12842437 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 22199501 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 16236124 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 79591756 # Number of instructions simulated -sim_seconds 0.001131 # Number of seconds simulated -sim_ticks 1130602014 # Number of ticks simulated +sim_seconds 0.000914 # Number of seconds simulated +sim_ticks 913992014 # Number of ticks simulated system.cpu.commit.COM:branches 13754477 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3893678 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 3798224 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 89505192 +system.cpu.commit.COM:committed_per_cycle.samples 61093189 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 62882698 7025.59% - 1 8753972 978.04% - 2 5175203 578.20% - 3 3243621 362.39% - 4 2169519 242.39% - 5 1432847 160.09% - 6 1161882 129.81% - 7 791772 88.46% - 8 3893678 435.02% + 0 33945527 5556.35% + 1 9263496 1516.29% + 2 5234944 856.88% + 3 3369457 551.53% + 4 2068681 338.61% + 5 1423240 232.96% + 6 1205139 197.26% + 7 784481 128.41% + 8 3798224 621.71% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 20379399 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 35224018 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 359967 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 359791 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 21665941 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8215609 # The number of squashed insts skipped by commit system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 14.205014 # CPI: Cycles Per Instruction -system.cpu.cpi_total 14.205014 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 19540231 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 4453.766964 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3237.815878 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 19382637 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 701886951 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.008065 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 157594 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 95950 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 199591922 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.003155 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 61644 # number of ReadReq MSHR misses +system.cpu.cpi 11.483501 # CPI: Cycles Per Instruction +system.cpu.cpi_total 11.483501 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 19669616 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 4470.389268 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3240.793422 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 19511676 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 706053281 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.008030 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 157940 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 96341 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 199629634 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.003132 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 61599 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 4830.124895 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3999.409028 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 13942631 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3239786953 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.045899 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 670746 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 527274 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 573803212 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 9707.501078 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 9477.511675 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 13569879 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 10129757960 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.071407 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1043498 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 900030 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 1359719645 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.009818 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 143472 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 3332.672727 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 3759.399862 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 162.470348 # Average number of references to valid blocks. +system.cpu.dcache.WriteReq_mshr_misses 143468 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 3321.963636 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 3975 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 161.320715 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 110 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 125901 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 366594 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 473312202 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 1 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 365416 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 3975 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 34153608 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 4758.521747 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3770.525625 # average overall mshr miss latency -system.cpu.dcache.demand_hits 33325268 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 3941673904 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.024253 # miss rate for demand accesses -system.cpu.dcache.demand_misses 828340 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 623224 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 773395134 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.006006 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 205116 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 34282993 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 9019.034891 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 7604.096607 # average overall mshr miss latency +system.cpu.dcache.demand_hits 33081555 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 10835811241 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.035045 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1201438 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 996371 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 1559349279 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.005982 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 205067 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 34153608 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 4758.521747 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3770.525625 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 34282993 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 9019.034891 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 7604.096607 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 33325268 # number of overall hits -system.cpu.dcache.overall_miss_latency 3941673904 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.024253 # miss rate for overall accesses -system.cpu.dcache.overall_misses 828340 # number of overall misses -system.cpu.dcache.overall_mshr_hits 623224 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 773395134 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.006006 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 205116 # number of overall MSHR misses +system.cpu.dcache.overall_hits 33081555 # number of overall hits +system.cpu.dcache.overall_miss_latency 10835811241 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.035045 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1201438 # number of overall misses +system.cpu.dcache.overall_mshr_hits 996371 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 1559349279 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.005982 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 205067 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 201020 # number of replacements -system.cpu.dcache.sampled_refs 205116 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 200971 # number of replacements +system.cpu.dcache.sampled_refs 205067 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4057.039034 # Cycle average of tags in use -system.cpu.dcache.total_refs 33325268 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 27784000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 147771 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 11948269 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 95198 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3558048 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 131593428 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 51674084 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 25481309 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 4702945 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 281359 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 401531 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 27047110 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 22733117 # Number of cache lines fetched -system.cpu.fetch.Cycles 51481541 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 159026 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 148267180 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 3966980 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.287100 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 22733117 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 18080227 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.573826 # Number of inst fetches per cycle +system.cpu.dcache.tagsinuse 4063.517542 # Cycle average of tags in use +system.cpu.dcache.total_refs 33081555 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 17025000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 147753 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 13116101 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 95141 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3521692 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 99189601 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 29616630 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 18020228 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1276894 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 291919 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 340231 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 15617287 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 13002150 # Number of cache lines fetched +system.cpu.fetch.Cycles 31529148 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 124397 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 100725428 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 547316 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.250397 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 13002150 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 9796371 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.614964 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 94208138 +system.cpu.fetch.rateDist.samples 62370084 system.cpu.fetch.rateDist.min_value 0 - 0 65459635 6948.41% - 1 1687117 179.08% - 2 1748812 185.63% - 3 1938924 205.81% - 4 6981531 741.08% - 5 6100701 647.58% - 6 758078 80.47% - 7 1979150 210.08% - 8 7554190 801.86% + 0 43843090 7029.51% + 1 1383259 221.78% + 2 1262238 202.38% + 3 1426265 228.68% + 4 3918105 628.20% + 5 1724208 276.45% + 6 613107 98.30% + 7 1031700 165.42% + 8 7168112 1149.29% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 22733116 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3345.551905 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2359.548288 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 22631700 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 339292492 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.004461 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 101416 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 13878 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 206550138 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.003851 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 87538 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 13002150 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3387.778909 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2412.580892 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 12899943 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 346254719 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.007861 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 102207 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 14535 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 211515792 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.006743 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 87672 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets 3731.567010 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 258.538675 # Average number of references to valid blocks. +system.cpu.icache.avg_blocked_cycles_no_targets 5804 # average number of cycles each access was blocked +system.cpu.icache.avg_refs 147.140366 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 97 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 1 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 361962 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 5804 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 22733116 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3345.551905 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2359.548288 # average overall mshr miss latency -system.cpu.icache.demand_hits 22631700 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 339292492 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.004461 # miss rate for demand accesses -system.cpu.icache.demand_misses 101416 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 13878 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 206550138 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.003851 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 87538 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 13002150 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3387.778909 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2412.580892 # average overall mshr miss latency +system.cpu.icache.demand_hits 12899943 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 346254719 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.007861 # miss rate for demand accesses +system.cpu.icache.demand_misses 102207 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 14535 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 211515792 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.006743 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 87672 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 22733116 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3345.551905 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2359.548288 # average overall mshr miss latency +system.cpu.icache.overall_accesses 13002150 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3387.778909 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2412.580892 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 22631700 # number of overall hits -system.cpu.icache.overall_miss_latency 339292492 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.004461 # miss rate for overall accesses -system.cpu.icache.overall_misses 101416 # number of overall misses -system.cpu.icache.overall_mshr_hits 13878 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 206550138 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.003851 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 87538 # number of overall MSHR misses +system.cpu.icache.overall_hits 12899943 # number of overall hits +system.cpu.icache.overall_miss_latency 346254719 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.007861 # miss rate for overall accesses +system.cpu.icache.overall_misses 102207 # number of overall misses +system.cpu.icache.overall_mshr_hits 14535 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 211515792 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.006743 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 87672 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,80 +215,80 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 85490 # number of replacements -system.cpu.icache.sampled_refs 87537 # Sample count of references to valid blocks. +system.cpu.icache.replacements 85624 # number of replacements +system.cpu.icache.sampled_refs 87671 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1835.330854 # Cycle average of tags in use -system.cpu.icache.total_refs 22631700 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1862.743229 # Cycle average of tags in use +system.cpu.icache.total_refs 12899943 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1036393877 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 14379719 # Number of branches executed -system.cpu.iew.EXEC:nop 9265977 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.989418 # Inst execution rate -system.cpu.iew.EXEC:refs 43156162 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 15338261 # Number of stores executed +system.cpu.idleCycles 851621931 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 14377755 # Number of branches executed +system.cpu.iew.EXEC:nop 9220461 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.335296 # Inst execution rate +system.cpu.iew.EXEC:refs 36382036 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 15204952 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 46157981 # num instructions consuming a value -system.cpu.iew.WB:count 86105601 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.741496 # average fanout of values written-back +system.cpu.iew.WB:consumers 46748099 # num instructions consuming a value +system.cpu.iew.WB:count 82847738 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.736514 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 34225955 # num instructions producing a value -system.cpu.iew.WB:rate 0.913993 # insts written-back per cycle -system.cpu.iew.WB:sent 86171133 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 389534 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 3213991 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 28863760 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 4784 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1402526 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 16312214 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 110003367 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 27817901 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 453087 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 93211232 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 28742 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 34430613 # num instructions producing a value +system.cpu.iew.WB:rate 1.328325 # insts written-back per cycle +system.cpu.iew.WB:sent 82914162 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 396555 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 4917376 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 22199501 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 4762 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 311974 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 16236124 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 96553237 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 21177084 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 433562 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 83282498 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 37202 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 12962 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 4702945 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 194395 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 1528 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 6922047 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 1365052 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5008 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.iewLSQFullEvents 11594 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1276894 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 204710 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 98563 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 1300046 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 1230 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 3825 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1528 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 8484361 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1467595 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 3825 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 102872 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 286662 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.070398 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.070398 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 93664319 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 27684 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1255 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1820102 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1391505 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 27684 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 103251 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 293304 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.087081 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.087081 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 83716060 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 0 0.00% # Type of FU issued - IntAlu 49995908 53.38% # Type of FU issued - IntMult 43196 0.05% # Type of FU issued + IntAlu 46816661 55.92% # Type of FU issued + IntMult 44502 0.05% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 123595 0.13% # Type of FU issued + FloatAdd 125345 0.15% # Type of FU issued FloatCmp 86 0.00% # Type of FU issued - FloatCvt 122386 0.13% # Type of FU issued + FloatCvt 122997 0.15% # Type of FU issued FloatMult 51 0.00% # Type of FU issued - FloatDiv 37853 0.04% # Type of FU issued + FloatDiv 37854 0.05% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 27919833 29.81% # Type of FU issued - MemWrite 15421411 16.46% # Type of FU issued + MemRead 21285503 25.43% # Type of FU issued + MemWrite 15283061 18.26% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 1229792 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.013130 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 1123822 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.013424 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 83895 6.82% # attempts to use FU when none available + IntAlu 98385 8.75% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -297,84 +297,84 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 589327 47.92% # attempts to use FU when none available - MemWrite 556570 45.26% # attempts to use FU when none available + MemRead 476117 42.37% # attempts to use FU when none available + MemWrite 549320 48.88% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 94208138 +system.cpu.iq.ISSUE:issued_per_cycle.samples 62370084 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 54322746 5766.25% - 1 13333515 1415.33% - 2 10626230 1127.95% - 3 8813553 935.54% - 4 4440243 471.32% - 5 1597603 169.58% - 6 685526 72.77% - 7 334234 35.48% - 8 54488 5.78% + 0 25315225 4058.87% + 1 13800975 2212.76% + 2 10743054 1722.47% + 3 5596398 897.29% + 4 4388925 703.69% + 5 1495414 239.76% + 6 664039 106.47% + 7 305653 49.01% + 8 60401 9.68% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.994227 # Inst issue rate -system.cpu.iq.iqInstsAdded 100732606 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 93664319 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 4784 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 20911338 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 73995 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 201 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 16334966 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 292646 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3929.598028 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2043.469607 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 122985 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 666699531 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.579748 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 169661 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 346697097 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.579748 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 169661 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 147771 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 147307 # number of Writeback hits -system.cpu.l2cache.Writeback_miss_rate 0.003140 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 464 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 0.003140 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 464 # number of Writeback MSHR misses +system.cpu.iq.ISSUE:rate 1.342247 # Inst issue rate +system.cpu.iq.iqInstsAdded 87328014 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 83716060 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 4762 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 7507881 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 113500 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 179 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 6033024 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 292729 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 7766.621627 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2997.837795 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 123055 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1317793758 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.579628 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 169674 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 508655130 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.579628 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 169674 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 147753 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 147285 # number of Writeback hits +system.cpu.l2cache.Writeback_miss_rate 0.003167 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 468 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 0.003167 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 468 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.593139 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.593300 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 292646 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3929.598028 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2043.469607 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 122985 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 666699531 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.579748 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 169661 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 292729 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 7766.621627 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2997.837795 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 123055 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1317793758 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.579628 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 169674 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 346697097 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.579748 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 169661 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 508655130 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.579628 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 169674 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 440417 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3918.880417 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2043.469607 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 440482 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 7745.258419 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2997.837795 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 270292 # number of overall hits -system.cpu.l2cache.overall_miss_latency 666699531 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.386282 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 170125 # number of overall misses +system.cpu.l2cache.overall_hits 270340 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1317793758 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.386263 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 170142 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 346697097 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.385228 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 169661 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 508655130 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.385201 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 169674 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -386,32 +386,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 136892 # number of replacements -system.cpu.l2cache.sampled_refs 169660 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 136905 # number of replacements +system.cpu.l2cache.sampled_refs 169673 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 30349.297230 # Cycle average of tags in use -system.cpu.l2cache.total_refs 270292 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 625483000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 115938 # number of writebacks -system.cpu.numCycles 94208138 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 7563765 # Number of cycles rename is blocking +system.cpu.l2cache.tagsinuse 30821.723437 # Cycle average of tags in use +system.cpu.l2cache.total_refs 270340 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 468003000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 115935 # number of writebacks +system.cpu.numCycles 62370084 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 8787185 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 87866 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 52361095 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 3315491 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 3509 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 154857350 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 130101763 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 82913656 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 25182526 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 4702945 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 3542613 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 30366775 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 855194 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 4773 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 6398047 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 4771 # count of temporary serializing insts renamed -system.cpu.timesIdled 275758 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 113083 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 30263464 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 3026568 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 587 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 118807787 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 98380136 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 59048113 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 17777635 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1276894 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 3354217 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 6501232 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 910689 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 4741 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 5955323 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 4739 # count of temporary serializing insts renamed +system.cpu.timesIdled 280733 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr index eb1796ead..f33d007a7 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 9ae62655d..567f53165 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -1,48 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -70,6 +29,7 @@ commitToFetchDelay=1 commitToIEWDelay=1 commitToRenameDelay=1 commitWidth=8 +cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 @@ -155,7 +115,7 @@ split=false split_size=0 store_compressed=false subblock_size=0 -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -331,7 +291,7 @@ split=false split_size=0 store_compressed=false subblock_size=0 -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -388,7 +348,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing egid=100 env= euid=100 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out index 690cc5723..bf1cbf0ac 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -31,7 +28,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 input=cin output=cout env= -cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing system=system uid=100 euid=100 @@ -173,6 +170,7 @@ type=DerivO3CPU clock=1 phase=0 numThreads=1 +cpu_id=0 activity=0 workload=system.cpu.workload checker=null @@ -253,7 +251,7 @@ assoc=2 block_size=64 latency=1 mshrs=10 -tgts_per_mshr=5 +tgts_per_mshr=20 write_buffers=8 prioritizeRequests=false protocol=null @@ -291,7 +289,7 @@ assoc=2 block_size=64 latency=1 mshrs=10 -tgts_per_mshr=5 +tgts_per_mshr=20 write_buffers=8 prioritizeRequests=false protocol=null @@ -367,39 +365,3 @@ clock=1000 width=64 responder_set=false -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt index bc6866525..3521e50a1 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 1060300638 # Number of BTB hits -global.BPredUnit.BTBLookups 1075264664 # Number of BTB lookups +global.BPredUnit.BTBHits 929108954 # Number of BTB hits +global.BPredUnit.BTBLookups 938262248 # Number of BTB lookups global.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 20658855 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1028649695 # Number of conditional branches predicted -global.BPredUnit.lookups 1098978166 # Number of BP lookups -global.BPredUnit.usedRAS 20738311 # Number of times the RAS was used to get a target. -host_inst_rate 28281 # Simulator instruction rate (inst/s) -host_mem_usage 1256892 # Number of bytes of host memory used -host_seconds 61385.49 # Real time elapsed on the host -host_tick_rate 405833 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 114920109 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 60881817 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 938731548 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 389309694 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.condIncorrect 21205625 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 887467305 # Number of conditional branches predicted +global.BPredUnit.lookups 962390884 # Number of BP lookups +global.BPredUnit.usedRAS 21400461 # Number of times the RAS was used to get a target. +host_inst_rate 41899 # Simulator instruction rate (inst/s) +host_mem_usage 150980 # Number of bytes of host memory used +host_seconds 41434.26 # Real time elapsed on the host +host_tick_rate 599461 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 138710917 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 68670490 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 815007661 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 388931456 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1736043781 # Number of instructions simulated -sim_seconds 0.024912 # Number of seconds simulated -sim_ticks 24912272090 # Number of ticks simulated +sim_seconds 0.024838 # Number of seconds simulated +sim_ticks 24838210102 # Number of ticks simulated system.cpu.commit.COM:branches 214632552 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 72343657 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 66487461 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 5678957793 +system.cpu.commit.COM:committed_per_cycle.samples 7112101736 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 5103057521 8985.90% - 1 193842571 341.33% - 2 126727829 223.15% - 3 63255233 111.39% - 4 47590442 83.80% - 5 34302037 60.40% - 6 22774532 40.10% - 7 15063971 26.53% - 8 72343657 127.39% + 0 6522703166 9171.27% + 1 208562151 293.25% + 2 123042509 173.00% + 3 62023833 87.21% + 4 51435586 72.32% + 5 40600313 57.09% + 6 22309158 31.37% + 7 14937559 21.00% + 8 66487461 93.48% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 445666361 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 606571343 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 20658355 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 21205131 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 3012390712 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2701603860 # The number of squashed insts skipped by commit system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 14.350025 # CPI: Cycles Per Instruction -system.cpu.cpi_total 14.350025 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 466176479 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 5764.172372 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5678.042412 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 454097633 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 69624550394 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.025910 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 12078846 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 4784670 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 41416640690 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.015647 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 7294176 # number of ReadReq MSHR misses +system.cpu.cpi 14.307364 # CPI: Cycles Per Instruction +system.cpu.cpi_total 14.307364 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 489384352 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5253.286413 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5452.839977 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 474368420 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 78882991559 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.030683 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 15015932 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 7713263 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 39820285465 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.014922 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 7302669 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 11148.179412 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 14223.476157 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 157574910 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 35156809407 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.019621 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 3153592 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1270515 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 26783900812 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.011716 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1883077 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 972.020892 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 2881.979981 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 66.650940 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 659829 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 896062 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 641367573 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 2582432746 # number of cycles access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 8690.039906 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 14121.575874 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 155407108 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 46243126214 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.033108 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 5321394 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 3438755 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 26585829481 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.011713 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1882639 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 985.727671 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 3841.099983 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 68.563354 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 637482 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 65141 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 628383647 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 250213094 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 626904981 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 6878.830546 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 7431.476663 # average overall mshr miss latency -system.cpu.dcache.demand_hits 611672543 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 104781359801 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.024298 # miss rate for demand accesses -system.cpu.dcache.demand_misses 15232438 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 6055185 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 68200541502 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.014639 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 9177253 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 650112854 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 6152.535381 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 7229.601331 # average overall mshr miss latency +system.cpu.dcache.demand_hits 629775528 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 125126117773 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.031283 # miss rate for demand accesses +system.cpu.dcache.demand_misses 20337326 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 11152018 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 66406114946 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.014129 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 9185308 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 626904981 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 6878.830546 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 7431.476663 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 650112854 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 6152.535381 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 7229.601331 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 611672543 # number of overall hits -system.cpu.dcache.overall_miss_latency 104781359801 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.024298 # miss rate for overall accesses -system.cpu.dcache.overall_misses 15232438 # number of overall misses -system.cpu.dcache.overall_mshr_hits 6055185 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 68200541502 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.014639 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 9177253 # number of overall MSHR misses +system.cpu.dcache.overall_hits 629775528 # number of overall hits +system.cpu.dcache.overall_miss_latency 125126117773 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.031283 # miss rate for overall accesses +system.cpu.dcache.overall_misses 20337326 # number of overall misses +system.cpu.dcache.overall_mshr_hits 11152018 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 66406114946 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.014129 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 9185308 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,91 +118,91 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 9173157 # number of replacements -system.cpu.dcache.sampled_refs 9177253 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 9181212 # number of replacements +system.cpu.dcache.sampled_refs 9185308 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4093.061614 # Cycle average of tags in use -system.cpu.dcache.total_refs 611672543 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 39716000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 2244715 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 3168036062 # Number of cycles decode is blocked +system.cpu.dcache.tagsinuse 4093.052798 # Cycle average of tags in use +system.cpu.dcache.total_refs 629775528 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 39780000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 2244995 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 5295615421 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 511 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 48557069 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 6641345328 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 1298412925 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 1202046298 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 501929792 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 1629 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 10462509 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 1098978166 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 541280485 # Number of cache lines fetched -system.cpu.fetch.Cycles 1955627258 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 11328270 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 7938391391 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 242391708 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.177803 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 541280485 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1081038949 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.284345 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BranchResolved 51642597 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 5750899999 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 834310560 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 972356636 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 417727902 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 1635 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 9819120 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 962390884 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 341574441 # Number of cache lines fetched +system.cpu.fetch.Cycles 1454523625 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 5354005 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 6616091478 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 145044249 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.127810 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 341574441 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 950509415 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.878651 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 6180887586 +system.cpu.fetch.rateDist.samples 7529829639 system.cpu.fetch.rateDist.min_value 0 - 0 4766540797 7711.74% - 1 80764415 130.67% - 2 63598055 102.89% - 3 58203597 94.17% - 4 424384465 686.61% - 5 69131012 111.85% - 6 94422767 152.77% - 7 44649271 72.24% - 8 579193207 937.07% + 0 6416880458 8521.95% + 1 35027129 46.52% + 2 21417088 28.44% + 3 34363919 45.64% + 4 372287950 494.42% + 5 53476407 71.02% + 6 32781145 43.54% + 7 26846633 35.65% + 8 536748910 712.83% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 541280484 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 5378.819380 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 4616.750831 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 541279194 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 6938677 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1290 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 387 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 4168926 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_accesses 341574441 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5436.849282 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4708.305648 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 341573187 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 6817809 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 1254 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 351 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 4251600 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 903 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets 4207.523810 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 599423.249169 # Average number of references to valid blocks. +system.cpu.icache.avg_blocked_cycles_no_targets 4779 # average number of cycles each access was blocked +system.cpu.icache.avg_refs 378264.880399 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 21 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 1 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 88358 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 4779 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 541280484 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 5378.819380 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 4616.750831 # average overall mshr miss latency -system.cpu.icache.demand_hits 541279194 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 6938677 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses -system.cpu.icache.demand_misses 1290 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 387 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 4168926 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.demand_accesses 341574441 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5436.849282 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4708.305648 # average overall mshr miss latency +system.cpu.icache.demand_hits 341573187 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 6817809 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses +system.cpu.icache.demand_misses 1254 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 351 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 4251600 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 903 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 541280484 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 5378.819380 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 4616.750831 # average overall mshr miss latency +system.cpu.icache.overall_accesses 341574441 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5436.849282 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4708.305648 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 541279194 # number of overall hits -system.cpu.icache.overall_miss_latency 6938677 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses -system.cpu.icache.overall_misses 1290 # number of overall misses -system.cpu.icache.overall_mshr_hits 387 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 4168926 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses +system.cpu.icache.overall_hits 341573187 # number of overall hits +system.cpu.icache.overall_miss_latency 6817809 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses +system.cpu.icache.overall_misses 1254 # number of overall misses +system.cpu.icache.overall_mshr_hits 351 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 4251600 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 903 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -218,77 +218,77 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 1 # number of replacements system.cpu.icache.sampled_refs 903 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 716.132429 # Cycle average of tags in use -system.cpu.icache.total_refs 541279194 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 719.119159 # Cycle average of tags in use +system.cpu.icache.total_refs 341573187 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 18731384505 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 250098653 # Number of branches executed -system.cpu.iew.EXEC:nop 147895912 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.440971 # Inst execution rate -system.cpu.iew.EXEC:refs 918923683 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 177016651 # Number of stores executed +system.cpu.idleCycles 17308380464 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 264199071 # Number of branches executed +system.cpu.iew.EXEC:nop 130726584 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.347587 # Inst execution rate +system.cpu.iew.EXEC:refs 833351854 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 181613826 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1839076786 # num instructions consuming a value -system.cpu.iew.WB:count 2471794731 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.797100 # average fanout of values written-back +system.cpu.iew.WB:consumers 1860973502 # num instructions consuming a value +system.cpu.iew.WB:count 2467010272 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.791148 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1465928228 # num instructions producing a value -system.cpu.iew.WB:rate 0.399909 # insts written-back per cycle -system.cpu.iew.WB:sent 2475054397 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 21956654 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 2471410228 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 938731548 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 111073783 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 389309694 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 4831881465 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 741907032 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 286170200 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 2725595031 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 1536928 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1472305742 # num instructions producing a value +system.cpu.iew.WB:rate 0.327632 # insts written-back per cycle +system.cpu.iew.WB:sent 2471732034 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 22834368 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 4630364405 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 815007661 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 46 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 31860417 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 388931456 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 4520549939 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 651738028 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 279876672 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 2617267318 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 2938028 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 161620 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 501929792 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 6153373 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 8 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 233590575 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 41593346 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 516978 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.iewLSQFullEvents 161905 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 417727902 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 6385903 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 122063096 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 39544757 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 151090 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 47985 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 8 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 493065187 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 228404712 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 47985 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 726441 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 21230213 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.069686 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.069686 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 3011765231 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 4644371 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 12 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 369341300 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 228026474 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 4644371 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 832035 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 22002333 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.069894 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.069894 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 2897143990 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 0 0.00% # Type of FU issued - IntAlu 1970711875 65.43% # Type of FU issued - IntMult 679 0.00% # Type of FU issued + IntAlu 1942173026 67.04% # Type of FU issued + IntMult 100 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 206 0.00% # Type of FU issued + FloatAdd 210 0.00% # Type of FU issued FloatCmp 15 0.00% # Type of FU issued - FloatCvt 146 0.00% # Type of FU issued - FloatMult 12 0.00% # Type of FU issued + FloatCvt 140 0.00% # Type of FU issued + FloatMult 13 0.00% # Type of FU issued FloatDiv 24 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 862446019 28.64% # Type of FU issued - MemWrite 178606255 5.93% # Type of FU issued + MemRead 770673405 26.60% # Type of FU issued + MemWrite 184297057 6.36% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 11307551 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.003754 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 12298143 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.004245 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 509990 4.51% # attempts to use FU when none available + IntAlu 765509 6.22% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -297,84 +297,84 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 9173598 81.13% # attempts to use FU when none available - MemWrite 1623963 14.36% # attempts to use FU when none available + MemRead 9714303 78.99% # attempts to use FU when none available + MemWrite 1818331 14.79% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 6180887586 +system.cpu.iq.ISSUE:issued_per_cycle.samples 7529829639 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 4878979324 7893.65% - 1 360055339 582.53% - 2 481197713 778.53% - 3 280796976 454.30% - 4 94854448 153.46% - 5 50760526 82.12% - 6 26723872 43.24% - 7 6795220 10.99% - 8 724168 1.17% + 0 6294390011 8359.27% + 1 325228389 431.92% + 2 480486573 638.11% + 3 243738023 323.70% + 4 97825007 129.92% + 5 51561666 68.48% + 6 27659179 36.73% + 7 6861374 9.11% + 8 2079417 2.76% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.487271 # Inst issue rate -system.cpu.iq.iqInstsAdded 4683985508 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 3011765231 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 2916477755 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 6096386 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 3050829124 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 9178154 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 7336.712513 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2076.036854 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 7008989 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 15914539999 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.236340 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 2169165 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 4503266483 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.236340 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 2169165 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 2244715 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 2215400 # number of Writeback hits -system.cpu.l2cache.Writeback_miss_rate 0.013060 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 29315 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 0.013060 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 29315 # number of Writeback MSHR misses +system.cpu.iq.ISSUE:rate 0.384756 # Inst issue rate +system.cpu.iq.iqInstsAdded 4389823309 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 2897143990 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 2623608231 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 10330579 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2673985156 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 9186210 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 7225.224344 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2102.004971 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 7015727 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 15682226609 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.236276 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 2170483 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 4562366056 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.236276 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 2170483 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 2244995 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2215762 # number of Writeback hits +system.cpu.l2cache.Writeback_miss_rate 0.013021 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 29233 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 0.013021 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 29233 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.252507 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 4.253196 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 9178154 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 7336.712513 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2076.036854 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 7008989 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 15914539999 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.236340 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 2169165 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 9186210 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 7225.224344 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2102.004971 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 7015727 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 15682226609 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.236276 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 2170483 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4503266483 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.236340 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 2169165 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 4562366056 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.236276 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 2170483 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 11422869 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 7238.883228 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2076.036854 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 11431205 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 7129.205138 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2102.004971 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 9224389 # number of overall hits -system.cpu.l2cache.overall_miss_latency 15914539999 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.192463 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 2198480 # number of overall misses +system.cpu.l2cache.overall_hits 9231489 # number of overall hits +system.cpu.l2cache.overall_miss_latency 15682226609 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.192431 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 2199716 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4503266483 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.189897 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 2169165 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 4562366056 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.189874 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 2170483 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -386,32 +386,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 2136397 # number of replacements -system.cpu.l2cache.sampled_refs 2169165 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 2137715 # number of replacements +system.cpu.l2cache.sampled_refs 2170483 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 32623.472165 # Cycle average of tags in use -system.cpu.l2cache.total_refs 9224389 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 520424000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 1039341 # number of writebacks -system.cpu.numCycles 6180887586 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 2894504060 # Number of cycles rename is blocking +system.cpu.l2cache.tagsinuse 32622.966749 # Cycle average of tags in use +system.cpu.l2cache.total_refs 9231489 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 513093000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 1039675 # number of writebacks +system.cpu.numCycles 7529829639 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 5035061268 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 6511750 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 1451413065 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 266047107 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 3125053 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 8501370508 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 6112671585 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 4584914520 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1056218413 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 501929792 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 276756270 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 3208711557 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 65986 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 49 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 1117979447 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 47 # count of temporary serializing insts renamed -system.cpu.timesIdled 7293390 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 12523289 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 970889170 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 234469237 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 2022618 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 7453165021 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 5328451425 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 4004220538 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 843247999 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 417727902 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 262813407 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 2628017575 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 89893 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 51 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 1009480859 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 49 # count of temporary serializing insts renamed +system.cpu.timesIdled 6494671 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 29 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr index cdd59eda7..d0a887867 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr @@ -1,2 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7006 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. +warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 5604f880f..9795f2e42 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -1,11 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 +dummy=0 [system] type=System @@ -33,6 +29,7 @@ commitToFetchDelay=1 commitToIEWDelay=1 commitToRenameDelay=1 commitWidth=8 +cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 @@ -118,7 +115,7 @@ split=false split_size=0 store_compressed=false subblock_size=0 -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -294,7 +291,7 @@ split=false split_size=0 store_compressed=false subblock_size=0 -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -351,11 +348,11 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing egid=100 env= euid=100 -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/twolf +executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin output=cout diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out index a78c52d7f..504c6e888 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -27,11 +24,11 @@ responder_set=false [system.cpu.workload] type=LiveProcess cmd=twolf smred -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/twolf +executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf input=cin output=cout env= -cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing system=system uid=100 euid=100 @@ -173,6 +170,7 @@ type=DerivO3CPU clock=1 phase=0 numThreads=1 +cpu_id=0 activity=0 workload=system.cpu.workload checker=null @@ -253,7 +251,7 @@ assoc=2 block_size=64 latency=1 mshrs=10 -tgts_per_mshr=5 +tgts_per_mshr=20 write_buffers=8 prioritizeRequests=false protocol=null @@ -291,7 +289,7 @@ assoc=2 block_size=64 latency=1 mshrs=10 -tgts_per_mshr=5 +tgts_per_mshr=20 write_buffers=8 prioritizeRequests=false protocol=null diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt index c77face31..dba9e1470 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 11848811 # Number of BTB hits -global.BPredUnit.BTBLookups 15227898 # Number of BTB lookups -global.BPredUnit.RASInCorrect 1227 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 2015952 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 12943595 # Number of conditional branches predicted -global.BPredUnit.lookups 17560137 # Number of BP lookups -global.BPredUnit.usedRAS 1685355 # Number of times the RAS was used to get a target. -host_inst_rate 110871 # Simulator instruction rate (inst/s) -host_mem_usage 184176 # Number of bytes of host memory used -host_seconds 759.26 # Real time elapsed on the host -host_tick_rate 138735 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 9867030 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 3328836 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 29553768 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 9396457 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 13130842 # Number of BTB hits +global.BPredUnit.BTBLookups 17054746 # Number of BTB lookups +global.BPredUnit.RASInCorrect 1205 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1949700 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 14620230 # Number of conditional branches predicted +global.BPredUnit.lookups 19607486 # Number of BP lookups +global.BPredUnit.usedRAS 1766776 # Number of times the RAS was used to get a target. +host_inst_rate 70212 # Simulator instruction rate (inst/s) +host_mem_usage 153248 # Number of bytes of host memory used +host_seconds 1198.94 # Real time elapsed on the host +host_tick_rate 95357 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 19046664 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 5327434 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 34568849 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 10915344 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 84179709 # Number of instructions simulated -sim_seconds 0.000105 # Number of seconds simulated -sim_ticks 105335101 # Number of ticks simulated +sim_seconds 0.000114 # Number of seconds simulated +sim_ticks 114327081 # Number of ticks simulated system.cpu.commit.COM:branches 10240685 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3300349 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 2895131 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 65617496 +system.cpu.commit.COM:committed_per_cycle.samples 73926385 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 32041205 4883.03% - 1 13628356 2076.94% - 2 7878182 1200.62% - 3 3859920 588.25% - 4 2040157 310.92% - 5 1456623 221.99% - 6 796888 121.44% - 7 615816 93.85% - 8 3300349 502.97% + 0 37511035 5074.11% + 1 16507127 2232.91% + 2 8529257 1153.75% + 3 3749717 507.22% + 4 1879220 254.20% + 5 1361115 184.12% + 6 851721 115.21% + 7 642062 86.85% + 8 2895131 391.62% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 20034413 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 26537108 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 2003468 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 1937238 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 39205061 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 58539227 # The number of squashed insts skipped by commit system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 1.251312 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.251312 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 23022109 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 5495.207331 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4910.485944 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 23021236 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4797316 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000038 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 873 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 375 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2445422 # number of ReadReq MSHR miss cycles +system.cpu.cpi 1.358131 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.358131 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 23376895 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5393.890593 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4863.252964 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 23375917 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 5275225 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000042 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 978 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 472 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2460806 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 506 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 4880.722363 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4578.932720 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6495178 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 28918280 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000911 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 5925 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 4186 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 7962764 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 6579.789722 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6507.873418 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6492638 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 55697920 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001302 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 8465 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 6727 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 11310684 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1739 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 2807.125000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 3125.260571 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 13194.641931 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 8 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 875 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 22457 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 2734603 # number of cycles access was blocked +system.cpu.dcache.WriteReq_mshr_misses 1738 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 2809.444444 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 13310.407754 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 9 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 25285 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 29523212 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 4959.634598 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 4652.742959 # average overall mshr miss latency -system.cpu.dcache.demand_hits 29516414 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 33715596 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000230 # miss rate for demand accesses -system.cpu.dcache.demand_misses 6798 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 4561 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 10408186 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000076 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2237 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 29877998 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 6456.967595 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 6137.027629 # average overall mshr miss latency +system.cpu.dcache.demand_hits 29868555 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 60973145 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000316 # miss rate for demand accesses +system.cpu.dcache.demand_misses 9443 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 7199 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 13771490 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000075 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2244 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 29523212 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 4959.634598 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 4652.742959 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 29516414 # number of overall hits -system.cpu.dcache.overall_miss_latency 33715596 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000230 # miss rate for overall accesses -system.cpu.dcache.overall_misses 6798 # number of overall misses -system.cpu.dcache.overall_mshr_hits 4561 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 10408186 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000076 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2237 # number of overall MSHR misses +system.cpu.dcache.overall_accesses 29877998 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 6456.967595 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 6137.027629 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 29868555 # number of overall hits +system.cpu.dcache.overall_miss_latency 60973145 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000316 # miss rate for overall accesses +system.cpu.dcache.overall_misses 9443 # number of overall misses +system.cpu.dcache.overall_mshr_hits 7199 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 13771490 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000075 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2244 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 158 # number of replacements -system.cpu.dcache.sampled_refs 2237 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 160 # number of replacements +system.cpu.dcache.sampled_refs 2244 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1400.647488 # Cycle average of tags in use -system.cpu.dcache.total_refs 29516414 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1415.957077 # Cycle average of tags in use +system.cpu.dcache.total_refs 29868555 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 105 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 2047370 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 12661 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 2829477 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 146297095 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 36266329 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 27223403 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 6075840 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 45354 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 80395 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 17560137 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 17576948 # Number of cache lines fetched -system.cpu.fetch.Cycles 45711428 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 479088 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 150837354 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 2061309 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.244934 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 17576948 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 13534166 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.103924 # Number of inst fetches per cycle +system.cpu.dcache.writebacks 106 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 5155486 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 12562 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3109369 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 165294506 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 40322652 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 28299602 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 8350763 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 41264 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 148646 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 19607486 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 19380281 # Number of cache lines fetched +system.cpu.fetch.Cycles 48705122 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 491925 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 170506876 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 2058666 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.238310 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 19380281 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 14897618 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.072348 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 71693337 +system.cpu.fetch.rateDist.samples 82277149 system.cpu.fetch.rateDist.min_value 0 - 0 43559639 6075.83% - 1 2788432 388.94% - 2 2133609 297.60% - 3 3200202 446.37% - 4 4098889 571.73% - 5 1363717 190.22% - 6 1885995 263.06% - 7 1651845 230.40% - 8 11011009 1535.85% + 0 52952312 6435.85% + 1 3129610 380.37% + 2 1369966 166.51% + 3 2017219 245.17% + 4 3854384 468.46% + 5 1357405 164.98% + 6 1550178 188.41% + 7 1288552 156.61% + 8 14757523 1793.64% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 17576948 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3407.568545 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2506.978423 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 17563424 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 46083957 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000769 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 13524 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 3467 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 25212682 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000572 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 10057 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets 3513.269231 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1746.387988 # Average number of references to valid blocks. +system.cpu.icache.ReadReq_accesses 19380281 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3416.377011 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2534.518183 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 19366483 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 47139170 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000712 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 13798 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 3761 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 25438959 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000518 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 10037 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 1929.509116 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 26 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 91345 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 17576948 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3407.568545 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2506.978423 # average overall mshr miss latency -system.cpu.icache.demand_hits 17563424 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 46083957 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000769 # miss rate for demand accesses -system.cpu.icache.demand_misses 13524 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 3467 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 25212682 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000572 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 10057 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 19380281 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3416.377011 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2534.518183 # average overall mshr miss latency +system.cpu.icache.demand_hits 19366483 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 47139170 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000712 # miss rate for demand accesses +system.cpu.icache.demand_misses 13798 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 3761 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 25438959 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000518 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 10037 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 17576948 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3407.568545 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2506.978423 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 17563424 # number of overall hits -system.cpu.icache.overall_miss_latency 46083957 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000769 # miss rate for overall accesses -system.cpu.icache.overall_misses 13524 # number of overall misses -system.cpu.icache.overall_mshr_hits 3467 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 25212682 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000572 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 10057 # number of overall MSHR misses +system.cpu.icache.overall_accesses 19380281 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3416.377011 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2534.518183 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 19366483 # number of overall hits +system.cpu.icache.overall_miss_latency 47139170 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000712 # miss rate for overall accesses +system.cpu.icache.overall_misses 13798 # number of overall misses +system.cpu.icache.overall_mshr_hits 3761 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 25438959 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000518 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 10037 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,162 +215,162 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 8145 # number of replacements -system.cpu.icache.sampled_refs 10057 # Sample count of references to valid blocks. +system.cpu.icache.replacements 8123 # number of replacements +system.cpu.icache.sampled_refs 10037 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1487.085502 # Cycle average of tags in use -system.cpu.icache.total_refs 17563424 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1498.249784 # Cycle average of tags in use +system.cpu.icache.total_refs 19366483 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 33641765 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 12581618 # Number of branches executed -system.cpu.iew.EXEC:nop 11617565 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.388001 # Inst execution rate -system.cpu.iew.EXEC:refs 31473535 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 7134398 # Number of stores executed +system.cpu.idleCycles 32049933 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 12923262 # Number of branches executed +system.cpu.iew.EXEC:nop 13162253 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.241494 # Inst execution rate +system.cpu.iew.EXEC:refs 31990682 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 7220394 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 88408054 # num instructions consuming a value -system.cpu.iew.WB:count 97920299 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.731090 # average fanout of values written-back +system.cpu.iew.WB:consumers 91915926 # num instructions consuming a value +system.cpu.iew.WB:count 100065162 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.718590 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 64634219 # num instructions producing a value -system.cpu.iew.WB:rate 1.365821 # insts written-back per cycle -system.cpu.iew.WB:sent 98494929 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 2154192 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 104376 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 29553768 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 436 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 2191495 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 9396457 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 131107086 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 24339137 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2193063 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 99510422 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 16363 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 66049838 # num instructions producing a value +system.cpu.iew.WB:rate 1.216196 # insts written-back per cycle +system.cpu.iew.WB:sent 100916733 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 2084205 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 596692 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 34568849 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 437 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 864110 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 10915344 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 150440832 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 24770288 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2226727 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 102146587 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 177017 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 879 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 6075840 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 34734 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 9915 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 36009 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 941599 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 3004 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.iewLSQFullEvents 827 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 8350763 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 211777 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 3149 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 865223 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 1107 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 23070 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 9915 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 9519355 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 2893762 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 23070 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 196104 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1958088 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.799161 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.799161 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 101703485 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 167324 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 9618 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 14534436 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 4412649 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 167324 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 194984 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1889221 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.736306 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.736306 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 104373314 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 7 0.00% # Type of FU issued - IntAlu 62578225 61.53% # Type of FU issued - IntMult 472394 0.46% # Type of FU issued + IntAlu 64752207 62.04% # Type of FU issued + IntMult 471285 0.45% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 2776755 2.73% # Type of FU issued - FloatCmp 115486 0.11% # Type of FU issued - FloatCvt 2376016 2.34% # Type of FU issued - FloatMult 302348 0.30% # Type of FU issued - FloatDiv 754954 0.74% # Type of FU issued - FloatSqrt 321 0.00% # Type of FU issued - MemRead 25019338 24.60% # Type of FU issued - MemWrite 7307641 7.19% # Type of FU issued + FloatAdd 2789912 2.67% # Type of FU issued + FloatCmp 115515 0.11% # Type of FU issued + FloatCvt 2364267 2.27% # Type of FU issued + FloatMult 305289 0.29% # Type of FU issued + FloatDiv 755087 0.72% # Type of FU issued + FloatSqrt 324 0.00% # Type of FU issued + MemRead 25418322 24.35% # Type of FU issued + MemWrite 7401099 7.09% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 1392706 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.013694 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 1952486 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.018707 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist -(null) 0 0.00% # attempts to use FU when none available -IntAlu 193189 13.87% # attempts to use FU when none available -IntMult 0 0.00% # attempts to use FU when none available -IntDiv 0 0.00% # attempts to use FU when none available -FloatAdd 1883 0.14% # attempts to use FU when none available -FloatCmp 96 0.01% # attempts to use FU when none available -FloatCvt 2836 0.20% # attempts to use FU when none available -FloatMult 2464 0.18% # attempts to use FU when none available -FloatDiv 659899 47.38% # attempts to use FU when none available -FloatSqrt 0 0.00% # attempts to use FU when none available -MemRead 465101 33.40% # attempts to use FU when none available -MemWrite 67238 4.83% # attempts to use FU when none available -IprAccess 0 0.00% # attempts to use FU when none available -InstPrefetch 0 0.00% # attempts to use FU when none available + (null) 0 0.00% # attempts to use FU when none available + IntAlu 163325 8.36% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 1017 0.05% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 12505 0.64% # attempts to use FU when none available + FloatMult 2432 0.12% # attempts to use FU when none available + FloatDiv 905685 46.39% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 774173 39.65% # attempts to use FU when none available + MemWrite 93349 4.78% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 71693337 +system.cpu.iq.ISSUE:issued_per_cycle.samples 82277149 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 27977053 3902.32% - 1 15408153 2149.18% - 2 12854527 1792.99% - 3 7056557 984.27% - 4 4494209 626.87% - 5 2427532 338.60% - 6 1097338 153.06% - 7 305661 42.63% - 8 72307 10.09% + 0 35738506 4343.67% + 1 18264427 2219.87% + 2 12740961 1548.54% + 3 6961052 846.05% + 4 4806764 584.22% + 5 2441659 296.76% + 6 994924 120.92% + 7 291934 35.48% + 8 36922 4.49% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.418590 # Inst issue rate -system.cpu.iq.iqInstsAdded 119489085 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 101703485 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 436 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 34413373 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 132312 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 28441004 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 12293 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3855.809345 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2071.040418 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 7221 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 19556665 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.412593 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 5072 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 10504317 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.412593 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 5072 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 105 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 105 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.444401 # Average number of references to valid blocks. +system.cpu.iq.ISSUE:rate 1.268558 # Inst issue rate +system.cpu.iq.iqInstsAdded 137278142 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 104373314 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 437 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 52505275 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 293840 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 48 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 49588547 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 12278 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4378.207161 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2293.937242 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 7195 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 22254427 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.413993 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 5083 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 11660083 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.413993 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 5083 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 106 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 106 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 1.436356 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 12293 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3855.809345 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2071.040418 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 7221 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 19556665 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.412593 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 5072 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 12278 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4378.207161 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2293.937242 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 7195 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 22254427 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.413993 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 5083 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 10504317 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.412593 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 5072 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 11660083 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.413993 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 5083 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 12398 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3855.809345 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2071.040418 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 7326 # number of overall hits -system.cpu.l2cache.overall_miss_latency 19556665 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.409098 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 5072 # number of overall misses +system.cpu.l2cache.overall_accesses 12384 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4378.207161 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2293.937242 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 7301 # number of overall hits +system.cpu.l2cache.overall_miss_latency 22254427 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.410449 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 5083 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 10504317 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.409098 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 5072 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 11660083 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.410449 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 5083 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -383,31 +383,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 5072 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 5083 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3261.872945 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7326 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3292.223620 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7301 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 71693337 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 812700 # Number of cycles rename is blocking +system.cpu.numCycles 82277149 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 2387077 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 369396 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 37208342 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 772307 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 122 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 182866276 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 141908898 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 104156212 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 26334995 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 6075840 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 1200845 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 35728851 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 60615 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 555 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 2896644 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 544 # count of temporary serializing insts renamed -system.cpu.timesIdled 10380 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 1473927 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 41553511 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1059964 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 61 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 206590907 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 160246119 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 117849091 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 27232157 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 8350763 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 2654523 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 49421730 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 99118 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 461 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 5497153 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 451 # count of temporary serializing insts renamed +system.cpu.timesIdled 10204 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.out b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.out index 00387ae5c..98777e0af 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.out +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.out @@ -66,7 +66,7 @@ The rand generator seed was at utemp() : 1 I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 - 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46 + 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 @@ -103,7 +103,7 @@ The rand generator seed was at utemp() : 1 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 - 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48 + 40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr index eb1796ead..f33d007a7 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. From 2952c34096357dffc207778ea1b73e71387ac010 Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Mon, 16 Apr 2007 11:31:54 -0400 Subject: [PATCH 09/68] Fixes for splash, may conflict with Korey's SMT work and doesn't support 03cpu yet. src/cpu/simple/base.cc: Cpu's should start as unallocated, not suspended src/cpu/simple_thread.cc: Wait for a thread to be assigned to activate the cpu src/kern/tru64/tru64.hh: When looking for a open cpu to assign threads, look for an unallocated one, not a suspended one. --HG-- extra : convert_revision : 5e3ad2e96b4a715ed38293ceaccff5b9f4ea7985 --- src/cpu/simple/base.cc | 2 +- src/cpu/simple_thread.cc | 8 ++++---- src/kern/tru64/tru64.hh | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 877dc5bd4..4fed2059b 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -79,7 +79,7 @@ BaseSimpleCPU::BaseSimpleCPU(Params *p) /* asid */ 0); #endif // !FULL_SYSTEM - thread->setStatus(ThreadContext::Suspended); + thread->setStatus(ThreadContext::Unallocated); tc = thread->getTC(); diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc index 39f31782b..191ae2f2e 100644 --- a/src/cpu/simple_thread.cc +++ b/src/cpu/simple_thread.cc @@ -221,10 +221,10 @@ SimpleThread::activate(int delay) lastActivate = curTick; - if (status() == ThreadContext::Unallocated) { - cpu->activateWhenReady(tid); - return; - } +// if (status() == ThreadContext::Unallocated) { +// cpu->activateWhenReady(tid); +// return; +// } _status = ThreadContext::Active; diff --git a/src/kern/tru64/tru64.hh b/src/kern/tru64/tru64.hh index b94276035..a7703be7c 100644 --- a/src/kern/tru64/tru64.hh +++ b/src/kern/tru64/tru64.hh @@ -792,7 +792,7 @@ class Tru64 : public OperatingSystem for (int i = 0; i < process->numCpus(); ++i) { ThreadContext *tc = process->threadContexts[i]; - if (tc->status() == ThreadContext::Suspended) { + if (tc->status() == ThreadContext::Unallocated) { // inactive context... grab it init_thread_context(tc, attrp, uniq_val); From d92fff858bdded7dbfa475837e91ada109b29f2c Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Wed, 18 Apr 2007 08:04:46 -0700 Subject: [PATCH 10/68] fix SIGUSR1 and SIGUSR2 by clearing the variables after they're used --HG-- extra : convert_revision : ed5351f291d45d585bf811a062e162e16b86e886 --- src/sim/simulate.cc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/sim/simulate.cc b/src/sim/simulate.cc index 55cbb50a9..36bdff45e 100644 --- a/src/sim/simulate.cc +++ b/src/sim/simulate.cc @@ -92,10 +92,9 @@ simulate(Tick num_cycles) if (async_event) { async_event = false; if (async_statdump || async_statreset) { + Stats::StatEvent(async_statdump, async_statreset); async_statdump = false; async_statreset = false; - - Stats::StatEvent(async_statdump, async_statreset); } if (async_exit) { From 6f4c1aa47519975366ee108ec5bb0fb1bf4e718d Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Wed, 18 Apr 2007 11:15:52 -0700 Subject: [PATCH 11/68] Move the turbolaser python simobject stuff into the encumbered directory --HG-- extra : convert_revision : 7062ce81183b989f0d922b00d02433633474a854 --- src/python/SConscript | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/python/SConscript b/src/python/SConscript index e1095eabe..3c5ab4da1 100644 --- a/src/python/SConscript +++ b/src/python/SConscript @@ -103,7 +103,6 @@ SimObject('m5/objects/Process.py') SimObject('m5/objects/Repl.py') SimObject('m5/objects/Root.py') SimObject('m5/objects/Sampler.py') -SimObject('m5/objects/Scsi.py') SimObject('m5/objects/SimConsole.py') SimObject('m5/objects/SimpleCPU.py') SimObject('m5/objects/SimpleDisk.py') @@ -114,7 +113,3 @@ SimObject('m5/objects/T1000.py') #SimObject('m5/objects/Tru64System.py') SimObject('m5/objects/Tsunami.py') SimObject('m5/objects/Uart.py') - -if env['ALPHA_TLASER']: - SimObject('m5/objects/DmaEngine.py') - SimObject('m5/objects/Turbolaser.py') From 5825104982d75daee20cd82da3ea2581c31d5292 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Wed, 18 Apr 2007 16:56:06 -0700 Subject: [PATCH 12/68] update the stuff that's removed from the SConscripts since things have moved around a bit --HG-- extra : convert_revision : 79322a65af6140d0c41aed0b381587eb05d72fd9 --- util/make_release.py | 35 ++++++++++++++--------------------- 1 file changed, 14 insertions(+), 21 deletions(-) diff --git a/util/make_release.py b/util/make_release.py index 8d69614dc..7362bd77c 100755 --- a/util/make_release.py +++ b/util/make_release.py @@ -133,30 +133,23 @@ rmtree(release_dir, 'src/dev/i8*') remove(release_dir, 'util/chgcopyright') remove(release_dir, 'util/make_release.py') -# fix up the SConscript to deal with files we've removed -mem_expr = re.compile('.*mem/cache/(tags/split|prefetch/(ghb|stride)).*') -inscript = file(joinpath(release_dir, 'src', 'SConscript'), 'r').readlines() -outscript = file(joinpath(release_dir, 'src', 'SConscript'), 'w') -for line in inscript: - if mem_expr.match(line): - continue +def remove_sources(regex, subdir): + script = joinpath(release_dir, subdir, 'SConscript') + if isinstance(regex, str): + regex = re.compile(regex) + inscript = file(script, 'r').readlines() + outscript = file(script, 'w') + for line in inscript: + if regex.match(line): + continue - outscript.write(line) -outscript.close() + outscript.write(line) + outscript.close() # fix up the SConscript to deal with files we've removed -mem_expr = re.compile('.*i8254xGBe.*') -inscript = file(joinpath(release_dir, 'src', 'dev', 'SConscript'), 'r').readlines() -outscript = file(joinpath(release_dir, 'src', 'dev', 'SConscript'), 'w') -for line in inscript: - if mem_expr.match(line): - continue - - outscript.write(line) -outscript.close() - - - +remove_sources(r'.*split.*\.cc', 'src/mem/cache/tags') +remove_sources(r'.*(ghb|stride)_prefetcher\.cc', 'src/mem/cache/prefetch') +remove_sources(r'.*i8254xGBe.*', 'src/dev') benches = [ 'bzip2', 'eon', 'gzip', 'mcf', 'parser', 'perlbmk', 'twolf', 'vortex' ] From 25e92383c839f6d69f933f614fd3f9acef907075 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Fri, 20 Apr 2007 20:21:59 -0400 Subject: [PATCH 13/68] spec-surge-client.rcS: fix script to reflect new benchmark directory sturcture configs/boot/spec-surge-client.rcS: fix script to reflect new benchmark directory sturcture --HG-- extra : convert_revision : 45f9d8aebabd1f3f8d1e826e07840e2365511a35 --- configs/boot/spec-surge-client.rcS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/boot/spec-surge-client.rcS b/configs/boot/spec-surge-client.rcS index 03f25986c..0dd2ba7db 100644 --- a/configs/boot/spec-surge-client.rcS +++ b/configs/boot/spec-surge-client.rcS @@ -35,7 +35,7 @@ echo "waiting for server..." netcat -c -l -p 8000 echo -n "running surge client..." -/bin/bash -c "cd /benchmarks/specsurge && ./spec-m5 1 20 1 192.168.0.1 5 40000 1000000000 1000" +/bin/bash -c "cd /benchmarks/surge && ./spec-m5 1 20 1 192.168.0.1 5 40000 1000000000 1000" echo "done." echo -n "halting machine" From e8ace88e897a4b0f61526ac0fe88740d337f0509 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Sat, 21 Apr 2007 17:50:47 -0400 Subject: [PATCH 14/68] create base/fenv.c to standerdize fenv across platforms. It's a c file and not a cpp file because c99 (which defines fenv) doesn't necessarily extend to c++ and it is a problem with solaris. If really desired this could wrap the ieeefp interface found in bsd* as well, but I see no need at the moment. src/arch/alpha/isa/fp.isa: src/arch/sparc/isa/formats/basic.isa: use m5_fesetround()/m5_fegetround() istead of fenv interface directly src/arch/sparc/isa/includes.isa: use base/fenv instead of fenv directly src/base/SConscript: add fenv to sconscript src/base/fenv.hh: src/base/random.cc: m5 implementation to standerdize fenv across platforms. --HG-- extra : convert_revision : 38d2629affd964dcd1a5ab0db4ac3cb21438e72c --- src/arch/alpha/isa/fp.isa | 12 +++--- src/arch/sparc/isa/formats/basic.isa | 31 ++++----------- src/arch/sparc/isa/includes.isa | 12 +----- src/base/SConscript | 1 + src/base/fenv.c | 56 ++++++++++++++++++++++++++++ src/base/fenv.hh | 21 ++++++----- src/base/random.cc | 8 ++-- 7 files changed, 87 insertions(+), 54 deletions(-) create mode 100644 src/base/fenv.c diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa index a350aa05f..773e7d10c 100644 --- a/src/arch/alpha/isa/fp.isa +++ b/src/arch/alpha/isa/fp.isa @@ -192,10 +192,10 @@ output decoder {{ } const int AlphaFP::alphaToC99RoundingMode[] = { - FE_TOWARDZERO, // Chopped - FE_DOWNWARD, // Minus_Infinity - FE_TONEAREST, // Normal - FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR + M5_FE_TOWARDZERO, // Chopped + M5_FE_DOWNWARD, // Minus_Infinity + M5_FE_TONEAREST, // Normal + M5_FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR }; const char *AlphaFP::roundingModeSuffix[] = { "c", "m", "", "d" }; @@ -228,10 +228,10 @@ def template FloatingPointExecute {{ if (roundingMode == Normal) { %(code)s; } else { - fesetround(getC99RoundingMode( + m5_fesetround(getC99RoundingMode( xc->readMiscRegNoEffect(AlphaISA::MISCREG_FPCR))); %(code)s; - fesetround(FE_TONEAREST); + m5_fesetround(M5_FE_TONEAREST); } #else if (roundingMode != Normal && !warnedOnRounding) { diff --git a/src/arch/sparc/isa/formats/basic.isa b/src/arch/sparc/isa/formats/basic.isa index 7665d2d4f..5b0868132 100644 --- a/src/arch/sparc/isa/formats/basic.isa +++ b/src/arch/sparc/isa/formats/basic.isa @@ -109,37 +109,22 @@ def format FpBasic(code, *flags) {{ fp_code = """ Fsr |= bits(Fsr,4,0) << 5; Fsr = insertBits(Fsr,4,0,0); -#if defined(__sun) || defined (__OpenBSD__) - fp_rnd newrnd = FP_RN; + int newrnd = M5_FE_TONEAREST; switch (Fsr<31:30>) { - case 0: newrnd = FP_RN; break; - case 1: newrnd = FP_RZ; break; - case 2: newrnd = FP_RP; break; - case 3: newrnd = FP_RM; break; + case 0: newrnd = M5_FE_TONEAREST; break; + case 1: newrnd = M5_FE_TOWARDZERO; break; + case 2: newrnd = M5_FE_UPWARD; break; + case 3: newrnd = M5_FE_DOWNWARD; break; } - fp_rnd oldrnd = fpsetround(newrnd); -#else - int newrnd = FE_TONEAREST; - switch (Fsr<31:30>) { - case 0: newrnd = FE_TONEAREST; break; - case 1: newrnd = FE_TOWARDZERO; break; - case 2: newrnd = FE_UPWARD; break; - case 3: newrnd = FE_DOWNWARD; break; - } - int oldrnd = fegetround(); - fesetround(newrnd); -#endif + int oldrnd = m5_fegetround(); + m5_fesetround(newrnd); """ fp_code += code fp_code += """ -#if defined(__sun) || defined (__OpenBSD__) - fpsetround(oldrnd); -#else - fesetround(oldrnd); -#endif + m5_fesetround(oldrnd); """ fp_code = filterDoubles(fp_code) iop = InstObjParams(name, Name, 'SparcStaticInst', fp_code, flags) diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa index 05e9e8731..e9cd660b5 100644 --- a/src/arch/sparc/isa/includes.isa +++ b/src/arch/sparc/isa/includes.isa @@ -53,22 +53,14 @@ output decoder {{ #include "cpu/thread_context.hh" // for Jump::branchTarget() #include "mem/packet.hh" -#if defined(linux) || defined(__APPLE__) -#include -#endif +#include "base/fenv.hh" #include using namespace SparcISA; }}; output exec {{ -#if defined(linux) || defined(__APPLE__) -#include -#endif - -#if defined(__sun) || defined (__OpenBSD__) -#include -#endif +#include "base/fenv.hh" #if FULL_SYSTEM #include "sim/pseudo_inst.hh" diff --git a/src/base/SConscript b/src/base/SConscript index 5e4aaafc2..cc9d06a0e 100644 --- a/src/base/SConscript +++ b/src/base/SConscript @@ -57,6 +57,7 @@ Source('circlebuf.cc') Source('cprintf.cc') Source('crc.cc') Source('fast_alloc.cc') +Source('fenv.c') Source('fifo_buffer.cc') Source('hostinfo.cc') Source('hybrid_pred.cc') diff --git a/src/base/fenv.c b/src/base/fenv.c new file mode 100644 index 000000000..269913a60 --- /dev/null +++ b/src/base/fenv.c @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2007 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + */ + +#include +#include +#include + +void m5_fesetround(int rm); +int m5_fegetround(); + +static const int m5_round_ops[] = {FE_DOWNWARD, FE_TONEAREST, FE_TOWARDZERO, FE_UPWARD}; + +void m5_fesetround(int rm) +{ + assert(rm > 0 && rm < 4); + fesetround(m5_round_ops[rm]); +} + +int m5_fegetround() +{ + int x; + int rm = fegetround(); + for(x = 0; x < 4; x++) + if (m5_round_ops[x] == rm) + return x; + abort(); + return 0; +} + diff --git a/src/base/fenv.hh b/src/base/fenv.hh index 013d2f09b..42b383888 100644 --- a/src/base/fenv.hh +++ b/src/base/fenv.hh @@ -33,20 +33,21 @@ #include "config/use_fenv.hh" +#define M5_FE_DOWNWARD 0 +#define M5_FE_TONEAREST 1 +#define M5_FE_TOWARDZERO 2 +#define M5_FE_UPWARD 3 + #if USE_FENV - -#include - +extern "C" { +void m5_fesetround(int rm); +int m5_fegetround(); +} #else // Dummy definitions to allow code to compile w/o a real . - -#define FE_TONEAREST 0 -#define FE_DOWNWARD 0 -#define FE_UPWARD 0 -#define FE_TOWARDZERO 0 - -inline int fesetround(int rounding_mode) { return 0; } +inline void m5_fesetround(int rm) { ; } +inline int m5_fegetround() {return 0; } #endif // USE_FENV diff --git a/src/base/random.cc b/src/base/random.cc index ceab337d9..5390ceb46 100644 --- a/src/base/random.cc +++ b/src/base/random.cc @@ -29,9 +29,6 @@ * Ali Saidi */ -#if defined(__sun) -#include -#endif #ifdef __SUNPRO_CC #include #include @@ -61,9 +58,10 @@ m5round(double r) { #if defined(__sun) double val; - fp_rnd oldrnd = fpsetround(FP_RN); + int oldrnd = m5_fegetround(); + m5_fesetround(M5_FP_TONEAREST); val = rint(r); - fpsetround(oldrnd); + m5_fesetround(oldrnd); return val; #else return round(r); From 53ba34391ff7b82dd143c7cce0d31bf56882d5ae Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Sat, 21 Apr 2007 19:11:38 -0400 Subject: [PATCH 15/68] fixes for solaris compile --HG-- extra : convert_revision : c82a62a61650e3700d237da917c453e5a9676320 --- src/arch/alpha/ev5.cc | 14 +++++++------- src/arch/alpha/floatregfile.hh | 4 ++-- src/arch/alpha/intregfile.hh | 4 ++-- src/base/random.cc | 3 ++- src/cpu/o3/lsq_unit.hh | 5 +++-- src/dev/alpha/console.cc | 2 +- 6 files changed, 17 insertions(+), 15 deletions(-) diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc index ec5090eb8..86b8fd2d0 100644 --- a/src/arch/alpha/ev5.cc +++ b/src/arch/alpha/ev5.cc @@ -245,13 +245,13 @@ AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc) { AlphaISA::PTE &pte = tc->getDTBPtr()->index(!tc->misspeculating()); - retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32; - retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8; - retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12; - retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1; - retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2; - retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4; - retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57; + retval |= ((uint64_t)pte.ppn & ULL(0x7ffffff)) << 32; + retval |= ((uint64_t)pte.xre & ULL(0xf)) << 8; + retval |= ((uint64_t)pte.xwe & ULL(0xf)) << 12; + retval |= ((uint64_t)pte.fonr & ULL(0x1)) << 1; + retval |= ((uint64_t)pte.fonw & ULL(0x1))<< 2; + retval |= ((uint64_t)pte.asma & ULL(0x1)) << 4; + retval |= ((uint64_t)pte.asn & ULL(0x7f)) << 57; } break; diff --git a/src/arch/alpha/floatregfile.hh b/src/arch/alpha/floatregfile.hh index d289f5785..0c5fe17a7 100644 --- a/src/arch/alpha/floatregfile.hh +++ b/src/arch/alpha/floatregfile.hh @@ -35,7 +35,7 @@ #include "arch/alpha/isa_traits.hh" #include "arch/alpha/types.hh" -#include +#include #include class Checkpoint; @@ -61,7 +61,7 @@ namespace AlphaISA void unserialize(Checkpoint *cp, const std::string §ion); void clear() - { bzero(d, sizeof(d)); } + { std::memset(d, 0, sizeof(d)); } }; } diff --git a/src/arch/alpha/intregfile.hh b/src/arch/alpha/intregfile.hh index 0d65f69e0..dea160992 100644 --- a/src/arch/alpha/intregfile.hh +++ b/src/arch/alpha/intregfile.hh @@ -35,7 +35,7 @@ #include "arch/alpha/types.hh" #include -#include +#include class Checkpoint; @@ -71,7 +71,7 @@ namespace AlphaISA void unserialize(Checkpoint *cp, const std::string §ion); void clear() - { bzero(regs, sizeof(regs)); } + { std::memset(regs, 0, sizeof(regs)); } }; } diff --git a/src/base/random.cc b/src/base/random.cc index 5390ceb46..8a2e3c1c0 100644 --- a/src/base/random.cc +++ b/src/base/random.cc @@ -37,6 +37,7 @@ #include #include +#include "base/fenv.hh" #include "base/random.hh" using namespace std; @@ -59,7 +60,7 @@ m5round(double r) #if defined(__sun) double val; int oldrnd = m5_fegetround(); - m5_fesetround(M5_FP_TONEAREST); + m5_fesetround(M5_FE_TONEAREST); val = rint(r); m5_fesetround(oldrnd); return val; diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index f24de20d9..cc33e025d 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -33,6 +33,7 @@ #define __CPU_O3_LSQ_UNIT_HH__ #include +#include #include #include @@ -292,7 +293,7 @@ class LSQUnit { : inst(NULL), req(NULL), size(0), canWB(0), committed(0), completed(0) { - bzero(data, sizeof(data)); + std::memset(data, 0, sizeof(data)); } /** Constructs a store queue entry for a given instruction. */ @@ -300,7 +301,7 @@ class LSQUnit { : inst(_inst), req(NULL), size(0), canWB(0), committed(0), completed(0) { - bzero(data, sizeof(data)); + std::memset(data, 0, sizeof(data)); } /** The store instruction. */ diff --git a/src/dev/alpha/console.cc b/src/dev/alpha/console.cc index f077efe6c..443f376a5 100644 --- a/src/dev/alpha/console.cc +++ b/src/dev/alpha/console.cc @@ -76,7 +76,7 @@ AlphaConsole::AlphaConsole(Params *p) alphaAccess->diskOperation = 0; alphaAccess->outputChar = 0; alphaAccess->inputChar = 0; - bzero(alphaAccess->cpuStack, sizeof(alphaAccess->cpuStack)); + std::memset(alphaAccess->cpuStack, 0, sizeof(alphaAccess->cpuStack)); } From d1f9414e111b4b5e6d0f60ca64a415a47765e9e0 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Sun, 22 Apr 2007 14:39:39 -0400 Subject: [PATCH 16/68] Update configs to set the CPU clock properly. --HG-- extra : convert_revision : 62fec666f987e9a9a441e319458908483cd2c5ff --- tests/configs/o3-timing-mp.py | 3 ++- tests/configs/o3-timing.py | 1 + tests/configs/simple-atomic-mp.py | 3 ++- tests/configs/simple-atomic.py | 3 ++- tests/configs/simple-timing-mp.py | 3 ++- tests/configs/simple-timing.py | 3 ++- 6 files changed, 11 insertions(+), 5 deletions(-) diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py index 331e2c569..1e414294c 100644 --- a/tests/configs/o3-timing-mp.py +++ b/tests/configs/o3-timing-mp.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -73,6 +73,7 @@ for cpu in cpus: L1(size = '32kB', assoc = 4)) # connect cpu level-1 caches to shared level-2 cache cpu.connectMemPorts(system.toL2Bus) + cpu.clock = '2GHz' # connect memory to membus system.physmem.port = system.membus.port diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py index 5600d9f22..d20a7e0c8 100644 --- a/tests/configs/o3-timing.py +++ b/tests/configs/o3-timing.py @@ -40,6 +40,7 @@ class MyCache(BaseCache): cpu = DerivO3CPU(cpu_id=0) cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), MyCache(size = '2MB')) +cpu.clock = '2GHz' system = System(cpu = cpu, physmem = PhysicalMemory(), diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py index f9e4e2767..e8000cd0a 100644 --- a/tests/configs/simple-atomic-mp.py +++ b/tests/configs/simple-atomic-mp.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -72,6 +72,7 @@ for cpu in cpus: L1(size = '32kB', assoc = 4)) # connect cpu level-1 caches to shared level-2 cache cpu.connectMemPorts(system.toL2Bus) + cpu.clock = '2GHz' # connect memory to membus system.physmem.port = system.membus.port diff --git a/tests/configs/simple-atomic.py b/tests/configs/simple-atomic.py index a8a876994..cc303886b 100644 --- a/tests/configs/simple-atomic.py +++ b/tests/configs/simple-atomic.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -34,5 +34,6 @@ system = System(cpu = AtomicSimpleCPU(cpu_id=0), membus = Bus()) system.physmem.port = system.membus.port system.cpu.connectMemPorts(system.membus) +system.cpu.clock = '2GHz' root = Root(system = system) diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py index 0d99d8714..a263bcf57 100644 --- a/tests/configs/simple-timing-mp.py +++ b/tests/configs/simple-timing-mp.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -72,6 +72,7 @@ for cpu in cpus: L1(size = '32kB', assoc = 4)) # connect cpu level-1 caches to shared level-2 cache cpu.connectMemPorts(system.toL2Bus) + cpu.clock = '2GHz' # connect memory to membus system.physmem.port = system.membus.port diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py index d7d505a5a..6c4b8232f 100644 --- a/tests/configs/simple-timing.py +++ b/tests/configs/simple-timing.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -44,5 +44,6 @@ system = System(cpu = cpu, membus = Bus()) system.physmem.port = system.membus.port cpu.connectMemPorts(system.membus) +cpu.clock = '2GHz' root = Root(system = system) From d70f01ba5c7fdd94e20a7a2544e41f7f59cc383f Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Sun, 22 Apr 2007 14:50:37 -0400 Subject: [PATCH 17/68] Update refs for new CPU frequency changes. tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini: tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out: tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt: tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr: tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout: tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini: tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out: tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt: tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr: tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout: tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini: tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out: tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt: tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr: tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout: tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini: tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out: tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt: tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout: tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini: tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out: tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt: tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr: tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout: tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini: tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out: tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt: tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout: tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini: tests/quick/50.memtest/ref/alpha/linux/memtest/config.out: tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt: tests/quick/50.memtest/ref/alpha/linux/memtest/stdout: Update refs --HG-- extra : convert_revision : 8d9deb2b907843064b40e46207d9c9361941f022 --- .../ref/alpha/linux/o3-timing/config.ini | 2 +- .../ref/alpha/linux/o3-timing/config.out | 2 +- .../ref/alpha/linux/o3-timing/m5stats.txt | 486 +++++------ .../00.hello/ref/alpha/linux/o3-timing/stderr | 1 - .../00.hello/ref/alpha/linux/o3-timing/stdout | 6 +- .../ref/alpha/linux/simple-atomic/config.ini | 60 +- .../ref/alpha/linux/simple-atomic/config.out | 61 +- .../ref/alpha/linux/simple-atomic/m5stats.txt | 12 +- .../ref/alpha/linux/simple-atomic/stderr | 1 + .../ref/alpha/linux/simple-atomic/stdout | 11 +- .../ref/alpha/linux/simple-timing/config.ini | 60 +- .../ref/alpha/linux/simple-timing/config.out | 61 +- .../ref/alpha/linux/simple-timing/m5stats.txt | 100 +-- .../ref/alpha/linux/simple-timing/stderr | 1 + .../ref/alpha/linux/simple-timing/stdout | 11 +- .../ref/alpha/tru64/o3-timing/config.ini | 2 +- .../ref/alpha/tru64/o3-timing/config.out | 2 +- .../ref/alpha/tru64/o3-timing/m5stats.txt | 460 +++++----- .../00.hello/ref/alpha/tru64/o3-timing/stdout | 6 +- .../ref/alpha/tru64/simple-atomic/config.ini | 60 +- .../ref/alpha/tru64/simple-atomic/config.out | 61 +- .../ref/alpha/tru64/simple-atomic/m5stats.txt | 10 +- .../ref/alpha/tru64/simple-atomic/stderr | 1 + .../ref/alpha/tru64/simple-atomic/stdout | 11 +- .../ref/alpha/tru64/simple-timing/config.ini | 60 +- .../ref/alpha/tru64/simple-timing/config.out | 61 +- .../ref/alpha/tru64/simple-timing/m5stats.txt | 98 +-- .../ref/alpha/tru64/simple-timing/stderr | 1 + .../ref/alpha/tru64/simple-timing/stdout | 11 +- .../ref/alpha/linux/o3-timing/config.ini | 2 +- .../ref/alpha/linux/o3-timing/config.out | 2 +- .../ref/alpha/linux/o3-timing/m5stats.txt | 820 +++++++++--------- .../ref/alpha/linux/o3-timing/stderr | 2 - .../ref/alpha/linux/o3-timing/stdout | 6 +- .../ref/alpha/eio/simple-atomic/config.ini | 59 +- .../ref/alpha/eio/simple-atomic/config.out | 60 +- .../ref/alpha/eio/simple-atomic/m5stats.txt | 12 +- .../ref/alpha/eio/simple-atomic/stdout | 11 +- .../ref/alpha/eio/simple-timing/config.ini | 59 +- .../ref/alpha/eio/simple-timing/config.out | 60 +- .../ref/alpha/eio/simple-timing/m5stats.txt | 100 +-- .../ref/alpha/eio/simple-timing/stdout | 11 +- .../ref/alpha/linux/memtest/config.ini | 52 +- .../ref/alpha/linux/memtest/config.out | 53 +- .../ref/alpha/linux/memtest/m5stats.txt | 18 +- .../50.memtest/ref/alpha/linux/memtest/stdout | 7 +- 46 files changed, 1171 insertions(+), 1882 deletions(-) diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 4d44e14fe..2a139492e 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -23,7 +23,7 @@ activity=0 backComSize=5 choiceCtrBits=2 choicePredictorSize=8192 -clock=1 +clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out index 686c3b2f6..8155faf63 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out @@ -167,7 +167,7 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL [system.cpu] type=DerivO3CPU -clock=1 +clock=500 phase=0 numThreads=1 cpu_id=0 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index 988584966..0a0a4f78e 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 615 # Number of BTB hits -global.BPredUnit.BTBLookups 1663 # Number of BTB lookups -global.BPredUnit.RASInCorrect 78 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 439 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1180 # Number of conditional branches predicted -global.BPredUnit.lookups 2032 # Number of BP lookups -global.BPredUnit.usedRAS 304 # Number of times the RAS was used to get a target. -host_inst_rate 15105 # Simulator instruction rate (inst/s) -host_mem_usage 154056 # Number of bytes of host memory used -host_seconds 0.37 # Real time elapsed on the host -host_tick_rate 3572881 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 24 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 13 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2144 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 606 # Number of BTB hits +global.BPredUnit.BTBLookups 1858 # Number of BTB lookups +global.BPredUnit.RASInCorrect 54 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 415 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1270 # Number of conditional branches predicted +global.BPredUnit.lookups 2195 # Number of BP lookups +global.BPredUnit.usedRAS 306 # Number of times the RAS was used to get a target. +host_inst_rate 5017 # Simulator instruction rate (inst/s) +host_mem_usage 154084 # Number of bytes of host memory used +host_seconds 1.12 # Real time elapsed on the host +host_tick_rate 3160160 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 31 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 138 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2061 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1230 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5623 # Number of instructions simulated -sim_seconds 0.000001 # Number of seconds simulated -sim_ticks 1331134 # Number of ticks simulated +sim_seconds 0.000004 # Number of seconds simulated +sim_ticks 3543500 # Number of ticks simulated system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 101 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 121 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 30311 +system.cpu.commit.COM:committed_per_cycle.samples 6315 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 27595 9103.96% - 1 1579 520.93% - 2 482 159.02% - 3 232 76.54% - 4 131 43.22% - 5 104 34.31% - 6 60 19.79% - 7 27 8.91% - 8 101 33.32% + 0 4255 6737.93% + 1 915 1448.93% + 2 408 646.08% + 3 162 256.53% + 4 140 221.69% + 5 91 144.10% + 6 121 191.61% + 7 102 161.52% + 8 121 191.61% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,69 +43,69 @@ system.cpu.commit.COM:loads 979 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 1791 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 370 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 341 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4834 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4458 # The number of squashed insts skipped by commit system.cpu.committedInsts 5623 # Number of Instructions Simulated system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 236.730215 # CPI: Cycles Per Instruction -system.cpu.cpi_total 236.730215 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1606 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 7256.076023 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7095.200000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1435 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1240789 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.106476 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 171 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 71 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 709520 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.062267 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses +system.cpu.cpi 630.179619 # CPI: Cycles Per Instruction +system.cpu.cpi_total 630.179619 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1516 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 4941.176471 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4361.386139 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1380 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 672000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.089710 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 136 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 440500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.066623 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 8026.070225 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7200.452055 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 456 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2857281 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.438424 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 356 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 525633 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 3265.671642 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3819.444444 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 477 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 1094000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.412562 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 335 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 263 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 275000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.088670 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 72 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 10.930636 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 10.734104 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2418 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 7776.223909 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 7139.612717 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1891 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 4098070 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.217949 # miss rate for demand accesses -system.cpu.dcache.demand_misses 527 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 354 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1235153 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.071547 # mshr miss rate for demand accesses +system.cpu.dcache.demand_accesses 2328 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3749.469214 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4135.838150 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1857 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 1766000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.202320 # miss rate for demand accesses +system.cpu.dcache.demand_misses 471 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 298 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 715500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.074313 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 173 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2418 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 7776.223909 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 7139.612717 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 2328 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3749.469214 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4135.838150 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1891 # number of overall hits -system.cpu.dcache.overall_miss_latency 4098070 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.217949 # miss rate for overall accesses -system.cpu.dcache.overall_misses 527 # number of overall misses -system.cpu.dcache.overall_mshr_hits 354 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1235153 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.071547 # mshr miss rate for overall accesses +system.cpu.dcache.overall_hits 1857 # number of overall hits +system.cpu.dcache.overall_miss_latency 1766000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.202320 # miss rate for overall accesses +system.cpu.dcache.overall_misses 471 # number of overall misses +system.cpu.dcache.overall_mshr_hits 298 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 715500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.074313 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 173 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -121,89 +121,89 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 102.478227 # Cycle average of tags in use -system.cpu.dcache.total_refs 1891 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 111.557376 # Cycle average of tags in use +system.cpu.dcache.total_refs 1857 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 17469 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 70 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 169 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 11765 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 10684 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2098 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 907 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 200 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 61 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 2032 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1710 # Number of cache lines fetched -system.cpu.fetch.Cycles 3962 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 268 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 12603 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 472 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.065089 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1710 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 919 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.403696 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 381 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 81 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 172 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12164 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 3741 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2151 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 772 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 244 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 43 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 2195 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1616 # Number of cache lines fetched +system.cpu.fetch.Cycles 3951 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 151 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13452 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 448 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.309678 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1616 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 912 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.897856 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 31219 +system.cpu.fetch.rateDist.samples 7088 system.cpu.fetch.rateDist.min_value 0 - 0 28979 9282.49% - 1 197 63.10% - 2 198 63.42% - 3 167 53.49% - 4 197 63.10% - 5 187 59.90% - 6 222 71.11% - 7 122 39.08% - 8 950 304.30% + 0 4755 6708.52% + 1 197 277.93% + 2 177 249.72% + 3 163 229.97% + 4 234 330.14% + 5 170 239.84% + 6 198 279.35% + 7 114 160.84% + 8 1080 1523.70% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 1710 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 5139.251163 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 4349.151613 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1280 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 2209878 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.251462 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 430 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 120 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 1348237 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.181287 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 310 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 1616 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 4068.597561 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 3148.089172 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1288 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1334500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.202970 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 328 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 988500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.194307 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 314 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4.129032 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.101911 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1710 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 5139.251163 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 4349.151613 # average overall mshr miss latency -system.cpu.icache.demand_hits 1280 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 2209878 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.251462 # miss rate for demand accesses -system.cpu.icache.demand_misses 430 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 120 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1348237 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.181287 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 310 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 1616 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 4068.597561 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 3148.089172 # average overall mshr miss latency +system.cpu.icache.demand_hits 1288 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1334500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.202970 # miss rate for demand accesses +system.cpu.icache.demand_misses 328 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 14 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 988500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.194307 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 314 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1710 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 5139.251163 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 4349.151613 # average overall mshr miss latency +system.cpu.icache.overall_accesses 1616 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 4068.597561 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 3148.089172 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1280 # number of overall hits -system.cpu.icache.overall_miss_latency 2209878 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.251462 # miss rate for overall accesses -system.cpu.icache.overall_misses 430 # number of overall misses -system.cpu.icache.overall_mshr_hits 120 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1348237 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.181287 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 310 # number of overall MSHR misses +system.cpu.icache.overall_hits 1288 # number of overall hits +system.cpu.icache.overall_miss_latency 1334500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.202970 # miss rate for overall accesses +system.cpu.icache.overall_misses 328 # number of overall misses +system.cpu.icache.overall_mshr_hits 14 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 988500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.194307 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 314 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -216,61 +216,60 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 310 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 148.421347 # Cycle average of tags in use -system.cpu.icache.total_refs 1280 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 166.037293 # Cycle average of tags in use +system.cpu.icache.total_refs 1288 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1299916 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1267 # Number of branches executed -system.cpu.iew.EXEC:nop 48 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.270476 # Inst execution rate -system.cpu.iew.EXEC:refs 2748 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1031 # Number of stores executed +system.cpu.iew.EXEC:branches 1203 # Number of branches executed +system.cpu.iew.EXEC:nop 41 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.125423 # Inst execution rate +system.cpu.iew.EXEC:refs 2585 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 989 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5354 # num instructions consuming a value -system.cpu.iew.WB:count 8160 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.757378 # average fanout of values written-back +system.cpu.iew.WB:consumers 5598 # num instructions consuming a value +system.cpu.iew.WB:count 7767 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.741872 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4055 # num instructions producing a value -system.cpu.iew.WB:rate 0.261379 # insts written-back per cycle -system.cpu.iew.WB:sent 8228 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 404 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 7230 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2144 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 24 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 10469 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1717 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 299 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 8444 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 4153 # num instructions producing a value +system.cpu.iew.WB:rate 1.095796 # insts written-back per cycle +system.cpu.iew.WB:sent 7849 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 3 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2061 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 240 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1230 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 10115 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1596 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 554 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 7977 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 907 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 772 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 81 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 57 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 60 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 68 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1165 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 60 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 279 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.004224 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.004224 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8743 # Type of FU issued +system.cpu.iew.lsq.thread.0.squashedLoads 1082 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 418 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 68 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 284 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 109 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.001587 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.001587 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 8531 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 2 0.02% # Type of FU issued - IntAlu 5868 67.12% # Type of FU issued + IntAlu 5713 66.97% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -279,16 +278,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1809 20.69% # Type of FU issued - MemWrite 1061 12.14% # Type of FU issued + MemRead 1773 20.78% # Type of FU issued + MemWrite 1040 12.19% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 87 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009951 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 128 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.015004 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 1 1.15% # attempts to use FU when none available + IntAlu 7 5.47% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -297,43 +296,43 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 54 62.07% # attempts to use FU when none available - MemWrite 32 36.78% # attempts to use FU when none available + MemRead 78 60.94% # attempts to use FU when none available + MemWrite 43 33.59% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 31219 +system.cpu.iq.ISSUE:issued_per_cycle.samples 7088 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 27042 8662.03% - 1 1845 590.99% - 2 1151 368.69% - 3 572 183.22% - 4 318 101.86% - 5 182 58.30% - 6 76 24.34% - 7 22 7.05% - 8 11 3.52% + 0 4068 5739.28% + 1 771 1087.75% + 2 763 1076.47% + 3 485 684.26% + 4 504 711.06% + 5 295 416.20% + 6 144 203.16% + 7 40 56.43% + 8 18 25.40% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.280054 # Inst issue rate -system.cpu.iq.iqInstsAdded 10397 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8743 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4378 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 68 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2580 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 481 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4807.594595 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2390.114345 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 2312453 # number of ReadReq miss cycles +system.cpu.iq.ISSUE:rate 1.203584 # Inst issue rate +system.cpu.iq.iqInstsAdded 10051 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8531 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 4086 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2494 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 485 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 3318.556701 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1934.377320 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 1609500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 481 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1149645 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_misses 485 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 938173 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 481 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 485 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -342,32 +341,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4807.594595 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2390.114345 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 485 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 3318.556701 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1934.377320 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2312453 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 1609500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 481 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 485 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1149645 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 938173 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 481 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 485 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4807.594595 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2390.114345 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 485 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 3318.556701 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1934.377320 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2312453 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 1609500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 481 # number of overall misses +system.cpu.l2cache.overall_misses 485 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1149645 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 938173 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 481 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 485 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -380,31 +379,28 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 481 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 485 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 250.999286 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 277.255174 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 31219 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 7810 # Number of cycles rename is blocking +system.cpu.numCycles 7088 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 3 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 10837 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 465 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 6 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 14384 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11306 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8499 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 2010 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 907 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 491 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4448 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 9164 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:IdleCycles 3933 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 65 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 14798 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11577 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8671 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 2005 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 772 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 115 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4620 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 260 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 825 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed -system.cpu.timesIdled 365 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:skidInsts 396 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr index 8053728f7..f33d007a7 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr @@ -1,3 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout index ef47b0265..eeba3846f 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2007 13:12:55 -M5 started Fri Mar 30 13:13:02 2007 +M5 compiled Apr 21 2007 21:50:58 +M5 started Sat Apr 21 21:51:06 2007 M5 executing on zamp.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1331134 because target called exit() +Exiting @ tick 3543500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini index 79673d775..26009ca4f 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -1,51 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[debug] -break_cycles= - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -56,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -65,6 +21,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +phase=0 progress_interval=0 simulate_stalls=false system=system @@ -76,6 +33,7 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=hello +cwd= egid=100 env= euid=100 @@ -101,14 +59,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out index 31870d5f3..f8e40871a 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -30,6 +28,7 @@ executable=tests/test-progs/hello/bin/alpha/linux/hello input=cin output=cout env= +cwd= system=system uid=100 euid=100 @@ -48,61 +47,11 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 +phase=0 defer_registration=false width=1 function_trace=false function_trace_start=0 simulate_stalls=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[debug] -break_cycles= - -[statsreset] -reset_cycle=0 - diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt index 96973fa46..0f64469e9 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 684709 # Simulator instruction rate (inst/s) -host_mem_usage 148256 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 650634 # Simulator tick rate (ticks/s) +host_inst_rate 357156 # Simulator instruction rate (inst/s) +host_mem_usage 148180 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 171417285 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 5641 # Number of ticks simulated +sim_seconds 0.000003 # Number of seconds simulated +sim_ticks 2820500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 5642 # number of cpu cycles simulated diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr index 87866a2a5..f33d007a7 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr @@ -1 +1,2 @@ warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout index c451577a3..5acc408a3 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout @@ -6,8 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 3 2006 17:10:27 -M5 started Fri Nov 3 17:10:43 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic -Exiting @ tick 5641 because target called exit() +M5 compiled Apr 21 2007 21:50:58 +M5 started Sat Apr 21 21:51:08 2007 +M5 executing on zamp.eecs.umich.edu +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 2820500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index 13004a42a..025531062 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -1,51 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[debug] -break_cycles= - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -56,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -65,6 +21,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +phase=0 progress_interval=0 system=system workload=system.cpu.workload @@ -199,6 +156,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=hello +cwd= egid=100 env= euid=100 @@ -224,14 +182,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out index 58b3f5296..fa1054e9e 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -30,6 +28,7 @@ executable=tests/test-progs/hello/bin/alpha/linux/hello input=cin output=cout env= +cwd= system=system uid=100 euid=100 @@ -48,7 +47,8 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 +phase=0 defer_registration=false // width not specified function_trace=false @@ -176,54 +176,3 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[debug] -break_cycles= - -[statsreset] -reset_cycle=0 - diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt index 68f6bcca4..afdac247d 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 167195 # Simulator instruction rate (inst/s) -host_mem_usage 179768 # Number of bytes of host memory used +host_inst_rate 215467 # Simulator instruction rate (inst/s) +host_mem_usage 153656 # Number of bytes of host memory used host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 51710933 # Simulator tick rate (ticks/s) +host_tick_rate 193088667 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated -sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 1767066 # Number of ticks simulated +sim_seconds 0.000005 # Number of seconds simulated +sim_ticks 5135000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 979 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3990.760870 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2990.760870 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 3750 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2750 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 887 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 367150 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 345000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.093973 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 275150 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 253000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.093973 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 92 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3977.109589 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2977.109589 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 3582.191781 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2582.191781 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 739 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 290329 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 261500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.089901 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 217329 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 188500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 1791 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3984.721212 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2984.721212 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 3675.757576 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2675.757576 # average overall mshr miss latency system.cpu.dcache.demand_hits 1626 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 657479 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 606500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.092127 # miss rate for demand accesses system.cpu.dcache.demand_misses 165 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 492479 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 441500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.092127 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 165 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 1791 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3984.721212 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2984.721212 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 3675.757576 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2675.757576 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1626 # number of overall hits -system.cpu.dcache.overall_miss_latency 657479 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 606500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.092127 # miss rate for overall accesses system.cpu.dcache.overall_misses 165 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 492479 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 441500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.092127 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 97.858233 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 105.359700 # Cycle average of tags in use system.cpu.dcache.total_refs 1626 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 5643 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3980.490975 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2980.490975 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 3729.241877 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2729.241877 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 5366 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1102596 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 1033000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.049087 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 277 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 825596 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 756000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.049087 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 277 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 5643 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3980.490975 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2980.490975 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 3729.241877 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2729.241877 # average overall mshr miss latency system.cpu.icache.demand_hits 5366 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1102596 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 1033000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.049087 # miss rate for demand accesses system.cpu.icache.demand_misses 277 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 825596 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 756000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.049087 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 277 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 5643 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3980.490975 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2980.490975 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 3729.241877 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2729.241877 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 5366 # number of overall hits -system.cpu.icache.overall_miss_latency 1102596 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 1033000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.049087 # miss rate for overall accesses system.cpu.icache.overall_misses 277 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 825596 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 756000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.049087 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 277 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 277 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 122.802112 # Cycle average of tags in use +system.cpu.icache.tagsinuse 131.245403 # Cycle average of tags in use system.cpu.icache.total_refs 5366 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 441 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2984.340136 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1983.340136 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1316094 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 2712.018141 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1711.018141 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 1196000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 441 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 874653 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 754559 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 441 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2984.340136 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1983.340136 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 2712.018141 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1711.018141 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1316094 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 1196000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 441 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 874653 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 754559 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 441 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2984.340136 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1983.340136 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_miss_latency 2712.018141 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1711.018141 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1316094 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 1196000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 441 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 874653 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 754559 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 441 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 441 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 220.802916 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 236.577060 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1767066 # number of cpu cycles simulated +system.cpu.numCycles 5135000 # number of cpu cycles simulated system.cpu.num_insts 5642 # Number of instructions executed system.cpu.num_refs 1792 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr index 87866a2a5..f33d007a7 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr @@ -1 +1,2 @@ warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout index 61f79d88f..a79e87c66 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout @@ -6,8 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 3 2006 17:10:27 -M5 started Fri Nov 3 17:10:44 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing -Exiting @ tick 1767066 because target called exit() +M5 compiled Apr 21 2007 21:50:58 +M5 started Sat Apr 21 21:51:09 2007 +M5 executing on zamp.eecs.umich.edu +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 5135000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index bd6b9bcdc..1e3b2746e 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -23,7 +23,7 @@ activity=0 backComSize=5 choiceCtrBits=2 choicePredictorSize=8192 -clock=1 +clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out index 58df46dcb..5df02e4ff 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out @@ -167,7 +167,7 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL [system.cpu] type=DerivO3CPU -clock=1 +clock=500 phase=0 numThreads=1 cpu_id=0 diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt index 1919ca3fe..cc70d3787 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 187 # Number of BTB hits -global.BPredUnit.BTBLookups 653 # Number of BTB lookups -global.BPredUnit.RASInCorrect 41 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 217 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 426 # Number of conditional branches predicted -global.BPredUnit.lookups 832 # Number of BP lookups -global.BPredUnit.usedRAS 170 # Number of times the RAS was used to get a target. -host_inst_rate 19984 # Simulator instruction rate (inst/s) -host_mem_usage 153584 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host -host_tick_rate 6228839 # Simulator tick rate (ticks/s) +global.BPredUnit.BTBHits 162 # Number of BTB hits +global.BPredUnit.BTBLookups 671 # Number of BTB lookups +global.BPredUnit.RASInCorrect 36 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 220 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 427 # Number of conditional branches predicted +global.BPredUnit.lookups 860 # Number of BP lookups +global.BPredUnit.usedRAS 174 # Number of times the RAS was used to get a target. +host_inst_rate 32334 # Simulator instruction rate (inst/s) +host_mem_usage 153596 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 21839716 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 9 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 8 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 701 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 382 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 692 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 385 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated -sim_seconds 0.000001 # Number of seconds simulated -sim_ticks 746028 # Number of ticks simulated +sim_seconds 0.000002 # Number of seconds simulated +sim_ticks 1619000 # Number of ticks simulated system.cpu.commit.COM:branches 396 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 52 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 59 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 29809 +system.cpu.commit.COM:committed_per_cycle.samples 2977 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 28885 9690.03% - 1 239 80.18% - 2 325 109.03% - 3 129 43.28% - 4 78 26.17% - 5 53 17.78% - 6 29 9.73% - 7 19 6.37% - 8 52 17.44% + 0 2102 7060.80% + 1 212 712.13% + 2 297 997.65% + 3 114 382.94% + 4 83 278.80% + 5 58 194.83% + 6 30 100.77% + 7 22 73.90% + 8 59 198.19% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,69 +43,69 @@ system.cpu.commit.COM:loads 415 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 709 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 140 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 138 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1536 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1420 # The number of squashed insts skipped by commit system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 312.537914 # CPI: Cycles Per Instruction -system.cpu.cpi_total 312.537914 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 565 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 7055.843750 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7158.016393 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 469 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 677361 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.169912 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 96 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 436639 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.107965 # mshr miss rate for ReadReq accesses +system.cpu.cpi 678.257227 # CPI: Cycles Per Instruction +system.cpu.cpi_total 678.257227 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 537 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 4625 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3811.475410 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 465 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 333000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.134078 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 72 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 232500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.113594 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 7089.086420 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6946.208333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 213 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 574216 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 81 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 57 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 166709 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 5013.888889 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4520.833333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 222 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 361000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.244898 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 72 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 48 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 108500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.023529 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 8.082353 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 859 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 7071.056497 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 7098.211765 # average overall mshr miss latency -system.cpu.dcache.demand_hits 682 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1251577 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.206054 # miss rate for demand accesses -system.cpu.dcache.demand_misses 177 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 92 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 603348 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.098952 # mshr miss rate for demand accesses +system.cpu.dcache.demand_accesses 831 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 4819.444444 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4011.764706 # average overall mshr miss latency +system.cpu.dcache.demand_hits 687 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 694000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.173285 # miss rate for demand accesses +system.cpu.dcache.demand_misses 144 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 59 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 341000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.102286 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 859 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 7071.056497 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 7098.211765 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 831 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 4819.444444 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4011.764706 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 682 # number of overall hits -system.cpu.dcache.overall_miss_latency 1251577 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.206054 # miss rate for overall accesses -system.cpu.dcache.overall_misses 177 # number of overall misses -system.cpu.dcache.overall_mshr_hits 92 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 603348 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.098952 # mshr miss rate for overall accesses +system.cpu.dcache.overall_hits 687 # number of overall hits +system.cpu.dcache.overall_miss_latency 694000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.173285 # miss rate for overall accesses +system.cpu.dcache.overall_misses 144 # number of overall misses +system.cpu.dcache.overall_mshr_hits 59 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 341000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.102286 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -121,89 +121,89 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 46.650284 # Cycle average of tags in use -system.cpu.dcache.total_refs 682 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 50.824604 # Cycle average of tags in use +system.cpu.dcache.total_refs 687 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 23701 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 129 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 4617 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 5228 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 877 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 297 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 4 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 832 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 760 # Number of cache lines fetched -system.cpu.fetch.Cycles 1674 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 131 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 5310 # Number of instructions fetch has processed +system.cpu.decode.DECODE:BlockedCycles 83 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 83 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 138 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 4642 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 2009 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 884 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 261 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 313 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 2 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 860 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 736 # Number of cache lines fetched +system.cpu.fetch.Cycles 1668 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 78 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 5463 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 230 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.027635 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 760 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 357 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.176371 # Number of inst fetches per cycle +system.cpu.fetch.branchRate 0.265514 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 736 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 336 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.686632 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 30107 +system.cpu.fetch.rateDist.samples 3239 system.cpu.fetch.rateDist.min_value 0 - 0 29196 9697.41% - 1 37 12.29% - 2 87 28.90% - 3 73 24.25% - 4 125 41.52% - 5 66 21.92% - 6 42 13.95% - 7 50 16.61% - 8 431 143.16% + 0 2309 7128.74% + 1 47 145.11% + 2 82 253.16% + 3 70 216.12% + 4 128 395.18% + 5 58 179.07% + 6 37 114.23% + 7 46 142.02% + 8 462 1426.37% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 760 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4979.783333 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 4157.255435 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 520 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1195148 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.315789 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 240 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 764935 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.242105 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 184 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 736 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 4129.533679 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 3209.677419 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 543 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 797000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.262228 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 193 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 7 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 597000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.252717 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 186 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2.826087 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2.919355 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 760 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4979.783333 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 4157.255435 # average overall mshr miss latency -system.cpu.icache.demand_hits 520 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1195148 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.315789 # miss rate for demand accesses -system.cpu.icache.demand_misses 240 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 764935 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.242105 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 184 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 736 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 4129.533679 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 3209.677419 # average overall mshr miss latency +system.cpu.icache.demand_hits 543 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 797000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.262228 # miss rate for demand accesses +system.cpu.icache.demand_misses 193 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 7 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 597000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.252717 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 186 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 760 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4979.783333 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 4157.255435 # average overall mshr miss latency +system.cpu.icache.overall_accesses 736 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 4129.533679 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 3209.677419 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 520 # number of overall hits -system.cpu.icache.overall_miss_latency 1195148 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.315789 # miss rate for overall accesses -system.cpu.icache.overall_misses 240 # number of overall misses -system.cpu.icache.overall_mshr_hits 56 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 764935 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.242105 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 184 # number of overall MSHR misses +system.cpu.icache.overall_hits 543 # number of overall hits +system.cpu.icache.overall_miss_latency 797000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.262228 # miss rate for overall accesses +system.cpu.icache.overall_misses 193 # number of overall misses +system.cpu.icache.overall_mshr_hits 7 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 597000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.252717 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 186 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -216,61 +216,60 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 184 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 186 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 91.559894 # Cycle average of tags in use -system.cpu.icache.total_refs 520 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 104.079729 # Cycle average of tags in use +system.cpu.icache.total_refs 543 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 715922 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 547 # Number of branches executed -system.cpu.iew.EXEC:nop 269 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.108081 # Inst execution rate -system.cpu.iew.EXEC:refs 940 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 340 # Number of stores executed +system.cpu.iew.EXEC:branches 535 # Number of branches executed +system.cpu.iew.EXEC:nop 256 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.978388 # Inst execution rate +system.cpu.iew.EXEC:refs 913 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 339 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1841 # num instructions consuming a value -system.cpu.iew.WB:count 3178 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.788702 # average fanout of values written-back +system.cpu.iew.WB:consumers 1857 # num instructions consuming a value +system.cpu.iew.WB:count 3126 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.787291 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1452 # num instructions producing a value -system.cpu.iew.WB:rate 0.105557 # insts written-back per cycle -system.cpu.iew.WB:sent 3194 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 151 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 16588 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 701 # Number of dispatched load instructions +system.cpu.iew.WB:producers 1462 # num instructions producing a value +system.cpu.iew.WB:rate 0.965113 # insts written-back per cycle +system.cpu.iew.WB:sent 3139 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 156 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 692 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 62 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 382 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 4113 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 600 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 110 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 3254 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 99 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 385 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 4013 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 574 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 208 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 3169 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 297 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 261 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 29 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 27 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 15 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 10 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 286 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 88 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 15 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 96 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 55 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.003200 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.003200 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 3364 # Type of FU issued +system.cpu.iew.lsq.thread.0.squashedLoads 277 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 91 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 103 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.001474 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.001474 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 3377 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 0 0.00% # Type of FU issued - IntAlu 2398 71.28% # Type of FU issued + IntAlu 2413 71.45% # Type of FU issued IntMult 1 0.03% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 0 0.00% # Type of FU issued @@ -279,16 +278,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 618 18.37% # Type of FU issued - MemWrite 347 10.32% # Type of FU issued + MemRead 617 18.27% # Type of FU issued + MemWrite 346 10.25% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 34 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.010107 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 37 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.010956 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 1 2.94% # attempts to use FU when none available + IntAlu 1 2.70% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -297,43 +296,43 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 11 32.35% # attempts to use FU when none available - MemWrite 22 64.71% # attempts to use FU when none available + MemRead 14 37.84% # attempts to use FU when none available + MemWrite 22 59.46% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 30107 +system.cpu.iq.ISSUE:issued_per_cycle.samples 3239 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 28628 9508.75% - 1 616 204.60% - 2 335 111.27% - 3 225 74.73% - 4 177 58.79% - 5 80 26.57% - 6 31 10.30% - 7 11 3.65% - 8 4 1.33% + 0 2006 6193.27% + 1 362 1117.63% + 2 258 796.54% + 3 236 728.62% + 4 193 595.86% + 5 111 342.70% + 6 53 163.63% + 7 14 43.22% + 8 6 18.52% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.111735 # Inst issue rate -system.cpu.iq.iqInstsAdded 3838 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 3364 # Number of instructions issued +system.cpu.iq.ISSUE:rate 1.042606 # Inst issue rate +system.cpu.iq.iqInstsAdded 3751 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 3377 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1301 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 35 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1220 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 4 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 682 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 269 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4610.717472 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2315.289963 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1240283 # number of ReadReq miss cycles +system.cpu.iq.iqSquashedOperandsExamined 564 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 271 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 3298.892989 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1993.811808 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 894000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 269 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 622813 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_misses 271 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 540323 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 269 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 271 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -342,32 +341,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 269 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4610.717472 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2315.289963 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 271 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 3298.892989 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1993.811808 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1240283 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 894000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 269 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 271 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 622813 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 540323 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 269 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 271 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 269 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4610.717472 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2315.289963 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 271 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 3298.892989 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1993.811808 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1240283 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 894000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 269 # number of overall misses +system.cpu.l2cache.overall_misses 271 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 622813 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 540323 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 269 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 271 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -380,30 +379,27 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 269 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 271 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 138.742329 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 155.098898 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 30107 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 16613 # Number of cycles rename is blocking +system.cpu.numCycles 3239 # number of cpu cycles simulated system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 14 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 5311 # Number of cycles rename is idle +system.cpu.rename.RENAME:IdleCycles 2100 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 5020 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 4436 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 3192 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 802 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 297 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 23 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1424 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 7061 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:RenameLookups 5014 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 4443 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 3193 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 795 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 261 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 7 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1425 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 76 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 78 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 52 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.timesIdled 207 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout index 25e5ec43b..835f03aa2 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2007 13:12:55 -M5 started Fri Mar 30 13:13:05 2007 +M5 compiled Apr 21 2007 21:50:58 +M5 started Sat Apr 21 21:51:10 2007 M5 executing on zamp.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 746028 because target called exit() +Exiting @ tick 1619000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini index 41c8029a3..3e6a662e6 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -1,51 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[debug] -break_cycles= - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -56,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -65,6 +21,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +phase=0 progress_interval=0 simulate_stalls=false system=system @@ -76,6 +33,7 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=hello +cwd= egid=100 env= euid=100 @@ -101,14 +59,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out index 88d1a9a45..a2be80e9b 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -30,6 +28,7 @@ executable=tests/test-progs/hello/bin/alpha/tru64/hello input=cin output=cout env= +cwd= system=system uid=100 euid=100 @@ -48,61 +47,11 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 +phase=0 defer_registration=false width=1 function_trace=false function_trace_start=0 simulate_stalls=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[debug] -break_cycles= - -[statsreset] -reset_cycle=0 - diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt index 25dace389..16257c237 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 480164 # Simulator instruction rate (inst/s) -host_mem_usage 147928 # Number of bytes of host memory used +host_inst_rate 254768 # Simulator instruction rate (inst/s) +host_mem_usage 147764 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 437596 # Simulator tick rate (ticks/s) +host_tick_rate 121316260 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2578 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 2577 # Number of ticks simulated +sim_seconds 0.000001 # Number of seconds simulated +sim_ticks 1288500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 2578 # number of cpu cycles simulated diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr index b3cdfe967..9f8e7c2e9 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr @@ -1,2 +1,3 @@ warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout index 099a6d041..ddbbe3d32 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout @@ -6,8 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 3 2006 17:10:27 -M5 started Fri Nov 3 17:10:50 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic -Exiting @ tick 2577 because target called exit() +M5 compiled Apr 21 2007 21:50:58 +M5 started Sat Apr 21 21:51:10 2007 +M5 executing on zamp.eecs.umich.edu +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 1288500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index 62041169c..52183bdb1 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -1,51 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[debug] -break_cycles= - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -56,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -65,6 +21,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +phase=0 progress_interval=0 system=system workload=system.cpu.workload @@ -199,6 +156,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=hello +cwd= egid=100 env= euid=100 @@ -224,14 +182,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out index 85dfbaa94..05d289a63 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -30,6 +28,7 @@ executable=tests/test-progs/hello/bin/alpha/tru64/hello input=cin output=cout env= +cwd= system=system uid=100 euid=100 @@ -48,7 +47,8 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 +phase=0 defer_registration=false // width not specified function_trace=false @@ -176,54 +176,3 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[debug] -break_cycles= - -[statsreset] -reset_cycle=0 - diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt index 010da4162..8671d784f 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 153015 # Simulator instruction rate (inst/s) -host_mem_usage 179088 # Number of bytes of host memory used +host_inst_rate 125225 # Simulator instruction rate (inst/s) +host_mem_usage 153176 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 56749783 # Simulator tick rate (ticks/s) +host_tick_rate 116347710 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2578 # Number of instructions simulated -sim_seconds 0.000001 # Number of seconds simulated -sim_ticks 980012 # Number of ticks simulated +sim_seconds 0.000002 # Number of seconds simulated +sim_ticks 2444000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3988.472727 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2988.472727 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 3890.909091 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2890.909091 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 219366 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 214000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 164366 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 159000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3991.518519 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2991.518519 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 3722.222222 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2722.222222 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 267 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 107771 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 100500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.091837 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 27 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 80771 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 73500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.091837 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 27 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3989.475610 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2989.475610 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 3835.365854 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2835.365854 # average overall mshr miss latency system.cpu.dcache.demand_hits 627 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 327137 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 314500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.115656 # miss rate for demand accesses system.cpu.dcache.demand_misses 82 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 245137 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 232500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.115656 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 82 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3989.475610 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2989.475610 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 3835.365854 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2835.365854 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 627 # number of overall hits -system.cpu.dcache.overall_miss_latency 327137 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 314500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.115656 # miss rate for overall accesses system.cpu.dcache.overall_misses 82 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 245137 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 232500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.115656 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 82 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 45.884153 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 51.430454 # Cycle average of tags in use system.cpu.dcache.total_refs 627 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 2579 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3986.705521 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2986.705521 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 3733.128834 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2733.128834 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 2416 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 649833 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 608500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.063203 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 486833 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 445500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.063203 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 2579 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3986.705521 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2986.705521 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 3733.128834 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2733.128834 # average overall mshr miss latency system.cpu.icache.demand_hits 2416 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 649833 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 608500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.063203 # miss rate for demand accesses system.cpu.icache.demand_misses 163 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 486833 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 445500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.063203 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 2579 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3986.705521 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2986.705521 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 3733.128834 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2733.128834 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 2416 # number of overall hits -system.cpu.icache.overall_miss_latency 649833 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 608500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.063203 # miss rate for overall accesses system.cpu.icache.overall_misses 163 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 486833 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 445500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.063203 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 76.367476 # Cycle average of tags in use +system.cpu.icache.tagsinuse 89.421061 # Cycle average of tags in use system.cpu.icache.total_refs 2416 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 245 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2987.632653 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1986.632653 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 731970 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 2767.346939 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1766.346939 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 678000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 245 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 486725 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 432755 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 245 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2987.632653 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1986.632653 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 2767.346939 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1766.346939 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 731970 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 678000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 486725 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 432755 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 245 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2987.632653 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1986.632653 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 2767.346939 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1766.346939 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 731970 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 678000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 245 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 486725 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 432755 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 245 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 122.501625 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 140.951761 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 980012 # number of cpu cycles simulated +system.cpu.numCycles 2444000 # number of cpu cycles simulated system.cpu.num_insts 2578 # Number of instructions executed system.cpu.num_refs 710 # Number of memory references system.cpu.workload.PROG:num_syscalls 4 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr index b3cdfe967..9f8e7c2e9 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr @@ -1,2 +1,3 @@ warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout index cf7a58ef1..d2bc8bfb7 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout @@ -6,8 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 3 2006 17:10:27 -M5 started Fri Nov 3 17:10:51 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing -Exiting @ tick 980012 because target called exit() +M5 compiled Apr 21 2007 21:50:58 +M5 started Sat Apr 21 21:51:11 2007 +M5 executing on zamp.eecs.umich.edu +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 2444000 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index e11ca74dd..5e1ced152 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -23,7 +23,7 @@ activity=0 backComSize=5 choiceCtrBits=2 choicePredictorSize=8192 -clock=1 +clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out index 0d9c5215b..f04ad4ffd 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out @@ -183,7 +183,7 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL [system.cpu] type=DerivO3CPU -clock=1 +clock=500 phase=0 numThreads=1 cpu_id=0 diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt index 684314d31..9ba76e066 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 827 # Number of BTB hits -global.BPredUnit.BTBLookups 3697 # Number of BTB lookups -global.BPredUnit.RASInCorrect 179 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1207 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 2534 # Number of conditional branches predicted -global.BPredUnit.lookups 4455 # Number of BP lookups -global.BPredUnit.usedRAS 640 # Number of times the RAS was used to get a target. -host_inst_rate 15344 # Simulator instruction rate (inst/s) -host_mem_usage 154676 # Number of bytes of host memory used -host_seconds 0.73 # Real time elapsed on the host -host_tick_rate 2857242 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 24 # Number of conflicting loads. -memdepunit.memDep.conflictingLoads 26 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 4 # Number of conflicting stores. -memdepunit.memDep.conflictingStores 5 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2132 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedLoads 2142 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1150 # Number of stores inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1138 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 687 # Number of BTB hits +global.BPredUnit.BTBLookups 3480 # Number of BTB lookups +global.BPredUnit.RASInCorrect 113 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1086 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 2328 # Number of conditional branches predicted +global.BPredUnit.lookups 4062 # Number of BP lookups +global.BPredUnit.usedRAS 562 # Number of times the RAS was used to get a target. +host_inst_rate 49499 # Simulator instruction rate (inst/s) +host_mem_usage 154724 # Number of bytes of host memory used +host_seconds 0.23 # Real time elapsed on the host +host_tick_rate 20219756 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 15 # Number of conflicting loads. +memdepunit.memDep.conflictingLoads 21 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 59 # Number of conflicting stores. +memdepunit.memDep.conflictingStores 54 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 1911 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 1833 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1079 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1058 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 11247 # Number of instructions simulated -sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 2095164 # Number of ticks simulated +sim_seconds 0.000005 # Number of seconds simulated +sim_ticks 4600500 # Number of ticks simulated system.cpu.commit.COM:branches 1724 # Number of branches committed system.cpu.commit.COM:branches_0 862 # Number of branches committed system.cpu.commit.COM:branches_1 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 123 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 179 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 165684 +system.cpu.commit.COM:committed_per_cycle.samples 9158 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 159919 9652.05% - 1 3333 201.17% - 2 1165 70.31% - 3 515 31.08% - 4 270 16.30% - 5 201 12.13% - 6 102 6.16% - 7 56 3.38% - 8 123 7.42% + 0 4902 5352.70% + 1 1725 1883.60% + 2 937 1023.15% + 3 472 515.40% + 4 355 387.64% + 5 234 255.51% + 6 234 255.51% + 7 120 131.03% + 8 179 195.46% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -61,141 +61,141 @@ system.cpu.commit.COM:refs_1 1791 # Nu system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 947 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 843 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 11281 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 9432 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 7371 # The number of squashed insts skipped by commit system.cpu.committedInsts_0 5623 # Number of Instructions Simulated system.cpu.committedInsts_1 5624 # Number of Instructions Simulated system.cpu.committedInsts_total 11247 # Number of Instructions Simulated -system.cpu.cpi_0 372.606082 # CPI: Cycles Per Instruction -system.cpu.cpi_1 372.539829 # CPI: Cycles Per Instruction -system.cpu.cpi_total 186.286476 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 3234 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses_0 3234 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 10308.511696 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency_0 10308.511696 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 10789.975000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 10789.975000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2892 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits_0 2892 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3525511 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency_0 3525511 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.105751 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate_0 0.105751 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 342 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses_0 342 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 142 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits_0 142 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2157995 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency_0 2157995 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.061843 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.061843 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 200 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses_0 200 # number of ReadReq MSHR misses +system.cpu.cpi_0 818.157567 # CPI: Cycles Per Instruction +system.cpu.cpi_1 818.012091 # CPI: Cycles Per Instruction +system.cpu.cpi_total 409.042411 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 2909 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses_0 2909 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 6520.912548 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency_0 6520.912548 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6121.212121 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 6121.212121 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 2646 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits_0 2646 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 1715000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency_0 1715000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.090409 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate_0 0.090409 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 263 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses_0 263 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 65 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits_0 65 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1212000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency_0 1212000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.068065 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.068065 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 198 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses_0 198 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 1624 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses_0 1624 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 8945.050491 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency_0 8945.050491 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 9931.897260 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 9931.897260 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 911 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits_0 911 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 6377821 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency_0 6377821 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.439039 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate_0 0.439039 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 713 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses_0 713 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 567 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits_0 567 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1450057 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency_0 1450057 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 4509.846827 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency_0 4509.846827 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4681.506849 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 4681.506849 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 1167 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits_0 1167 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 2061000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency_0 2061000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.281404 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate_0 0.281404 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 457 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses_0 457 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 311 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits_0 311 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 683500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency_0 683500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.089901 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 146 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses_0 146 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 994 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 10.991329 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.avg_refs 11.084302 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 994 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 4858 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses_0 4858 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 4533 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses_0 4533 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 9387.044550 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency_0 9387.044550 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 5244.444444 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency_0 5244.444444 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency_1 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 10427.895954 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency_0 10427.895954 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 5510.174419 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency_0 5510.174419 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency_1 # average overall mshr miss latency -system.cpu.dcache.demand_hits 3803 # number of demand (read+write) hits -system.cpu.dcache.demand_hits_0 3803 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 3813 # number of demand (read+write) hits +system.cpu.dcache.demand_hits_0 3813 # number of demand (read+write) hits system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 9903332 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency_0 9903332 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 3776000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency_0 3776000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.217168 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate_0 0.217168 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate 0.158835 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate_0 0.158835 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate_1 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1055 # number of demand (read+write) misses -system.cpu.dcache.demand_misses_0 1055 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 720 # number of demand (read+write) misses +system.cpu.dcache.demand_misses_0 720 # number of demand (read+write) misses system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 709 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits_0 709 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits 376 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits_0 376 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3608052 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency_0 3608052 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 1895500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency_0 1895500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.071223 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate_0 0.071223 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate 0.075888 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate_0 0.075888 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate_1 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 346 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses_0 346 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 344 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses_0 344 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 4858 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses_0 4858 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 4533 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses_0 4533 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 9387.044550 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency_0 9387.044550 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 5244.444444 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency_0 5244.444444 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency_1 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 10427.895954 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency_0 10427.895954 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 5510.174419 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency_0 5510.174419 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency_1 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 3803 # number of overall hits -system.cpu.dcache.overall_hits_0 3803 # number of overall hits +system.cpu.dcache.overall_hits 3813 # number of overall hits +system.cpu.dcache.overall_hits_0 3813 # number of overall hits system.cpu.dcache.overall_hits_1 0 # number of overall hits -system.cpu.dcache.overall_miss_latency 9903332 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency_0 9903332 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 3776000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency_0 3776000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.217168 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate_0 0.217168 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate 0.158835 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate_0 0.158835 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate_1 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1055 # number of overall misses -system.cpu.dcache.overall_misses_0 1055 # number of overall misses +system.cpu.dcache.overall_misses 720 # number of overall misses +system.cpu.dcache.overall_misses_0 720 # number of overall misses system.cpu.dcache.overall_misses_1 0 # number of overall misses -system.cpu.dcache.overall_mshr_hits 709 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits_0 709 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits 376 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits_0 376 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3608052 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency_0 3608052 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 1895500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency_0 1895500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.071223 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate_0 0.071223 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate 0.075888 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate_0 0.075888 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate_1 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 346 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses_0 346 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 344 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses_0 344 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -215,153 +215,153 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.replacements_0 0 # number of replacements system.cpu.dcache.replacements_1 0 # number of replacements -system.cpu.dcache.sampled_refs 346 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 344 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 200.098842 # Cycle average of tags in use -system.cpu.dcache.total_refs 3803 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 218.590181 # Cycle average of tags in use +system.cpu.dcache.total_refs 3813 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dcache.writebacks_0 0 # number of writebacks system.cpu.dcache.writebacks_1 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 112235 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 273 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 396 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 24032 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 212833 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 4096 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1856 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 672 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 181 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 4455 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 3542 # Number of cache lines fetched -system.cpu.fetch.Cycles 8000 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 608 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 26459 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 1268 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.026888 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 3542 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1467 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.159692 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 1876 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 260 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 354 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 22033 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 11054 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 3598 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1407 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 337 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 284 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 4062 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 2946 # Number of cache lines fetched +system.cpu.fetch.Cycles 6973 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 278 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 24430 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 1145 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.441378 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 2946 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1249 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.654569 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 165688 +system.cpu.fetch.rateDist.samples 9203 system.cpu.fetch.rateDist.min_value 0 - 0 161234 9731.18% - 1 342 20.64% - 2 283 17.08% - 3 285 17.20% - 4 390 23.54% - 5 369 22.27% - 6 367 22.15% - 7 255 15.39% - 8 2163 130.55% + 0 5177 5625.34% + 1 291 316.20% + 2 234 254.26% + 3 263 285.78% + 4 314 341.19% + 5 294 319.46% + 6 311 337.93% + 7 262 284.69% + 8 2057 2235.14% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 3542 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses_0 3542 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 7880.839306 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency_0 7880.839306 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 7272.060897 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 7272.060897 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 2677 # number of ReadReq hits -system.cpu.icache.ReadReq_hits_0 2677 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 6816926 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency_0 6816926 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.244212 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate_0 0.244212 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 865 # number of ReadReq misses -system.cpu.icache.ReadReq_misses_0 865 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 241 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits_0 241 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 4537766 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency_0 4537766 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.176172 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate_0 0.176172 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 624 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses_0 624 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 2946 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses_0 2946 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 4950.682853 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency_0 4950.682853 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4079.838710 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 4079.838710 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 2287 # number of ReadReq hits +system.cpu.icache.ReadReq_hits_0 2287 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 3262500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency_0 3262500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.223693 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate_0 0.223693 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 659 # number of ReadReq misses +system.cpu.icache.ReadReq_misses_0 659 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 39 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits_0 39 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 2529500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency_0 2529500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.210455 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate_0 0.210455 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 620 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses_0 620 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4.290064 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.688710 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 3542 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses_0 3542 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 2946 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses_0 2946 # number of demand (read+write) accesses system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 7880.839306 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency_0 7880.839306 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency 4950.682853 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency_0 4950.682853 # average overall miss latency system.cpu.icache.demand_avg_miss_latency_1 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 7272.060897 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency_0 7272.060897 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4079.838710 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency_0 4079.838710 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency_1 # average overall mshr miss latency -system.cpu.icache.demand_hits 2677 # number of demand (read+write) hits -system.cpu.icache.demand_hits_0 2677 # number of demand (read+write) hits +system.cpu.icache.demand_hits 2287 # number of demand (read+write) hits +system.cpu.icache.demand_hits_0 2287 # number of demand (read+write) hits system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 6816926 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency_0 6816926 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 3262500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency_0 3262500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.244212 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate_0 0.244212 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate 0.223693 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate_0 0.223693 # miss rate for demand accesses system.cpu.icache.demand_miss_rate_1 # miss rate for demand accesses -system.cpu.icache.demand_misses 865 # number of demand (read+write) misses -system.cpu.icache.demand_misses_0 865 # number of demand (read+write) misses +system.cpu.icache.demand_misses 659 # number of demand (read+write) misses +system.cpu.icache.demand_misses_0 659 # number of demand (read+write) misses system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 241 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits_0 241 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits 39 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits_0 39 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 4537766 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency_0 4537766 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 2529500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency_0 2529500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.176172 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate_0 0.176172 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.210455 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate_0 0.210455 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate_1 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 624 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses_0 624 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 620 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses_0 620 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 3542 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses_0 3542 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 2946 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses_0 2946 # number of overall (read+write) accesses system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 7880.839306 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency_0 7880.839306 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 4950.682853 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency_0 4950.682853 # average overall miss latency system.cpu.icache.overall_avg_miss_latency_1 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 7272.060897 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency_0 7272.060897 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4079.838710 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency_0 4079.838710 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency_1 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 2677 # number of overall hits -system.cpu.icache.overall_hits_0 2677 # number of overall hits +system.cpu.icache.overall_hits 2287 # number of overall hits +system.cpu.icache.overall_hits_0 2287 # number of overall hits system.cpu.icache.overall_hits_1 0 # number of overall hits -system.cpu.icache.overall_miss_latency 6816926 # number of overall miss cycles -system.cpu.icache.overall_miss_latency_0 6816926 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 3262500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency_0 3262500 # number of overall miss cycles system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.244212 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate_0 0.244212 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.223693 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate_0 0.223693 # miss rate for overall accesses system.cpu.icache.overall_miss_rate_1 # miss rate for overall accesses -system.cpu.icache.overall_misses 865 # number of overall misses -system.cpu.icache.overall_misses_0 865 # number of overall misses +system.cpu.icache.overall_misses 659 # number of overall misses +system.cpu.icache.overall_misses_0 659 # number of overall misses system.cpu.icache.overall_misses_1 0 # number of overall misses -system.cpu.icache.overall_mshr_hits 241 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits_0 241 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits 39 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits_0 39 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 4537766 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency_0 4537766 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 2529500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency_0 2529500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.176172 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate_0 0.176172 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.210455 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate_0 0.210455 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate_1 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 624 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses_0 624 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 620 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses_0 620 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -378,107 +378,107 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 6 # number of replacements -system.cpu.icache.replacements_0 6 # number of replacements +system.cpu.icache.replacements 9 # number of replacements +system.cpu.icache.replacements_0 9 # number of replacements system.cpu.icache.replacements_1 0 # number of replacements -system.cpu.icache.sampled_refs 624 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 620 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 289.929418 # Cycle average of tags in use -system.cpu.icache.total_refs 2677 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 315.428279 # Cycle average of tags in use +system.cpu.icache.total_refs 2287 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks_0 0 # number of writebacks system.cpu.icache.writebacks_1 0 # number of writebacks -system.cpu.idleCycles 1929477 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 2535 # Number of branches executed -system.cpu.iew.EXEC:branches_0 1269 # Number of branches executed -system.cpu.iew.EXEC:branches_1 1266 # Number of branches executed -system.cpu.iew.EXEC:nop 84 # number of nop insts executed -system.cpu.iew.EXEC:nop_0 42 # number of nop insts executed -system.cpu.iew.EXEC:nop_1 42 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.100864 # Inst execution rate -system.cpu.iew.EXEC:refs 5422 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_0 2727 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_1 2695 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1997 # Number of stores executed -system.cpu.iew.EXEC:stores_0 1003 # Number of stores executed -system.cpu.iew.EXEC:stores_1 994 # Number of stores executed +system.cpu.idleCycles -1 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 2339 # Number of branches executed +system.cpu.iew.EXEC:branches_0 1175 # Number of branches executed +system.cpu.iew.EXEC:branches_1 1164 # Number of branches executed +system.cpu.iew.EXEC:nop 72 # number of nop insts executed +system.cpu.iew.EXEC:nop_0 36 # number of nop insts executed +system.cpu.iew.EXEC:nop_1 36 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.666196 # Inst execution rate +system.cpu.iew.EXEC:refs 4928 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_0 2490 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_1 2438 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1865 # Number of stores executed +system.cpu.iew.EXEC:stores_0 938 # Number of stores executed +system.cpu.iew.EXEC:stores_1 927 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed -system.cpu.iew.WB:consumers 10258 # num instructions consuming a value -system.cpu.iew.WB:consumers_0 5162 # num instructions consuming a value -system.cpu.iew.WB:consumers_1 5096 # num instructions consuming a value -system.cpu.iew.WB:count 16101 # cumulative count of insts written-back -system.cpu.iew.WB:count_0 8089 # cumulative count of insts written-back -system.cpu.iew.WB:count_1 8012 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.770326 # average fanout of values written-back -system.cpu.iew.WB:fanout_0 0.768888 # average fanout of values written-back -system.cpu.iew.WB:fanout_1 0.771782 # average fanout of values written-back +system.cpu.iew.WB:consumers 10157 # num instructions consuming a value +system.cpu.iew.WB:consumers_0 5143 # num instructions consuming a value +system.cpu.iew.WB:consumers_1 5014 # num instructions consuming a value +system.cpu.iew.WB:count 14949 # cumulative count of insts written-back +system.cpu.iew.WB:count_0 7544 # cumulative count of insts written-back +system.cpu.iew.WB:count_1 7405 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.769912 # average fanout of values written-back +system.cpu.iew.WB:fanout_0 0.768229 # average fanout of values written-back +system.cpu.iew.WB:fanout_1 0.771639 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 7902 # num instructions producing a value -system.cpu.iew.WB:producers_0 3969 # num instructions producing a value -system.cpu.iew.WB:producers_1 3933 # num instructions producing a value -system.cpu.iew.WB:rate 0.097177 # insts written-back per cycle -system.cpu.iew.WB:rate_0 0.048821 # insts written-back per cycle -system.cpu.iew.WB:rate_1 0.048356 # insts written-back per cycle -system.cpu.iew.WB:sent 16249 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_0 8166 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_1 8083 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 1031 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 84087 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 4274 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 41 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 468 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2288 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 20693 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 3425 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_0 1724 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_1 1701 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 741 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 16712 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 57 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 7820 # num instructions producing a value +system.cpu.iew.WB:producers_0 3951 # num instructions producing a value +system.cpu.iew.WB:producers_1 3869 # num instructions producing a value +system.cpu.iew.WB:rate 1.624362 # insts written-back per cycle +system.cpu.iew.WB:rate_0 0.819733 # insts written-back per cycle +system.cpu.iew.WB:rate_1 0.804629 # insts written-back per cycle +system.cpu.iew.WB:sent 15070 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_0 7606 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_1 7464 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 927 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 6 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 3744 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 587 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2137 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 18669 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 3063 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_0 1552 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_1 1511 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1008 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 15334 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1856 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 131 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1407 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 70 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 42 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 60 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 56 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1153 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 338 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 932 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 267 # Number of stores squashed system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.1.forwLoads 65 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.1.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.1.forwLoads 49 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.1.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.1.memOrderViolation 59 # Number of memory ordering violations +system.cpu.iew.lsq.thread.1.memOrderViolation 57 # Number of memory ordering violations system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.1.squashedLoads 1163 # Number of loads squashed -system.cpu.iew.lsq.thread.1.squashedStores 326 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 119 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 791 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 240 # Number of branches that were predicted taken incorrectly -system.cpu.ipc_0 0.002684 # IPC: Instructions Per Cycle -system.cpu.ipc_1 0.002684 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.005368 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8768 # Type of FU issued +system.cpu.iew.lsq.thread.1.squashedLoads 854 # Number of loads squashed +system.cpu.iew.lsq.thread.1.squashedStores 246 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 113 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 753 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 174 # Number of branches that were predicted taken incorrectly +system.cpu.ipc_0 0.001222 # IPC: Instructions Per Cycle +system.cpu.ipc_1 0.001222 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.002445 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 8271 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 2 0.02% # Type of FU issued - IntAlu 5895 67.23% # Type of FU issued + IntAlu 5600 67.71% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -487,15 +487,15 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1838 20.96% # Type of FU issued - MemWrite 1030 11.75% # Type of FU issued + MemRead 1701 20.57% # Type of FU issued + MemWrite 965 11.67% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:FU_type_1 8685 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1 8071 # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.start_dist (null) 2 0.02% # Type of FU issued - IntAlu 5859 67.46% # Type of FU issued + IntAlu 5485 67.96% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -504,15 +504,15 @@ system.cpu.iq.ISSUE:FU_type_1.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1800 20.73% # Type of FU issued - MemWrite 1021 11.76% # Type of FU issued + MemRead 1640 20.32% # Type of FU issued + MemWrite 941 11.66% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.end_dist -system.cpu.iq.ISSUE:FU_type 17453 # Type of FU issued +system.cpu.iq.ISSUE:FU_type 16342 # Type of FU issued system.cpu.iq.ISSUE:FU_type.start_dist (null) 4 0.02% # Type of FU issued - IntAlu 11754 67.35% # Type of FU issued + IntAlu 11085 67.83% # Type of FU issued IntMult 2 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 4 0.02% # Type of FU issued @@ -521,20 +521,20 @@ system.cpu.iq.ISSUE:FU_type.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 3638 20.84% # Type of FU issued - MemWrite 2051 11.75% # Type of FU issued + MemRead 3341 20.44% # Type of FU issued + MemWrite 1906 11.66% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 133 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_0 69 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_1 64 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.007620 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_0 0.003953 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_1 0.003667 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 184 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_0 95 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_1 89 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011259 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_0 0.005813 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_1 0.005446 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 0 0.00% # attempts to use FU when none available + IntAlu 11 5.98% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -543,133 +543,135 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 79 59.40% # attempts to use FU when none available - MemWrite 54 40.60% # attempts to use FU when none available + MemRead 108 58.70% # attempts to use FU when none available + MemWrite 65 35.33% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 165688 +system.cpu.iq.ISSUE:issued_per_cycle.samples 9203 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 156701 9457.59% - 1 4387 264.77% - 2 2473 149.26% - 3 1076 64.94% - 4 569 34.34% - 5 325 19.62% - 6 120 7.24% - 7 25 1.51% - 8 12 0.72% + 0 3452 3750.95% + 1 1399 1520.16% + 2 1479 1607.08% + 3 1070 1162.66% + 4 845 918.18% + 5 528 573.73% + 6 290 315.11% + 7 105 114.09% + 8 35 38.03% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.105337 # Inst issue rate -system.cpu.iq.iqInstsAdded 20568 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 17453 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 41 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 8303 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 214 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 4870 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 968 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses_0 968 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 7151.675620 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency_0 7151.675620 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 3855.918388 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 3855.918388 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 6922822 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency_0 6922822 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate_0 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 968 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses_0 968 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 3732529 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency_0 3732529 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate_0 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 968 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses_0 968 # number of ReadReq MSHR misses +system.cpu.iq.ISSUE:rate 1.775725 # Inst issue rate +system.cpu.iq.iqInstsAdded 18557 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 16342 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 40 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 6288 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 37 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 3616 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 960 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses_0 960 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4143.899896 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency_0 4143.899896 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2323.820647 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 2323.820647 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits_0 1 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 3974000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency_0 3974000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.998958 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate_0 0.998958 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 959 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses_0 959 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 2228544 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency_0 2228544 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.998958 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.998958 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 959 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses_0 959 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.001043 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 968 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses_0 968 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 960 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses_0 960 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 7151.675620 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency_0 7151.675620 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 4143.899896 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency_0 4143.899896 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency_1 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 3855.918388 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency_0 3855.918388 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2323.820647 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency_0 2323.820647 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency_1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits_0 0 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits_0 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 6922822 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency_0 6922822 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 3974000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency_0 3974000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate_0 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate 0.998958 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate_0 0.998958 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate_1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 968 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses_0 968 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 959 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses_0 959 # number of demand (read+write) misses system.cpu.l2cache.demand_misses_1 0 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 3732529 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency_0 3732529 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2228544 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency_0 2228544 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate_0 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.998958 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate_0 0.998958 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate_1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 968 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses_0 968 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 959 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses_0 959 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 968 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses_0 968 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 960 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses_0 960 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 7151.675620 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency_0 7151.675620 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 4143.899896 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency_0 4143.899896 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency_1 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 3855.918388 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency_0 3855.918388 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2323.820647 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency_0 2323.820647 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency_1 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_hits_0 0 # number of overall hits +system.cpu.l2cache.overall_hits 1 # number of overall hits +system.cpu.l2cache.overall_hits_0 1 # number of overall hits system.cpu.l2cache.overall_hits_1 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 6922822 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency_0 6922822 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 3974000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency_0 3974000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate_0 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate 0.998958 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate_0 0.998958 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate_1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 968 # number of overall misses -system.cpu.l2cache.overall_misses_0 968 # number of overall misses +system.cpu.l2cache.overall_misses 959 # number of overall misses +system.cpu.l2cache.overall_misses_0 959 # number of overall misses system.cpu.l2cache.overall_misses_1 0 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 3732529 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency_0 3732529 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2228544 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency_0 2228544 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate_0 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.998958 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate_0 0.998958 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate_1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 968 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses_0 968 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 959 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses_0 959 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -689,35 +691,33 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements_0 0 # number of replacements system.cpu.l2cache.replacements_1 0 # number of replacements -system.cpu.l2cache.sampled_refs 968 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 959 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 491.189820 # Cycle average of tags in use -system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 534.228654 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks_0 0 # number of writebacks system.cpu.l2cache.writebacks_1 0 # number of writebacks -system.cpu.numCycles 165688 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 87802 # Number of cycles rename is blocking +system.cpu.numCycles 9203 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 514 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 8102 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 24 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 213369 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2127 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 18 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 28570 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 22635 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 17117 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 3694 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1856 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 2143 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 9015 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 22337 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 51 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 4330 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 37 # count of temporary serializing insts renamed -system.cpu.timesIdled 688 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IdleCycles 11467 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 762 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 26335 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 20742 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 15622 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 3447 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1407 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 876 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 7520 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 508 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 2622 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 38 # count of temporary serializing insts renamed +system.cpu.timesIdled 1 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr index 54505c240..d0a887867 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr @@ -1,5 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7001 -0: system.remote_gdb.listener: listening for remote gdb on port 7002 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: Increasing stack size by one page. diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout index b4ae56cae..ea08dc448 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout @@ -7,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2007 13:12:55 -M5 started Fri Mar 30 13:13:07 2007 +M5 compiled Apr 21 2007 21:50:58 +M5 started Sat Apr 21 21:51:11 2007 M5 executing on zamp.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 2095164 because target called exit() +Exiting @ tick 4600500 because target called exit() diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini index 71c721b07..0c1dbb0ba 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini @@ -1,51 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[debug] -break_cycles= - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -56,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -65,6 +21,7 @@ max_insts_all_threads=0 max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 +phase=0 progress_interval=0 simulate_stalls=false system=system @@ -93,14 +50,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out index 95a0614c9..5e988f3f9 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -40,61 +38,11 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 +phase=0 defer_registration=false width=1 function_trace=false function_trace_start=0 simulate_stalls=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[debug] -break_cycles= - -[statsreset] -reset_cycle=0 - diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt index 50d3a76c7..bc0a96087 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1281059 # Simulator instruction rate (inst/s) -host_mem_usage 147756 # Number of bytes of host memory used -host_seconds 0.39 # Real time elapsed on the host -host_tick_rate 1279755 # Simulator tick rate (ticks/s) +host_inst_rate 689098 # Simulator instruction rate (inst/s) +host_mem_usage 147724 # Number of bytes of host memory used +host_seconds 0.73 # Real time elapsed on the host +host_tick_rate 344128671 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 499999 # Number of ticks simulated +sim_seconds 0.000250 # Number of seconds simulated +sim_ticks 249999500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 500000 # number of cpu cycles simulated diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout index 18a78c936..47ee09274 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout @@ -7,8 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 3 2006 17:10:27 -M5 started Fri Nov 3 17:10:57 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic -Exiting @ tick 499999 because a thread reached the max instruction count +M5 compiled Apr 21 2007 21:50:58 +M5 started Sat Apr 21 21:51:12 2007 +M5 executing on zamp.eecs.umich.edu +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 249999500 because a thread reached the max instruction count diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini index 2be814794..eef4c0a1a 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini @@ -1,51 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[debug] -break_cycles= - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -56,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -65,6 +21,7 @@ max_insts_all_threads=0 max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 +phase=0 progress_interval=0 system=system workload=system.cpu.workload @@ -216,14 +173,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out index bd0dbfad0..e897b733f 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -40,7 +38,8 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 +phase=0 defer_registration=false // width not specified function_trace=false @@ -168,54 +167,3 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[debug] -break_cycles= - -[statsreset] -reset_cycle=0 - diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt index d8d06877e..a6caa5891 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 542626 # Simulator instruction rate (inst/s) -host_mem_usage 178896 # Number of bytes of host memory used -host_seconds 0.92 # Real time elapsed on the host -host_tick_rate 4319791 # Simulator tick rate (ticks/s) +host_inst_rate 518674 # Simulator instruction rate (inst/s) +host_mem_usage 153108 # Number of bytes of host memory used +host_seconds 0.96 # Real time elapsed on the host +host_tick_rate 355827019 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated -sim_seconds 0.000004 # Number of seconds simulated -sim_ticks 3982316 # Number of ticks simulated +sim_seconds 0.000343 # Number of seconds simulated +sim_ticks 343161000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3670.641270 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2670.641270 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 3793.650794 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2793.650794 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 124120 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1156252 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 1195000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002531 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 315 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 841252 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 880000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002531 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 315 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3907.374101 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2907.374101 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 3600.719424 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2600.719424 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 56201 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 543125 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 500500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 139 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 404125 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 361500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 180775 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3743.121145 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2743.121145 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 3734.581498 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2734.581498 # average overall mshr miss latency system.cpu.dcache.demand_hits 180321 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1699377 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 1695500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002511 # miss rate for demand accesses system.cpu.dcache.demand_misses 454 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1245377 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 1241500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002511 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 454 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3743.121145 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2743.121145 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 3734.581498 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2734.581498 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 180321 # number of overall hits -system.cpu.dcache.overall_miss_latency 1699377 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 1695500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002511 # miss rate for overall accesses system.cpu.dcache.overall_misses 454 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1245377 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 1241500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002511 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 454 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 227.376906 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 291.533202 # Cycle average of tags in use system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 500000 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3977.722084 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2977.722084 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 3739.454094 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2739.454094 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 499597 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1603022 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 1507000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000806 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 403 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 1200022 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 1104000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000806 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 403 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 500000 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3977.722084 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2977.722084 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 3739.454094 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2739.454094 # average overall mshr miss latency system.cpu.icache.demand_hits 499597 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1603022 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 1507000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000806 # miss rate for demand accesses system.cpu.icache.demand_misses 403 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1200022 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 1104000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000806 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 403 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 500000 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3977.722084 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2977.722084 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 3739.454094 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2739.454094 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 499597 # number of overall hits -system.cpu.icache.overall_miss_latency 1603022 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 1507000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses system.cpu.icache.overall_misses 403 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1200022 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 1104000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000806 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 403 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 221.721362 # Cycle average of tags in use +system.cpu.icache.tagsinuse 268.106513 # Cycle average of tags in use system.cpu.icache.total_refs 499597 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 857 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2853.441074 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1852.441074 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 2445399 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 2736.872812 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1735.872812 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 2345500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 857 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1587542 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1487643 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 857 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 857 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2853.441074 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1852.441074 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 2736.872812 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1735.872812 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2445399 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 2345500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 857 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1587542 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 1487643 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 857 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2853.441074 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1852.441074 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 2736.872812 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1735.872812 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2445399 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 2345500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 857 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1587542 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 1487643 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 857 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 857 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 449.313470 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 559.642213 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 3982316 # number of cpu cycles simulated +system.cpu.numCycles 343161000 # number of cpu cycles simulated system.cpu.num_insts 500000 # Number of instructions executed system.cpu.num_refs 182203 # Number of memory references system.cpu.workload.PROG:num_syscalls 18 # Number of system calls diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout index 787ea041d..8126fb0fb 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout @@ -7,8 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 3 2006 17:10:27 -M5 started Fri Nov 3 17:10:58 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing -Exiting @ tick 3982316 because a thread reached the max instruction count +M5 compiled Apr 21 2007 21:50:58 +M5 started Sat Apr 21 21:51:14 2007 +M5 executing on zamp.eecs.umich.edu +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 343161000 because a thread reached the max instruction count diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini index 05eb91461..363cb64d4 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini @@ -1,48 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -610,12 +569,3 @@ responder_set=false width=16 port=system.l2c.cpu_side system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out index b8ae04bc0..b3f4ec871 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -524,51 +521,3 @@ clock=2 width=16 responder_set=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 - diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt index a65b235b0..285ab3702 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt @@ -1,8 +1,8 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 435124 # Number of bytes of host memory used -host_seconds 28.46 # Real time elapsed on the host -host_tick_rate 202211 # Simulator tick rate (ticks/s) +host_mem_usage 303680 # Number of bytes of host memory used +host_seconds 32.50 # Real time elapsed on the host +host_tick_rate 177110 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_seconds 0.000006 # Number of seconds simulated sim_ticks 5755736 # Number of ticks simulated @@ -887,15 +887,15 @@ system.l2c.ReadReq_mshr_misses 66414 # nu system.l2c.ReadReq_mshr_uncacheable 78703 # number of ReadReq MSHR uncacheable system.l2c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency system.l2c.ReadResp_mshr_uncacheable_latency 420484 # number of ReadResp MSHR uncacheable cycles -system.l2c.WriteReqNoAck|Writeback_accesses 86614 # number of WriteReqNoAck|Writeback accesses(hits+misses) -system.l2c.WriteReqNoAck|Writeback_hits 18299 # number of WriteReqNoAck|Writeback hits -system.l2c.WriteReqNoAck|Writeback_miss_rate 0.788729 # miss rate for WriteReqNoAck|Writeback accesses -system.l2c.WriteReqNoAck|Writeback_misses 68315 # number of WriteReqNoAck|Writeback misses -system.l2c.WriteReqNoAck|Writeback_mshr_miss_rate 0.788729 # mshr miss rate for WriteReqNoAck|Writeback accesses -system.l2c.WriteReqNoAck|Writeback_mshr_misses 68315 # number of WriteReqNoAck|Writeback MSHR misses system.l2c.WriteReq_mshr_uncacheable 42661 # number of WriteReq MSHR uncacheable system.l2c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency system.l2c.WriteResp_mshr_uncacheable_latency 298282 # number of WriteResp MSHR uncacheable cycles +system.l2c.Writeback_accesses 86614 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 18299 # number of Writeback hits +system.l2c.Writeback_miss_rate 0.788729 # miss rate for Writeback accesses +system.l2c.Writeback_misses 68315 # number of Writeback misses +system.l2c.Writeback_mshr_miss_rate 0.788729 # mshr miss rate for Writeback accesses +system.l2c.Writeback_mshr_misses 68315 # number of Writeback MSHR misses system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.l2c.avg_refs 1.277186 # Average number of references to valid blocks. diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout index 3d3289d71..ea4812a6d 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 6 2007 20:30:01 -M5 started Tue Feb 6 21:04:07 2007 -M5 executing on vm1 +M5 compiled Apr 21 2007 21:50:58 +M5 started Sat Apr 21 21:51:15 2007 +M5 executing on zamp.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest warning: overwriting port funcmem.functional value cpu1.functional with cpu2.functional warning: overwriting port funcmem.functional value cpu2.functional with cpu3.functional @@ -15,4 +15,5 @@ warning: overwriting port funcmem.functional value cpu3.functional with cpu4.fun warning: overwriting port funcmem.functional value cpu4.functional with cpu5.functional warning: overwriting port funcmem.functional value cpu5.functional with cpu6.functional warning: overwriting port funcmem.functional value cpu6.functional with cpu7.functional +Global frequency set at 1000000000000 ticks per second Exiting @ tick 5755736 because Maximum number of loads reached! From 8c7a6e1654bc682677b0e48764183198c2c7e868 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Sun, 22 Apr 2007 15:11:54 -0400 Subject: [PATCH 18/68] Use proper cycles for IPC and CPI equations. src/cpu/o3/cpu.cc: Use proper cycles for these equations. --HG-- extra : convert_revision : cd49410eed978c789d788e80462abed6cb89fbae --- src/cpu/o3/cpu.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 2e6a43f9c..a775b66d5 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -384,25 +384,25 @@ FullO3CPU::fullCPURegStats() .name(name() + ".cpi") .desc("CPI: Cycles Per Instruction") .precision(6); - cpi = simTicks / committedInsts; + cpi = numCycles / committedInsts; totalCpi .name(name() + ".cpi_total") .desc("CPI: Total CPI of All Threads") .precision(6); - totalCpi = simTicks / totalCommittedInsts; + totalCpi = numCycles / totalCommittedInsts; ipc .name(name() + ".ipc") .desc("IPC: Instructions Per Cycle") .precision(6); - ipc = committedInsts / simTicks; + ipc = committedInsts / numCycles; totalIpc .name(name() + ".ipc_total") .desc("IPC: Total IPC of All Threads") .precision(6); - totalIpc = totalCommittedInsts / simTicks; + totalIpc = totalCommittedInsts / numCycles; } From 67a37e83f3b69f832ae05c4612979c2c31bb4d3e Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Sun, 22 Apr 2007 15:29:59 -0400 Subject: [PATCH 19/68] Updated refs for calculating IPC/CPI. --HG-- extra : convert_revision : ee8dfee5eaa345dcb08f5d06d054655b1f6f79da --- .../ref/alpha/linux/o3-timing/m5stats.txt | 14 +++++++------- .../ref/alpha/tru64/o3-timing/m5stats.txt | 16 ++++++++-------- .../ref/alpha/linux/o3-timing/m5stats.txt | 16 ++++++++-------- 3 files changed, 23 insertions(+), 23 deletions(-) diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index 0a0a4f78e..86aa4129f 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 415 # Nu global.BPredUnit.condPredicted 1270 # Number of conditional branches predicted global.BPredUnit.lookups 2195 # Number of BP lookups global.BPredUnit.usedRAS 306 # Number of times the RAS was used to get a target. -host_inst_rate 5017 # Simulator instruction rate (inst/s) +host_inst_rate 22780 # Simulator instruction rate (inst/s) host_mem_usage 154084 # Number of bytes of host memory used -host_seconds 1.12 # Real time elapsed on the host -host_tick_rate 3160160 # Simulator tick rate (ticks/s) +host_seconds 0.25 # Real time elapsed on the host +host_tick_rate 14337041 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 31 # Number of conflicting loads. memdepunit.memDep.conflictingStores 138 # Number of conflicting stores. memdepunit.memDep.insertedLoads 2061 # Number of loads inserted to the mem dependence unit. @@ -49,8 +49,8 @@ system.cpu.commit.commitNonSpecStalls 17 # Th system.cpu.commit.commitSquashedInsts 4458 # The number of squashed insts skipped by commit system.cpu.committedInsts 5623 # Number of Instructions Simulated system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 630.179619 # CPI: Cycles Per Instruction -system.cpu.cpi_total 630.179619 # CPI: Total CPI of All Threads +system.cpu.cpi 1.260537 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.260537 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 1516 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 4941.176471 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4361.386139 # average ReadReq mshr miss latency @@ -264,8 +264,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 418 # system.cpu.iew.memOrderViolationEvents 68 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 284 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 109 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.001587 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.001587 # IPC: Total IPC of All Threads +system.cpu.ipc 0.793313 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.793313 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0 8531 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 2 0.02% # Type of FU issued diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt index cc70d3787..d3074bcf9 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 220 # Nu global.BPredUnit.condPredicted 427 # Number of conditional branches predicted global.BPredUnit.lookups 860 # Number of BP lookups global.BPredUnit.usedRAS 174 # Number of times the RAS was used to get a target. -host_inst_rate 32334 # Simulator instruction rate (inst/s) -host_mem_usage 153596 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host -host_tick_rate 21839716 # Simulator tick rate (ticks/s) +host_inst_rate 31252 # Simulator instruction rate (inst/s) +host_mem_usage 153592 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host +host_tick_rate 21107113 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 9 # Number of conflicting loads. memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. memdepunit.memDep.insertedLoads 692 # Number of loads inserted to the mem dependence unit. @@ -49,8 +49,8 @@ system.cpu.commit.commitNonSpecStalls 4 # Th system.cpu.commit.commitSquashedInsts 1420 # The number of squashed insts skipped by commit system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 678.257227 # CPI: Cycles Per Instruction -system.cpu.cpi_total 678.257227 # CPI: Total CPI of All Threads +system.cpu.cpi 1.356933 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.356933 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 537 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 4625 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3811.475410 # average ReadReq mshr miss latency @@ -264,8 +264,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 91 # system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 103 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.001474 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.001474 # IPC: Total IPC of All Threads +system.cpu.ipc 0.736956 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.736956 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0 3377 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 0 0.00% # Type of FU issued diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt index 9ba76e066..b44194dff 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 1086 # Nu global.BPredUnit.condPredicted 2328 # Number of conditional branches predicted global.BPredUnit.lookups 4062 # Number of BP lookups global.BPredUnit.usedRAS 562 # Number of times the RAS was used to get a target. -host_inst_rate 49499 # Simulator instruction rate (inst/s) +host_inst_rate 49679 # Simulator instruction rate (inst/s) host_mem_usage 154724 # Number of bytes of host memory used host_seconds 0.23 # Real time elapsed on the host -host_tick_rate 20219756 # Simulator tick rate (ticks/s) +host_tick_rate 20293608 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 15 # Number of conflicting loads. memdepunit.memDep.conflictingLoads 21 # Number of conflicting loads. memdepunit.memDep.conflictingStores 59 # Number of conflicting stores. @@ -68,9 +68,9 @@ system.cpu.commit.commitSquashedInsts 7371 # Th system.cpu.committedInsts_0 5623 # Number of Instructions Simulated system.cpu.committedInsts_1 5624 # Number of Instructions Simulated system.cpu.committedInsts_total 11247 # Number of Instructions Simulated -system.cpu.cpi_0 818.157567 # CPI: Cycles Per Instruction -system.cpu.cpi_1 818.012091 # CPI: Cycles Per Instruction -system.cpu.cpi_total 409.042411 # CPI: Total CPI of All Threads +system.cpu.cpi_0 1.636671 # CPI: Cycles Per Instruction +system.cpu.cpi_1 1.636380 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.818263 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 2909 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses_0 2909 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 6520.912548 # average ReadReq miss latency @@ -472,9 +472,9 @@ system.cpu.iew.lsq.thread.1.squashedStores 246 # system.cpu.iew.memOrderViolationEvents 113 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 753 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 174 # Number of branches that were predicted taken incorrectly -system.cpu.ipc_0 0.001222 # IPC: Instructions Per Cycle -system.cpu.ipc_1 0.001222 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.002445 # IPC: Total IPC of All Threads +system.cpu.ipc_0 0.610996 # IPC: Instructions Per Cycle +system.cpu.ipc_1 0.611105 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.222101 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0 8271 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 2 0.02% # Type of FU issued From 46f6fa8b45a1a1a572085f33c5173b189f76e407 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Mon, 23 Apr 2007 12:13:19 -0400 Subject: [PATCH 20/68] Update refs for CPU clock changes and O3 CPI/IPC calculation updates. tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini: tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out: tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt: tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout: tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini: tests/quick/00.hello/ref/mips/linux/simple-timing/config.out: tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt: tests/quick/00.hello/ref/mips/linux/simple-timing/stdout: tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini: tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out: tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt: tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout: tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini: tests/quick/00.hello/ref/sparc/linux/simple-timing/config.out: tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt: tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout: tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini: tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.out: tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt: tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr: tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout: tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini: tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out: tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt: tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr: tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout: tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini: tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out: tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt: tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr: tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout: Update refs. --HG-- extra : convert_revision : 34a0d18f213386700e2acdd1eb9ebc5fa6daa7f5 --- .../ref/mips/linux/simple-atomic/config.ini | 61 +-- .../ref/mips/linux/simple-atomic/config.out | 62 +-- .../ref/mips/linux/simple-atomic/m5stats.txt | 12 +- .../ref/mips/linux/simple-atomic/stdout | 11 +- .../ref/mips/linux/simple-timing/config.ini | 65 +-- .../ref/mips/linux/simple-timing/config.out | 148 ++---- .../ref/mips/linux/simple-timing/m5stats.txt | 106 ++-- .../ref/mips/linux/simple-timing/stdout | 11 +- .../ref/sparc/linux/simple-atomic/config.ini | 61 +-- .../ref/sparc/linux/simple-atomic/config.out | 62 +-- .../ref/sparc/linux/simple-atomic/m5stats.txt | 12 +- .../ref/sparc/linux/simple-atomic/stdout | 11 +- .../ref/sparc/linux/simple-timing/config.ini | 62 +-- .../ref/sparc/linux/simple-timing/config.out | 145 ++---- .../ref/sparc/linux/simple-timing/m5stats.txt | 98 ++-- .../ref/sparc/linux/simple-timing/stdout | 11 +- .../ref/sparc/linux/o3-timing/config.ini | 2 +- .../ref/sparc/linux/o3-timing/config.out | 2 +- .../ref/sparc/linux/o3-timing/m5stats.txt | 479 +++++++++--------- .../ref/sparc/linux/o3-timing/stderr | 1 - .../ref/sparc/linux/o3-timing/stdout | 8 +- .../ref/sparc/linux/simple-atomic/config.ini | 2 +- .../ref/sparc/linux/simple-atomic/config.out | 2 +- .../ref/sparc/linux/simple-atomic/m5stats.txt | 12 +- .../ref/sparc/linux/simple-atomic/stderr | 1 - .../ref/sparc/linux/simple-atomic/stdout | 10 +- .../ref/sparc/linux/simple-timing/config.ini | 2 +- .../ref/sparc/linux/simple-timing/config.out | 2 +- .../ref/sparc/linux/simple-timing/m5stats.txt | 100 ++-- .../ref/sparc/linux/simple-timing/stderr | 1 - .../ref/sparc/linux/simple-timing/stdout | 8 +- 31 files changed, 584 insertions(+), 986 deletions(-) diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini index 59cadaa12..80ef56747 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -1,50 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[debug] -break_cycles= - -[exetrace] -intel_format=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -55,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -64,7 +21,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.physmem +phase=0 progress_interval=0 simulate_stalls=false system=system @@ -76,6 +33,7 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=hello +cwd= egid=100 env= euid=100 @@ -92,6 +50,7 @@ uid=100 type=Bus bus_id=0 clock=1000 +responder_set=false width=64 port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port @@ -100,14 +59,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out index 064f467da..9f8b84468 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -21,6 +19,7 @@ type=Bus bus_id=0 clock=1000 width=64 +responder_set=false [system.cpu.workload] type=LiveProcess @@ -29,6 +28,7 @@ executable=tests/test-progs/hello/bin/mips/linux/hello input=cin output=cout env= +cwd= system=system uid=100 euid=100 @@ -44,64 +44,14 @@ max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 progress_interval=0 -mem=system.physmem system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 +phase=0 defer_registration=false width=1 function_trace=false function_trace_start=0 simulate_stalls=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -trace_system=client - -[debug] -break_cycles= - -[statsreset] -reset_cycle=0 - diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt index 3b2a2730b..daf99515d 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 52255 # Simulator instruction rate (inst/s) -host_mem_usage 148024 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host -host_tick_rate 52038 # Simulator tick rate (ticks/s) +host_inst_rate 7127 # Simulator instruction rate (inst/s) +host_mem_usage 148488 # Number of bytes of host memory used +host_seconds 0.79 # Real time elapsed on the host +host_tick_rate 3561193 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5657 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 5656 # Number of ticks simulated +sim_seconds 0.000003 # Number of seconds simulated +sim_ticks 2828000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 5657 # number of cpu cycles simulated diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout index 600b178b3..b975f8f18 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout @@ -6,8 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 9 2006 19:28:25 -M5 started Mon Oct 9 19:28:56 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/MIPS_SE/m5.debug -d build/MIPS_SE/tests/debug/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic -Exiting @ tick 5656 because target called exit() +M5 compiled Apr 22 2007 20:47:32 +M5 started Sun Apr 22 20:47:35 2007 +M5 executing on zamp.eecs.umich.edu +command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 2828000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index 8e1bb0388..29fcae5de 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -1,50 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[debug] -break_cycles= - -[exetrace] -intel_format=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -55,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -64,7 +21,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.cpu.dcache +phase=0 progress_interval=0 system=system workload=system.cpu.workload @@ -78,7 +35,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -118,7 +74,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -158,7 +113,6 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 hit_latency=1 latency=1 @@ -195,12 +149,14 @@ mem_side=system.membus.port[1] type=Bus bus_id=0 clock=1000 +responder_set=false width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload] type=LiveProcess cmd=hello +cwd= egid=100 env= euid=100 @@ -217,6 +173,7 @@ uid=100 type=Bus bus_id=0 clock=1000 +responder_set=false width=64 port=system.physmem.port system.cpu.l2cache.mem_side @@ -225,14 +182,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out index d683d2355..d5d160f1e 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -21,10 +19,52 @@ type=Bus bus_id=0 clock=1000 width=64 +responder_set=false -[system.cpu.dcache] +[system.cpu.workload] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/mips/linux/hello +input=cin +output=cout +env= +cwd= +system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 + +[system.cpu] +type=TimingSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=500 +phase=0 +defer_registration=false +// width not specified +function_trace=false +function_trace_start=0 +// simulate_stalls not specified + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.icache] type=BaseCache -size=262144 +size=131072 assoc=2 block_size=64 latency=1 @@ -32,7 +72,6 @@ mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false protocol=null trace_addr=0 hash_delay=1 @@ -61,48 +100,9 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[system.cpu.workload] -type=LiveProcess -cmd=hello -executable=tests/test-progs/hello/bin/mips/linux/hello -input=cin -output=cout -env= -system=system -uid=100 -euid=100 -gid=100 -egid=100 -pid=100 -ppid=99 - -[system.cpu] -type=TimingSimpleCPU -max_insts_any_thread=0 -max_insts_all_threads=0 -max_loads_any_thread=0 -max_loads_all_threads=0 -progress_interval=0 -mem=system.cpu.dcache -system=system -cpu_id=0 -workload=system.cpu.workload -clock=1 -defer_registration=false -// width not specified -function_trace=false -function_trace_start=0 -// simulate_stalls not specified - -[system.cpu.toL2Bus] -type=Bus -bus_id=0 -clock=1000 -width=64 - -[system.cpu.icache] +[system.cpu.dcache] type=BaseCache -size=131072 +size=262144 assoc=2 block_size=64 latency=1 @@ -110,7 +110,6 @@ mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false protocol=null trace_addr=0 hash_delay=1 @@ -149,7 +148,6 @@ mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false protocol=null trace_addr=0 hash_delay=1 @@ -178,53 +176,3 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -trace_system=client - -[debug] -break_cycles= - -[statsreset] -reset_cycle=0 - diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt index ae23f7eec..71b0896dd 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 57798 # Simulator instruction rate (inst/s) -host_mem_usage 179040 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host -host_tick_rate 17679602 # Simulator tick rate (ticks/s) +host_inst_rate 224031 # Simulator instruction rate (inst/s) +host_mem_usage 153864 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 205051803 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5657 # Number of instructions simulated -sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 1738011 # Number of ticks simulated +sim_seconds 0.000005 # Number of seconds simulated +sim_ticks 5264500 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3987.109756 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2987.109756 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 3762.195122 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2762.195122 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 1048 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 326943 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 308500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.072566 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 244943 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 226500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.072566 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3968.740000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2968.740000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 3690 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2690 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 198437 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 184500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.054113 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 50 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 148437 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 134500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.054113 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 50 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2054 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3980.151515 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2980.151515 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 3734.848485 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2734.848485 # average overall mshr miss latency system.cpu.dcache.demand_hits 1922 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 525380 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 493000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.064265 # miss rate for demand accesses system.cpu.dcache.demand_misses 132 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 393380 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 361000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.064265 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 132 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 2054 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3980.151515 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2980.151515 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_miss_latency 3734.848485 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2734.848485 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1922 # number of overall hits -system.cpu.dcache.overall_miss_latency 525380 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 493000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.064265 # miss rate for overall accesses system.cpu.dcache.overall_misses 132 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 393380 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 361000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.064265 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 132 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 82.396200 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 86.050916 # Cycle average of tags in use system.cpu.dcache.total_refs 1922 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3978.069307 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2978.069307 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 3740.924092 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2740.924092 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 5355 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1205355 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 1133500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.053552 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 902355 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 830500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 5658 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3978.069307 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2978.069307 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 3740.924092 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2740.924092 # average overall mshr miss latency system.cpu.icache.demand_hits 5355 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1205355 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 1133500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.053552 # miss rate for demand accesses system.cpu.icache.demand_misses 303 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 902355 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 830500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.053552 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3978.069307 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2978.069307 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_miss_latency 3740.924092 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2740.924092 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 5355 # number of overall hits -system.cpu.icache.overall_miss_latency 1205355 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 1133500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses system.cpu.icache.overall_misses 303 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 902355 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 830500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.053552 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 13 # number of replacements system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 133.062649 # Cycle average of tags in use +system.cpu.icache.tagsinuse 137.160443 # Cycle average of tags in use system.cpu.icache.total_refs 5355 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 435 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2983.237875 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1982.237875 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 2743.648961 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1742.648961 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1291742 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 1188000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.995402 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 433 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 858309 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 754567 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995402 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 433 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -162,29 +162,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2983.237875 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1982.237875 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 2743.648961 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1742.648961 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1291742 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 1188000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.995402 # miss rate for demand accesses system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 858309 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 754567 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.995402 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 433 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2983.237875 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1982.237875 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_miss_latency 2743.648961 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1742.648961 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1291742 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 1188000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.995402 # miss rate for overall accesses system.cpu.l2cache.overall_misses 433 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 858309 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 754567 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.995402 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 433 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -201,12 +201,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 433 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 216.976175 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 224.535228 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1738011 # number of cpu cycles simulated +system.cpu.numCycles 5264500 # number of cpu cycles simulated system.cpu.num_insts 5657 # Number of instructions executed system.cpu.num_refs 2055 # Number of memory references system.cpu.workload.PROG:num_syscalls 13 # Number of system calls diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout index 8722547ad..1cc143ec3 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout @@ -6,8 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 13 2006 18:43:33 -M5 started Fri Oct 13 18:44:16 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/MIPS_SE/m5.debug -d build/MIPS_SE/tests/debug/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing -Exiting @ tick 1738011 because target called exit() +M5 compiled Apr 22 2007 20:47:32 +M5 started Sun Apr 22 20:47:36 2007 +M5 executing on zamp.eecs.umich.edu +command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 5264500 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini index 9da46d74f..5d4dafee7 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -1,50 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[debug] -break_cycles= - -[exetrace] -intel_format=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -55,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -64,7 +21,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.physmem +phase=0 progress_interval=0 simulate_stalls=false system=system @@ -76,6 +33,7 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=hello +cwd= egid=100 env= euid=100 @@ -92,6 +50,7 @@ uid=100 type=Bus bus_id=0 clock=1000 +responder_set=false width=64 port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port @@ -100,14 +59,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out index fc125a624..1a521c678 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -21,6 +19,7 @@ type=Bus bus_id=0 clock=1000 width=64 +responder_set=false [system.cpu.workload] type=LiveProcess @@ -29,6 +28,7 @@ executable=tests/test-progs/hello/bin/sparc/linux/hello input=cin output=cout env= +cwd= system=system uid=100 euid=100 @@ -44,64 +44,14 @@ max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 progress_interval=0 -mem=system.physmem system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 +phase=0 defer_registration=false width=1 function_trace=false function_trace_start=0 simulate_stalls=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -trace_system=client - -[debug] -break_cycles= - -[statsreset] -reset_cycle=0 - diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt index 5c79f4d62..bbc3d0e4f 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 58121 # Simulator instruction rate (inst/s) -host_mem_usage 148396 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -host_tick_rate 57840 # Simulator tick rate (ticks/s) +host_inst_rate 16183 # Simulator instruction rate (inst/s) +host_mem_usage 149132 # Number of bytes of host memory used +host_seconds 0.30 # Real time elapsed on the host +host_tick_rate 8071210 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4863 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 4862 # Number of ticks simulated +sim_seconds 0.000002 # Number of seconds simulated +sim_ticks 2431000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 4863 # number of cpu cycles simulated diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout index 1d76c6089..84e837005 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout @@ -5,8 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 27 2006 02:07:29 -M5 started Fri Oct 27 02:08:08 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/SPARC_SE/m5.debug -d build/SPARC_SE/tests/debug/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic -Exiting @ tick 4862 because target called exit() +M5 compiled Apr 22 2007 20:15:56 +M5 started Sun Apr 22 20:26:04 2007 +M5 executing on zamp.eecs.umich.edu +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 2431000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini index da87d03a1..4371849c9 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -1,50 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[debug] -break_cycles= - -[exetrace] -intel_format=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -55,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -64,7 +21,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.cpu.dcache +phase=0 progress_interval=0 system=system workload=system.cpu.workload @@ -192,12 +149,14 @@ mem_side=system.membus.port[1] type=Bus bus_id=0 clock=1000 +responder_set=false width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload] type=LiveProcess cmd=hello +cwd= egid=100 env= euid=100 @@ -214,6 +173,7 @@ uid=100 type=Bus bus_id=0 clock=1000 +responder_set=false width=64 port=system.physmem.port system.cpu.l2cache.mem_side @@ -222,14 +182,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.out b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.out index 5210081b3..b02683337 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.out +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -21,10 +19,52 @@ type=Bus bus_id=0 clock=1000 width=64 +responder_set=false -[system.cpu.dcache] +[system.cpu.workload] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/sparc/linux/hello +input=cin +output=cout +env= +cwd= +system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 + +[system.cpu] +type=TimingSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +workload=system.cpu.workload +clock=500 +phase=0 +defer_registration=false +// width not specified +function_trace=false +function_trace_start=0 +// simulate_stalls not specified + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false + +[system.cpu.icache] type=BaseCache -size=262144 +size=131072 assoc=2 block_size=64 latency=1 @@ -60,48 +100,9 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[system.cpu.workload] -type=LiveProcess -cmd=hello -executable=tests/test-progs/hello/bin/sparc/linux/hello -input=cin -output=cout -env= -system=system -uid=100 -euid=100 -gid=100 -egid=100 -pid=100 -ppid=99 - -[system.cpu] -type=TimingSimpleCPU -max_insts_any_thread=0 -max_insts_all_threads=0 -max_loads_any_thread=0 -max_loads_all_threads=0 -progress_interval=0 -mem=system.cpu.dcache -system=system -cpu_id=0 -workload=system.cpu.workload -clock=1 -defer_registration=false -// width not specified -function_trace=false -function_trace_start=0 -// simulate_stalls not specified - -[system.cpu.toL2Bus] -type=Bus -bus_id=0 -clock=1000 -width=64 - -[system.cpu.icache] +[system.cpu.dcache] type=BaseCache -size=131072 +size=262144 assoc=2 block_size=64 latency=1 @@ -175,53 +176,3 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -trace_system=client - -[debug] -break_cycles= - -[statsreset] -reset_cycle=0 - diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt index b0f73986b..c6b55a6f2 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 158849 # Simulator instruction rate (inst/s) -host_mem_usage 179428 # Number of bytes of host memory used +host_inst_rate 189060 # Simulator instruction rate (inst/s) +host_mem_usage 154496 # Number of bytes of host memory used host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 50697812 # Simulator tick rate (ticks/s) +host_tick_rate 164285984 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4863 # Number of instructions simulated -sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 1573001 # Number of ticks simulated +sim_seconds 0.000004 # Number of seconds simulated +sim_ticks 4347500 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 608 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3971.370370 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2971.370370 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 3740.740741 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2740.740741 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 554 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 214454 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 202000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.088816 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 160454 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 148000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.088816 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 661 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3981.559524 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2981.559524 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 3625 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2625 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 577 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 334451 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 304500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.127080 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 84 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 250451 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 220500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.127080 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 84 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 1269 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3977.572464 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2977.572464 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 3670.289855 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2670.289855 # average overall mshr miss latency system.cpu.dcache.demand_hits 1131 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 548905 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 506500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.108747 # miss rate for demand accesses system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 410905 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 368500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.108747 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 1269 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3977.572464 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2977.572464 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 3670.289855 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2670.289855 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1131 # number of overall hits -system.cpu.dcache.overall_miss_latency 548905 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 506500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.108747 # miss rate for overall accesses system.cpu.dcache.overall_misses 138 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 410905 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 368500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.108747 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 81.997528 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 84.314216 # Cycle average of tags in use system.cpu.dcache.total_refs 1131 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 4864 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3977.960938 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2977.960938 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 3796.875000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2796.875000 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 4608 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1018358 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 972000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.052632 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 256 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 762358 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 716000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.052632 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 256 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 4864 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3977.960938 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2977.960938 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 3796.875000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2796.875000 # average overall mshr miss latency system.cpu.icache.demand_hits 4608 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1018358 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 972000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.052632 # miss rate for demand accesses system.cpu.icache.demand_misses 256 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 762358 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 716000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.052632 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 256 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 4864 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3977.960938 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2977.960938 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 3796.875000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2796.875000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 4608 # number of overall hits -system.cpu.icache.overall_miss_latency 1018358 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 972000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.052632 # miss rate for overall accesses system.cpu.icache.overall_misses 256 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 762358 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 716000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.052632 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 256 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 256 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 114.778311 # Cycle average of tags in use +system.cpu.icache.tagsinuse 114.238100 # Cycle average of tags in use system.cpu.icache.total_refs 4608 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 391 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2985.429668 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1984.429668 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1167303 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 2760.869565 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1759.869565 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 1079500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 391 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 775912 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 688109 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 391 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 391 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2985.429668 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1984.429668 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 2760.869565 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1759.869565 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1167303 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 1079500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 391 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 775912 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 688109 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 391 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 391 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2985.429668 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1984.429668 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 2760.869565 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1759.869565 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1167303 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 1079500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 391 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 775912 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 688109 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 391 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 391 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 195.424915 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 197.030867 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1573001 # number of cpu cycles simulated +system.cpu.numCycles 4347500 # number of cpu cycles simulated system.cpu.num_insts 4863 # Number of instructions executed system.cpu.num_refs 1269 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout index b1da2e4ab..6a58f8e2a 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout @@ -5,8 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 27 2006 02:07:29 -M5 started Fri Oct 27 02:08:11 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/SPARC_SE/m5.debug -d build/SPARC_SE/tests/debug/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing -Exiting @ tick 1573001 because target called exit() +M5 compiled Apr 22 2007 20:15:56 +M5 started Sun Apr 22 20:26:05 2007 +M5 executing on zamp.eecs.umich.edu +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 4347500 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini index f804a40fe..1f1e7a355 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -23,7 +23,7 @@ activity=0 backComSize=5 choiceCtrBits=2 choicePredictorSize=8192 -clock=1 +clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.out b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.out index d248f77bf..ac1dcb9ba 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.out +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.out @@ -167,7 +167,7 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL [system.cpu] type=DerivO3CPU -clock=1 +clock=500 phase=0 numThreads=1 cpu_id=0 diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt index 7c0d31494..8359db0f2 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 2990 # Number of BTB hits -global.BPredUnit.BTBLookups 7055 # Number of BTB lookups +global.BPredUnit.BTBHits 3154 # Number of BTB hits +global.BPredUnit.BTBLookups 9574 # Number of BTB lookups global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 2077 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 7846 # Number of conditional branches predicted -global.BPredUnit.lookups 7846 # Number of BP lookups +global.BPredUnit.condIncorrect 2047 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 10459 # Number of conditional branches predicted +global.BPredUnit.lookups 10459 # Number of BP lookups global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 15119 # Simulator instruction rate (inst/s) -host_mem_usage 154868 # Number of bytes of host memory used -host_seconds 0.73 # Real time elapsed on the host -host_tick_rate 1956796 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. +host_inst_rate 26468 # Simulator instruction rate (inst/s) +host_mem_usage 154944 # Number of bytes of host memory used +host_seconds 0.41 # Real time elapsed on the host +host_tick_rate 32157366 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 14 # Number of conflicting loads. memdepunit.memDep.conflictingStores 0 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 3250 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 2817 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 3573 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 3440 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 10976 # Number of instructions simulated -sim_seconds 0.000001 # Number of seconds simulated -sim_ticks 1421211 # Number of ticks simulated +sim_seconds 0.000013 # Number of seconds simulated +sim_ticks 13345500 # Number of ticks simulated system.cpu.commit.COM:branches 2152 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 172 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 164 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 221349 +system.cpu.commit.COM:committed_per_cycle.samples 23147 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 215844 9751.30% - 1 2970 134.18% - 2 1290 58.28% - 3 631 28.51% - 4 208 9.40% - 5 90 4.07% - 6 133 6.01% - 7 11 0.50% - 8 172 7.77% + 0 17950 7754.78% + 1 2912 1258.05% + 2 993 429.00% + 3 424 183.18% + 4 287 123.99% + 5 235 101.53% + 6 103 44.50% + 7 79 34.13% + 8 164 70.85% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 1462 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 2760 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 2077 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 2047 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 10976 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 327 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 14263 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 18321 # The number of squashed insts skipped by commit system.cpu.committedInsts 10976 # Number of Instructions Simulated system.cpu.committedInsts_total 10976 # Number of Instructions Simulated -system.cpu.cpi 129.483509 # CPI: Cycles Per Instruction -system.cpu.cpi_total 129.483509 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 2737 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 6585.044776 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6511.939394 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2603 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 882396 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.048959 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 134 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 68 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 429788 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.024114 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 66 # number of ReadReq MSHR misses +system.cpu.cpi 2.431851 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.431851 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 2813 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 4311.764706 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3546.153846 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 2728 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 366500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.030217 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 85 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 20 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 230500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.023107 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 65 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits system.cpu.dcache.WriteReq_accesses 1292 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 7960.583924 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7136.918605 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 869 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3367327 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.327399 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 423 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 337 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 613775 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 4645.408163 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3470.930233 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 1096 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 910500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.151703 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 196 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 110 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 298500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.066563 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 86 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 22.881579 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 25.364238 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 4029 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 7629.664273 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 6865.546053 # average overall mshr miss latency -system.cpu.dcache.demand_hits 3472 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 4249723 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.138248 # miss rate for demand accesses -system.cpu.dcache.demand_misses 557 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 405 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1043563 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.037726 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 152 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 4105 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 4544.483986 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3503.311258 # average overall mshr miss latency +system.cpu.dcache.demand_hits 3824 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 1277000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.068453 # miss rate for demand accesses +system.cpu.dcache.demand_misses 281 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 130 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 529000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.036784 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 151 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 4029 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 7629.664273 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 6865.546053 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 4105 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 4544.483986 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3503.311258 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 3472 # number of overall hits -system.cpu.dcache.overall_miss_latency 4249723 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.138248 # miss rate for overall accesses -system.cpu.dcache.overall_misses 557 # number of overall misses -system.cpu.dcache.overall_mshr_hits 405 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1043563 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.037726 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 152 # number of overall MSHR misses +system.cpu.dcache.overall_hits 3824 # number of overall hits +system.cpu.dcache.overall_miss_latency 1277000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.068453 # miss rate for overall accesses +system.cpu.dcache.overall_misses 281 # number of overall misses +system.cpu.dcache.overall_mshr_hits 130 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 529000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.036784 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 151 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -121,88 +121,88 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 152 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 151 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 90.938737 # Cycle average of tags in use -system.cpu.dcache.total_refs 3478 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 112.362185 # Cycle average of tags in use +system.cpu.dcache.total_refs 3830 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 192719 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 39774 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 20128 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 8238 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 3162 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 264 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 7846 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 5085 # Number of cache lines fetched -system.cpu.fetch.Cycles 14399 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 745 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 43304 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 2134 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.034947 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 5085 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 2990 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.192881 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 4942 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 48420 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 8618 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 9347 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 3545 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 240 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 10459 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 5440 # Number of cache lines fetched +system.cpu.fetch.Cycles 16262 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 216 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 55152 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 2110 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.391840 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 5440 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 3154 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.066237 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 224511 +system.cpu.fetch.rateDist.samples 26692 system.cpu.fetch.rateDist.min_value 0 - 0 215198 9585.19% - 1 2258 100.57% - 2 627 27.93% - 3 958 42.67% - 4 553 24.63% - 5 816 36.35% - 6 951 42.36% - 7 280 12.47% - 8 2870 127.83% + 0 15871 5945.98% + 1 2250 842.95% + 2 637 238.65% + 3 971 363.78% + 4 550 206.05% + 5 848 317.70% + 6 962 360.41% + 7 321 120.26% + 8 4282 1604.23% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 5085 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 5148.266776 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 4502.972752 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 4474 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 3145591 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.120157 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 611 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 244 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 1652591 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.072173 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 367 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 5440 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3939.473684 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2944.591029 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 5060 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1497000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.069853 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 380 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 1116000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.069669 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 379 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 12.325069 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 13.350923 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 5085 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 5148.266776 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 4502.972752 # average overall mshr miss latency -system.cpu.icache.demand_hits 4474 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 3145591 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.120157 # miss rate for demand accesses -system.cpu.icache.demand_misses 611 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 244 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1652591 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.072173 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 367 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 5440 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3939.473684 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2944.591029 # average overall mshr miss latency +system.cpu.icache.demand_hits 5060 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1497000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.069853 # miss rate for demand accesses +system.cpu.icache.demand_misses 380 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 1 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 1116000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.069669 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 379 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 5085 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 5148.266776 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 4502.972752 # average overall mshr miss latency +system.cpu.icache.overall_accesses 5440 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3939.473684 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2944.591029 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 4474 # number of overall hits -system.cpu.icache.overall_miss_latency 3145591 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.120157 # miss rate for overall accesses -system.cpu.icache.overall_misses 611 # number of overall misses -system.cpu.icache.overall_mshr_hits 244 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1652591 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.072173 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 367 # number of overall MSHR misses +system.cpu.icache.overall_hits 5060 # number of overall hits +system.cpu.icache.overall_miss_latency 1497000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.069853 # miss rate for overall accesses +system.cpu.icache.overall_misses 380 # number of overall misses +system.cpu.icache.overall_mshr_hits 1 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 1116000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.069669 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 379 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,61 +215,60 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.sampled_refs 363 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 379 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 172.869174 # Cycle average of tags in use -system.cpu.icache.total_refs 4474 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 242.916499 # Cycle average of tags in use +system.cpu.icache.total_refs 5060 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1196701 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 3576 # Number of branches executed +system.cpu.iew.EXEC:branches 3713 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.092548 # Inst execution rate -system.cpu.iew.EXEC:refs 5257 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 2386 # Number of stores executed +system.cpu.iew.EXEC:rate 0.830061 # Inst execution rate +system.cpu.iew.EXEC:refs 5553 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 2589 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 9737 # num instructions consuming a value -system.cpu.iew.WB:count 19769 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.790901 # average fanout of values written-back +system.cpu.iew.WB:consumers 10966 # num instructions consuming a value +system.cpu.iew.WB:count 21367 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.799836 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 7701 # num instructions producing a value -system.cpu.iew.WB:rate 0.088054 # insts written-back per cycle -system.cpu.iew.WB:sent 20061 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 2593 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 476 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 3250 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 617 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 2705 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2817 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 25240 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 2871 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1780 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 20778 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 8771 # num instructions producing a value +system.cpu.iew.WB:rate 0.800502 # insts written-back per cycle +system.cpu.iew.WB:sent 21712 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 2654 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 3573 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 630 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1509 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 3440 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 29298 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 2964 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3437 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 22156 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 3162 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 3545 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 39 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 52 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 54 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1788 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1519 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 54 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 962 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1631 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.007723 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.007723 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 22558 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 75 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 2111 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 2142 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 75 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1030 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1624 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.411209 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.411209 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 25593 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 1831 8.12% # Type of FU issued - IntAlu 15054 66.73% # Type of FU issued + (null) 1919 7.50% # Type of FU issued + IntAlu 17231 67.33% # Type of FU issued IntMult 0 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 0 0.00% # Type of FU issued @@ -278,16 +277,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 3091 13.70% # Type of FU issued - MemWrite 2582 11.45% # Type of FU issued + MemRead 3429 13.40% # Type of FU issued + MemWrite 3014 11.78% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 162 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.007181 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 238 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.009299 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 42 25.93% # attempts to use FU when none available + IntAlu 99 41.60% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -296,43 +295,43 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 14 8.64% # attempts to use FU when none available - MemWrite 106 65.43% # attempts to use FU when none available + MemRead 22 9.24% # attempts to use FU when none available + MemWrite 117 49.16% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 224511 +system.cpu.iq.ISSUE:issued_per_cycle.samples 26692 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 215315 9590.40% - 1 4124 183.69% - 2 1297 57.77% - 3 1306 58.17% - 4 1190 53.00% - 5 707 31.49% - 6 433 19.29% - 7 83 3.70% - 8 56 2.49% + 0 17644 6610.22% + 1 3262 1222.09% + 2 1371 513.64% + 3 1071 401.24% + 4 1568 587.44% + 5 925 346.55% + 6 579 216.92% + 7 171 64.06% + 8 101 37.84% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.100476 # Inst issue rate -system.cpu.iq.iqInstsAdded 24623 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 22558 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 617 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 11469 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 174 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 290 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 5834 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 513 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4754.779727 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2343.506823 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 2439202 # number of ReadReq miss cycles +system.cpu.iq.ISSUE:rate 0.958827 # Inst issue rate +system.cpu.iq.iqInstsAdded 28668 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 25593 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 630 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 15737 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 133 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 303 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 7975 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 526 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 3018.060837 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1812.857414 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 1587500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 513 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1202219 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_misses 526 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 953563 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 513 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 526 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -341,32 +340,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 513 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4754.779727 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2343.506823 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 526 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 3018.060837 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1812.857414 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2439202 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 1587500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 513 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 526 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1202219 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 953563 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 513 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 526 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 513 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4754.779727 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2343.506823 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 526 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 3018.060837 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1812.857414 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2439202 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 1587500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 513 # number of overall misses +system.cpu.l2cache.overall_misses 526 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1202219 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 953563 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 513 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 526 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -379,32 +378,28 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 512 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 526 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 262.946375 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 353.661697 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 224511 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 960 # Number of cycles rename is blocking +system.cpu.numCycles 26692 # number of cpu cycles simulated system.cpu.rename.RENAME:CommittedMaps 9868 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 20098 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 481 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 46931 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 31260 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 25831 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 7921 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 3162 # Number of cycles rename is squashing -system.cpu.rename.RENAME:SquashedInsts 8042 # Number of squashed instructions processed by rename -system.cpu.rename.RENAME:UnblockCycles 1212 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 15963 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 190573 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 638 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 5594 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 629 # count of temporary serializing insts renamed -system.cpu.timesIdled 289 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IdleCycles 8631 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 59097 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 39751 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 31999 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 9086 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 3545 # Number of cycles rename is squashing +system.cpu.rename.RENAME:SquashedInsts 8167 # Number of squashed instructions processed by rename +system.cpu.rename.RENAME:UnblockCycles 716 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 22131 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 4224 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 665 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 4954 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 658 # count of temporary serializing insts renamed system.cpu.workload.PROG:num_syscalls 8 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr index 48affb0e2..7873672f2 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr @@ -1,4 +1,3 @@ warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x0 length 0x0. -0: system.remote_gdb.listener: listening for remote gdb on port 7003 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout index 6cba2ba7e..0bb67880e 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout @@ -16,9 +16,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 9 2007 03:06:26 -M5 started Mon Apr 9 03:06:54 2007 -M5 executing on zizzer.eecs.umich.edu +M5 compiled Apr 22 2007 20:15:56 +M5 started Sun Apr 22 20:26:05 2007 +M5 executing on zamp.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing tests/run.py quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1421211 because target called exit() +Exiting @ tick 13345500 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini index 06059c3eb..7e9c12db2 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini @@ -12,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out index 7f9a83d25..29915233b 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out @@ -47,7 +47,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false width=1 diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt index 1ed7d50eb..22ea72ebd 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 65718 # Simulator instruction rate (inst/s) -host_mem_usage 179556 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host -host_tick_rate 65601 # Simulator tick rate (ticks/s) +host_inst_rate 430012 # Simulator instruction rate (inst/s) +host_mem_usage 149064 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 207711772 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 11001 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 11000 # Number of ticks simulated +sim_seconds 0.000005 # Number of seconds simulated +sim_ticks 5500000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 11001 # number of cpu cycles simulated diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr index a3b9f045a..7873672f2 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr @@ -1,4 +1,3 @@ warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x0 length 0x0. -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout index c89235e64..66bfb4931 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout @@ -16,9 +16,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 29 2007 15:29:35 -M5 started Thu Mar 29 15:39:35 2007 -M5 executing on zeep -command line: build/SPARC_SE/m5.debug -d build/SPARC_SE/tests/debug/quick/02.insttest/sparc/linux/simple-atomic tests/run.py quick/02.insttest/sparc/linux/simple-atomic +M5 compiled Apr 22 2007 20:15:56 +M5 started Sun Apr 22 20:26:06 2007 +M5 executing on zamp.eecs.umich.edu +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic tests/run.py quick/02.insttest/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 11000 because target called exit() +Exiting @ tick 5500000 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini index 85d14933a..394f564a5 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -12,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out index ec2d1886a..9d999c4c3 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out @@ -47,7 +47,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false // width not specified diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt index a4396b3da..aef9433e6 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 39129 # Simulator instruction rate (inst/s) -host_mem_usage 153232 # Number of bytes of host memory used -host_seconds 0.28 # Real time elapsed on the host -host_tick_rate 6030675 # Simulator tick rate (ticks/s) +host_inst_rate 285170 # Simulator instruction rate (inst/s) +host_mem_usage 154424 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 211576923 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 11001 # Number of instructions simulated -sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 1698003 # Number of ticks simulated +sim_seconds 0.000008 # Number of seconds simulated +sim_ticks 8251500 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1462 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3977.759259 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2977.759259 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 3712.962963 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2712.962963 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 1408 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 214799 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 200500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.036936 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 160799 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 146500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.036936 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits system.cpu.dcache.WriteReq_accesses 1292 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3963.647727 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2963.647727 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 3676.136364 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2676.136364 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 1204 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 348801 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 323500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.068111 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 88 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 260801 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 235500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.068111 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 88 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -39,29 +39,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2754 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3969.014085 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2969.014085 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 3690.140845 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2690.140845 # average overall mshr miss latency system.cpu.dcache.demand_hits 2612 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 563600 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 524000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.051561 # miss rate for demand accesses system.cpu.dcache.demand_misses 142 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 421600 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 382000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.051561 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 142 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 2754 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3969.014085 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2969.014085 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 3690.140845 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2690.140845 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 2612 # number of overall hits -system.cpu.dcache.overall_miss_latency 563600 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 524000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.051561 # miss rate for overall accesses system.cpu.dcache.overall_misses 142 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 421600 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 382000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.051561 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -78,18 +78,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 86.872921 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 106.692969 # Cycle average of tags in use system.cpu.dcache.total_refs 2618 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 11002 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3961.367491 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2961.367491 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 3743.816254 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2743.816254 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 10719 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1121067 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 1059500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.025723 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 283 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 838067 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 776500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.025723 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 283 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -101,29 +101,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 11002 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3961.367491 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2961.367491 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 3743.816254 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2743.816254 # average overall mshr miss latency system.cpu.icache.demand_hits 10719 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1121067 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 1059500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.025723 # miss rate for demand accesses system.cpu.icache.demand_misses 283 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 838067 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 776500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.025723 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 283 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 11002 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3961.367491 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2961.367491 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 3743.816254 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2743.816254 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 10719 # number of overall hits -system.cpu.icache.overall_miss_latency 1121067 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 1059500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.025723 # miss rate for overall accesses system.cpu.icache.overall_misses 283 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 838067 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 776500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.025723 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 283 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -140,18 +140,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 283 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 125.297191 # Cycle average of tags in use +system.cpu.icache.tagsinuse 170.449932 # Cycle average of tags in use system.cpu.icache.total_refs 10719 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 423 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2968.515366 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1967.515366 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1255682 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 2730.496454 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1729.496454 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 1155000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 423 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 832259 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 731577 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 423 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -163,29 +163,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 423 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2968.515366 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1967.515366 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 2730.496454 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1729.496454 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1255682 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 1155000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 423 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 832259 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 731577 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 423 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 423 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2968.515366 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1967.515366 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 2730.496454 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1729.496454 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1255682 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 1155000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 423 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 832259 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 731577 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 423 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -202,12 +202,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 423 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 211.742547 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 276.385948 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1698003 # number of cpu cycles simulated +system.cpu.numCycles 8251500 # number of cpu cycles simulated system.cpu.num_insts 11001 # Number of instructions executed system.cpu.num_refs 2760 # Number of memory references system.cpu.workload.PROG:num_syscalls 8 # Number of system calls diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr index fce46c90e..7873672f2 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr @@ -1,4 +1,3 @@ warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x0 length 0x0. -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout index 100a1ebce..dd4d8d282 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout @@ -16,9 +16,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2007 05:25:15 -M5 started Sun Apr 8 22:54:12 2007 -M5 executing on zizzer.eecs.umich.edu +M5 compiled Apr 22 2007 20:15:56 +M5 started Sun Apr 22 20:26:07 2007 +M5 executing on zamp.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing tests/run.py quick/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1698003 because target called exit() +Exiting @ tick 8251500 because target called exit() From 6a79ada182819776bca566908fde8599a1590d2e Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Mon, 23 Apr 2007 14:40:46 -0400 Subject: [PATCH 21/68] update_refs for ALPHA_FS with new disk image. tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout: update_refs --HG-- extra : convert_revision : 942d42bcd0ab962a7dda897e455329bf15105887 --- .../tsunami-simple-atomic-dual/config.ini | 6 +- .../tsunami-simple-atomic-dual/config.out | 5 +- .../tsunami-simple-atomic-dual/m5stats.txt | 382 ++++++++--------- .../linux/tsunami-simple-atomic-dual/stderr | 7 +- .../linux/tsunami-simple-atomic-dual/stdout | 11 +- .../linux/tsunami-simple-atomic/config.ini | 6 +- .../linux/tsunami-simple-atomic/config.out | 5 +- .../linux/tsunami-simple-atomic/m5stats.txt | 202 ++++----- .../alpha/linux/tsunami-simple-atomic/stderr | 5 +- .../alpha/linux/tsunami-simple-atomic/stdout | 11 +- .../tsunami-simple-timing-dual/config.ini | 6 +- .../tsunami-simple-timing-dual/config.out | 5 +- .../tsunami-simple-timing-dual/m5stats.txt | 398 +++++++++--------- .../linux/tsunami-simple-timing-dual/stderr | 7 +- .../linux/tsunami-simple-timing-dual/stdout | 11 +- .../linux/tsunami-simple-timing/config.ini | 6 +- .../linux/tsunami-simple-timing/config.out | 5 +- .../linux/tsunami-simple-timing/m5stats.txt | 202 ++++----- .../alpha/linux/tsunami-simple-timing/stderr | 5 +- .../alpha/linux/tsunami-simple-timing/stdout | 11 +- .../twosys-tsunami-simple-atomic/config.ini | 12 +- .../twosys-tsunami-simple-atomic/config.out | 11 +- .../twosys-tsunami-simple-atomic/m5stats.txt | 104 ++--- .../linux/twosys-tsunami-simple-atomic/stderr | 10 +- .../linux/twosys-tsunami-simple-atomic/stdout | 13 +- 25 files changed, 706 insertions(+), 740 deletions(-) diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index ce952d718..8145ecdc4 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -1,11 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=2000000000 -max_tick=0 -output_file=cout -progress_interval=0 +dummy=0 [system] type=LinuxAlphaSystem diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out index 313620c59..e0c23706f 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=2000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt index 4dbe8c13c..1c69cf2f2 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt @@ -1,220 +1,224 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1026206 # Simulator instruction rate (inst/s) -host_mem_usage 240860 # Number of bytes of host memory used -host_seconds 63.27 # Real time elapsed on the host -host_tick_rate 58764450 # Simulator tick rate (ticks/s) +host_inst_rate 242742 # Simulator instruction rate (inst/s) +host_mem_usage 197416 # Number of bytes of host memory used +host_seconds 260.02 # Real time elapsed on the host +host_tick_rate 14386097 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 64932819 # Number of instructions simulated -sim_seconds 1.859157 # Number of seconds simulated -sim_ticks 3718314928 # Number of ticks simulated -system.cpu0.dtb.accesses 544556 # DTB accesses -system.cpu0.dtb.acv 335 # DTB access violations -system.cpu0.dtb.hits 14841931 # DTB hits -system.cpu0.dtb.misses 7356 # DTB misses -system.cpu0.dtb.read_accesses 377530 # DTB read accesses -system.cpu0.dtb.read_acv 210 # DTB read access violations -system.cpu0.dtb.read_hits 8970576 # DTB read hits -system.cpu0.dtb.read_misses 6581 # DTB read misses -system.cpu0.dtb.write_accesses 167026 # DTB write accesses -system.cpu0.dtb.write_acv 125 # DTB write access violations -system.cpu0.dtb.write_hits 5871355 # DTB write hits -system.cpu0.dtb.write_misses 775 # DTB write misses -system.cpu0.idle_fraction 0.984944 # Percentage of idle cycles -system.cpu0.itb.accesses 3586919 # ITB accesses -system.cpu0.itb.acv 184 # ITB acv -system.cpu0.itb.hits 3583450 # ITB hits -system.cpu0.itb.misses 3469 # ITB misses -system.cpu0.kern.callpal 182754 # number of callpals executed +sim_insts 63117303 # Number of instructions simulated +sim_seconds 1.870326 # Number of seconds simulated +sim_ticks 3740652145 # Number of ticks simulated +system.cpu0.dtb.accesses 698037 # DTB accesses +system.cpu0.dtb.acv 251 # DTB access violations +system.cpu0.dtb.hits 15070122 # DTB hits +system.cpu0.dtb.misses 7805 # DTB misses +system.cpu0.dtb.read_accesses 508987 # DTB read accesses +system.cpu0.dtb.read_acv 152 # DTB read access violations +system.cpu0.dtb.read_hits 9141132 # DTB read hits +system.cpu0.dtb.read_misses 7079 # DTB read misses +system.cpu0.dtb.write_accesses 189050 # DTB write accesses +system.cpu0.dtb.write_acv 99 # DTB write access violations +system.cpu0.dtb.write_hits 5928990 # DTB write hits +system.cpu0.dtb.write_misses 726 # DTB write misses +system.cpu0.idle_fraction 0.984722 # Percentage of idle cycles +system.cpu0.itb.accesses 3856317 # ITB accesses +system.cpu0.itb.acv 127 # ITB acv +system.cpu0.itb.hits 3852832 # ITB hits +system.cpu0.itb.misses 3485 # ITB misses +system.cpu0.kern.callpal 183079 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal_wripir 115 0.06% 0.06% # number of callpals executed +system.cpu0.kern.callpal_wripir 111 0.06% 0.06% # number of callpals executed system.cpu0.kern.callpal_wrmces 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal_wrfen 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal_swpctx 3791 2.07% 2.14% # number of callpals executed -system.cpu0.kern.callpal_tbi 49 0.03% 2.17% # number of callpals executed -system.cpu0.kern.callpal_wrent 7 0.00% 2.17% # number of callpals executed -system.cpu0.kern.callpal_swpipl 167832 91.83% 94.01% # number of callpals executed -system.cpu0.kern.callpal_rdps 5780 3.16% 97.17% # number of callpals executed +system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal_swpctx 3761 2.05% 2.12% # number of callpals executed +system.cpu0.kern.callpal_tbi 38 0.02% 2.14% # number of callpals executed +system.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed +system.cpu0.kern.callpal_swpipl 167848 91.68% 93.82% # number of callpals executed +system.cpu0.kern.callpal_rdps 6134 3.35% 97.17% # number of callpals executed system.cpu0.kern.callpal_wrkgp 1 0.00% 97.17% # number of callpals executed -system.cpu0.kern.callpal_wrusp 2 0.00% 97.17% # number of callpals executed -system.cpu0.kern.callpal_rdusp 9 0.00% 97.17% # number of callpals executed +system.cpu0.kern.callpal_wrusp 3 0.00% 97.17% # number of callpals executed +system.cpu0.kern.callpal_rdusp 7 0.00% 97.18% # number of callpals executed system.cpu0.kern.callpal_whami 2 0.00% 97.18% # number of callpals executed -system.cpu0.kern.callpal_rti 4696 2.57% 99.75% # number of callpals executed -system.cpu0.kern.callpal_callsys 344 0.19% 99.93% # number of callpals executed -system.cpu0.kern.callpal_imb 122 0.07% 100.00% # number of callpals executed +system.cpu0.kern.callpal_rti 4664 2.55% 99.73% # number of callpals executed +system.cpu0.kern.callpal_callsys 357 0.19% 99.92% # number of callpals executed +system.cpu0.kern.callpal_imb 142 0.08% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 196249 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6184 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 174678 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 70736 40.50% 40.50% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_21 245 0.14% 40.64% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_22 1896 1.09% 41.72% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_30 8 0.00% 41.73% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 101793 58.27% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 140889 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 69374 49.24% 49.24% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_21 245 0.17% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_22 1896 1.35% 50.76% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 69366 49.23% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 3718314513 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 3683820285 99.07% 99.07% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 40474 0.00% 99.07% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 163056 0.00% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 2026 0.00% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 34288672 0.92% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used 0.806564 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_0 0.980745 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.hwrei 196899 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6163 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 174663 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 70908 40.60% 40.60% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_21 234 0.13% 40.73% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_22 1908 1.09% 41.82% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_30 8 0.00% 41.83% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 101605 58.17% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 141224 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 69541 49.24% 49.24% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_21 234 0.17% 49.41% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_30 8 0.01% 50.76% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_31 69533 49.24% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 3740651730 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 3706247513 99.08% 99.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 38699 0.00% 99.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 164088 0.00% 99.09% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 1899 0.00% 99.09% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 34199531 0.91% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used 0.808551 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_0 0.980721 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.681442 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1192 -system.cpu0.kern.mode_good_user 1193 +system.cpu0.kern.ipl_used_31 0.684346 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1155 +system.cpu0.kern.mode_good_user 1156 system.cpu0.kern.mode_good_idle 0 -system.cpu0.kern.mode_switch_kernel 7143 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1193 # number of protection mode switches +system.cpu0.kern.mode_switch_kernel 7081 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1156 # number of protection mode switches system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good 0.286108 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.166877 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good 0.280563 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.163113 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 3716671550 99.96% 99.96% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 1642961 0.04% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_kernel 3738737730 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 1913998 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3792 # number of times the context was actually changed -system.cpu0.kern.syscall 199 # number of syscalls executed -system.cpu0.kern.syscall_2 8 4.02% 4.02% # number of syscalls executed -system.cpu0.kern.syscall_3 17 8.54% 12.56% # number of syscalls executed -system.cpu0.kern.syscall_4 4 2.01% 14.57% # number of syscalls executed -system.cpu0.kern.syscall_6 29 14.57% 29.15% # number of syscalls executed -system.cpu0.kern.syscall_12 1 0.50% 29.65% # number of syscalls executed -system.cpu0.kern.syscall_17 4 2.01% 31.66% # number of syscalls executed -system.cpu0.kern.syscall_19 10 5.03% 36.68% # number of syscalls executed -system.cpu0.kern.syscall_20 6 3.02% 39.70% # number of syscalls executed -system.cpu0.kern.syscall_23 1 0.50% 40.20% # number of syscalls executed -system.cpu0.kern.syscall_24 3 1.51% 41.71% # number of syscalls executed -system.cpu0.kern.syscall_33 6 3.02% 44.72% # number of syscalls executed -system.cpu0.kern.syscall_41 2 1.01% 45.73% # number of syscalls executed -system.cpu0.kern.syscall_45 31 15.58% 61.31% # number of syscalls executed -system.cpu0.kern.syscall_47 3 1.51% 62.81% # number of syscalls executed -system.cpu0.kern.syscall_48 10 5.03% 67.84% # number of syscalls executed -system.cpu0.kern.syscall_54 9 4.52% 72.36% # number of syscalls executed -system.cpu0.kern.syscall_59 6 3.02% 75.38% # number of syscalls executed -system.cpu0.kern.syscall_71 20 10.05% 85.43% # number of syscalls executed -system.cpu0.kern.syscall_73 3 1.51% 86.93% # number of syscalls executed -system.cpu0.kern.syscall_74 5 2.51% 89.45% # number of syscalls executed -system.cpu0.kern.syscall_87 1 0.50% 89.95% # number of syscalls executed -system.cpu0.kern.syscall_90 3 1.51% 91.46% # number of syscalls executed -system.cpu0.kern.syscall_92 8 4.02% 95.48% # number of syscalls executed -system.cpu0.kern.syscall_97 2 1.01% 96.48% # number of syscalls executed -system.cpu0.kern.syscall_98 2 1.01% 97.49% # number of syscalls executed -system.cpu0.kern.syscall_132 1 0.50% 97.99% # number of syscalls executed -system.cpu0.kern.syscall_144 2 1.01% 98.99% # number of syscalls executed -system.cpu0.kern.syscall_147 2 1.01% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.015056 # Percentage of non-idle cycles -system.cpu0.numCycles 55984201 # number of cpu cycles simulated -system.cpu0.num_insts 55980548 # Number of instructions executed -system.cpu0.num_refs 15081320 # Number of memory references -system.cpu1.dtb.accesses 761000 # DTB accesses -system.cpu1.dtb.acv 32 # DTB access violations -system.cpu1.dtb.hits 2658022 # DTB hits -system.cpu1.dtb.misses 4173 # DTB misses -system.cpu1.dtb.read_accesses 523552 # DTB read accesses -system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_hits 1679180 # DTB read hits -system.cpu1.dtb.read_misses 3798 # DTB read misses -system.cpu1.dtb.write_accesses 237448 # DTB write accesses -system.cpu1.dtb.write_acv 32 # DTB write access violations -system.cpu1.dtb.write_hits 978842 # DTB write hits -system.cpu1.dtb.write_misses 375 # DTB write misses -system.cpu1.idle_fraction 0.997592 # Percentage of idle cycles -system.cpu1.itb.accesses 2420426 # ITB accesses -system.cpu1.itb.acv 0 # ITB acv -system.cpu1.itb.hits 2418839 # ITB hits -system.cpu1.itb.misses 1587 # ITB misses -system.cpu1.kern.callpal 34411 # number of callpals executed +system.cpu0.kern.swap_context 3762 # number of times the context was actually changed +system.cpu0.kern.syscall 226 # number of syscalls executed +system.cpu0.kern.syscall_2 6 2.65% 2.65% # number of syscalls executed +system.cpu0.kern.syscall_3 19 8.41% 11.06% # number of syscalls executed +system.cpu0.kern.syscall_4 2 0.88% 11.95% # number of syscalls executed +system.cpu0.kern.syscall_6 32 14.16% 26.11% # number of syscalls executed +system.cpu0.kern.syscall_12 1 0.44% 26.55% # number of syscalls executed +system.cpu0.kern.syscall_15 1 0.44% 26.99% # number of syscalls executed +system.cpu0.kern.syscall_17 9 3.98% 30.97% # number of syscalls executed +system.cpu0.kern.syscall_19 8 3.54% 34.51% # number of syscalls executed +system.cpu0.kern.syscall_20 6 2.65% 37.17% # number of syscalls executed +system.cpu0.kern.syscall_23 2 0.88% 38.05% # number of syscalls executed +system.cpu0.kern.syscall_24 4 1.77% 39.82% # number of syscalls executed +system.cpu0.kern.syscall_33 7 3.10% 42.92% # number of syscalls executed +system.cpu0.kern.syscall_41 2 0.88% 43.81% # number of syscalls executed +system.cpu0.kern.syscall_45 37 16.37% 60.18% # number of syscalls executed +system.cpu0.kern.syscall_47 4 1.77% 61.95% # number of syscalls executed +system.cpu0.kern.syscall_48 8 3.54% 65.49% # number of syscalls executed +system.cpu0.kern.syscall_54 10 4.42% 69.91% # number of syscalls executed +system.cpu0.kern.syscall_58 1 0.44% 70.35% # number of syscalls executed +system.cpu0.kern.syscall_59 4 1.77% 72.12% # number of syscalls executed +system.cpu0.kern.syscall_71 30 13.27% 85.40% # number of syscalls executed +system.cpu0.kern.syscall_73 3 1.33% 86.73% # number of syscalls executed +system.cpu0.kern.syscall_74 8 3.54% 90.27% # number of syscalls executed +system.cpu0.kern.syscall_87 1 0.44% 90.71% # number of syscalls executed +system.cpu0.kern.syscall_90 2 0.88% 91.59% # number of syscalls executed +system.cpu0.kern.syscall_92 9 3.98% 95.58% # number of syscalls executed +system.cpu0.kern.syscall_97 2 0.88% 96.46% # number of syscalls executed +system.cpu0.kern.syscall_98 2 0.88% 97.35% # number of syscalls executed +system.cpu0.kern.syscall_132 2 0.88% 98.23% # number of syscalls executed +system.cpu0.kern.syscall_144 2 0.88% 99.12% # number of syscalls executed +system.cpu0.kern.syscall_147 2 0.88% 100.00% # number of syscalls executed +system.cpu0.not_idle_fraction 0.015278 # Percentage of non-idle cycles +system.cpu0.numCycles 57148679 # number of cpu cycles simulated +system.cpu0.num_insts 57145067 # Number of instructions executed +system.cpu0.num_refs 15309549 # Number of memory references +system.cpu1.dtb.accesses 323622 # DTB accesses +system.cpu1.dtb.acv 116 # DTB access violations +system.cpu1.dtb.hits 1925621 # DTB hits +system.cpu1.dtb.misses 3692 # DTB misses +system.cpu1.dtb.read_accesses 220342 # DTB read accesses +system.cpu1.dtb.read_acv 58 # DTB read access violations +system.cpu1.dtb.read_hits 1169530 # DTB read hits +system.cpu1.dtb.read_misses 3277 # DTB read misses +system.cpu1.dtb.write_accesses 103280 # DTB write accesses +system.cpu1.dtb.write_acv 58 # DTB write access violations +system.cpu1.dtb.write_hits 756091 # DTB write hits +system.cpu1.dtb.write_misses 415 # DTB write misses +system.cpu1.idle_fraction 0.998403 # Percentage of idle cycles +system.cpu1.itb.accesses 1471328 # ITB accesses +system.cpu1.itb.acv 57 # ITB acv +system.cpu1.itb.hits 1469789 # ITB hits +system.cpu1.itb.misses 1539 # ITB misses +system.cpu1.kern.callpal 32276 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu1.kern.callpal_wripir 8 0.02% 0.03% # number of callpals executed system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal_swpctx 468 1.36% 1.39% # number of callpals executed -system.cpu1.kern.callpal_tbi 5 0.01% 1.41% # number of callpals executed -system.cpu1.kern.callpal_wrent 7 0.02% 1.43% # number of callpals executed -system.cpu1.kern.callpal_swpipl 28036 81.47% 82.90% # number of callpals executed -system.cpu1.kern.callpal_rdps 3042 8.84% 91.74% # number of callpals executed -system.cpu1.kern.callpal_wrkgp 1 0.00% 91.74% # number of callpals executed -system.cpu1.kern.callpal_wrusp 5 0.01% 91.76% # number of callpals executed -system.cpu1.kern.callpal_whami 3 0.01% 91.77% # number of callpals executed -system.cpu1.kern.callpal_rti 2586 7.52% 99.28% # number of callpals executed -system.cpu1.kern.callpal_callsys 187 0.54% 99.83% # number of callpals executed -system.cpu1.kern.callpal_imb 59 0.17% 100.00% # number of callpals executed +system.cpu1.kern.callpal_swpctx 473 1.47% 1.50% # number of callpals executed +system.cpu1.kern.callpal_tbi 15 0.05% 1.55% # number of callpals executed +system.cpu1.kern.callpal_wrent 7 0.02% 1.57% # number of callpals executed +system.cpu1.kern.callpal_swpipl 26366 81.69% 83.26% # number of callpals executed +system.cpu1.kern.callpal_rdps 2589 8.02% 91.28% # number of callpals executed +system.cpu1.kern.callpal_wrkgp 1 0.00% 91.28% # number of callpals executed +system.cpu1.kern.callpal_wrusp 4 0.01% 91.29% # number of callpals executed +system.cpu1.kern.callpal_rdusp 2 0.01% 91.30% # number of callpals executed +system.cpu1.kern.callpal_whami 3 0.01% 91.31% # number of callpals executed +system.cpu1.kern.callpal_rti 2608 8.08% 99.39% # number of callpals executed +system.cpu1.kern.callpal_callsys 158 0.49% 99.88% # number of callpals executed +system.cpu1.kern.callpal_imb 38 0.12% 100.00% # number of callpals executed system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 42215 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 2214 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 32633 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 11168 34.22% 34.22% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_22 1895 5.81% 40.03% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_30 115 0.35% 40.38% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 19455 59.62% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 24201 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 11153 46.08% 46.08% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_22 1895 7.83% 53.92% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_30 115 0.48% 54.39% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 11038 45.61% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 3717892668 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 3695802544 99.41% 99.41% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 162970 0.00% 99.41% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 29122 0.00% 99.41% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 21898032 0.59% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used 0.741611 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_0 0.998657 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.hwrei 39700 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 2208 # number of quiesce instructions executed +system.cpu1.kern.ipl_count 30993 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 10390 33.52% 33.52% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_22 1907 6.15% 39.68% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_30 111 0.36% 40.03% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_31 18585 59.97% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 22667 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 10380 45.79% 45.79% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_22 1907 8.41% 54.21% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_30 111 0.49% 54.70% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_31 10269 45.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 3740237217 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 3718223353 99.41% 99.41% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 164002 0.00% 99.42% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_30 28353 0.00% 99.42% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 21821509 0.58% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used 0.731359 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_0 0.999038 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.567361 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good_kernel 602 -system.cpu1.kern.mode_good_user 563 -system.cpu1.kern.mode_good_idle 39 -system.cpu1.kern.mode_switch_kernel 1011 # number of protection mode switches -system.cpu1.kern.mode_switch_user 563 # number of protection mode switches -system.cpu1.kern.mode_switch_idle 2045 # number of protection mode switches -system.cpu1.kern.mode_switch_good 0.332689 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.595450 # fraction of useful protection mode switches +system.cpu1.kern.ipl_used_31 0.552542 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good_kernel 613 +system.cpu1.kern.mode_good_user 580 +system.cpu1.kern.mode_good_idle 33 +system.cpu1.kern.mode_switch_kernel 1035 # number of protection mode switches +system.cpu1.kern.mode_switch_user 580 # number of protection mode switches +system.cpu1.kern.mode_switch_idle 2048 # number of protection mode switches +system.cpu1.kern.mode_switch_good 0.334698 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.592271 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_idle 0.019071 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 4872726 0.13% 0.13% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 1950903 0.05% 0.18% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 3710606044 99.82% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 469 # number of times the context was actually changed -system.cpu1.kern.syscall 130 # number of syscalls executed -system.cpu1.kern.syscall_3 13 10.00% 10.00% # number of syscalls executed -system.cpu1.kern.syscall_6 14 10.77% 20.77% # number of syscalls executed -system.cpu1.kern.syscall_15 1 0.77% 21.54% # number of syscalls executed -system.cpu1.kern.syscall_17 11 8.46% 30.00% # number of syscalls executed -system.cpu1.kern.syscall_23 3 2.31% 32.31% # number of syscalls executed -system.cpu1.kern.syscall_24 3 2.31% 34.62% # number of syscalls executed -system.cpu1.kern.syscall_33 5 3.85% 38.46% # number of syscalls executed -system.cpu1.kern.syscall_45 24 18.46% 56.92% # number of syscalls executed -system.cpu1.kern.syscall_47 3 2.31% 59.23% # number of syscalls executed -system.cpu1.kern.syscall_54 1 0.77% 60.00% # number of syscalls executed -system.cpu1.kern.syscall_58 1 0.77% 60.77% # number of syscalls executed -system.cpu1.kern.syscall_59 1 0.77% 61.54% # number of syscalls executed -system.cpu1.kern.syscall_71 34 26.15% 87.69% # number of syscalls executed -system.cpu1.kern.syscall_74 11 8.46% 96.15% # number of syscalls executed -system.cpu1.kern.syscall_92 2 1.54% 97.69% # number of syscalls executed -system.cpu1.kern.syscall_132 3 2.31% 100.00% # number of syscalls executed -system.cpu1.not_idle_fraction 0.002408 # Percentage of non-idle cycles -system.cpu1.numCycles 8953858 # number of cpu cycles simulated -system.cpu1.num_insts 8952271 # Number of instructions executed -system.cpu1.num_refs 2670182 # Number of memory references +system.cpu1.kern.mode_switch_good_idle 0.016113 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks_kernel 2788269 0.07% 0.07% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 1016578 0.03% 0.10% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 3735959544 99.90% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 474 # number of times the context was actually changed +system.cpu1.kern.syscall 100 # number of syscalls executed +system.cpu1.kern.syscall_2 2 2.00% 2.00% # number of syscalls executed +system.cpu1.kern.syscall_3 11 11.00% 13.00% # number of syscalls executed +system.cpu1.kern.syscall_4 2 2.00% 15.00% # number of syscalls executed +system.cpu1.kern.syscall_6 10 10.00% 25.00% # number of syscalls executed +system.cpu1.kern.syscall_17 6 6.00% 31.00% # number of syscalls executed +system.cpu1.kern.syscall_19 2 2.00% 33.00% # number of syscalls executed +system.cpu1.kern.syscall_23 2 2.00% 35.00% # number of syscalls executed +system.cpu1.kern.syscall_24 2 2.00% 37.00% # number of syscalls executed +system.cpu1.kern.syscall_33 4 4.00% 41.00% # number of syscalls executed +system.cpu1.kern.syscall_45 17 17.00% 58.00% # number of syscalls executed +system.cpu1.kern.syscall_47 2 2.00% 60.00% # number of syscalls executed +system.cpu1.kern.syscall_48 2 2.00% 62.00% # number of syscalls executed +system.cpu1.kern.syscall_59 3 3.00% 65.00% # number of syscalls executed +system.cpu1.kern.syscall_71 24 24.00% 89.00% # number of syscalls executed +system.cpu1.kern.syscall_74 8 8.00% 97.00% # number of syscalls executed +system.cpu1.kern.syscall_90 1 1.00% 98.00% # number of syscalls executed +system.cpu1.kern.syscall_132 2 2.00% 100.00% # number of syscalls executed +system.cpu1.not_idle_fraction 0.001597 # Percentage of non-idle cycles +system.cpu1.numCycles 5973832 # number of cpu cycles simulated +system.cpu1.num_insts 5972236 # Number of instructions executed +system.cpu1.num_refs 1937415 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2702336 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 302 # Number of full page size DMA writes. -system.disk0.dma_write_txs 408 # Number of DMA write transactions. +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -226,7 +230,7 @@ system.tsunami.ethernet.coalescedRxIdle # av system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post system.tsunami.ethernet.coalescedRxOrn # average number of RxOrn's coalesced into each post system.tsunami.ethernet.coalescedSwi # average number of Swi's coalesced into each post -system.tsunami.ethernet.coalescedTotal no value # average number of interrupts coalesced into each post +system.tsunami.ethernet.coalescedTotal # average number of interrupts coalesced into each post system.tsunami.ethernet.coalescedTxDesc # average number of TxDesc's coalesced into each post system.tsunami.ethernet.coalescedTxIdle # average number of TxIdle's coalesced into each post system.tsunami.ethernet.coalescedTxOk # average number of TxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr index 9a6301977..2dc23577d 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr @@ -1,8 +1,7 @@ Warning: rounding error > tolerance 0.002000 rounded to 0 - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Listening for console connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 -0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001 +Listening for system connection on port 3457 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 +0: system.remote_gdb.listener: listening for remote gdb on port 7002 warn: Entering event queue @ 0. Starting simulation... warn: 195723: Trying to launch CPU number 1! diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout index 1cecd3a25..fe4bfd9cb 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout @@ -5,8 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 25 2007 15:05:30 -M5 started Thu Jan 25 15:06:16 2007 -M5 executing on zeep -command line: /n/zeep/y/binkertn/build/rtc/build/ALPHA_FS/m5.opt -d /n/zeep/y/binkertn/build/rtc/build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -Exiting @ tick 3718314928 because m5_exit instruction encountered +M5 compiled Apr 22 2007 03:02:42 +M5 started Sun Apr 22 03:06:34 2007 +M5 executing on zed +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual +Global frequency set at 2000000000 ticks per second +Exiting @ tick 3740652145 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index 8cb8b6cbd..26242f3b3 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -1,11 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=2000000000 -max_tick=0 -output_file=cout -progress_interval=0 +dummy=0 [system] type=LinuxAlphaSystem diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out index ab56c5d90..7a0f99013 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=2000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt index a10779a99..2514bef95 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt @@ -1,125 +1,125 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1452138 # Simulator instruction rate (inst/s) -host_mem_usage 239532 # Number of bytes of host memory used -host_seconds 42.57 # Real time elapsed on the host -host_tick_rate 85380734 # Simulator tick rate (ticks/s) +host_inst_rate 424352 # Simulator instruction rate (inst/s) +host_mem_usage 197360 # Number of bytes of host memory used +host_seconds 141.39 # Real time elapsed on the host +host_tick_rate 25861787 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 61811715 # Number of instructions simulated -sim_seconds 1.817169 # Number of seconds simulated -sim_ticks 3634338452 # Number of ticks simulated -system.cpu.dtb.accesses 1304494 # DTB accesses +sim_insts 60000671 # Number of instructions simulated +sim_seconds 1.828353 # Number of seconds simulated +sim_ticks 3656706837 # Number of ticks simulated +system.cpu.dtb.accesses 1020787 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 16556949 # DTB hits -system.cpu.dtb.misses 11425 # DTB misses -system.cpu.dtb.read_accesses 900425 # DTB read accesses +system.cpu.dtb.hits 16052251 # DTB hits +system.cpu.dtb.misses 11471 # DTB misses +system.cpu.dtb.read_accesses 728856 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 10041919 # DTB read hits -system.cpu.dtb.read_misses 10280 # DTB read misses -system.cpu.dtb.write_accesses 404069 # DTB write accesses +system.cpu.dtb.read_hits 9702902 # DTB read hits +system.cpu.dtb.read_misses 10329 # DTB read misses +system.cpu.dtb.write_accesses 291931 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_hits 6515030 # DTB write hits -system.cpu.dtb.write_misses 1145 # DTB write misses -system.cpu.idle_fraction 0.982991 # Percentage of idle cycles -system.cpu.itb.accesses 5655354 # ITB accesses +system.cpu.dtb.write_hits 6349349 # DTB write hits +system.cpu.dtb.write_misses 1142 # DTB write misses +system.cpu.idle_fraction 0.983590 # Percentage of idle cycles +system.cpu.itb.accesses 4978040 # ITB accesses system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 5650364 # ITB hits -system.cpu.itb.misses 4990 # ITB misses -system.cpu.kern.callpal 193847 # number of callpals executed +system.cpu.itb.hits 4973034 # ITB hits +system.cpu.itb.misses 5006 # ITB misses +system.cpu.kern.callpal 192107 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_swpctx 4203 2.17% 2.17% # number of callpals executed -system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed -system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal_swpipl 176756 91.18% 93.38% # number of callpals executed -system.cpu.kern.callpal_rdps 6881 3.55% 96.93% # number of callpals executed -system.cpu.kern.callpal_wrkgp 1 0.00% 96.94% # number of callpals executed -system.cpu.kern.callpal_wrusp 7 0.00% 96.94% # number of callpals executed -system.cpu.kern.callpal_rdusp 9 0.00% 96.94% # number of callpals executed +system.cpu.kern.callpal_swpctx 4180 2.18% 2.18% # number of callpals executed +system.cpu.kern.callpal_tbi 54 0.03% 2.21% # number of callpals executed +system.cpu.kern.callpal_wrent 7 0.00% 2.21% # number of callpals executed +system.cpu.kern.callpal_swpipl 175185 91.19% 93.40% # number of callpals executed +system.cpu.kern.callpal_rdps 6770 3.52% 96.93% # number of callpals executed +system.cpu.kern.callpal_wrkgp 1 0.00% 96.93% # number of callpals executed +system.cpu.kern.callpal_wrusp 7 0.00% 96.93% # number of callpals executed +system.cpu.kern.callpal_rdusp 9 0.00% 96.93% # number of callpals executed system.cpu.kern.callpal_whami 2 0.00% 96.94% # number of callpals executed -system.cpu.kern.callpal_rti 5211 2.69% 99.63% # number of callpals executed -system.cpu.kern.callpal_callsys 531 0.27% 99.91% # number of callpals executed +system.cpu.kern.callpal_rti 5192 2.70% 99.64% # number of callpals executed +system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 212913 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6275 # number of quiesce instructions executed -system.cpu.kern.ipl_count 184066 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 75351 40.94% 40.94% # number of times we switched to this ipl -system.cpu.kern.ipl_count_21 245 0.13% 41.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 1853 1.01% 42.08% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 106617 57.92% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 150066 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 73984 49.30% 49.30% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_21 245 0.16% 49.46% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 1853 1.23% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 73984 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 3634338037 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 3599646965 99.05% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 40474 0.00% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 159358 0.00% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 34491240 0.95% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used 0.815284 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_0 0.981858 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.hwrei 211235 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6241 # number of quiesce instructions executed +system.cpu.kern.ipl_count 182476 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 74792 40.99% 40.99% # number of times we switched to this ipl +system.cpu.kern.ipl_count_21 233 0.13% 41.11% # number of times we switched to this ipl +system.cpu.kern.ipl_count_22 1865 1.02% 42.14% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 105586 57.86% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 148948 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 73425 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_21 233 0.16% 49.45% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_22 1865 1.25% 50.70% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_31 73425 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 3656706422 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 3622173235 99.06% 99.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 38530 0.00% 99.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 160390 0.00% 99.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 34334267 0.94% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used 0.816261 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used_0 0.981723 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.693923 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1937 -system.cpu.kern.mode_good_user 1757 -system.cpu.kern.mode_good_idle 180 -system.cpu.kern.mode_switch_kernel 5978 # number of protection mode switches -system.cpu.kern.mode_switch_user 1757 # number of protection mode switches -system.cpu.kern.mode_switch_idle 2102 # number of protection mode switches -system.cpu.kern.mode_switch_good 0.393819 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.324021 # fraction of useful protection mode switches +system.cpu.kern.ipl_used_31 0.695405 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1907 +system.cpu.kern.mode_good_user 1736 +system.cpu.kern.mode_good_idle 171 +system.cpu.kern.mode_switch_kernel 5941 # number of protection mode switches +system.cpu.kern.mode_switch_user 1736 # number of protection mode switches +system.cpu.kern.mode_switch_idle 2097 # number of protection mode switches +system.cpu.kern.mode_switch_good 0.390219 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.320990 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_idle 0.085633 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 54841721 1.51% 1.51% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 3591234 0.10% 1.61% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 3575905080 98.39% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4204 # number of times the context was actually changed -system.cpu.kern.syscall 329 # number of syscalls executed -system.cpu.kern.syscall_2 8 2.43% 2.43% # number of syscalls executed -system.cpu.kern.syscall_3 30 9.12% 11.55% # number of syscalls executed -system.cpu.kern.syscall_4 4 1.22% 12.77% # number of syscalls executed -system.cpu.kern.syscall_6 43 13.07% 25.84% # number of syscalls executed -system.cpu.kern.syscall_12 1 0.30% 26.14% # number of syscalls executed -system.cpu.kern.syscall_15 1 0.30% 26.44% # number of syscalls executed -system.cpu.kern.syscall_17 15 4.56% 31.00% # number of syscalls executed -system.cpu.kern.syscall_19 10 3.04% 34.04% # number of syscalls executed -system.cpu.kern.syscall_20 6 1.82% 35.87% # number of syscalls executed -system.cpu.kern.syscall_23 4 1.22% 37.08% # number of syscalls executed -system.cpu.kern.syscall_24 6 1.82% 38.91% # number of syscalls executed -system.cpu.kern.syscall_33 11 3.34% 42.25% # number of syscalls executed -system.cpu.kern.syscall_41 2 0.61% 42.86% # number of syscalls executed -system.cpu.kern.syscall_45 55 16.72% 59.57% # number of syscalls executed -system.cpu.kern.syscall_47 6 1.82% 61.40% # number of syscalls executed -system.cpu.kern.syscall_48 10 3.04% 64.44% # number of syscalls executed -system.cpu.kern.syscall_54 10 3.04% 67.48% # number of syscalls executed -system.cpu.kern.syscall_58 1 0.30% 67.78% # number of syscalls executed -system.cpu.kern.syscall_59 7 2.13% 69.91% # number of syscalls executed -system.cpu.kern.syscall_71 54 16.41% 86.32% # number of syscalls executed -system.cpu.kern.syscall_73 3 0.91% 87.23% # number of syscalls executed -system.cpu.kern.syscall_74 16 4.86% 92.10% # number of syscalls executed -system.cpu.kern.syscall_87 1 0.30% 92.40% # number of syscalls executed -system.cpu.kern.syscall_90 3 0.91% 93.31% # number of syscalls executed -system.cpu.kern.syscall_92 10 3.04% 96.35% # number of syscalls executed -system.cpu.kern.syscall_97 2 0.61% 96.96% # number of syscalls executed -system.cpu.kern.syscall_98 2 0.61% 97.57% # number of syscalls executed -system.cpu.kern.syscall_132 4 1.22% 98.78% # number of syscalls executed +system.cpu.kern.mode_switch_good_idle 0.081545 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks_kernel 53661287 1.47% 1.47% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 2930128 0.08% 1.55% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 3600115005 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4181 # number of times the context was actually changed +system.cpu.kern.syscall 326 # number of syscalls executed +system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed +system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed +system.cpu.kern.syscall_4 4 1.23% 12.88% # number of syscalls executed +system.cpu.kern.syscall_6 42 12.88% 25.77% # number of syscalls executed +system.cpu.kern.syscall_12 1 0.31% 26.07% # number of syscalls executed +system.cpu.kern.syscall_15 1 0.31% 26.38% # number of syscalls executed +system.cpu.kern.syscall_17 15 4.60% 30.98% # number of syscalls executed +system.cpu.kern.syscall_19 10 3.07% 34.05% # number of syscalls executed +system.cpu.kern.syscall_20 6 1.84% 35.89% # number of syscalls executed +system.cpu.kern.syscall_23 4 1.23% 37.12% # number of syscalls executed +system.cpu.kern.syscall_24 6 1.84% 38.96% # number of syscalls executed +system.cpu.kern.syscall_33 11 3.37% 42.33% # number of syscalls executed +system.cpu.kern.syscall_41 2 0.61% 42.94% # number of syscalls executed +system.cpu.kern.syscall_45 54 16.56% 59.51% # number of syscalls executed +system.cpu.kern.syscall_47 6 1.84% 61.35% # number of syscalls executed +system.cpu.kern.syscall_48 10 3.07% 64.42% # number of syscalls executed +system.cpu.kern.syscall_54 10 3.07% 67.48% # number of syscalls executed +system.cpu.kern.syscall_58 1 0.31% 67.79% # number of syscalls executed +system.cpu.kern.syscall_59 7 2.15% 69.94% # number of syscalls executed +system.cpu.kern.syscall_71 54 16.56% 86.50% # number of syscalls executed +system.cpu.kern.syscall_73 3 0.92% 87.42% # number of syscalls executed +system.cpu.kern.syscall_74 16 4.91% 92.33% # number of syscalls executed +system.cpu.kern.syscall_87 1 0.31% 92.64% # number of syscalls executed +system.cpu.kern.syscall_90 3 0.92% 93.56% # number of syscalls executed +system.cpu.kern.syscall_92 9 2.76% 96.32% # number of syscalls executed +system.cpu.kern.syscall_97 2 0.61% 96.93% # number of syscalls executed +system.cpu.kern.syscall_98 2 0.61% 97.55% # number of syscalls executed +system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed -system.cpu.not_idle_fraction 0.017009 # Percentage of non-idle cycles -system.cpu.numCycles 61816889 # number of cpu cycles simulated -system.cpu.num_insts 61811715 # Number of instructions executed -system.cpu.num_refs 16805478 # Number of memory references +system.cpu.not_idle_fraction 0.016410 # Percentage of non-idle cycles +system.cpu.numCycles 60005861 # number of cpu cycles simulated +system.cpu.num_insts 60000671 # Number of instructions executed +system.cpu.num_refs 16300569 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2702336 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 302 # Number of full page size DMA writes. -system.disk0.dma_write_txs 408 # Number of DMA write transactions. +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -131,7 +131,7 @@ system.tsunami.ethernet.coalescedRxIdle # av system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post system.tsunami.ethernet.coalescedRxOrn # average number of RxOrn's coalesced into each post system.tsunami.ethernet.coalescedSwi # average number of Swi's coalesced into each post -system.tsunami.ethernet.coalescedTotal no value # average number of interrupts coalesced into each post +system.tsunami.ethernet.coalescedTotal # average number of interrupts coalesced into each post system.tsunami.ethernet.coalescedTxDesc # average number of TxDesc's coalesced into each post system.tsunami.ethernet.coalescedTxIdle # average number of TxIdle's coalesced into each post system.tsunami.ethernet.coalescedTxOk # average number of TxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr index 69304a604..bffa97023 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr @@ -1,6 +1,5 @@ Warning: rounding error > tolerance 0.002000 rounded to 0 - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Listening for console connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 +Listening for system connection on port 3456 +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout index 631453025..802d081ea 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout @@ -5,8 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 25 2007 15:05:30 -M5 started Thu Jan 25 15:05:33 2007 -M5 executing on zeep -command line: /n/zeep/y/binkertn/build/rtc/build/ALPHA_FS/m5.opt -d /n/zeep/y/binkertn/build/rtc/build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -Exiting @ tick 3634338452 because m5_exit instruction encountered +M5 compiled Apr 22 2007 03:02:42 +M5 started Sun Apr 22 03:06:33 2007 +M5 executing on zed +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic +Global frequency set at 2000000000 ticks per second +Exiting @ tick 3656706837 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 856856ae8..b24dc5968 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -1,11 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=2000000000 -max_tick=0 -output_file=cout -progress_interval=0 +dummy=0 [system] type=LinuxAlphaSystem diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out index a4dd003e4..b41d5083f 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=2000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt index d6bc028f1..b2e9ad6be 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt @@ -1,228 +1,228 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 359240 # Simulator instruction rate (inst/s) -host_mem_usage 240844 # Number of bytes of host memory used -host_seconds 186.42 # Real time elapsed on the host -host_tick_rate 21297758 # Simulator tick rate (ticks/s) +host_inst_rate 93328 # Simulator instruction rate (inst/s) +host_mem_usage 194108 # Number of bytes of host memory used +host_seconds 698.07 # Real time elapsed on the host +host_tick_rate 5697629 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 66968427 # Number of instructions simulated -sim_seconds 1.985132 # Number of seconds simulated -sim_ticks 3970264174 # Number of ticks simulated -system.cpu0.dtb.accesses 1003481 # DTB accesses -system.cpu0.dtb.acv 289 # DTB access violations -system.cpu0.dtb.hits 13332650 # DTB hits -system.cpu0.dtb.misses 8437 # DTB misses -system.cpu0.dtb.read_accesses 695694 # DTB read accesses -system.cpu0.dtb.read_acv 174 # DTB read access violations -system.cpu0.dtb.read_hits 8285777 # DTB read hits -system.cpu0.dtb.read_misses 7640 # DTB read misses -system.cpu0.dtb.write_accesses 307787 # DTB write accesses -system.cpu0.dtb.write_acv 115 # DTB write access violations -system.cpu0.dtb.write_hits 5046873 # DTB write hits -system.cpu0.dtb.write_misses 797 # DTB write misses -system.cpu0.idle_fraction 0.928155 # Percentage of idle cycles -system.cpu0.itb.accesses 4220935 # ITB accesses -system.cpu0.itb.acv 143 # ITB acv -system.cpu0.itb.hits 4217111 # ITB hits -system.cpu0.itb.misses 3824 # ITB misses -system.cpu0.kern.callpal 144637 # number of callpals executed +sim_insts 65149483 # Number of instructions simulated +sim_seconds 1.988682 # Number of seconds simulated +sim_ticks 3977364188 # Number of ticks simulated +system.cpu0.dtb.accesses 676531 # DTB accesses +system.cpu0.dtb.acv 306 # DTB access violations +system.cpu0.dtb.hits 12726689 # DTB hits +system.cpu0.dtb.misses 8261 # DTB misses +system.cpu0.dtb.read_accesses 494241 # DTB read accesses +system.cpu0.dtb.read_acv 184 # DTB read access violations +system.cpu0.dtb.read_hits 7906502 # DTB read hits +system.cpu0.dtb.read_misses 7534 # DTB read misses +system.cpu0.dtb.write_accesses 182290 # DTB write accesses +system.cpu0.dtb.write_acv 122 # DTB write access violations +system.cpu0.dtb.write_hits 4820187 # DTB write hits +system.cpu0.dtb.write_misses 727 # DTB write misses +system.cpu0.idle_fraction 0.930926 # Percentage of idle cycles +system.cpu0.itb.accesses 3412074 # ITB accesses +system.cpu0.itb.acv 161 # ITB acv +system.cpu0.itb.hits 3408241 # ITB hits +system.cpu0.itb.misses 3833 # ITB misses +system.cpu0.kern.callpal 142537 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal_wripir 571 0.39% 0.40% # number of callpals executed +system.cpu0.kern.callpal_wripir 572 0.40% 0.40% # number of callpals executed system.cpu0.kern.callpal_wrmces 1 0.00% 0.40% # number of callpals executed system.cpu0.kern.callpal_wrfen 1 0.00% 0.40% # number of callpals executed system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.40% # number of callpals executed -system.cpu0.kern.callpal_swpctx 2907 2.01% 2.41% # number of callpals executed -system.cpu0.kern.callpal_tbi 44 0.03% 2.44% # number of callpals executed -system.cpu0.kern.callpal_wrent 7 0.00% 2.44% # number of callpals executed -system.cpu0.kern.callpal_swpipl 129633 89.63% 92.07% # number of callpals executed -system.cpu0.kern.callpal_rdps 6650 4.60% 96.67% # number of callpals executed -system.cpu0.kern.callpal_wrkgp 1 0.00% 96.67% # number of callpals executed -system.cpu0.kern.callpal_wrusp 4 0.00% 96.67% # number of callpals executed -system.cpu0.kern.callpal_rdusp 7 0.00% 96.68% # number of callpals executed -system.cpu0.kern.callpal_whami 2 0.00% 96.68% # number of callpals executed -system.cpu0.kern.callpal_rti 4286 2.96% 99.64% # number of callpals executed -system.cpu0.kern.callpal_callsys 372 0.26% 99.90% # number of callpals executed -system.cpu0.kern.callpal_imb 149 0.10% 100.00% # number of callpals executed +system.cpu0.kern.callpal_swpctx 2878 2.02% 2.42% # number of callpals executed +system.cpu0.kern.callpal_tbi 47 0.03% 2.46% # number of callpals executed +system.cpu0.kern.callpal_wrent 7 0.00% 2.46% # number of callpals executed +system.cpu0.kern.callpal_swpipl 127687 89.58% 92.04% # number of callpals executed +system.cpu0.kern.callpal_rdps 6611 4.64% 96.68% # number of callpals executed +system.cpu0.kern.callpal_wrkgp 1 0.00% 96.68% # number of callpals executed +system.cpu0.kern.callpal_wrusp 3 0.00% 96.68% # number of callpals executed +system.cpu0.kern.callpal_rdusp 8 0.01% 96.69% # number of callpals executed +system.cpu0.kern.callpal_whami 2 0.00% 96.69% # number of callpals executed +system.cpu0.kern.callpal_rti 4215 2.96% 99.65% # number of callpals executed +system.cpu0.kern.callpal_callsys 355 0.25% 99.90% # number of callpals executed +system.cpu0.kern.callpal_imb 147 0.10% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 159963 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6648 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 136551 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 54497 39.91% 39.91% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_21 143 0.10% 40.01% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_22 2005 1.47% 41.48% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_30 483 0.35% 41.84% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 79423 58.16% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 110306 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 54079 49.03% 49.03% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_21 143 0.13% 49.16% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_22 2005 1.82% 50.97% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_30 483 0.44% 51.41% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 53596 48.59% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 3970262390 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 3836377682 96.63% 96.63% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 133000 0.00% 96.63% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 1870128 0.05% 96.68% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 1206048 0.03% 96.71% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 130675532 3.29% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used 0.807801 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_0 0.992330 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.hwrei 157722 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6621 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 134525 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 53714 39.93% 39.93% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_21 131 0.10% 40.03% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_22 2009 1.49% 41.52% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_30 482 0.36% 41.88% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 78189 58.12% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 108736 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 53298 49.02% 49.02% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_21 131 0.12% 49.14% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_22 2009 1.85% 50.98% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_30 482 0.44% 51.43% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_31 52816 48.57% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 3976579702 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 3843539628 96.65% 96.65% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 123584 0.00% 96.66% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 1875640 0.05% 96.70% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 1201752 0.03% 96.73% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 129839098 3.27% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used 0.808296 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_0 0.992255 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.674817 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1253 -system.cpu0.kern.mode_good_user 1254 +system.cpu0.kern.ipl_used_31 0.675491 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1191 +system.cpu0.kern.mode_good_user 1191 system.cpu0.kern.mode_good_idle 0 -system.cpu0.kern.mode_switch_kernel 6799 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1254 # number of protection mode switches +system.cpu0.kern.mode_switch_kernel 6700 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1191 # number of protection mode switches system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good 0.311313 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.184292 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good 0.301863 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.177761 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 3956507378 99.65% 99.65% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 13755004 0.35% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_kernel 3965298428 99.76% 99.76% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 9599262 0.24% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2908 # number of times the context was actually changed -system.cpu0.kern.syscall 227 # number of syscalls executed -system.cpu0.kern.syscall_2 6 2.64% 2.64% # number of syscalls executed -system.cpu0.kern.syscall_3 19 8.37% 11.01% # number of syscalls executed -system.cpu0.kern.syscall_4 3 1.32% 12.33% # number of syscalls executed -system.cpu0.kern.syscall_6 31 13.66% 25.99% # number of syscalls executed -system.cpu0.kern.syscall_12 1 0.44% 26.43% # number of syscalls executed -system.cpu0.kern.syscall_15 1 0.44% 26.87% # number of syscalls executed -system.cpu0.kern.syscall_17 10 4.41% 31.28% # number of syscalls executed -system.cpu0.kern.syscall_19 6 2.64% 33.92% # number of syscalls executed -system.cpu0.kern.syscall_20 4 1.76% 35.68% # number of syscalls executed -system.cpu0.kern.syscall_23 2 0.88% 36.56% # number of syscalls executed -system.cpu0.kern.syscall_24 4 1.76% 38.33% # number of syscalls executed -system.cpu0.kern.syscall_33 8 3.52% 41.85% # number of syscalls executed -system.cpu0.kern.syscall_41 2 0.88% 42.73% # number of syscalls executed -system.cpu0.kern.syscall_45 40 17.62% 60.35% # number of syscalls executed -system.cpu0.kern.syscall_47 4 1.76% 62.11% # number of syscalls executed -system.cpu0.kern.syscall_48 7 3.08% 65.20% # number of syscalls executed -system.cpu0.kern.syscall_54 9 3.96% 69.16% # number of syscalls executed -system.cpu0.kern.syscall_58 1 0.44% 69.60% # number of syscalls executed -system.cpu0.kern.syscall_59 5 2.20% 71.81% # number of syscalls executed -system.cpu0.kern.syscall_71 32 14.10% 85.90% # number of syscalls executed -system.cpu0.kern.syscall_73 3 1.32% 87.22% # number of syscalls executed -system.cpu0.kern.syscall_74 9 3.96% 91.19% # number of syscalls executed -system.cpu0.kern.syscall_87 1 0.44% 91.63% # number of syscalls executed -system.cpu0.kern.syscall_90 2 0.88% 92.51% # number of syscalls executed -system.cpu0.kern.syscall_92 8 3.52% 96.04% # number of syscalls executed -system.cpu0.kern.syscall_97 2 0.88% 96.92% # number of syscalls executed -system.cpu0.kern.syscall_98 2 0.88% 97.80% # number of syscalls executed -system.cpu0.kern.syscall_132 2 0.88% 98.68% # number of syscalls executed -system.cpu0.kern.syscall_144 1 0.44% 99.12% # number of syscalls executed -system.cpu0.kern.syscall_147 2 0.88% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.071845 # Percentage of non-idle cycles -system.cpu0.numCycles 3970264174 # number of cpu cycles simulated -system.cpu0.num_insts 52311968 # Number of instructions executed -system.cpu0.num_refs 13564877 # Number of memory references -system.cpu1.dtb.accesses 302962 # DTB accesses -system.cpu1.dtb.acv 84 # DTB access violations -system.cpu1.dtb.hits 4640482 # DTB hits -system.cpu1.dtb.misses 3107 # DTB misses -system.cpu1.dtb.read_accesses 205912 # DTB read accesses -system.cpu1.dtb.read_acv 36 # DTB read access violations -system.cpu1.dtb.read_hits 2668410 # DTB read hits -system.cpu1.dtb.read_misses 2747 # DTB read misses -system.cpu1.dtb.write_accesses 97050 # DTB write accesses -system.cpu1.dtb.write_acv 48 # DTB write access violations -system.cpu1.dtb.write_hits 1972072 # DTB write hits -system.cpu1.dtb.write_misses 360 # DTB write misses -system.cpu1.idle_fraction 0.974914 # Percentage of idle cycles -system.cpu1.itb.accesses 1965758 # ITB accesses -system.cpu1.itb.acv 41 # ITB acv -system.cpu1.itb.hits 1964511 # ITB hits -system.cpu1.itb.misses 1247 # ITB misses -system.cpu1.kern.callpal 80671 # number of callpals executed +system.cpu0.kern.swap_context 2879 # number of times the context was actually changed +system.cpu0.kern.syscall 216 # number of syscalls executed +system.cpu0.kern.syscall_2 7 3.24% 3.24% # number of syscalls executed +system.cpu0.kern.syscall_3 18 8.33% 11.57% # number of syscalls executed +system.cpu0.kern.syscall_4 3 1.39% 12.96% # number of syscalls executed +system.cpu0.kern.syscall_6 30 13.89% 26.85% # number of syscalls executed +system.cpu0.kern.syscall_12 1 0.46% 27.31% # number of syscalls executed +system.cpu0.kern.syscall_15 1 0.46% 27.78% # number of syscalls executed +system.cpu0.kern.syscall_17 9 4.17% 31.94% # number of syscalls executed +system.cpu0.kern.syscall_19 6 2.78% 34.72% # number of syscalls executed +system.cpu0.kern.syscall_20 4 1.85% 36.57% # number of syscalls executed +system.cpu0.kern.syscall_23 2 0.93% 37.50% # number of syscalls executed +system.cpu0.kern.syscall_24 4 1.85% 39.35% # number of syscalls executed +system.cpu0.kern.syscall_33 7 3.24% 42.59% # number of syscalls executed +system.cpu0.kern.syscall_41 2 0.93% 43.52% # number of syscalls executed +system.cpu0.kern.syscall_45 36 16.67% 60.19% # number of syscalls executed +system.cpu0.kern.syscall_47 4 1.85% 62.04% # number of syscalls executed +system.cpu0.kern.syscall_48 8 3.70% 65.74% # number of syscalls executed +system.cpu0.kern.syscall_54 9 4.17% 69.91% # number of syscalls executed +system.cpu0.kern.syscall_58 1 0.46% 70.37% # number of syscalls executed +system.cpu0.kern.syscall_59 6 2.78% 73.15% # number of syscalls executed +system.cpu0.kern.syscall_71 28 12.96% 86.11% # number of syscalls executed +system.cpu0.kern.syscall_73 3 1.39% 87.50% # number of syscalls executed +system.cpu0.kern.syscall_74 8 3.70% 91.20% # number of syscalls executed +system.cpu0.kern.syscall_87 1 0.46% 91.67% # number of syscalls executed +system.cpu0.kern.syscall_90 2 0.93% 92.59% # number of syscalls executed +system.cpu0.kern.syscall_92 7 3.24% 95.83% # number of syscalls executed +system.cpu0.kern.syscall_97 2 0.93% 96.76% # number of syscalls executed +system.cpu0.kern.syscall_98 2 0.93% 97.69% # number of syscalls executed +system.cpu0.kern.syscall_132 2 0.93% 98.61% # number of syscalls executed +system.cpu0.kern.syscall_144 1 0.46% 99.07% # number of syscalls executed +system.cpu0.kern.syscall_147 2 0.93% 100.00% # number of syscalls executed +system.cpu0.not_idle_fraction 0.069074 # Percentage of non-idle cycles +system.cpu0.numCycles 3976579942 # number of cpu cycles simulated +system.cpu0.num_insts 50251013 # Number of instructions executed +system.cpu0.num_refs 12958414 # Number of memory references +system.cpu1.dtb.accesses 346252 # DTB accesses +system.cpu1.dtb.acv 67 # DTB access violations +system.cpu1.dtb.hits 4740978 # DTB hits +system.cpu1.dtb.misses 3345 # DTB misses +system.cpu1.dtb.read_accesses 235843 # DTB read accesses +system.cpu1.dtb.read_acv 26 # DTB read access violations +system.cpu1.dtb.read_hits 2707473 # DTB read hits +system.cpu1.dtb.read_misses 2918 # DTB read misses +system.cpu1.dtb.write_accesses 110409 # DTB write accesses +system.cpu1.dtb.write_acv 41 # DTB write access violations +system.cpu1.dtb.write_hits 2033505 # DTB write hits +system.cpu1.dtb.write_misses 427 # DTB write misses +system.cpu1.idle_fraction 0.974575 # Percentage of idle cycles +system.cpu1.itb.accesses 2097220 # ITB accesses +system.cpu1.itb.acv 23 # ITB acv +system.cpu1.itb.hits 2095948 # ITB hits +system.cpu1.itb.misses 1272 # ITB misses +system.cpu1.kern.callpal 80965 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal_wripir 483 0.60% 0.60% # number of callpals executed +system.cpu1.kern.callpal_wripir 482 0.60% 0.60% # number of callpals executed system.cpu1.kern.callpal_wrmces 1 0.00% 0.60% # number of callpals executed system.cpu1.kern.callpal_wrfen 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal_swpctx 2277 2.82% 3.43% # number of callpals executed -system.cpu1.kern.callpal_tbi 10 0.01% 3.44% # number of callpals executed -system.cpu1.kern.callpal_wrent 7 0.01% 3.45% # number of callpals executed -system.cpu1.kern.callpal_swpipl 71267 88.34% 91.79% # number of callpals executed -system.cpu1.kern.callpal_rdps 2378 2.95% 94.74% # number of callpals executed -system.cpu1.kern.callpal_wrkgp 1 0.00% 94.74% # number of callpals executed -system.cpu1.kern.callpal_wrusp 3 0.00% 94.74% # number of callpals executed -system.cpu1.kern.callpal_rdusp 2 0.00% 94.74% # number of callpals executed -system.cpu1.kern.callpal_whami 3 0.00% 94.75% # number of callpals executed -system.cpu1.kern.callpal_rti 4044 5.01% 99.76% # number of callpals executed -system.cpu1.kern.callpal_callsys 161 0.20% 99.96% # number of callpals executed -system.cpu1.kern.callpal_imb 31 0.04% 100.00% # number of callpals executed +system.cpu1.kern.callpal_swpctx 2289 2.83% 3.43% # number of callpals executed +system.cpu1.kern.callpal_tbi 7 0.01% 3.43% # number of callpals executed +system.cpu1.kern.callpal_wrent 7 0.01% 3.44% # number of callpals executed +system.cpu1.kern.callpal_swpipl 71577 88.40% 91.85% # number of callpals executed +system.cpu1.kern.callpal_rdps 2303 2.84% 94.69% # number of callpals executed +system.cpu1.kern.callpal_wrkgp 1 0.00% 94.69% # number of callpals executed +system.cpu1.kern.callpal_wrusp 4 0.00% 94.70% # number of callpals executed +system.cpu1.kern.callpal_rdusp 1 0.00% 94.70% # number of callpals executed +system.cpu1.kern.callpal_whami 3 0.00% 94.70% # number of callpals executed +system.cpu1.kern.callpal_rti 4092 5.05% 99.76% # number of callpals executed +system.cpu1.kern.callpal_callsys 162 0.20% 99.96% # number of callpals executed +system.cpu1.kern.callpal_imb 33 0.04% 100.00% # number of callpals executed system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 87720 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 2808 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 77880 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 30262 38.86% 38.86% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_22 1997 2.56% 41.42% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_30 571 0.73% 42.15% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 45050 57.85% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 60603 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 29303 48.35% 48.35% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_22 1997 3.30% 51.65% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_30 571 0.94% 52.59% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 28732 47.41% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 3968772136 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 3846937158 96.93% 96.93% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 1867822 0.05% 96.98% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 1457952 0.04% 97.01% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 118509204 2.99% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used 0.778159 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_0 0.968310 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.hwrei 88247 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 2815 # number of quiesce instructions executed +system.cpu1.kern.ipl_count 78243 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 30463 38.93% 38.93% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_22 2001 2.56% 41.49% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_30 572 0.73% 42.22% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_31 45207 57.78% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 61005 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 29502 48.36% 48.36% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_22 2001 3.28% 51.64% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_30 572 0.94% 52.58% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_31 28930 47.42% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 3977362404 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 3855394306 96.93% 96.93% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 1873360 0.05% 96.98% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_30 1461344 0.04% 97.02% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 118633394 2.98% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used 0.779686 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_0 0.968454 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.637780 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good_kernel 1014 -system.cpu1.kern.mode_good_user 519 -system.cpu1.kern.mode_good_idle 495 -system.cpu1.kern.mode_switch_kernel 2345 # number of protection mode switches -system.cpu1.kern.mode_switch_user 519 # number of protection mode switches -system.cpu1.kern.mode_switch_idle 3028 # number of protection mode switches -system.cpu1.kern.mode_switch_good 0.344196 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.432409 # fraction of useful protection mode switches +system.cpu1.kern.ipl_used_31 0.639945 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good_kernel 1058 +system.cpu1.kern.mode_good_user 562 +system.cpu1.kern.mode_good_idle 496 +system.cpu1.kern.mode_switch_kernel 2397 # number of protection mode switches +system.cpu1.kern.mode_switch_user 562 # number of protection mode switches +system.cpu1.kern.mode_switch_idle 3035 # number of protection mode switches +system.cpu1.kern.mode_switch_good 0.353020 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.441385 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_idle 0.163474 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 63257834 1.59% 1.59% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 5106070 0.13% 1.72% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 3899443084 98.28% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2278 # number of times the context was actually changed -system.cpu1.kern.syscall 102 # number of syscalls executed -system.cpu1.kern.syscall_2 2 1.96% 1.96% # number of syscalls executed -system.cpu1.kern.syscall_3 11 10.78% 12.75% # number of syscalls executed -system.cpu1.kern.syscall_4 1 0.98% 13.73% # number of syscalls executed -system.cpu1.kern.syscall_6 12 11.76% 25.49% # number of syscalls executed -system.cpu1.kern.syscall_17 5 4.90% 30.39% # number of syscalls executed -system.cpu1.kern.syscall_19 4 3.92% 34.31% # number of syscalls executed -system.cpu1.kern.syscall_20 2 1.96% 36.27% # number of syscalls executed -system.cpu1.kern.syscall_23 2 1.96% 38.24% # number of syscalls executed -system.cpu1.kern.syscall_24 2 1.96% 40.20% # number of syscalls executed -system.cpu1.kern.syscall_33 3 2.94% 43.14% # number of syscalls executed -system.cpu1.kern.syscall_45 15 14.71% 57.84% # number of syscalls executed -system.cpu1.kern.syscall_47 2 1.96% 59.80% # number of syscalls executed -system.cpu1.kern.syscall_48 3 2.94% 62.75% # number of syscalls executed -system.cpu1.kern.syscall_54 1 0.98% 63.73% # number of syscalls executed -system.cpu1.kern.syscall_59 2 1.96% 65.69% # number of syscalls executed -system.cpu1.kern.syscall_71 22 21.57% 87.25% # number of syscalls executed -system.cpu1.kern.syscall_74 7 6.86% 94.12% # number of syscalls executed -system.cpu1.kern.syscall_90 1 0.98% 95.10% # number of syscalls executed -system.cpu1.kern.syscall_92 2 1.96% 97.06% # number of syscalls executed -system.cpu1.kern.syscall_132 2 1.96% 99.02% # number of syscalls executed -system.cpu1.kern.syscall_144 1 0.98% 100.00% # number of syscalls executed -system.cpu1.not_idle_fraction 0.025086 # Percentage of non-idle cycles -system.cpu1.numCycles 3968772376 # number of cpu cycles simulated -system.cpu1.num_insts 14656459 # Number of instructions executed -system.cpu1.num_refs 4670067 # Number of memory references +system.cpu1.kern.mode_switch_good_idle 0.163427 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks_kernel 64042452 1.61% 1.61% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 5753306 0.14% 1.75% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 3907566638 98.25% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2290 # number of times the context was actually changed +system.cpu1.kern.syscall 110 # number of syscalls executed +system.cpu1.kern.syscall_2 1 0.91% 0.91% # number of syscalls executed +system.cpu1.kern.syscall_3 12 10.91% 11.82% # number of syscalls executed +system.cpu1.kern.syscall_4 1 0.91% 12.73% # number of syscalls executed +system.cpu1.kern.syscall_6 12 10.91% 23.64% # number of syscalls executed +system.cpu1.kern.syscall_17 6 5.45% 29.09% # number of syscalls executed +system.cpu1.kern.syscall_19 4 3.64% 32.73% # number of syscalls executed +system.cpu1.kern.syscall_20 2 1.82% 34.55% # number of syscalls executed +system.cpu1.kern.syscall_23 2 1.82% 36.36% # number of syscalls executed +system.cpu1.kern.syscall_24 2 1.82% 38.18% # number of syscalls executed +system.cpu1.kern.syscall_33 4 3.64% 41.82% # number of syscalls executed +system.cpu1.kern.syscall_45 18 16.36% 58.18% # number of syscalls executed +system.cpu1.kern.syscall_47 2 1.82% 60.00% # number of syscalls executed +system.cpu1.kern.syscall_48 2 1.82% 61.82% # number of syscalls executed +system.cpu1.kern.syscall_54 1 0.91% 62.73% # number of syscalls executed +system.cpu1.kern.syscall_59 1 0.91% 63.64% # number of syscalls executed +system.cpu1.kern.syscall_71 26 23.64% 87.27% # number of syscalls executed +system.cpu1.kern.syscall_74 8 7.27% 94.55% # number of syscalls executed +system.cpu1.kern.syscall_90 1 0.91% 95.45% # number of syscalls executed +system.cpu1.kern.syscall_92 2 1.82% 97.27% # number of syscalls executed +system.cpu1.kern.syscall_132 2 1.82% 99.09% # number of syscalls executed +system.cpu1.kern.syscall_144 1 0.91% 100.00% # number of syscalls executed +system.cpu1.not_idle_fraction 0.025425 # Percentage of non-idle cycles +system.cpu1.numCycles 3977364188 # number of cpu cycles simulated +system.cpu1.num_insts 14898470 # Number of instructions executed +system.cpu1.num_refs 4770918 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2702336 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 302 # Number of full page size DMA writes. -system.disk0.dma_write_txs 408 # Number of DMA write transactions. +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -234,7 +234,7 @@ system.tsunami.ethernet.coalescedRxIdle # av system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post system.tsunami.ethernet.coalescedRxOrn # average number of RxOrn's coalesced into each post system.tsunami.ethernet.coalescedSwi # average number of Swi's coalesced into each post -system.tsunami.ethernet.coalescedTotal no value # average number of interrupts coalesced into each post +system.tsunami.ethernet.coalescedTotal # average number of interrupts coalesced into each post system.tsunami.ethernet.coalescedTxDesc # average number of TxDesc's coalesced into each post system.tsunami.ethernet.coalescedTxIdle # average number of TxIdle's coalesced into each post system.tsunami.ethernet.coalescedTxOk # average number of TxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr index 5b02d9b91..8aa8d4104 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr @@ -1,8 +1,7 @@ Warning: rounding error > tolerance 0.002000 rounded to 0 - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Listening for console connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 -0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001 +Listening for system connection on port 3456 +0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... warn: 1082476: Trying to launch CPU number 1! diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout index 9c25032e4..933603fb1 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout @@ -5,8 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 25 2007 15:05:30 -M5 started Thu Jan 25 15:09:33 2007 -M5 executing on zeep -command line: /n/zeep/y/binkertn/build/rtc/build/ALPHA_FS/m5.opt -d /n/zeep/y/binkertn/build/rtc/build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -Exiting @ tick 3970264174 because m5_exit instruction encountered +M5 compiled Apr 22 2007 03:02:42 +M5 started Sun Apr 22 03:17:05 2007 +M5 executing on zed +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual +Global frequency set at 2000000000 ticks per second +Exiting @ tick 3977364188 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index 6f48977b0..9edee8632 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -1,11 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=2000000000 -max_tick=0 -output_file=cout -progress_interval=0 +dummy=0 [system] type=LinuxAlphaSystem diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out index a99b59ae7..ad8a29167 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=2000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt index 75746eadf..c26624f69 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt @@ -1,125 +1,125 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 469266 # Simulator instruction rate (inst/s) -host_mem_usage 238376 # Number of bytes of host memory used -host_seconds 131.89 # Real time elapsed on the host -host_tick_rate 29380471 # Simulator tick rate (ticks/s) +host_inst_rate 133073 # Simulator instruction rate (inst/s) +host_mem_usage 193848 # Number of bytes of host memory used +host_seconds 451.52 # Real time elapsed on the host +host_tick_rate 8600063 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 61893104 # Number of instructions simulated -sim_seconds 1.937550 # Number of seconds simulated -sim_ticks 3875100962 # Number of ticks simulated -system.cpu.dtb.accesses 1304554 # DTB accesses +sim_insts 60085145 # Number of instructions simulated +sim_seconds 1.941556 # Number of seconds simulated +sim_ticks 3883111644 # Number of ticks simulated +system.cpu.dtb.accesses 1020793 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 16571487 # DTB hits -system.cpu.dtb.misses 11447 # DTB misses -system.cpu.dtb.read_accesses 900486 # DTB read accesses +system.cpu.dtb.hits 16070587 # DTB hits +system.cpu.dtb.misses 11472 # DTB misses +system.cpu.dtb.read_accesses 728862 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 10051940 # DTB read hits -system.cpu.dtb.read_misses 10303 # DTB read misses -system.cpu.dtb.write_accesses 404068 # DTB write accesses +system.cpu.dtb.read_hits 9714704 # DTB read hits +system.cpu.dtb.read_misses 10330 # DTB read misses +system.cpu.dtb.write_accesses 291931 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_hits 6519547 # DTB write hits -system.cpu.dtb.write_misses 1144 # DTB write misses -system.cpu.idle_fraction 0.918919 # Percentage of idle cycles -system.cpu.itb.accesses 5664253 # ITB accesses +system.cpu.dtb.write_hits 6355883 # DTB write hits +system.cpu.dtb.write_misses 1142 # DTB write misses +system.cpu.idle_fraction 0.921464 # Percentage of idle cycles +system.cpu.itb.accesses 4985774 # ITB accesses system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 5659250 # ITB hits -system.cpu.itb.misses 5003 # ITB misses -system.cpu.kern.callpal 195265 # number of callpals executed +system.cpu.itb.hits 4980764 # ITB hits +system.cpu.itb.misses 5010 # ITB misses +system.cpu.kern.callpal 193469 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_swpctx 4161 2.13% 2.13% # number of callpals executed -system.cpu.kern.callpal_tbi 54 0.03% 2.16% # number of callpals executed -system.cpu.kern.callpal_wrent 7 0.00% 2.16% # number of callpals executed -system.cpu.kern.callpal_swpipl 178117 91.22% 93.38% # number of callpals executed -system.cpu.kern.callpal_rdps 6978 3.57% 96.96% # number of callpals executed -system.cpu.kern.callpal_wrkgp 1 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal_wrusp 7 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal_swpctx 4148 2.14% 2.15% # number of callpals executed +system.cpu.kern.callpal_tbi 54 0.03% 2.17% # number of callpals executed +system.cpu.kern.callpal_wrent 7 0.00% 2.18% # number of callpals executed +system.cpu.kern.callpal_swpipl 176495 91.23% 93.40% # number of callpals executed +system.cpu.kern.callpal_rdps 6860 3.55% 96.95% # number of callpals executed +system.cpu.kern.callpal_wrkgp 1 0.00% 96.95% # number of callpals executed +system.cpu.kern.callpal_wrusp 7 0.00% 96.95% # number of callpals executed system.cpu.kern.callpal_rdusp 9 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal_whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal_rti 5213 2.67% 99.64% # number of callpals executed -system.cpu.kern.callpal_callsys 531 0.27% 99.91% # number of callpals executed +system.cpu.kern.callpal_whami 2 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal_rti 5186 2.68% 99.64% # number of callpals executed +system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 214368 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6180 # number of quiesce instructions executed -system.cpu.kern.ipl_count 185431 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 75630 40.79% 40.79% # number of times we switched to this ipl -system.cpu.kern.ipl_count_21 143 0.08% 40.86% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 1957 1.06% 41.92% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 107701 58.08% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 150626 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 74263 49.30% 49.30% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_21 143 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 1957 1.30% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 74263 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 3875099178 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 3747191842 96.70% 96.70% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 122728 0.00% 96.70% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 915876 0.02% 96.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 126868732 3.27% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used 0.812302 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_0 0.981925 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.hwrei 212596 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6154 # number of quiesce instructions executed +system.cpu.kern.ipl_count 183774 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 75067 40.85% 40.85% # number of times we switched to this ipl +system.cpu.kern.ipl_count_21 131 0.07% 40.92% # number of times we switched to this ipl +system.cpu.kern.ipl_count_22 1961 1.07% 41.99% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 106615 58.01% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 149492 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 73700 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_21 131 0.09% 49.39% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_22 1961 1.31% 50.70% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_31 73700 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 3883109860 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 3755985580 96.73% 96.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 112456 0.00% 96.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 918754 0.02% 96.75% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 126093070 3.25% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used 0.813456 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used_0 0.981790 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.689529 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1926 -system.cpu.kern.mode_good_user 1765 -system.cpu.kern.mode_good_idle 161 -system.cpu.kern.mode_switch_kernel 5968 # number of protection mode switches -system.cpu.kern.mode_switch_user 1765 # number of protection mode switches -system.cpu.kern.mode_switch_idle 2072 # number of protection mode switches -system.cpu.kern.mode_switch_good 0.392861 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.322721 # fraction of useful protection mode switches +system.cpu.kern.ipl_used_31 0.691272 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1897 +system.cpu.kern.mode_good_user 1742 +system.cpu.kern.mode_good_idle 155 +system.cpu.kern.mode_switch_kernel 5935 # number of protection mode switches +system.cpu.kern.mode_switch_user 1742 # number of protection mode switches +system.cpu.kern.mode_switch_idle 2065 # number of protection mode switches +system.cpu.kern.mode_switch_good 0.389448 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.319629 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_idle 0.077703 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 118484404 3.06% 3.06% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 18744972 0.48% 3.54% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 3737869794 96.46% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4162 # number of times the context was actually changed -system.cpu.kern.syscall 329 # number of syscalls executed -system.cpu.kern.syscall_2 8 2.43% 2.43% # number of syscalls executed -system.cpu.kern.syscall_3 30 9.12% 11.55% # number of syscalls executed -system.cpu.kern.syscall_4 4 1.22% 12.77% # number of syscalls executed -system.cpu.kern.syscall_6 43 13.07% 25.84% # number of syscalls executed -system.cpu.kern.syscall_12 1 0.30% 26.14% # number of syscalls executed -system.cpu.kern.syscall_15 1 0.30% 26.44% # number of syscalls executed -system.cpu.kern.syscall_17 15 4.56% 31.00% # number of syscalls executed -system.cpu.kern.syscall_19 10 3.04% 34.04% # number of syscalls executed -system.cpu.kern.syscall_20 6 1.82% 35.87% # number of syscalls executed -system.cpu.kern.syscall_23 4 1.22% 37.08% # number of syscalls executed -system.cpu.kern.syscall_24 6 1.82% 38.91% # number of syscalls executed -system.cpu.kern.syscall_33 11 3.34% 42.25% # number of syscalls executed -system.cpu.kern.syscall_41 2 0.61% 42.86% # number of syscalls executed -system.cpu.kern.syscall_45 55 16.72% 59.57% # number of syscalls executed -system.cpu.kern.syscall_47 6 1.82% 61.40% # number of syscalls executed -system.cpu.kern.syscall_48 10 3.04% 64.44% # number of syscalls executed -system.cpu.kern.syscall_54 10 3.04% 67.48% # number of syscalls executed -system.cpu.kern.syscall_58 1 0.30% 67.78% # number of syscalls executed -system.cpu.kern.syscall_59 7 2.13% 69.91% # number of syscalls executed -system.cpu.kern.syscall_71 54 16.41% 86.32% # number of syscalls executed -system.cpu.kern.syscall_73 3 0.91% 87.23% # number of syscalls executed -system.cpu.kern.syscall_74 16 4.86% 92.10% # number of syscalls executed -system.cpu.kern.syscall_87 1 0.30% 92.40% # number of syscalls executed -system.cpu.kern.syscall_90 3 0.91% 93.31% # number of syscalls executed -system.cpu.kern.syscall_92 10 3.04% 96.35% # number of syscalls executed -system.cpu.kern.syscall_97 2 0.61% 96.96% # number of syscalls executed -system.cpu.kern.syscall_98 2 0.61% 97.57% # number of syscalls executed -system.cpu.kern.syscall_132 4 1.22% 98.78% # number of syscalls executed +system.cpu.kern.mode_switch_good_idle 0.075061 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks_kernel 112874078 2.91% 2.91% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 15210360 0.39% 3.30% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 3755025414 96.70% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4149 # number of times the context was actually changed +system.cpu.kern.syscall 326 # number of syscalls executed +system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed +system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed +system.cpu.kern.syscall_4 4 1.23% 12.88% # number of syscalls executed +system.cpu.kern.syscall_6 42 12.88% 25.77% # number of syscalls executed +system.cpu.kern.syscall_12 1 0.31% 26.07% # number of syscalls executed +system.cpu.kern.syscall_15 1 0.31% 26.38% # number of syscalls executed +system.cpu.kern.syscall_17 15 4.60% 30.98% # number of syscalls executed +system.cpu.kern.syscall_19 10 3.07% 34.05% # number of syscalls executed +system.cpu.kern.syscall_20 6 1.84% 35.89% # number of syscalls executed +system.cpu.kern.syscall_23 4 1.23% 37.12% # number of syscalls executed +system.cpu.kern.syscall_24 6 1.84% 38.96% # number of syscalls executed +system.cpu.kern.syscall_33 11 3.37% 42.33% # number of syscalls executed +system.cpu.kern.syscall_41 2 0.61% 42.94% # number of syscalls executed +system.cpu.kern.syscall_45 54 16.56% 59.51% # number of syscalls executed +system.cpu.kern.syscall_47 6 1.84% 61.35% # number of syscalls executed +system.cpu.kern.syscall_48 10 3.07% 64.42% # number of syscalls executed +system.cpu.kern.syscall_54 10 3.07% 67.48% # number of syscalls executed +system.cpu.kern.syscall_58 1 0.31% 67.79% # number of syscalls executed +system.cpu.kern.syscall_59 7 2.15% 69.94% # number of syscalls executed +system.cpu.kern.syscall_71 54 16.56% 86.50% # number of syscalls executed +system.cpu.kern.syscall_73 3 0.92% 87.42% # number of syscalls executed +system.cpu.kern.syscall_74 16 4.91% 92.33% # number of syscalls executed +system.cpu.kern.syscall_87 1 0.31% 92.64% # number of syscalls executed +system.cpu.kern.syscall_90 3 0.92% 93.56% # number of syscalls executed +system.cpu.kern.syscall_92 9 2.76% 96.32% # number of syscalls executed +system.cpu.kern.syscall_97 2 0.61% 96.93% # number of syscalls executed +system.cpu.kern.syscall_98 2 0.61% 97.55% # number of syscalls executed +system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed -system.cpu.not_idle_fraction 0.081081 # Percentage of non-idle cycles -system.cpu.numCycles 3875100962 # number of cpu cycles simulated -system.cpu.num_insts 61893104 # Number of instructions executed -system.cpu.num_refs 16819569 # Number of memory references +system.cpu.not_idle_fraction 0.078536 # Percentage of non-idle cycles +system.cpu.numCycles 3883111644 # number of cpu cycles simulated +system.cpu.num_insts 60085145 # Number of instructions executed +system.cpu.num_refs 16318523 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2702336 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 302 # Number of full page size DMA writes. -system.disk0.dma_write_txs 408 # Number of DMA write transactions. +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -131,7 +131,7 @@ system.tsunami.ethernet.coalescedRxIdle # av system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post system.tsunami.ethernet.coalescedRxOrn # average number of RxOrn's coalesced into each post system.tsunami.ethernet.coalescedSwi # average number of Swi's coalesced into each post -system.tsunami.ethernet.coalescedTotal no value # average number of interrupts coalesced into each post +system.tsunami.ethernet.coalescedTotal # average number of interrupts coalesced into each post system.tsunami.ethernet.coalescedTxDesc # average number of TxDesc's coalesced into each post system.tsunami.ethernet.coalescedTxIdle # average number of TxIdle's coalesced into each post system.tsunami.ethernet.coalescedTxOk # average number of TxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr index 69304a604..738a31460 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr @@ -1,6 +1,5 @@ Warning: rounding error > tolerance 0.002000 rounded to 0 - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Listening for console connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 +Listening for system connection on port 3457 +0: system.remote_gdb.listener: listening for remote gdb on port 7002 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout index 206c366c1..2f1756e4d 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout @@ -5,8 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 25 2007 15:05:30 -M5 started Thu Jan 25 15:07:20 2007 -M5 executing on zeep -command line: /n/zeep/y/binkertn/build/rtc/build/ALPHA_FS/m5.opt -d /n/zeep/y/binkertn/build/rtc/build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing -Exiting @ tick 3875100962 because m5_exit instruction encountered +M5 compiled Apr 22 2007 03:02:42 +M5 started Sun Apr 22 03:17:05 2007 +M5 executing on zed +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing +Global frequency set at 2000000000 ticks per second +Exiting @ tick 3883111644 because m5_exit instruction encountered diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini index 2750dd3c0..c10da1360 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini @@ -1,11 +1,7 @@ [root] type=Root children=drivesys etherdump etherlink testsys -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 +dummy=0 [drivesys] type=LinuxAlphaSystem @@ -18,7 +14,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=drivesys.physmem -readfile=/z/saidi/work/m5.newmem/configs/boot/netperf-server.rcS +readfile=/z/hsul/work/m5/newmem/configs/boot/netperf-server.rcS symbolfile= system_rev=1024 system_type=34 @@ -214,7 +210,7 @@ dma_read_delay=0 dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 -hardware_address=00:90:00:00:00:02 +hardware_address=00:90:00:00:00:01 intr_delay=10000000 pci_bus=0 pci_dev=1 @@ -697,7 +693,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=testsys.physmem -readfile=/z/saidi/work/m5.newmem/configs/boot/netperf-stream-client.rcS +readfile=/z/hsul/work/m5/newmem/configs/boot/netperf-stream-client.rcS symbolfile= system_rev=1024 system_type=34 diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out index c422f07ac..4c39b0d8d 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [testsys.physmem] type=PhysicalMemory @@ -21,7 +18,7 @@ kernel=/dist/m5/system/binaries/vmlinux console=/dist/m5/system/binaries/console pal=/dist/m5/system/binaries/ts_osfpal boot_osflags=root=/dev/hda1 console=ttyS0 -readfile=/z/saidi/work/m5.newmem/configs/boot/netperf-stream-client.rcS +readfile=/z/hsul/work/m5/newmem/configs/boot/netperf-stream-client.rcS symbolfile= init_param=0 system_type=34 @@ -635,7 +632,7 @@ kernel=/dist/m5/system/binaries/vmlinux console=/dist/m5/system/binaries/console pal=/dist/m5/system/binaries/ts_osfpal boot_osflags=root=/dev/hda1 console=ttyS0 -readfile=/z/saidi/work/m5.newmem/configs/boot/netperf-server.rcS +readfile=/z/hsul/work/m5/newmem/configs/boot/netperf-server.rcS symbolfile= init_param=0 system_type=34 @@ -709,7 +706,7 @@ tx_delay=1000000 rx_fifo_size=524288 tx_fifo_size=524288 rx_filter=true -hardware_address=00:90:00:00:00:02 +hardware_address=00:90:00:00:00:01 rx_thread=false tx_thread=false rss=false diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt index 585dfef42..87f656822 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt @@ -2,15 +2,15 @@ ---------- Begin Simulation Statistics ---------- drivesys.cpu.dtb.accesses 401302 # DTB accesses drivesys.cpu.dtb.acv 40 # DTB access violations -drivesys.cpu.dtb.hits 624298 # DTB hits +drivesys.cpu.dtb.hits 624235 # DTB hits drivesys.cpu.dtb.misses 569 # DTB misses drivesys.cpu.dtb.read_accesses 268057 # DTB read accesses drivesys.cpu.dtb.read_acv 30 # DTB read access violations -drivesys.cpu.dtb.read_hits 393538 # DTB read hits +drivesys.cpu.dtb.read_hits 393500 # DTB read hits drivesys.cpu.dtb.read_misses 487 # DTB read misses drivesys.cpu.dtb.write_accesses 133245 # DTB write accesses drivesys.cpu.dtb.write_acv 10 # DTB write access violations -drivesys.cpu.dtb.write_hits 230760 # DTB write hits +drivesys.cpu.dtb.write_hits 230735 # DTB write hits drivesys.cpu.dtb.write_misses 82 # DTB write misses drivesys.cpu.idle_fraction 1.000000 # Percentage of idle cycles drivesys.cpu.itb.accesses 1337980 # ITB accesses @@ -39,11 +39,11 @@ drivesys.cpu.kern.ipl_good_0 1189 45.85% 45.85% # nu drivesys.cpu.kern.ipl_good_21 10 0.39% 46.24% # number of times we switched to this ipl from a different ipl drivesys.cpu.kern.ipl_good_22 205 7.91% 54.15% # number of times we switched to this ipl from a different ipl drivesys.cpu.kern.ipl_good_31 1189 45.85% 100.00% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_ticks 199572064521 # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks_0 199571744558 100.00% 100.00% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks 199572064520 # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks_0 199571744808 100.00% 100.00% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks_21 1620 0.00% 100.00% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks_31 300713 0.00% 100.00% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks_31 300462 0.00% 100.00% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_used 0.618707 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used_0 1 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl @@ -59,7 +59,7 @@ drivesys.cpu.kern.mode_switch_good 0.440882 # fr drivesys.cpu.kern.mode_switch_good_kernel 0.632184 # fraction of useful protection mode switches drivesys.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches drivesys.cpu.kern.mode_switch_good_idle 0.013761 # fraction of useful protection mode switches -drivesys.cpu.kern.mode_ticks_kernel 263475 0.24% 0.24% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks_kernel 263256 0.24% 0.24% # number of ticks spent at the given mode drivesys.cpu.kern.mode_ticks_user 1278343 1.18% 1.43% # number of ticks spent at the given mode drivesys.cpu.kern.mode_ticks_idle 106485080 98.57% 100.00% # number of ticks spent at the given mode drivesys.cpu.kern.swap_context 70 # number of times the context was actually changed @@ -77,9 +77,9 @@ drivesys.cpu.kern.syscall_106 1 4.55% 86.36% # nu drivesys.cpu.kern.syscall_118 2 9.09% 95.45% # number of syscalls executed drivesys.cpu.kern.syscall_150 1 4.55% 100.00% # number of syscalls executed drivesys.cpu.not_idle_fraction 0.000000 # Percentage of non-idle cycles -drivesys.cpu.numCycles 1959205 # number of cpu cycles simulated -drivesys.cpu.num_insts 1958989 # Number of instructions executed -drivesys.cpu.num_refs 626286 # Number of memory references +drivesys.cpu.numCycles 1958954 # number of cpu cycles simulated +drivesys.cpu.num_insts 1958738 # Number of instructions executed +drivesys.cpu.num_refs 626223 # Number of memory references drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -140,35 +140,35 @@ drivesys.tsunami.ethernet.txPPS 25 # Pa drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -host_inst_rate 65873683 # Simulator instruction rate (inst/s) -host_mem_usage 463096 # Number of bytes of host memory used -host_seconds 4.19 # Real time elapsed on the host -host_tick_rate 47718011872 # Simulator tick rate (ticks/s) +host_inst_rate 17087768 # Simulator instruction rate (inst/s) +host_mem_usage 406052 # Number of bytes of host memory used +host_seconds 16.00 # Real time elapsed on the host +host_tick_rate 12499419683 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 276082930 # Number of instructions simulated +sim_insts 273411112 # Number of instructions simulated sim_seconds 0.200001 # Number of seconds simulated sim_ticks 200000789468 # Number of ticks simulated testsys.cpu.dtb.accesses 335402 # DTB accesses testsys.cpu.dtb.acv 161 # DTB access violations -testsys.cpu.dtb.hits 1163399 # DTB hits +testsys.cpu.dtb.hits 1163686 # DTB hits testsys.cpu.dtb.misses 3815 # DTB misses testsys.cpu.dtb.read_accesses 225414 # DTB read accesses testsys.cpu.dtb.read_acv 80 # DTB read access violations -testsys.cpu.dtb.read_hits 658556 # DTB read hits +testsys.cpu.dtb.read_hits 658686 # DTB read hits testsys.cpu.dtb.read_misses 3287 # DTB read misses testsys.cpu.dtb.write_accesses 109988 # DTB write accesses testsys.cpu.dtb.write_acv 81 # DTB write access violations -testsys.cpu.dtb.write_hits 504843 # DTB write hits +testsys.cpu.dtb.write_hits 505000 # DTB write hits testsys.cpu.dtb.write_misses 528 # DTB write misses testsys.cpu.idle_fraction 0.999999 # Percentage of idle cycles -testsys.cpu.itb.accesses 1249804 # ITB accesses +testsys.cpu.itb.accesses 1249822 # ITB accesses testsys.cpu.itb.acv 69 # ITB acv -testsys.cpu.itb.hits 1248307 # ITB hits +testsys.cpu.itb.hits 1248325 # ITB hits testsys.cpu.itb.misses 1497 # ITB misses -testsys.cpu.kern.callpal 13124 # number of callpals executed +testsys.cpu.kern.callpal 13126 # number of callpals executed testsys.cpu.kern.callpal_swpctx 440 3.35% 3.35% # number of callpals executed -testsys.cpu.kern.callpal_tbi 20 0.15% 3.51% # number of callpals executed -testsys.cpu.kern.callpal_swpipl 11075 84.39% 87.89% # number of callpals executed +testsys.cpu.kern.callpal_tbi 20 0.15% 3.50% # number of callpals executed +testsys.cpu.kern.callpal_swpipl 11077 84.39% 87.89% # number of callpals executed testsys.cpu.kern.callpal_rdps 359 2.74% 90.63% # number of callpals executed testsys.cpu.kern.callpal_wrusp 3 0.02% 90.65% # number of callpals executed testsys.cpu.kern.callpal_rdusp 3 0.02% 90.67% # number of callpals executed @@ -176,28 +176,28 @@ testsys.cpu.kern.callpal_rti 1040 7.92% 98.60% # nu testsys.cpu.kern.callpal_callsys 140 1.07% 99.66% # number of callpals executed testsys.cpu.kern.callpal_imb 44 0.34% 100.00% # number of callpals executed testsys.cpu.kern.inst.arm 0 # number of arm instructions executed -testsys.cpu.kern.inst.hwrei 19054 # number of hwrei instructions executed +testsys.cpu.kern.inst.hwrei 19056 # number of hwrei instructions executed testsys.cpu.kern.inst.quiesce 377 # number of quiesce instructions executed -testsys.cpu.kern.ipl_count 12503 # number of times we switched to this ipl -testsys.cpu.kern.ipl_count_0 5061 40.48% 40.48% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count 12505 # number of times we switched to this ipl +testsys.cpu.kern.ipl_count_0 5061 40.47% 40.47% # number of times we switched to this ipl testsys.cpu.kern.ipl_count_21 183 1.46% 41.94% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count_22 205 1.64% 43.58% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count_31 7054 56.42% 100.00% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count_22 205 1.64% 43.57% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count_31 7056 56.43% 100.00% # number of times we switched to this ipl testsys.cpu.kern.ipl_good 10498 # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good_0 5055 48.15% 48.15% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good_21 183 1.74% 49.90% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good_22 205 1.95% 51.85% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good_31 5055 48.15% 100.00% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_ticks 199569923816 # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks_0 199569308246 100.00% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks 199569923781 # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks_0 199569307594 100.00% 100.00% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_ticks_21 30857 0.00% 100.00% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks_31 567083 0.00% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_used 0.839638 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_ticks_31 567700 0.00% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_used 0.839504 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used_0 0.998814 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used_31 0.716615 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used_31 0.716412 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.mode_good_kernel 654 testsys.cpu.kern.mode_good_user 649 testsys.cpu.kern.mode_good_idle 5 @@ -208,9 +208,9 @@ testsys.cpu.kern.mode_switch_good 0.614085 # fr testsys.cpu.kern.mode_switch_good_kernel 0.594545 # fraction of useful protection mode switches testsys.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches testsys.cpu.kern.mode_switch_good_idle 0.013123 # fraction of useful protection mode switches -testsys.cpu.kern.mode_ticks_kernel 1821166 2.16% 2.16% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks_user 1065606 1.26% 3.42% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks_idle 81403516 96.58% 100.00% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks_kernel 1821815 2.16% 2.16% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks_user 1065606 1.26% 3.43% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks_idle 81402910 96.57% 100.00% # number of ticks spent at the given mode testsys.cpu.kern.swap_context 440 # number of times the context was actually changed testsys.cpu.kern.syscall 83 # number of syscalls executed testsys.cpu.kern.syscall_2 3 3.61% 3.61% # number of syscalls executed @@ -235,9 +235,9 @@ testsys.cpu.kern.syscall_104 1 1.20% 93.98% # nu testsys.cpu.kern.syscall_105 3 3.61% 97.59% # number of syscalls executed testsys.cpu.kern.syscall_118 2 2.41% 100.00% # number of syscalls executed testsys.cpu.not_idle_fraction 0.000001 # Percentage of non-idle cycles -testsys.cpu.numCycles 3566149 # number of cpu cycles simulated -testsys.cpu.num_insts 3564583 # Number of instructions executed -testsys.cpu.num_refs 1173698 # Number of memory references +testsys.cpu.numCycles 3566766 # number of cpu cycles simulated +testsys.cpu.num_insts 3565200 # Number of instructions executed +testsys.cpu.num_refs 1173985 # Number of memory references testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -357,10 +357,10 @@ drivesys.tsunami.ethernet.coalescedRxIdle # a drivesys.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post drivesys.tsunami.ethernet.coalescedRxOrn # average number of RxOrn's coalesced into each post drivesys.tsunami.ethernet.coalescedSwi # average number of Swi's coalesced into each post -drivesys.tsunami.ethernet.coalescedTotal no value # average number of interrupts coalesced into each post -drivesys.tsunami.ethernet.coalescedTxDesc no value # average number of TxDesc's coalesced into each post -drivesys.tsunami.ethernet.coalescedTxIdle no value # average number of TxIdle's coalesced into each post -drivesys.tsunami.ethernet.coalescedTxOk no value # average number of TxOk's coalesced into each post +drivesys.tsunami.ethernet.coalescedTotal # average number of interrupts coalesced into each post +drivesys.tsunami.ethernet.coalescedTxDesc # average number of TxDesc's coalesced into each post +drivesys.tsunami.ethernet.coalescedTxIdle # average number of TxIdle's coalesced into each post +drivesys.tsunami.ethernet.coalescedTxOk # average number of TxOk's coalesced into each post drivesys.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA drivesys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA drivesys.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -383,12 +383,12 @@ drivesys.tsunami.ethernet.totalSwi 0 # to drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -host_inst_rate 145844125726 # Simulator instruction rate (inst/s) -host_mem_usage 463096 # Number of bytes of host memory used -host_seconds 0.00 # Real time elapsed on the host -host_tick_rate 385283333 # Simulator tick rate (ticks/s) +host_inst_rate 45169521229 # Simulator instruction rate (inst/s) +host_mem_usage 406052 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 123213356 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 276082930 # Number of instructions simulated +sim_insts 273411112 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated sim_ticks 785978 # Number of ticks simulated testsys.cpu.dtb.accesses 0 # DTB accesses @@ -446,10 +446,10 @@ testsys.tsunami.ethernet.coalescedRxIdle # av testsys.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post testsys.tsunami.ethernet.coalescedRxOrn # average number of RxOrn's coalesced into each post testsys.tsunami.ethernet.coalescedSwi # average number of Swi's coalesced into each post -testsys.tsunami.ethernet.coalescedTotal no value # average number of interrupts coalesced into each post -testsys.tsunami.ethernet.coalescedTxDesc no value # average number of TxDesc's coalesced into each post -testsys.tsunami.ethernet.coalescedTxIdle no value # average number of TxIdle's coalesced into each post -testsys.tsunami.ethernet.coalescedTxOk no value # average number of TxOk's coalesced into each post +testsys.tsunami.ethernet.coalescedTotal # average number of interrupts coalesced into each post +testsys.tsunami.ethernet.coalescedTxDesc # average number of TxDesc's coalesced into each post +testsys.tsunami.ethernet.coalescedTxIdle # average number of TxIdle's coalesced into each post +testsys.tsunami.ethernet.coalescedTxOk # average number of TxOk's coalesced into each post testsys.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA testsys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA testsys.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr index 0be24123b..5d8bcbd75 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr @@ -1,8 +1,6 @@ - 0: testsys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Listening for console connection on port 3456 - 0: drivesys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Listening for console connection on port 3457 -0: testsys.remote_gdb.listener: listening for remote gdb #0 on port 7000 -0: drivesys.remote_gdb.listener: listening for remote gdb #1 on port 7001 +Listening for testsys connection on port 3457 +Listening for drivesys connection on port 3458 +0: testsys.remote_gdb.listener: listening for remote gdb on port 7002 +0: drivesys.remote_gdb.listener: listening for remote gdb on port 7003 warn: Entering event queue @ 0. Starting simulation... warn: Obsolete M5 instruction ivlb encountered. diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout index e529ca1ae..20cc93dd8 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 25 2007 15:05:30 -M5 started Thu Jan 25 15:12:40 2007 -M5 executing on zeep -command line: /n/zeep/y/binkertn/build/rtc/build/ALPHA_FS/m5.opt -d /n/zeep/y/binkertn/build/rtc/build/ALPHA_FS/tests/opt/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -Resetting stats at cycle 4093398828093! -Resetting stats at cycle 4293399617561! -Exiting @ tick 4293400403539 because checkpoint +M5 compiled Apr 22 2007 03:02:42 +M5 started Sun Apr 22 03:24:38 2007 +M5 executing on zed +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 4300236341073 because checkpoint From c47804002aa8ae456ac95b8ee7be06cc56ca1b34 Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Mon, 23 Apr 2007 16:03:53 -0400 Subject: [PATCH 22/68] Fix the splash2 run script --HG-- extra : convert_revision : 2b5f6718ac93d3d1b9b1d1b290f1ff5fa10cd0d8 --- configs/splash2/run.py | 80 ++++++++++++++++++++++++++---------------- 1 file changed, 50 insertions(+), 30 deletions(-) diff --git a/configs/splash2/run.py b/configs/splash2/run.py index b162e0cc7..d051f1f1b 100644 --- a/configs/splash2/run.py +++ b/configs/splash2/run.py @@ -1,4 +1,4 @@ -# Copyright (c) 2005-2006 The Regents of The University of Michigan +# Copyright (c) 2005-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -60,7 +60,7 @@ parser.add_option("--l2size", parser.add_option("--l2latency", default = 10) parser.add_option("--rootdir", - help="ROot directory of Splash2", + help="Root directory of Splash2", default="/dist/splash2/codes") parser.add_option("-b", "--benchmark", help="Splash 2 benchmark to run") @@ -79,59 +79,79 @@ if not options.numcpus: # Define Splash2 Benchmarks # ==================== class Cholesky(LiveProcess): - executable = options.rootdir + '/kernels/cholesky/CHOLESKY' - cmd = 'CHOLESKY -p' + str(options.numcpus) + ' '\ - + options.rootdir + '/kernels/cholesky/inputs/tk23.O' + cwd = options.rootdir + '/kernels/cholesky' + executable = options.rootdir + '/kernels/cholesky/CHOLESKY' + cmd = 'CHOLESKY -p' + str(options.numcpus) + ' '\ + + options.rootdir + '/kernels/cholesky/inputs/tk23.O' class FFT(LiveProcess): - executable = options.rootdir + '/kernels/fft/FFT' - cmd = 'FFT -p' + str(options.numcpus) + ' -m18' + cwd = options.rootdir + '/kernels/fft' + executable = options.rootdir + '/kernels/fft/FFT' + cmd = 'FFT -p' + str(options.numcpus) + ' -m18' class LU_contig(LiveProcess): - executable = options.rootdir + '/kernels/lu/contiguous_blocks/LU' - cmd = 'LU -p' + str(options.numcpus) + executable = options.rootdir + '/kernels/lu/contiguous_blocks/LU' + cmd = 'LU -p' + str(options.numcpus) + cwd = options.rootdir + '/kernels/lu/contiguous_blocks' class LU_noncontig(LiveProcess): - executable = options.rootdir + '/kernels/lu/non_contiguous_blocks/LU' - cmd = 'LU -p' + str(options.numcpus) + executable = options.rootdir + '/kernels/lu/non_contiguous_blocks/LU' + cmd = 'LU -p' + str(options.numcpus) + cwd = options.rootdir + '/kernels/lu/non_contiguous_blocks' class Radix(LiveProcess): - executable = options.rootdir + '/kernels/radix/RADIX' - cmd = 'RADIX -n524288 -p' + str(options.numcpus) + executable = options.rootdir + '/kernels/radix/RADIX' + cmd = 'RADIX -n524288 -p' + str(options.numcpus) + cwd = options.rootdir + '/kernels/radix' class Barnes(LiveProcess): - executable = options.rootdir + '/apps/barnes/BARNES' - cmd = 'BARNES' - input = options.rootdir + '/apps/barnes/input.p' + str(options.numcpus) + executable = options.rootdir + '/apps/barnes/BARNES' + cmd = 'BARNES' + input = options.rootdir + '/apps/barnes/input.p' + str(options.numcpus) + cwd = options.rootdir + '/apps/barnes' class FMM(LiveProcess): - executable = options.rootdir + '/apps/fmm/FMM' - cmd = 'FMM' + executable = options.rootdir + '/apps/fmm/FMM' + cmd = 'FMM' + if str(options.numcpus) == '1': + input = options.rootdir + '/apps/fmm/inputs/input.2048' + else: input = options.rootdir + '/apps/fmm/inputs/input.2048.p' + str(options.numcpus) + cwd = options.rootdir + '/apps/fmm' class Ocean_contig(LiveProcess): - executable = options.rootdir + '/apps/ocean/contiguous_partitions/OCEAN' - cmd = 'OCEAN -p' + str(options.numcpus) + executable = options.rootdir + '/apps/ocean/contiguous_partitions/OCEAN' + cmd = 'OCEAN -p' + str(options.numcpus) + cwd = options.rootdir + '/apps/ocean/contiguous_partitions' class Ocean_noncontig(LiveProcess): - executable = options.rootdir + '/apps/ocean/non_contiguous_partitions/OCEAN' - cmd = 'OCEAN -p' + str(options.numcpus) + executable = options.rootdir + '/apps/ocean/non_contiguous_partitions/OCEAN' + cmd = 'OCEAN -p' + str(options.numcpus) + cwd = options.rootdir + '/apps/ocean/non_contiguous_partitions' class Raytrace(LiveProcess): - executable = options.rootdir + '/apps/raytrace/RAYTRACE' - cmd = 'RAYTRACE -p' + str(options.numcpus) + ' ' \ - + options.rootdir + 'apps/raytrace/inputs/teapot.env' + executable = options.rootdir + '/apps/raytrace/RAYTRACE' + cmd = 'RAYTRACE -p' + str(options.numcpus) + ' ' \ + + options.rootdir + '/apps/raytrace/inputs/teapot.env' + cwd = options.rootdir + '/apps/raytrace' class Water_nsquared(LiveProcess): - executable = options.rootdir + '/apps/water-nsquared/WATER-NSQUARED' - cmd = 'WATER-NSQUARED' + executable = options.rootdir + '/apps/water-nsquared/WATER-NSQUARED' + cmd = 'WATER-NSQUARED' + if options.numcpus==1: + input = options.rootdir + '/apps/water-nsquared/input' + else: input = options.rootdir + '/apps/water-nsquared/input.p' + str(options.numcpus) + cwd = options.rootdir + '/apps/water-nsquared' class Water_spatial(LiveProcess): - executable = options.rootdir + '/apps/water-spatial/WATER-SPATIAL' - cmd = 'WATER-SPATIAL' + executable = options.rootdir + '/apps/water-spatial/WATER-SPATIAL' + cmd = 'WATER-SPATIAL' + if options.numcpus==1: + input = options.rootdir + '/apps/water-spatial/input' + else: input = options.rootdir + '/apps/water-spatial/input.p' + str(options.numcpus) - + cwd = options.rootdir + '/apps/water-spatial' # -------------------- # Base L1 Cache Definition From 15cc194d714ce9c3f5fe706487534ed447847d88 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Thu, 26 Apr 2007 00:02:37 -0400 Subject: [PATCH 23/68] Remove unnecessary check. --HG-- extra : convert_revision : 8cc2943ebc41e4d430789ee7923dd0dc878be06b --- src/cpu/o3/commit_impl.hh | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index 65625065d..dd4c333d3 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -641,9 +641,6 @@ DefaultCommit::handleInterrupt() // an interrupt needed to be handled. DPRINTF(Commit, "Interrupt detected.\n"); - Fault new_interrupt = cpu->getInterrupts(); - assert(new_interrupt != NoFault); - // Clear the interrupt now that it's going to be handled toIEW->commitInfo[0].clearInterrupt = true; From 092951e2b1daab7049608b35b723f318d2fac948 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Thu, 26 Apr 2007 00:07:42 -0400 Subject: [PATCH 24/68] Remove extra delete that was causing segfault. --HG-- extra : convert_revision : 8a27ed80308c95988f3bc43d670dc0ac9e946d39 --- src/cpu/o3/lsq_unit_impl.hh | 1 - 1 file changed, 1 deletion(-) diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index 44e2cea76..bde4f8079 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -680,7 +680,6 @@ LSQUnit::writebackStores() inst->seqNum); WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); wb->schedule(curTick + 1); - delete state; completeStore(storeWBIdx); incrStIdx(storeWBIdx); continue; From 522e59840f2d3c44d7d95ebc44b44abebb1212c9 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Thu, 26 Apr 2007 00:10:06 -0400 Subject: [PATCH 25/68] Fix mutex test script for latest disk image. --HG-- extra : convert_revision : 1b0a251046674db1be8c9a2c026ff8c17f9cea06 --- configs/boot/mutex-test.rcS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/boot/mutex-test.rcS b/configs/boot/mutex-test.rcS index acf875368..798986c02 100644 --- a/configs/boot/mutex-test.rcS +++ b/configs/boot/mutex-test.rcS @@ -1,6 +1,6 @@ #!/bin/sh -cd /benchmarks/tests +cd /benchmarks /sbin/m5 resetstats ./pthread_mutex_test 4 10000 /sbin/m5 exit From 0ae6f0343941d777b593efe42b8e287d4f59f0c2 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Fri, 27 Apr 2007 11:15:15 -0700 Subject: [PATCH 26/68] Make sure that we don't rebuild libelf stuff that we don't have to since it doesn't work well on non-linux --HG-- extra : convert_revision : 2f1f81f756cccf25f1b2b04e6b5ca4b7a20e96b7 --- util/make_release.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/util/make_release.py b/util/make_release.py index 7362bd77c..250ee56ac 100755 --- a/util/make_release.py +++ b/util/make_release.py @@ -113,6 +113,10 @@ system('bk export -tplain -w -r+ %s' % release_dir) # make sure scons doesn't try to run flex unnecessarily touch(release_dir, 'src/encumbered/eio/exolex.cc') +# make sure scons doesn't try to rebuild the de.msg file since it +# might fail on non linux machines +touch(release_dir, 'ext/libelf/po/de.msg') + # get rid of non-shipping code rmtree(release_dir, 'src/encumbered/dev') rmtree(release_dir, 'src/cpu/ozone') From 0ce183da3018c76f555e54872f7f023050a2aae2 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Fri, 27 Apr 2007 11:16:20 -0700 Subject: [PATCH 27/68] Update release notes --HG-- extra : convert_revision : d57ffff1a35443214d8fe24d6388daa99b1d747d --- RELEASE_NOTES | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/RELEASE_NOTES b/RELEASE_NOTES index eebe0eb57..47507ba3b 100644 --- a/RELEASE_NOTES +++ b/RELEASE_NOTES @@ -7,12 +7,21 @@ Bug fixes since beta 2: 1. Many SPARC linux syscall emulation support fixes 2. Multiprocessor linux boot using the detailed O3 CPU module 3. Simulator performance and memory leak fixes -4. Fix issues with remote debugging -5. Many other minor fixes and enhancements +4. Fix issues with remote debugging +5. Several compile fixes, including gcc 4.1 +6. Many other minor fixes and enhancements Outstanding issues for 2.0 release: -------------------- -1. ??? +1. Better statistics for the caches. +2. Clean up more SimObject parameter stuff +3. Checkpoint/switchover testing +4. FS mode doesn't work under Cygwin +5. memtest regression crashes under Cygwin +6. Make repository public +7. Testing +8. Validation +9. Testing Nov. 28, 2006: m5_2.0_beta2 -------------------- From 7f39291c81cb65dc166926136c8f3cab253df160 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Fri, 27 Apr 2007 14:35:58 -0400 Subject: [PATCH 28/68] Update Alpha reference stats for clock changes. tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini: tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out: tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini: tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out: tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr: tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini: tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out: tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt: tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr: tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini: tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out: tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout: tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini: tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out: tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr: tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout: tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini: tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out: tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt: tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr: tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout: tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini: tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out: tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr: tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini: tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out: tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt: tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr: tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini: tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out: tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg: tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini: tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out: tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr: tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini: tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out: tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt: tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr: tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini: tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out: tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini: tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out: tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr: tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini: tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out: tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt: tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr: tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini: tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out: tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini: tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out: tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out: tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr: tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini: tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out: tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt: tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out: tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr: Update refs for clock changes. --HG-- extra : convert_revision : 7c32a3362da60fd12b7bf9219842f707319cda42 --- .../ref/alpha/tru64/o3-timing/config.ini | 2 +- .../ref/alpha/tru64/o3-timing/config.out | 2 +- .../ref/alpha/tru64/o3-timing/m5stats.txt | 561 +++++++++-------- .../ref/alpha/tru64/simple-atomic/config.ini | 57 +- .../ref/alpha/tru64/simple-atomic/config.out | 58 +- .../ref/alpha/tru64/simple-atomic/m5stats.txt | 12 +- .../ref/alpha/tru64/simple-atomic/stderr | 1 + .../ref/alpha/tru64/simple-timing/config.ini | 57 +- .../ref/alpha/tru64/simple-timing/config.out | 58 +- .../ref/alpha/tru64/simple-timing/m5stats.txt | 106 ++-- .../ref/alpha/tru64/simple-timing/stderr | 1 + .../ref/alpha/tru64/o3-timing/config.ini | 2 +- .../ref/alpha/tru64/o3-timing/config.out | 2 +- .../ref/alpha/tru64/o3-timing/m5stats.txt | 573 +++++++++-------- .../30.eon/ref/alpha/tru64/o3-timing/stdout | 2 +- .../ref/alpha/tru64/simple-atomic/config.ini | 57 +- .../ref/alpha/tru64/simple-atomic/config.out | 58 +- .../ref/alpha/tru64/simple-atomic/m5stats.txt | 20 +- .../ref/alpha/tru64/simple-atomic/stderr | 2 + .../ref/alpha/tru64/simple-atomic/stdout | 2 +- .../ref/alpha/tru64/simple-timing/config.ini | 34 +- .../ref/alpha/tru64/simple-timing/config.out | 31 +- .../ref/alpha/tru64/simple-timing/m5stats.txt | 210 +++---- .../ref/alpha/tru64/simple-timing/stderr | 3 +- .../ref/alpha/tru64/simple-timing/stdout | 2 +- .../ref/alpha/tru64/simple-atomic/config.ini | 34 +- .../ref/alpha/tru64/simple-atomic/config.out | 31 +- .../ref/alpha/tru64/simple-atomic/m5stats.txt | 12 +- .../ref/alpha/tru64/simple-atomic/stderr | 3 +- .../ref/alpha/tru64/simple-timing/config.ini | 34 +- .../ref/alpha/tru64/simple-timing/config.out | 31 +- .../ref/alpha/tru64/simple-timing/m5stats.txt | 122 ++-- .../ref/alpha/tru64/simple-timing/stderr | 3 +- .../ref/alpha/tru64/o3-timing/config.ini | 2 +- .../ref/alpha/tru64/o3-timing/config.out | 2 +- .../ref/alpha/tru64/o3-timing/m5stats.txt | 581 +++++++++--------- .../ref/alpha/tru64/o3-timing/smred.msg | 2 +- .../ref/alpha/tru64/simple-atomic/config.ini | 34 +- .../ref/alpha/tru64/simple-atomic/config.out | 31 +- .../ref/alpha/tru64/simple-atomic/m5stats.txt | 12 +- .../ref/alpha/tru64/simple-atomic/stderr | 2 +- .../ref/alpha/tru64/simple-timing/config.ini | 34 +- .../ref/alpha/tru64/simple-timing/config.out | 31 +- .../ref/alpha/tru64/simple-timing/m5stats.txt | 122 ++-- .../ref/alpha/tru64/simple-timing/stderr | 2 +- .../ref/alpha/tru64/o3-timing/config.ini | 2 +- .../ref/alpha/tru64/o3-timing/config.out | 2 +- .../ref/alpha/tru64/o3-timing/m5stats.txt | 568 ++++++++--------- .../ref/alpha/tru64/simple-atomic/config.ini | 57 +- .../ref/alpha/tru64/simple-atomic/config.out | 58 +- .../ref/alpha/tru64/simple-atomic/m5stats.txt | 12 +- .../ref/alpha/tru64/simple-atomic/stderr | 2 + .../ref/alpha/tru64/simple-timing/config.ini | 57 +- .../ref/alpha/tru64/simple-timing/config.out | 58 +- .../ref/alpha/tru64/simple-timing/m5stats.txt | 116 ++-- .../ref/alpha/tru64/simple-timing/stderr | 2 + .../ref/alpha/tru64/o3-timing/config.ini | 2 +- .../ref/alpha/tru64/o3-timing/config.out | 2 +- .../ref/alpha/tru64/o3-timing/m5stats.txt | 547 ++++++++--------- .../ref/alpha/tru64/simple-atomic/config.ini | 32 +- .../ref/alpha/tru64/simple-atomic/config.out | 29 +- .../ref/alpha/tru64/simple-atomic/m5stats.txt | 12 +- .../ref/alpha/tru64/simple-atomic/smred.out | 4 +- .../ref/alpha/tru64/simple-atomic/stderr | 2 +- .../ref/alpha/tru64/simple-timing/config.ini | 32 +- .../ref/alpha/tru64/simple-timing/config.out | 29 +- .../ref/alpha/tru64/simple-timing/m5stats.txt | 100 +-- .../ref/alpha/tru64/simple-timing/smred.out | 4 +- .../ref/alpha/tru64/simple-timing/stderr | 2 +- 69 files changed, 1969 insertions(+), 2800 deletions(-) diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 853e93096..2192c0d45 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -23,7 +23,7 @@ activity=0 backComSize=5 choiceCtrBits=2 choicePredictorSize=8192 -clock=1 +clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out index e04428224..4c50c2a46 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out @@ -167,7 +167,7 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL [system.cpu] type=DerivO3CPU -clock=1 +clock=500 phase=0 numThreads=1 cpu_id=0 diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt index 78a2b3f52..7e02db19e 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 71631614 # Number of BTB hits -global.BPredUnit.BTBLookups 80215513 # Number of BTB lookups -global.BPredUnit.RASInCorrect 194 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 4366377 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 76991765 # Number of conditional branches predicted -global.BPredUnit.lookups 83232960 # Number of BP lookups -global.BPredUnit.usedRAS 1776050 # Number of times the RAS was used to get a target. -host_inst_rate 91613 # Simulator instruction rate (inst/s) -host_mem_usage 151676 # Number of bytes of host memory used -host_seconds 6173.25 # Real time elapsed on the host -host_tick_rate 271486 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 26015543 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 23632204 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 134244919 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 44983310 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 74294088 # Number of BTB hits +global.BPredUnit.BTBLookups 83217138 # Number of BTB lookups +global.BPredUnit.RASInCorrect 175 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 4320797 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 79655810 # Number of conditional branches predicted +global.BPredUnit.lookups 86600861 # Number of BP lookups +global.BPredUnit.usedRAS 1992384 # Number of times the RAS was used to get a target. +host_inst_rate 121760 # Simulator instruction rate (inst/s) +host_mem_usage 154560 # Number of bytes of host memory used +host_seconds 4644.82 # Real time elapsed on the host +host_tick_rate 28265671 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 20253948 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 12668807 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 134508955 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 44216516 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated -sim_seconds 0.001676 # Number of seconds simulated -sim_ticks 1675949017 # Number of ticks simulated +sim_seconds 0.131289 # Number of seconds simulated +sim_ticks 131288904500 # Number of ticks simulated system.cpu.commit.COM:branches 62547159 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 16353031 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 25836005 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 801372491 +system.cpu.commit.COM:committed_per_cycle.samples 248547939 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 580782547 7247.35% - 1 101892793 1271.48% - 2 41339172 515.85% - 3 11939444 148.99% - 4 15719123 196.15% - 5 17754998 221.56% - 6 10147917 126.63% - 7 5443466 67.93% - 8 16353031 204.06% + 0 64112537 2579.48% + 1 73997996 2977.21% + 2 29649485 1192.91% + 3 7413919 298.29% + 4 16299890 655.80% + 5 20436719 822.24% + 6 3362671 135.29% + 7 7438717 299.29% + 8 25836005 1039.48% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 115049510 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 154862033 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 4365734 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 4320164 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 90079827 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 94497449 # The number of squashed insts skipped by commit system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 2.963384 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.963384 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 120253770 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3927.286441 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3434.366579 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 119156440 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4309529230 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.009125 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1097330 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 872988 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 770472667 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001866 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 224342 # number of ReadReq MSHR misses +system.cpu.cpi 0.464286 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.464286 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 115538611 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 2723.249468 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2089.628248 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 114910502 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 1710497500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.005436 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 628109 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 403470 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 469412000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001944 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 224639 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 9089.303046 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 9344.661839 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 37503702 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 17702499310 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.049368 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1947619 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1690762 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2400241806 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006511 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 256857 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 327.941025 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 3498.764706 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 325.562069 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 3493 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 17 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 1145498 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 59479 # number of cycles access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 3076.718619 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2314.396461 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 38683248 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 2363144500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.019469 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 768073 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 511246 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 594399500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006510 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 256827 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 539.249147 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 250 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 319.012661 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 1172 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 4 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 632000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 1000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 159705091 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 7229.030286 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 6589.195890 # average overall mshr miss latency -system.cpu.dcache.demand_hits 156660142 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 22012028540 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.019066 # miss rate for demand accesses -system.cpu.dcache.demand_misses 3044949 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2563750 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3170714473 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003013 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 481199 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 154989932 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 2917.701274 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2209.525699 # average overall mshr miss latency +system.cpu.dcache.demand_hits 153593750 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 4073642000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.009008 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1396182 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 914716 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 1063811500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.003106 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 481466 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 159705091 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 7229.030286 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 6589.195890 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 154989932 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 2917.701274 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2209.525699 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 156660142 # number of overall hits -system.cpu.dcache.overall_miss_latency 22012028540 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.019066 # miss rate for overall accesses -system.cpu.dcache.overall_misses 3044949 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2563750 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3170714473 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003013 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 481199 # number of overall MSHR misses +system.cpu.dcache.overall_hits 153593750 # number of overall hits +system.cpu.dcache.overall_miss_latency 4073642000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.009008 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1396182 # number of overall misses +system.cpu.dcache.overall_mshr_hits 914716 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 1063811500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.003106 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 481466 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 477103 # number of replacements -system.cpu.dcache.sampled_refs 481199 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 477370 # number of replacements +system.cpu.dcache.sampled_refs 481466 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4063.174314 # Cycle average of tags in use -system.cpu.dcache.total_refs 156660142 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 20910000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 338217 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 515310439 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 681 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 4340917 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 740208637 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 161139948 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 116871564 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 14453620 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 2001 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 8050541 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 83232960 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 72135284 # Number of cache lines fetched -system.cpu.fetch.Cycles 198811102 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1485258 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 751818937 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 5990379 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.102023 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 72135284 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 73407664 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.921543 # Number of inst fetches per cycle +system.cpu.dcache.tagsinuse 4095.510322 # Cycle average of tags in use +system.cpu.dcache.total_refs 153593750 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 24474000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 338333 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 34835558 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 676 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 4837262 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 747469994 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 87926948 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 115162373 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 14029871 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 2002 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 10623061 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 86600861 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 72219408 # Number of cache lines fetched +system.cpu.fetch.Cycles 200341434 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 435 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 760297798 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 4883794 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.329810 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 72219408 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 76286472 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.895514 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 815826112 +system.cpu.fetch.rateDist.samples 262577811 system.cpu.fetch.rateDist.min_value 0 - 0 689150299 8447.27% - 1 10579353 129.68% - 2 12110332 148.44% - 3 11560507 141.70% - 4 9007686 110.41% - 5 3425511 41.99% - 6 3768928 46.20% - 7 3222436 39.50% - 8 73001060 894.81% + 0 134455787 5120.61% + 1 11289278 429.94% + 2 12199345 464.60% + 3 11605085 441.97% + 4 7894720 300.66% + 5 3823699 145.62% + 6 3913283 149.03% + 7 3555410 135.40% + 8 73841204 2812.16% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 72135284 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 5699.600162 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 4917.297556 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 72134046 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 7056105 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000017 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1238 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 297 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 4627177 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_accesses 72219408 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 4241.833509 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 3311.810155 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 72218459 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 4025500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 949 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 43 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 3000500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000013 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 941 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 906 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets 3783 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 76656.797024 # Average number of references to valid blocks. +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 79711.323400 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 1 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 3783 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 72135284 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 5699.600162 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 4917.297556 # average overall mshr miss latency -system.cpu.icache.demand_hits 72134046 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 7056105 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000017 # miss rate for demand accesses -system.cpu.icache.demand_misses 1238 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 297 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 4627177 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_accesses 72219408 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 4241.833509 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 3311.810155 # average overall mshr miss latency +system.cpu.icache.demand_hits 72218459 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 4025500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses +system.cpu.icache.demand_misses 949 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 43 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 3000500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000013 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 941 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 906 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 72135284 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 5699.600162 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 4917.297556 # average overall mshr miss latency +system.cpu.icache.overall_accesses 72219408 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 4241.833509 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 3311.810155 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 72134046 # number of overall hits -system.cpu.icache.overall_miss_latency 7056105 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000017 # miss rate for overall accesses -system.cpu.icache.overall_misses 1238 # number of overall misses -system.cpu.icache.overall_mshr_hits 297 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 4627177 # number of overall MSHR miss cycles +system.cpu.icache.overall_hits 72218459 # number of overall hits +system.cpu.icache.overall_miss_latency 4025500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses +system.cpu.icache.overall_misses 949 # number of overall misses +system.cpu.icache.overall_mshr_hits 43 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 3000500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000013 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 941 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 906 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,81 +215,81 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 44 # number of replacements -system.cpu.icache.sampled_refs 941 # Sample count of references to valid blocks. +system.cpu.icache.replacements 34 # number of replacements +system.cpu.icache.sampled_refs 906 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 749.515669 # Cycle average of tags in use -system.cpu.icache.total_refs 72134046 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 774.513861 # Cycle average of tags in use +system.cpu.icache.total_refs 72218459 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 860122906 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 67691806 # Number of branches executed -system.cpu.iew.EXEC:nop 43795429 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.748142 # Inst execution rate -system.cpu.iew.EXEC:refs 168635664 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 41396142 # Number of stores executed +system.cpu.idleCycles 997 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 69153659 # Number of branches executed +system.cpu.iew.EXEC:nop 45896023 # number of nop insts executed +system.cpu.iew.EXEC:rate 2.341699 # Inst execution rate +system.cpu.iew.EXEC:refs 168426251 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 41748280 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 508232399 # num instructions consuming a value -system.cpu.iew.WB:count 603225060 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.792920 # average fanout of values written-back +system.cpu.iew.WB:consumers 525987328 # num instructions consuming a value +system.cpu.iew.WB:count 611675009 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.792003 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 402987686 # num instructions producing a value -system.cpu.iew.WB:rate 0.739404 # insts written-back per cycle -system.cpu.iew.WB:sent 604785539 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 4695315 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 442855270 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 134244919 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 5961708 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 44983310 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 691933738 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 127239522 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6754480 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 610353566 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 42801 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 416583352 # num instructions producing a value +system.cpu.iew.WB:rate 2.329500 # insts written-back per cycle +system.cpu.iew.WB:sent 613682130 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 4878985 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 11826 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 134508955 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 2507193 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 44216516 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 696353635 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 126677971 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 11034988 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 614878076 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 120734 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 14453620 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 431168 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 14029871 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 4036 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 1871526 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 4575118 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 24838 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 4056 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 10594878 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 23131 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 1001889 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 5578 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 19195409 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 5170787 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 1001889 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 542024 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 4153291 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.337452 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.337452 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 617108046 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 1076564 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 5809 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 19459445 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 4403993 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 1076564 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 574744 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 4304241 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 2.153847 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.153847 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 625913064 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 0 0.00% # Type of FU issued - IntAlu 445691749 72.22% # Type of FU issued - IntMult 6563 0.00% # Type of FU issued + IntAlu 452893161 72.36% # Type of FU issued + IntMult 6537 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 33 0.00% # Type of FU issued - FloatCmp 6 0.00% # Type of FU issued + FloatAdd 27 0.00% # Type of FU issued + FloatCmp 5 0.00% # Type of FU issued FloatCvt 5 0.00% # Type of FU issued - FloatMult 5 0.00% # Type of FU issued + FloatMult 4 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 129192933 20.94% # Type of FU issued - MemWrite 42216752 6.84% # Type of FU issued + MemRead 130507417 20.85% # Type of FU issued + MemWrite 42505908 6.79% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 3402065 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.005513 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 6267821 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.010014 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 2626203 77.19% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available + IntAlu 5230779 83.45% # attempts to use FU when none available + IntMult 183 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available FloatCmp 0 0.00% # attempts to use FU when none available @@ -297,80 +297,80 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 644339 18.94% # attempts to use FU when none available - MemWrite 131523 3.87% # attempts to use FU when none available + MemRead 663118 10.58% # attempts to use FU when none available + MemWrite 373741 5.96% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 815826112 +system.cpu.iq.ISSUE:issued_per_cycle.samples 262577811 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 553114491 6779.81% - 1 85371128 1046.44% - 2 77782451 953.42% - 3 52154516 639.28% - 4 28098332 344.42% - 5 10103046 123.84% - 6 7930576 97.21% - 7 956122 11.72% - 8 315450 3.87% + 0 49543053 1886.80% + 1 42653619 1624.42% + 2 65996372 2513.40% + 3 28722982 1093.88% + 4 36210264 1379.03% + 5 20379063 776.12% + 6 16095665 612.99% + 7 2026950 77.19% + 8 949843 36.17% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.756421 # Inst issue rate -system.cpu.iq.iqInstsAdded 648138284 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 617108046 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 80438129 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 1088392 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 57507029 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 482140 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 8078.944187 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2363.998861 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 455802 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 212783232 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.054627 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 26338 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 62263002 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054627 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 26338 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 338217 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 338217 # number of Writeback hits +system.cpu.iq.ISSUE:rate 2.383724 # Inst issue rate +system.cpu.iq.iqInstsAdded 650457589 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 625913064 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 83477196 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 265708 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 44589775 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 482372 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 5974.559204 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2202.761362 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 456056 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 157226500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.054555 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 26316 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 57967868 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054555 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 26316 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 338333 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 338333 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 30.147278 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 30.186541 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 482140 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 8078.944187 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2363.998861 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 455802 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 212783232 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.054627 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 26338 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 482372 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 5974.559204 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2202.761362 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 456056 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 157226500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.054555 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 26316 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 62263002 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.054627 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 26338 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 57967868 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.054555 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 26316 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 820357 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 8078.944187 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2363.998861 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 820705 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 5974.559204 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2202.761362 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 794019 # number of overall hits -system.cpu.l2cache.overall_miss_latency 212783232 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.032106 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 26338 # number of overall misses +system.cpu.l2cache.overall_hits 794389 # number of overall hits +system.cpu.l2cache.overall_miss_latency 157226500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.032065 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 26316 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 62263002 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.032106 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 26338 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 57967868 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.032065 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 26316 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -382,32 +382,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 935 # number of replacements -system.cpu.l2cache.sampled_refs 26338 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 932 # number of replacements +system.cpu.l2cache.sampled_refs 26316 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 24391.955858 # Cycle average of tags in use -system.cpu.l2cache.total_refs 794019 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 25073.756706 # Cycle average of tags in use +system.cpu.l2cache.total_refs 794389 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 908 # number of writebacks -system.cpu.numCycles 815826112 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 467231804 # Number of cycles rename is blocking +system.cpu.l2cache.writebacks 904 # number of writebacks +system.cpu.numCycles 262577811 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 2682297 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 38638370 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 170863189 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 8553533 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 36121 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 961623776 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 729244091 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 554812455 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 115192044 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 14453620 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 48042805 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 90957566 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 42650 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 30 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 77555696 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 28 # count of temporary serializing insts renamed -system.cpu.timesIdled 308219 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 30243185 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 96498295 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1942834 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 952429183 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 727912324 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 552445892 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 117213862 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 14029871 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 32153216 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 88591003 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 270 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 33 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 50706382 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 31 # count of temporary serializing insts renamed +system.cpu.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini index 841e8766f..27aeb9034 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini @@ -1,48 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -53,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -74,7 +33,7 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic egid=100 env= euid=100 @@ -100,14 +59,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out index b5a24e5fb..a8a9148d5 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -30,7 +28,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip input=cin output=cout env= -cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic system=system uid=100 euid=100 @@ -49,7 +47,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false width=1 @@ -57,51 +55,3 @@ function_trace=false function_trace_start=0 simulate_stalls=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt index b8593d3a3..7c260dd71 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 970342 # Simulator instruction rate (inst/s) -host_mem_usage 144620 # Number of bytes of host memory used -host_seconds 620.25 # Real time elapsed on the host -host_tick_rate 970342 # Simulator tick rate (ticks/s) +host_inst_rate 964119 # Simulator instruction rate (inst/s) +host_mem_usage 148524 # Number of bytes of host memory used +host_seconds 624.26 # Real time elapsed on the host +host_tick_rate 482059313 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856965 # Number of instructions simulated -sim_seconds 0.000602 # Number of seconds simulated -sim_ticks 601856964 # Number of ticks simulated +sim_seconds 0.300928 # Number of seconds simulated +sim_ticks 300928482000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 601856965 # number of cpu cycles simulated diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr index 87866a2a5..f33d007a7 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr @@ -1 +1,2 @@ warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini index 48a760b08..f70ed5de3 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -1,48 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -53,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -197,7 +156,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing egid=100 env= euid=100 @@ -223,14 +182,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out index eddb9ff53..d4c1bde6e 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -30,7 +28,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip input=cin output=cout env= -cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing system=system uid=100 euid=100 @@ -49,7 +47,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -178,51 +176,3 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt index 5e7441c54..5fbf59915 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 549029 # Simulator instruction rate (inst/s) -host_mem_usage 300652 # Number of bytes of host memory used -host_seconds 1096.22 # Real time elapsed on the host -host_tick_rate 1916109 # Simulator tick rate (ticks/s) +host_inst_rate 642291 # Simulator instruction rate (inst/s) +host_mem_usage 153996 # Number of bytes of host memory used +host_seconds 937.05 # Real time elapsed on the host +host_tick_rate 404322160 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856965 # Number of instructions simulated -sim_seconds 0.002100 # Number of seconds simulated -sim_ticks 2100480012 # Number of ticks simulated +sim_seconds 0.378869 # Number of seconds simulated +sim_ticks 378869140000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 2845.396229 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1845.396229 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 2584.255983 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1584.255983 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 572584774 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 520035000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 371352774 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 318803000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3026.723012 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2026.723012 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 2608.788455 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 1608.788455 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 39197158 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 769281001 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 663057500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.006442 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 254163 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 515118001 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 408894500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2946.597514 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 1946.597514 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 2597.947935 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 1597.947935 # average overall mshr miss latency system.cpu.dcache.demand_hits 153509968 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1341865775 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 1183092500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002958 # miss rate for demand accesses system.cpu.dcache.demand_misses 455395 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 886470775 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 727697500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2946.597514 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 1946.597514 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 2597.947935 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 1597.947935 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 153509968 # number of overall hits -system.cpu.dcache.overall_miss_latency 1341865775 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 1183092500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002958 # miss rate for overall accesses system.cpu.dcache.overall_misses 455395 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 886470775 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 727697500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 451299 # number of replacements system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4053.427393 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.423304 # Cycle average of tags in use system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 33693000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 102411000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 325723 # number of writebacks system.cpu.icache.ReadReq_accesses 601856966 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4085.659119 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3085.659119 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 3746.540881 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2746.540881 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 601856171 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 3248099 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 2978500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 2453099 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 2183500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 601856966 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4085.659119 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3085.659119 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 3746.540881 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2746.540881 # average overall mshr miss latency system.cpu.icache.demand_hits 601856171 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 3248099 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 2978500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses system.cpu.icache.demand_misses 795 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2453099 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 2183500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 601856966 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4085.659119 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3085.659119 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 3746.540881 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2746.540881 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 601856171 # number of overall hits -system.cpu.icache.overall_miss_latency 3248099 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 2978500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses system.cpu.icache.overall_misses 795 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2453099 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 2183500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,23 +138,23 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 24 # number of replacements system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 642.094524 # Cycle average of tags in use +system.cpu.icache.tagsinuse 674.110982 # Cycle average of tags in use system.cpu.icache.total_refs 601856171 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 456190 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3251.348149 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1946.946471 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 2564.564334 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1563.181738 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 430092 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 84853684 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 66930000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.057209 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 26098 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 50811409 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 40795917 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.057209 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 26098 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 325723 # number of WriteReqNoAck|Writeback accesses(hits+misses) -system.cpu.l2cache.WriteReqNoAck|Writeback_hits 325723 # number of WriteReqNoAck|Writeback hits +system.cpu.l2cache.Writeback_accesses 325723 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 325723 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 28.960648 # Average number of references to valid blocks. @@ -164,29 +164,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3251.348149 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1946.946471 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 2564.564334 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1563.181738 # average overall mshr miss latency system.cpu.l2cache.demand_hits 430092 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 84853684 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 66930000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.057209 # miss rate for demand accesses system.cpu.l2cache.demand_misses 26098 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 50811409 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 40795917 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.057209 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 26098 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 781913 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3251.348149 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1946.946471 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 2564.564334 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1563.181738 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 755815 # number of overall hits -system.cpu.l2cache.overall_miss_latency 84853684 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 66930000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.033377 # miss rate for overall accesses system.cpu.l2cache.overall_misses 26098 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 50811409 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 40795917 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.033377 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 26098 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -203,12 +203,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 903 # number of replacements system.cpu.l2cache.sampled_refs 26098 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 24085.007455 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 24878.910085 # Cycle average of tags in use system.cpu.l2cache.total_refs 755815 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 883 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 2100480012 # number of cpu cycles simulated +system.cpu.numCycles 378869140000 # number of cpu cycles simulated system.cpu.num_insts 601856965 # Number of instructions executed system.cpu.num_refs 154862034 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr index 87866a2a5..f33d007a7 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr @@ -1 +1,2 @@ warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini index 7d8c8259e..29e352b0e 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -23,7 +23,7 @@ activity=0 backComSize=5 choiceCtrBits=2 choicePredictorSize=8192 -clock=1 +clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out index 96829f8a9..c04c0d11b 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out @@ -167,7 +167,7 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL [system.cpu] type=DerivO3CPU -clock=1 +clock=500 phase=0 numThreads=1 cpu_id=0 diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt index bca3fa536..ce046cea7 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,112 +1,112 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 36573856 # Number of BTB hits -global.BPredUnit.BTBLookups 48300104 # Number of BTB lookups -global.BPredUnit.RASInCorrect 1110 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 6040473 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 37489973 # Number of conditional branches predicted -global.BPredUnit.lookups 66376995 # Number of BP lookups -global.BPredUnit.usedRAS 13616030 # Number of times the RAS was used to get a target. -host_inst_rate 78938 # Simulator instruction rate (inst/s) -host_mem_usage 153528 # Number of bytes of host memory used -host_seconds 4757.83 # Real time elapsed on the host -host_tick_rate 66128 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 89962751 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 64024234 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 131935591 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 95765344 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 38358431 # Number of BTB hits +global.BPredUnit.BTBLookups 50162851 # Number of BTB lookups +global.BPredUnit.RASInCorrect 1146 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 6112182 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 38942362 # Number of conditional branches predicted +global.BPredUnit.lookups 68824046 # Number of BP lookups +global.BPredUnit.usedRAS 14094584 # Number of times the RAS was used to get a target. +host_inst_rate 88313 # Simulator instruction rate (inst/s) +host_mem_usage 157144 # Number of bytes of host memory used +host_seconds 4252.75 # Real time elapsed on the host +host_tick_rate 26084457 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 79078987 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 58020753 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 131723270 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 96432918 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 375574675 # Number of instructions simulated -sim_seconds 0.000315 # Number of seconds simulated -sim_ticks 314625027 # Number of ticks simulated -system.cpu.commit.COM:branches 44587523 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 13381546 # number cycles where commit BW limit reached +sim_insts 375574812 # Number of instructions simulated +sim_seconds 0.110931 # Number of seconds simulated +sim_ticks 110930737500 # Number of ticks simulated +system.cpu.commit.COM:branches 44587533 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 15191652 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 276331431 +system.cpu.commit.COM:committed_per_cycle.samples 203296876 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 148231465 5364.26% - 1 40756250 1474.90% - 2 28135615 1018.18% - 3 18140880 656.49% - 4 10622787 384.42% - 5 8112500 293.58% - 6 5544405 200.64% - 7 3405983 123.26% - 8 13381546 484.26% + 0 83055980 4085.45% + 1 37801777 1859.44% + 2 20090473 988.23% + 3 18525905 911.27% + 4 11216575 551.73% + 5 8853752 435.51% + 6 5489461 270.02% + 7 3071301 151.07% + 8 15191652 747.26% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 398664447 # Number of instructions committed -system.cpu.commit.COM:loads 100651988 # Number of loads committed +system.cpu.commit.COM:count 398664587 # Number of instructions committed +system.cpu.commit.COM:loads 100651995 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 174183388 # Number of memory references committed +system.cpu.commit.COM:refs 174183397 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 6036288 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 398664447 # The number of committed instructions +system.cpu.commit.branchMispredicts 6107953 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 398664587 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 118579541 # The number of squashed insts skipped by commit -system.cpu.committedInsts 375574675 # Number of Instructions Simulated -system.cpu.committedInsts_total 375574675 # Number of Instructions Simulated -system.cpu.cpi 0.837716 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.837716 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 96374626 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 5603.456853 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5219.612576 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 96372656 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 11038810 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000020 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1970 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 984 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 5146538 # number of ReadReq MSHR miss cycles +system.cpu.commit.commitSquashedInsts 122897297 # The number of squashed insts skipped by commit +system.cpu.committedInsts 375574812 # Number of Instructions Simulated +system.cpu.committedInsts_total 375574812 # Number of Instructions Simulated +system.cpu.cpi 0.590725 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.590725 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 96817111 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 4478.552279 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3669.007021 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 96815619 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 6682000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000015 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1492 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 495 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 3658000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 986 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 73520727 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 6647.641993 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6867.316020 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 73501543 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 127528364 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000261 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 19184 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 15988 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 21947942 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_misses 997 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 4580.037179 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3751.017852 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 73511046 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 44348500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000132 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 9683 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 6490 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 11977000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 3196 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 2800 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_mshr_misses 3193 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 40620.324964 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 19 # number of cycles access was blocked +system.cpu.dcache.avg_refs 40650.755370 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 53200 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 169895353 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 6550.400586 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 6478.833094 # average overall mshr miss latency -system.cpu.dcache.demand_hits 169874199 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 138567174 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000125 # miss rate for demand accesses -system.cpu.dcache.demand_misses 21154 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 16972 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 27094480 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_accesses 170337840 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 4566.487696 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3731.503580 # average overall mshr miss latency +system.cpu.dcache.demand_hits 170326665 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 51030500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000066 # miss rate for demand accesses +system.cpu.dcache.demand_misses 11175 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 6985 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 15635000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 4182 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 4190 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 169895353 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 6550.400586 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 6478.833094 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 170337840 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 4566.487696 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3731.503580 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 169874199 # number of overall hits -system.cpu.dcache.overall_miss_latency 138567174 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000125 # miss rate for overall accesses -system.cpu.dcache.overall_misses 21154 # number of overall misses -system.cpu.dcache.overall_mshr_hits 16972 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 27094480 # number of overall MSHR miss cycles +system.cpu.dcache.overall_hits 170326665 # number of overall hits +system.cpu.dcache.overall_miss_latency 51030500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000066 # miss rate for overall accesses +system.cpu.dcache.overall_misses 11175 # number of overall misses +system.cpu.dcache.overall_mshr_hits 6985 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 15635000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 4182 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 4190 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 786 # number of replacements -system.cpu.dcache.sampled_refs 4182 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 787 # number of replacements +system.cpu.dcache.sampled_refs 4190 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3211.654167 # Cycle average of tags in use -system.cpu.dcache.total_refs 169874199 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3304.118717 # Cycle average of tags in use +system.cpu.dcache.total_refs 170326665 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 639 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 32658535 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 4257 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 11810746 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 562730439 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 143183566 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 99541453 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 18560140 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 12611 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 947878 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 66376995 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 68531131 # Number of cache lines fetched -system.cpu.fetch.Cycles 171584130 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1722712 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 577337575 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 6483468 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.225089 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 68531131 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 50189886 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.957796 # Number of inst fetches per cycle +system.cpu.dcache.writebacks 642 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 19129336 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 4391 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 12122968 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 582055742 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 80258799 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 100428895 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 18564601 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 12469 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 3479847 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 68824046 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 70113587 # Number of cache lines fetched +system.cpu.fetch.Cycles 177754526 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1413 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 605291130 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 6551564 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.310212 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 70113587 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 52453015 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.728239 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 294891572 +system.cpu.fetch.rateDist.samples 221861478 system.cpu.fetch.rateDist.min_value 0 - 0 191838575 6505.39% - 1 8000057 271.29% - 2 8353997 283.29% - 3 6793291 230.37% - 4 15387795 521.81% - 5 8442060 286.28% - 6 8794810 298.24% - 7 2528585 85.75% - 8 44752402 1517.59% + 0 114220541 5148.28% + 1 8239331 371.37% + 2 8549373 385.35% + 3 6969058 314.12% + 4 16046109 723.25% + 5 8875051 400.03% + 6 9195050 414.45% + 7 2819832 127.10% + 8 46947133 2116.06% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 68531131 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4689.224645 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3850.973049 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 68526132 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 23441434 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000073 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 4999 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 1103 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 15003391 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000057 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 3896 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 70113587 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3851.773227 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2889.186432 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 70109583 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15422500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000057 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 4004 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 83 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 11328500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000056 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 3921 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 17588.842916 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 17880.536343 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 68531131 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4689.224645 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3850.973049 # average overall mshr miss latency -system.cpu.icache.demand_hits 68526132 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 23441434 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000073 # miss rate for demand accesses -system.cpu.icache.demand_misses 4999 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 1103 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 15003391 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000057 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 3896 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 70113587 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3851.773227 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2889.186432 # average overall mshr miss latency +system.cpu.icache.demand_hits 70109583 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15422500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000057 # miss rate for demand accesses +system.cpu.icache.demand_misses 4004 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 83 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 11328500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000056 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 3921 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 68531131 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4689.224645 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3850.973049 # average overall mshr miss latency +system.cpu.icache.overall_accesses 70113587 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3851.773227 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2889.186432 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 68526132 # number of overall hits -system.cpu.icache.overall_miss_latency 23441434 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000073 # miss rate for overall accesses -system.cpu.icache.overall_misses 4999 # number of overall misses -system.cpu.icache.overall_mshr_hits 1103 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 15003391 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000057 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 3896 # number of overall MSHR misses +system.cpu.icache.overall_hits 70109583 # number of overall hits +system.cpu.icache.overall_miss_latency 15422500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000057 # miss rate for overall accesses +system.cpu.icache.overall_misses 4004 # number of overall misses +system.cpu.icache.overall_mshr_hits 83 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 11328500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000056 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 3921 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,162 +215,162 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 1976 # number of replacements -system.cpu.icache.sampled_refs 3896 # Sample count of references to valid blocks. +system.cpu.icache.replacements 1998 # number of replacements +system.cpu.icache.sampled_refs 3921 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1786.777118 # Cycle average of tags in use -system.cpu.icache.total_refs 68526132 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1828.295849 # Cycle average of tags in use +system.cpu.icache.total_refs 70109583 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 19733456 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 52475714 # Number of branches executed -system.cpu.iew.EXEC:nop 28200659 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.439607 # Inst execution rate -system.cpu.iew.EXEC:refs 190729803 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 78992420 # Number of stores executed +system.cpu.idleCycles -2 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 52992725 # Number of branches executed +system.cpu.iew.EXEC:nop 29946505 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.944645 # Inst execution rate +system.cpu.iew.EXEC:refs 194719104 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 80042784 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 302582293 # num instructions consuming a value -system.cpu.iew.WB:count 419651187 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.683002 # average fanout of values written-back +system.cpu.iew.WB:consumers 297392817 # num instructions consuming a value +system.cpu.iew.WB:count 427980775 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.704330 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 206664160 # num instructions producing a value -system.cpu.iew.WB:rate 1.423069 # insts written-back per cycle -system.cpu.iew.WB:sent 420984328 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 6525670 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 4581779 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 131935591 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 243 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 8433935 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 95765344 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 517242480 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 111737383 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7591261 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 424527920 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 366722 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 209462789 # num instructions producing a value +system.cpu.iew.WB:rate 1.929045 # insts written-back per cycle +system.cpu.iew.WB:sent 430386834 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 6770153 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 2285856 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 131723270 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 248 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 6165269 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 96432918 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 521561792 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 114676320 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 13198323 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 431441879 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 131901 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 32377 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 18560140 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 737234 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 25295 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 18564601 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 554549 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 8882 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 8984961 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 39727 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 10646448 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 56371 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 675434 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 175954 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 31283603 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 22233944 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 675434 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 1009222 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 5516448 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.193722 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.193722 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 432119181 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 636490 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 215134 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 31071275 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 22901516 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 636490 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1000963 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 5769190 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.692835 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.692835 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 444640202 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 33581 0.01% # Type of FU issued - IntAlu 171100299 39.60% # Type of FU issued - IntMult 2148839 0.50% # Type of FU issued + IntAlu 177043734 39.82% # Type of FU issued + IntMult 2204532 0.50% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 35472672 8.21% # Type of FU issued - FloatCmp 7906658 1.83% # Type of FU issued - FloatCvt 2966336 0.69% # Type of FU issued - FloatMult 16725823 3.87% # Type of FU issued - FloatDiv 1566508 0.36% # Type of FU issued + FloatAdd 36105087 8.12% # Type of FU issued + FloatCmp 7997969 1.80% # Type of FU issued + FloatCvt 3013999 0.68% # Type of FU issued + FloatMult 17176525 3.86% # Type of FU issued + FloatDiv 1578480 0.36% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 113251606 26.21% # Type of FU issued - MemWrite 80946859 18.73% # Type of FU issued + MemRead 116850777 26.28% # Type of FU issued + MemWrite 82635518 18.58% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 9237965 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.021378 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 12556872 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.028241 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 31984 0.35% # attempts to use FU when none available + IntAlu 57761 0.46% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 74124 0.80% # attempts to use FU when none available - FloatCmp 35886 0.39% # attempts to use FU when none available - FloatCvt 5384 0.06% # attempts to use FU when none available - FloatMult 1393766 15.09% # attempts to use FU when none available - FloatDiv 1142138 12.36% # attempts to use FU when none available + FloatAdd 28133 0.22% # attempts to use FU when none available + FloatCmp 21849 0.17% # attempts to use FU when none available + FloatCvt 3461 0.03% # attempts to use FU when none available + FloatMult 3478872 27.70% # attempts to use FU when none available + FloatDiv 916669 7.30% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 5413419 58.60% # attempts to use FU when none available - MemWrite 1141264 12.35% # attempts to use FU when none available + MemRead 6621449 52.73% # attempts to use FU when none available + MemWrite 1428678 11.38% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 294891572 +system.cpu.iq.ISSUE:issued_per_cycle.samples 221861478 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 116554693 3952.46% - 1 58404803 1980.55% - 2 49059967 1663.66% - 3 31805455 1078.55% - 4 23494336 796.71% - 5 9548381 323.79% - 6 4038173 136.94% - 7 1656320 56.17% - 8 329444 11.17% + 0 66879354 3014.46% + 1 37689855 1698.80% + 2 36617552 1650.47% + 3 29239458 1317.92% + 4 27293259 1230.19% + 5 13755301 620.00% + 6 5789291 260.94% + 7 3467682 156.30% + 8 1129726 50.92% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.465349 # Inst issue rate -system.cpu.iq.iqInstsAdded 489041578 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 432119181 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 243 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 113088119 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 1629891 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 97430194 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 8078 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4922.926872 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2406.841240 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 721 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 36217973 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.910745 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 7357 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 17707131 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.910745 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 7357 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 639 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 639 # number of Writeback hits +system.cpu.iq.ISSUE:rate 2.004134 # Inst issue rate +system.cpu.iq.iqInstsAdded 491615039 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 444640202 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 248 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 114649126 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 1134366 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 33 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 83844967 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 8108 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 3327.551159 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1909.064236 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 729 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 24554000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.910089 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 7379 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 14086985 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.910089 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 7379 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 642 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 642 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.184858 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.185798 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 8078 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4922.926872 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2406.841240 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 721 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 36217973 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.910745 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 7357 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 8108 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 3327.551159 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1909.064236 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 729 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 24554000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.910089 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 7379 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 17707131 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.910745 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 7357 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 14086985 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.910089 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 7379 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 8717 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4922.926872 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2406.841240 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 8750 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 3327.551159 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1909.064236 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1360 # number of overall hits -system.cpu.l2cache.overall_miss_latency 36217973 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.843983 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 7357 # number of overall misses +system.cpu.l2cache.overall_hits 1371 # number of overall hits +system.cpu.l2cache.overall_miss_latency 24554000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.843314 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 7379 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 17707131 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.843983 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 7357 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 14086985 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.843314 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 7379 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -383,31 +383,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 7357 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 7379 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 6462.850486 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1360 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 6669.459869 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1371 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 294891572 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 14686909 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 259532206 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 2446116 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 148616326 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 11769281 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 32 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 721460314 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 549210935 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 355537016 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 94743971 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 18560140 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 15563294 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 96004810 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 2720932 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 38133 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 34543353 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 264 # count of temporary serializing insts renamed -system.cpu.timesIdled 6492 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.numCycles 221861478 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 6569281 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 259532333 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 1971772 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 86889182 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 8681438 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 731270765 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 559458182 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 360795698 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 96896401 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 18564601 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 12635219 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 101263365 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 306794 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 37801 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 32486829 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 267 # count of temporary serializing insts renamed +system.cpu.timesIdled 2 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout index 039e2d4ce..68b00def4 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout @@ -1,2 +1,2 @@ Eon, Version 1.1 -OO-style eon Time= 0.000000 +OO-style eon Time= 0.100000 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini index 088cd1a9f..ba3b61431 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini @@ -1,48 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -53,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -74,7 +33,7 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic egid=100 env= euid=100 @@ -100,14 +59,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out index bec900d0f..de3317258 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -30,7 +28,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon input=cin output=cout env= -cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic system=system uid=100 euid=100 @@ -49,7 +47,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false width=1 @@ -57,51 +55,3 @@ function_trace=false function_trace_start=0 simulate_stalls=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt index a308f5e36..3892be109 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 841426 # Simulator instruction rate (inst/s) -host_mem_usage 147172 # Number of bytes of host memory used -host_seconds 473.80 # Real time elapsed on the host -host_tick_rate 841425 # Simulator tick rate (ticks/s) +host_inst_rate 844104 # Simulator instruction rate (inst/s) +host_mem_usage 151076 # Number of bytes of host memory used +host_seconds 472.29 # Real time elapsed on the host +host_tick_rate 422051705 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 398664450 # Number of instructions simulated -sim_seconds 0.000399 # Number of seconds simulated -sim_ticks 398664449 # Number of ticks simulated +sim_insts 398664597 # Number of instructions simulated +sim_seconds 0.199332 # Number of seconds simulated +sim_ticks 199332298000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 398664450 # number of cpu cycles simulated -system.cpu.num_insts 398664450 # Number of instructions executed -system.cpu.num_refs 174183390 # Number of memory references +system.cpu.numCycles 398664597 # number of cpu cycles simulated +system.cpu.num_insts 398664597 # Number of instructions executed +system.cpu.num_refs 174183399 # Number of memory references system.cpu.workload.PROG:num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr index 1d6957eca..4bb0d9bbe 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr @@ -1,9 +1,11 @@ warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera opening surfaces file chair.surfaces reading data +warn: Increasing stack size by one page. processing 8parts Grid measure is 6 by 3.0001 by 6 cell dimension is 0.863065 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout index 039e2d4ce..5f057b8dd 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout @@ -1,2 +1,2 @@ Eon, Version 1.1 -OO-style eon Time= 0.000000 +OO-style eon Time= 0.183333 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini index 452538e49..bc260bf15 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini @@ -1,33 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -38,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -182,11 +156,11 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing egid=100 env= euid=100 -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/eon +executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin output=cout diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out index 602da9705..0a9655414 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -27,11 +24,11 @@ responder_set=false [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/eon +executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon input=cin output=cout env= -cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing system=system uid=100 euid=100 @@ -50,7 +47,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -179,23 +176,3 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt index 328856ce7..552adff15 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,65 +1,65 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 689508 # Simulator instruction rate (inst/s) -host_mem_usage 185012 # Number of bytes of host memory used -host_seconds 578.19 # Real time elapsed on the host -host_tick_rate 1033135 # Simulator tick rate (ticks/s) +host_inst_rate 557007 # Simulator instruction rate (inst/s) +host_mem_usage 156576 # Number of bytes of host memory used +host_seconds 715.73 # Real time elapsed on the host +host_tick_rate 396092779 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 398664450 # Number of instructions simulated -sim_seconds 0.000597 # Number of seconds simulated -sim_ticks 597346012 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 94754482 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3956.610526 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2956.610526 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 94753532 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3758780 # number of ReadReq miss cycles +sim_insts 398664597 # Number of instructions simulated +sim_seconds 0.283494 # Number of seconds simulated +sim_ticks 283494379000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 94754489 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3630.526316 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2630.526316 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 94753539 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3449000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 950 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2808780 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2499000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 73520727 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3940.471580 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2940.471580 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 73517525 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 12617390 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3618.988132 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2618.988132 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 73517527 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 11588000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000044 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 3202 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 9415390 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 8386000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 3202 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 40527.711224 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 40527.713391 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 168275209 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3944.164258 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2944.164258 # average overall mshr miss latency -system.cpu.dcache.demand_hits 168271057 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 16376170 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 168275218 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3621.628131 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2621.628131 # average overall mshr miss latency +system.cpu.dcache.demand_hits 168271066 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 15037000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses system.cpu.dcache.demand_misses 4152 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 12224170 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 10885000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 168275209 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3944.164258 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2944.164258 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 168271057 # number of overall hits -system.cpu.dcache.overall_miss_latency 16376170 # number of overall miss cycles +system.cpu.dcache.overall_accesses 168275218 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3621.628131 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2621.628131 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 168271066 # number of overall hits +system.cpu.dcache.overall_miss_latency 15037000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_misses 4152 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 12224170 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 10885000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,54 +76,54 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 764 # number of replacements system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3222.413784 # Cycle average of tags in use -system.cpu.dcache.total_refs 168271057 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3289.772430 # Cycle average of tags in use +system.cpu.dcache.total_refs 168271066 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 625 # number of writebacks -system.cpu.icache.ReadReq_accesses 398664451 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3820.906097 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2820.906097 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 398660777 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 14038009 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 398664598 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3633.814321 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2633.814321 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 398660925 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 13347000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 3674 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 10364009 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 3673 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 9674000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 3674 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 108508.649156 # Average number of references to valid blocks. +system.cpu.icache.ReadReq_mshr_misses 3673 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 108538.231691 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 398664451 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3820.906097 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2820.906097 # average overall mshr miss latency -system.cpu.icache.demand_hits 398660777 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 14038009 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 398664598 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3633.814321 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2633.814321 # average overall mshr miss latency +system.cpu.icache.demand_hits 398660925 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 13347000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses -system.cpu.icache.demand_misses 3674 # number of demand (read+write) misses +system.cpu.icache.demand_misses 3673 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 10364009 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 9674000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000009 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 3674 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 3673 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 398664451 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3820.906097 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2820.906097 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 398660777 # number of overall hits -system.cpu.icache.overall_miss_latency 14038009 # number of overall miss cycles +system.cpu.icache.overall_accesses 398664598 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3633.814321 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2633.814321 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 398660925 # number of overall hits +system.cpu.icache.overall_miss_latency 13347000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses -system.cpu.icache.overall_misses 3674 # number of overall misses +system.cpu.icache.overall_misses 3673 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 10364009 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 9674000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 3674 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 3673 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -135,60 +135,60 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 1770 # number of replacements -system.cpu.icache.sampled_refs 3674 # Sample count of references to valid blocks. +system.cpu.icache.replacements 1769 # number of replacements +system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1765.882838 # Cycle average of tags in use -system.cpu.icache.total_refs 398660777 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1795.510184 # Cycle average of tags in use +system.cpu.icache.total_refs 398660925 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 7826 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2983.265505 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1924.984530 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 7825 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2707.276275 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1705.023697 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 651 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 21404930 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.916816 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 7175 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 13811764 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.916816 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 7175 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 19422000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.916805 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 7174 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 12231840 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.916805 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 7174 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 625 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.177840 # Average number of references to valid blocks. +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.177865 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 7826 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2983.265505 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1924.984530 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2707.276275 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1705.023697 # average overall mshr miss latency system.cpu.l2cache.demand_hits 651 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 21404930 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.916816 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 7175 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 19422000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.916805 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 7174 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 13811764 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.916816 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 7175 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 12231840 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.916805 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 7174 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 8451 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2983.265505 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1924.984530 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_accesses 8450 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2707.276275 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1705.023697 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1276 # number of overall hits -system.cpu.l2cache.overall_miss_latency 21404930 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.849012 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 7175 # number of overall misses +system.cpu.l2cache.overall_miss_latency 19422000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.848994 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 7174 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 13811764 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.849012 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 7175 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 12231840 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.848994 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 7174 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -201,16 +201,16 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 7175 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 7174 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 6344.042673 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 6483.699084 # Cycle average of tags in use system.cpu.l2cache.total_refs 1276 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 597346012 # number of cpu cycles simulated -system.cpu.num_insts 398664450 # Number of instructions executed -system.cpu.num_refs 174183390 # Number of memory references +system.cpu.numCycles 283494379000 # number of cpu cycles simulated +system.cpu.num_insts 398664597 # Number of instructions executed +system.cpu.num_refs 174183399 # Number of memory references system.cpu.workload.PROG:num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr index 8534c55aa..4bb0d9bbe 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr @@ -1,10 +1,11 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera opening surfaces file chair.surfaces reading data +warn: Increasing stack size by one page. processing 8parts Grid measure is 6 by 3.0001 by 6 cell dimension is 0.863065 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout index 039e2d4ce..1e8a0ac6f 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout @@ -1,2 +1,2 @@ Eon, Version 1.1 -OO-style eon Time= 0.000000 +OO-style eon Time= 0.283333 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini index 59c6e25e2..dc1116a7e 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini @@ -1,33 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -38,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -59,11 +33,11 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic egid=100 env= euid=100 -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin output=cout diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out index c6e4aa136..ef449bf6d 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -27,11 +24,11 @@ responder_set=false [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk input=cin output=cout env= -cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic system=system uid=100 euid=100 @@ -50,7 +47,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false width=1 @@ -58,23 +55,3 @@ function_trace=false function_trace_start=0 simulate_stalls=false -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt index 9db3f64bc..5fa1b5726 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1149393 # Simulator instruction rate (inst/s) -host_mem_usage 177516 # Number of bytes of host memory used -host_seconds 1747.87 # Real time elapsed on the host -host_tick_rate 1149393 # Simulator tick rate (ticks/s) +host_inst_rate 855453 # Simulator instruction rate (inst/s) +host_mem_usage 151192 # Number of bytes of host memory used +host_seconds 2348.45 # Real time elapsed on the host +host_tick_rate 427726617 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987607 # Number of instructions simulated -sim_seconds 0.002009 # Number of seconds simulated -sim_ticks 2008987606 # Number of ticks simulated +sim_seconds 1.004494 # Number of seconds simulated +sim_ticks 1004493803000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 2008987607 # number of cpu cycles simulated diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr index bc72461c8..a6133a5ee 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr @@ -1,3 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 0, ...) +warn: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini index 5f64dcebd..6f1f78d48 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini @@ -1,33 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -38,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -182,11 +156,11 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing egid=100 env= euid=100 -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin output=cout diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out index 6998f4828..1c3b86ae3 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -27,11 +24,11 @@ responder_set=false [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk input=cin output=cout env= -cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing system=system uid=100 euid=100 @@ -50,7 +47,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -179,23 +176,3 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt index 45f793ab7..afc2c695a 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,35 +1,35 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 752631 # Simulator instruction rate (inst/s) -host_mem_usage 230876 # Number of bytes of host memory used -host_seconds 2669.29 # Real time elapsed on the host -host_tick_rate 2836913 # Simulator tick rate (ticks/s) +host_inst_rate 594701 # Simulator instruction rate (inst/s) +host_mem_usage 156660 # Number of bytes of host memory used +host_seconds 3378.14 # Real time elapsed on the host +host_tick_rate 405574512 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987607 # Number of instructions simulated -sim_seconds 0.007573 # Number of seconds simulated -sim_ticks 7572532003 # Number of ticks simulated +sim_seconds 1.370090 # Number of seconds simulated +sim_ticks 1370089513500 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3107.171986 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2107.171986 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 3511.656558 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2511.656558 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 509611834 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4530853333 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 5120669500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3072661333 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3662477500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3884.267929 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2884.267929 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 3914.581944 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2914.581944 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 210722944 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 279480846 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 281662000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000341 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 71952 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 207528846 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 209710000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000341 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 71952 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 721864922 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3143.713388 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2143.713388 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 3530.603329 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2530.603329 # average overall mshr miss latency system.cpu.dcache.demand_hits 720334778 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 4810334179 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 5402331500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002120 # miss rate for demand accesses system.cpu.dcache.demand_misses 1530144 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3280190179 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 3872187500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002120 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 1530144 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3143.713388 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2143.713388 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_miss_latency 3530.603329 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2530.603329 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 720334778 # number of overall hits -system.cpu.dcache.overall_miss_latency 4810334179 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 5402331500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002120 # miss rate for overall accesses system.cpu.dcache.overall_misses 1530144 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3280190179 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 3872187500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002120 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 1530144 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,22 +76,22 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 1526048 # number of replacements system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4087.479154 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.457388 # Cycle average of tags in use system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 35165000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 325153000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 74589 # number of writebacks system.cpu.icache.ReadReq_accesses 2008987608 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3103.627312 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2103.627312 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 2952.765194 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1952.765194 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 2008977012 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 32886035 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 31287500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 10596 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 22290035 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 20691500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 10596 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.cpu.icache.avg_refs 189597.679502 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 2008987608 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3103.627312 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2103.627312 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 2952.765194 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1952.765194 # average overall mshr miss latency system.cpu.icache.demand_hits 2008977012 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 32886035 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 31287500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses system.cpu.icache.demand_misses 10596 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 22290035 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 20691500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 10596 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 2008987608 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3103.627312 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2103.627312 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_miss_latency 2952.765194 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1952.765194 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 2008977012 # number of overall hits -system.cpu.icache.overall_miss_latency 32886035 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 31287500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses system.cpu.icache.overall_misses 10596 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 22290035 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 20691500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 10596 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 9046 # number of replacements system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1471.254279 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1478.638648 # Cycle average of tags in use system.cpu.icache.total_refs 2008977012 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 1540740 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2153.828221 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1111.659139 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 2545.120588 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1544.109658 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 33878 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 3245521901 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 3835145500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.978012 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 1506862 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1675116913 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 2326760167 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.978012 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 1506862 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses) @@ -159,8 +159,8 @@ system.cpu.l2cache.Writeback_miss_rate 0.014399 # mi system.cpu.l2cache.Writeback_misses 1074 # number of Writeback misses system.cpu.l2cache.Writeback_mshr_miss_rate 0.014399 # mshr miss rate for Writeback accesses system.cpu.l2cache.Writeback_mshr_misses 1074 # number of Writeback MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0.071269 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked @@ -168,29 +168,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2153.828221 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1111.659139 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 2545.120588 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1544.109658 # average overall mshr miss latency system.cpu.l2cache.demand_hits 33878 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3245521901 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 3835145500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.978012 # miss rate for demand accesses system.cpu.l2cache.demand_misses 1506862 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1675116913 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2326760167 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.978012 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 1506862 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 1615329 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2152.294196 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1111.659139 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_miss_latency 2543.307872 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1544.109658 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 107393 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3245521901 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 3835145500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.933516 # miss rate for overall accesses system.cpu.l2cache.overall_misses 1507936 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1675116913 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2326760167 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.932851 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 1506862 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -207,12 +207,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 1474094 # number of replacements system.cpu.l2cache.sampled_refs 1506862 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 32444.706916 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 32754.836517 # Cycle average of tags in use system.cpu.l2cache.total_refs 107393 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 164189000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 1084960000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 66804 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 7572532003 # number of cpu cycles simulated +system.cpu.numCycles 1370089513500 # number of cpu cycles simulated system.cpu.num_insts 2008987607 # Number of instructions executed system.cpu.num_refs 722390435 # Number of memory references system.cpu.workload.PROG:num_syscalls 39 # Number of system calls diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr index bc72461c8..a6133a5ee 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr @@ -1,3 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 0, ...) +warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini index d565e945f..6aa726853 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -23,7 +23,7 @@ activity=0 backComSize=5 choiceCtrBits=2 choicePredictorSize=8192 -clock=1 +clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out index 85be70a92..e22560975 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out @@ -167,7 +167,7 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL [system.cpu] type=DerivO3CPU -clock=1 +clock=500 phase=0 numThreads=1 cpu_id=0 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt index 00598f40d..91b29d8d9 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 7945230 # Number of BTB hits -global.BPredUnit.BTBLookups 13714223 # Number of BTB lookups -global.BPredUnit.RASInCorrect 29001 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 454297 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 10141226 # Number of conditional branches predicted -global.BPredUnit.lookups 15617287 # Number of BP lookups -global.BPredUnit.usedRAS 1851141 # Number of times the RAS was used to get a target. -host_inst_rate 91600 # Simulator instruction rate (inst/s) -host_mem_usage 155864 # Number of bytes of host memory used -host_seconds 868.91 # Real time elapsed on the host -host_tick_rate 1051887 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 16262618 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 12842437 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 22199501 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 16236124 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 7744324 # Number of BTB hits +global.BPredUnit.BTBLookups 13591046 # Number of BTB lookups +global.BPredUnit.RASInCorrect 32932 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 452723 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 10077718 # Number of conditional branches predicted +global.BPredUnit.lookups 15489897 # Number of BP lookups +global.BPredUnit.usedRAS 1844517 # Number of times the RAS was used to get a target. +host_inst_rate 108228 # Simulator instruction rate (inst/s) +host_mem_usage 159488 # Number of bytes of host memory used +host_seconds 735.41 # Real time elapsed on the host +host_tick_rate 23792996 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 12942665 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 11520420 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 21780362 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 15866784 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 79591756 # Number of instructions simulated -sim_seconds 0.000914 # Number of seconds simulated -sim_ticks 913992014 # Number of ticks simulated +sim_seconds 0.017498 # Number of seconds simulated +sim_ticks 17497602000 # Number of ticks simulated system.cpu.commit.COM:branches 13754477 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3798224 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 4260073 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 61093189 +system.cpu.commit.COM:committed_per_cycle.samples 33996100 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 33945527 5556.35% - 1 9263496 1516.29% - 2 5234944 856.88% - 3 3369457 551.53% - 4 2068681 338.61% - 5 1423240 232.96% - 6 1205139 197.26% - 7 784481 128.41% - 8 3798224 621.71% + 0 8358440 2458.65% + 1 8230566 2421.03% + 2 4712162 1386.09% + 3 3108634 914.41% + 4 2121957 624.18% + 5 1131901 332.95% + 6 1374606 404.34% + 7 697761 205.25% + 8 4260073 1253.11% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 20379399 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 35224018 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 359791 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 356682 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 8215609 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6565781 # The number of squashed insts skipped by commit system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 11.483501 # CPI: Cycles Per Instruction -system.cpu.cpi_total 11.483501 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 19669616 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 4470.389268 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3240.793422 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 19511676 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 706053281 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.008030 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 157940 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 96341 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 199629634 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.003132 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 61599 # number of ReadReq MSHR misses +system.cpu.cpi 0.439684 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.439684 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 19603173 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 4020.633151 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2686.323277 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 19458721 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 580788500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.007369 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 144452 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 82734 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 165794500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.003148 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 61718 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 9707.501078 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 9477.511675 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 13569879 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 10129757960 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.071407 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1043498 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 900030 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1359719645 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009818 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 143468 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 3321.963636 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 3975 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 161.320715 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 110 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 1 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 365416 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 3975 # number of cycles access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 2642.114676 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3379.334983 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 13777457 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 2208596500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.057202 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 835920 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 692465 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 484782500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.009817 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 143455 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 161.990993 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 34282993 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 9019.034891 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 7604.096607 # average overall mshr miss latency -system.cpu.dcache.demand_hits 33081555 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10835811241 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.035045 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1201438 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 996371 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1559349279 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.005982 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 205067 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 34216550 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 2845.231198 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3170.870436 # average overall mshr miss latency +system.cpu.dcache.demand_hits 33236178 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 2789385000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.028652 # miss rate for demand accesses +system.cpu.dcache.demand_misses 980372 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 775199 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 650577000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.005996 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 205173 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 34282993 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 9019.034891 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 7604.096607 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 34216550 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 2845.231198 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3170.870436 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 33081555 # number of overall hits -system.cpu.dcache.overall_miss_latency 10835811241 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.035045 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1201438 # number of overall misses -system.cpu.dcache.overall_mshr_hits 996371 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1559349279 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.005982 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 205067 # number of overall MSHR misses +system.cpu.dcache.overall_hits 33236178 # number of overall hits +system.cpu.dcache.overall_miss_latency 2789385000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.028652 # miss rate for overall accesses +system.cpu.dcache.overall_misses 980372 # number of overall misses +system.cpu.dcache.overall_mshr_hits 775199 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 650577000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.005996 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 205173 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 200971 # number of replacements -system.cpu.dcache.sampled_refs 205067 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 201077 # number of replacements +system.cpu.dcache.sampled_refs 205173 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4063.517542 # Cycle average of tags in use -system.cpu.dcache.total_refs 33081555 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 17025000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 147753 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 13116101 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 95141 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3521692 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 99189601 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 29616630 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 18020228 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1276894 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 291919 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 340231 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 15617287 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 13002150 # Number of cache lines fetched -system.cpu.fetch.Cycles 31529148 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 124397 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 100725428 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 547316 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.250397 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 13002150 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 9796371 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.614964 # Number of inst fetches per cycle +system.cpu.dcache.tagsinuse 4079.993551 # Cycle average of tags in use +system.cpu.dcache.total_refs 33236178 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 90338000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 147781 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 1516721 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 98391 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3463978 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 98144908 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 14320248 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 17547399 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 999107 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 287801 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 611733 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 15489897 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 12778073 # Number of cache lines fetched +system.cpu.fetch.Cycles 31147667 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 14471 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 99913909 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 465674 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.442629 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 12778073 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 9588841 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.855074 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 62370084 +system.cpu.fetch.rateDist.samples 34995208 system.cpu.fetch.rateDist.min_value 0 - 0 43843090 7029.51% - 1 1383259 221.78% - 2 1262238 202.38% - 3 1426265 228.68% - 4 3918105 628.20% - 5 1724208 276.45% - 6 613107 98.30% - 7 1031700 165.42% - 8 7168112 1149.29% + 0 16625619 4750.83% + 1 1365816 390.29% + 2 1258616 359.65% + 3 1410956 403.19% + 4 3900976 1114.72% + 5 1678758 479.71% + 6 612174 174.93% + 7 1011089 288.92% + 8 7131204 2037.77% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 13002150 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3387.778909 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2412.580892 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 12899943 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 346254719 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.007861 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 102207 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 14535 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 211515792 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.006743 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 87672 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 12778073 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 2888.242687 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1894.538715 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 12690553 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 252779000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.006849 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 87520 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 654 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 164571000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.006798 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 86866 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets 5804 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 147.140366 # Average number of references to valid blocks. +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 146.093443 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 1 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 5804 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 13002150 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3387.778909 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2412.580892 # average overall mshr miss latency -system.cpu.icache.demand_hits 12899943 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 346254719 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.007861 # miss rate for demand accesses -system.cpu.icache.demand_misses 102207 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 14535 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 211515792 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.006743 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 87672 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 12778073 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 2888.242687 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1894.538715 # average overall mshr miss latency +system.cpu.icache.demand_hits 12690553 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 252779000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.006849 # miss rate for demand accesses +system.cpu.icache.demand_misses 87520 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 654 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 164571000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.006798 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 86866 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 13002150 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3387.778909 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2412.580892 # average overall mshr miss latency +system.cpu.icache.overall_accesses 12778073 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 2888.242687 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1894.538715 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 12899943 # number of overall hits -system.cpu.icache.overall_miss_latency 346254719 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.007861 # miss rate for overall accesses -system.cpu.icache.overall_misses 102207 # number of overall misses -system.cpu.icache.overall_mshr_hits 14535 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 211515792 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.006743 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 87672 # number of overall MSHR misses +system.cpu.icache.overall_hits 12690553 # number of overall hits +system.cpu.icache.overall_miss_latency 252779000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.006849 # miss rate for overall accesses +system.cpu.icache.overall_misses 87520 # number of overall misses +system.cpu.icache.overall_mshr_hits 654 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 164571000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.006798 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 86866 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,80 +215,80 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 85624 # number of replacements -system.cpu.icache.sampled_refs 87671 # Sample count of references to valid blocks. +system.cpu.icache.replacements 84818 # number of replacements +system.cpu.icache.sampled_refs 86866 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1862.743229 # Cycle average of tags in use -system.cpu.icache.total_refs 12899943 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tagsinuse 1921.828467 # Cycle average of tags in use +system.cpu.icache.total_refs 12690553 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 15230287000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 851621931 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 14377755 # Number of branches executed -system.cpu.iew.EXEC:nop 9220461 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.335296 # Inst execution rate -system.cpu.iew.EXEC:refs 36382036 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 15204952 # Number of stores executed +system.cpu.idleCycles 6484 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 14304724 # Number of branches executed +system.cpu.iew.EXEC:nop 9152219 # number of nop insts executed +system.cpu.iew.EXEC:rate 2.363053 # Inst execution rate +system.cpu.iew.EXEC:refs 36160680 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 15116998 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 46748099 # num instructions consuming a value -system.cpu.iew.WB:count 82847738 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.736514 # average fanout of values written-back +system.cpu.iew.WB:consumers 43283574 # num instructions consuming a value +system.cpu.iew.WB:count 82548148 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.757836 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 34430613 # num instructions producing a value -system.cpu.iew.WB:rate 1.328325 # insts written-back per cycle -system.cpu.iew.WB:sent 82914162 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 396555 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 4917376 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 22199501 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 4762 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 311974 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 16236124 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 96553237 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 21177084 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 433562 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 83282498 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 37202 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 32801872 # num instructions producing a value +system.cpu.iew.WB:rate 2.358841 # insts written-back per cycle +system.cpu.iew.WB:sent 82621578 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 398195 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 20355 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 21780362 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 4681 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 352010 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 15866784 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 94903979 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 21043682 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 752566 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 82695525 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 5889 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 11594 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1276894 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 204710 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 132 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 999107 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 7135 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 98563 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 1300046 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 1230 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 1325562 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 2239 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 27684 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1255 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1820102 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1391505 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 27684 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 103251 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 293304 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.087081 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.087081 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 83716060 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 16849 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1491 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1400963 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1022165 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 16849 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 105190 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 293005 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 2.274362 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.274362 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 83448091 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 0 0.00% # Type of FU issued - IntAlu 46816661 55.92% # Type of FU issued - IntMult 44502 0.05% # Type of FU issued + IntAlu 46687810 55.95% # Type of FU issued + IntMult 45238 0.05% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 125345 0.15% # Type of FU issued - FloatCmp 86 0.00% # Type of FU issued - FloatCvt 122997 0.15% # Type of FU issued - FloatMult 51 0.00% # Type of FU issued - FloatDiv 37854 0.05% # Type of FU issued + FloatAdd 120004 0.14% # Type of FU issued + FloatCmp 87 0.00% # Type of FU issued + FloatCvt 122290 0.15% # Type of FU issued + FloatMult 50 0.00% # Type of FU issued + FloatDiv 37770 0.05% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 21285503 25.43% # Type of FU issued - MemWrite 15283061 18.26% # Type of FU issued + MemRead 21206489 25.41% # Type of FU issued + MemWrite 15228353 18.25% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 1123822 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.013424 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 1422206 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.017043 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 98385 8.75% # attempts to use FU when none available + IntAlu 169452 11.91% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -297,84 +297,84 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 476117 42.37% # attempts to use FU when none available - MemWrite 549320 48.88% # attempts to use FU when none available + MemRead 649726 45.68% # attempts to use FU when none available + MemWrite 603028 42.40% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 62370084 +system.cpu.iq.ISSUE:issued_per_cycle.samples 34995208 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 25315225 4058.87% - 1 13800975 2212.76% - 2 10743054 1722.47% - 3 5596398 897.29% - 4 4388925 703.69% - 5 1495414 239.76% - 6 664039 106.47% - 7 305653 49.01% - 8 60401 9.68% + 0 5876071 1679.11% + 1 8518834 2434.29% + 2 6419045 1834.26% + 3 4436708 1267.80% + 4 4423684 1264.08% + 5 2554091 729.84% + 6 1512126 432.10% + 7 794096 226.92% + 8 460553 131.60% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.342247 # Inst issue rate -system.cpu.iq.iqInstsAdded 87328014 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 83716060 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 4762 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 7507881 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 113500 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 179 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 6033024 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 292729 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 7766.621627 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2997.837795 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 123055 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1317793758 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.579628 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 169674 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 508655130 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.579628 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 169674 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 147753 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 147285 # number of Writeback hits -system.cpu.l2cache.Writeback_miss_rate 0.003167 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 468 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 0.003167 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 468 # number of Writeback MSHR misses +system.cpu.iq.ISSUE:rate 2.384558 # Inst issue rate +system.cpu.iq.iqInstsAdded 85747079 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 83448091 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 4681 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 5951026 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 23998 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 98 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 4012087 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 291992 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 3325.548649 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1922.235296 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 122257 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 564462000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.581300 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 169735 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 326270608 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.581300 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 169735 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 147781 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 147317 # number of Writeback hits +system.cpu.l2cache.Writeback_miss_rate 0.003140 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 464 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 0.003140 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 464 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.593300 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.588205 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 292729 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 7766.621627 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2997.837795 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 123055 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1317793758 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.579628 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 169674 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 291992 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 3325.548649 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1922.235296 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 122257 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 564462000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.581300 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 169735 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 508655130 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.579628 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 169674 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 326270608 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.581300 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 169735 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 440482 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 7745.258419 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2997.837795 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 439773 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 3316.482471 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1922.235296 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 270340 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1317793758 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.386263 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 170142 # number of overall misses +system.cpu.l2cache.overall_hits 269574 # number of overall hits +system.cpu.l2cache.overall_miss_latency 564462000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.387016 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 170199 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 508655130 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.385201 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 169674 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 326270608 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.385960 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 169735 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -386,32 +386,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 136905 # number of replacements -system.cpu.l2cache.sampled_refs 169673 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 136967 # number of replacements +system.cpu.l2cache.sampled_refs 169735 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 30821.723437 # Cycle average of tags in use -system.cpu.l2cache.total_refs 270340 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 468003000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 115935 # number of writebacks -system.cpu.numCycles 62370084 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 8787185 # Number of cycles rename is blocking +system.cpu.l2cache.tagsinuse 32064.700481 # Cycle average of tags in use +system.cpu.l2cache.total_refs 269574 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 8508988000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 115938 # number of writebacks +system.cpu.numCycles 34995208 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 201241 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 113083 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 30263464 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 3026568 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 587 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 118807787 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 98380136 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 59048113 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 17777635 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1276894 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 3354217 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 6501232 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 910689 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 4741 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 5955323 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 4739 # count of temporary serializing insts renamed -system.cpu.timesIdled 280733 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 31178 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 14721876 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1110145 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 117085470 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 96973574 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 58152082 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 17754494 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 999107 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1242602 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 5605201 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 75888 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 4701 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 2792735 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 4699 # count of temporary serializing insts renamed +system.cpu.timesIdled 16 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg index 327142d7c..472b08431 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg @@ -134,7 +134,7 @@ DB Handle Chunk's StackPtr = 20797 DB[ 1] LOADED; Handles= 20797 - KERNEL in CORE[ 1] Restored @ 40054800 + KERNEL in CORE[ 1] Restored @ 4005c800 OPEN File ./input/lendian.wnv *Status = 0 diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini index 179e8ea77..57d9578d2 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini @@ -1,33 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -38,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -59,11 +33,11 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic egid=100 env= euid=100 -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin output=cout diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out index 725aaed50..fbb08bf4b 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -27,11 +24,11 @@ responder_set=false [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex input=cin output=cout env= -cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic system=system uid=100 euid=100 @@ -50,7 +47,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false width=1 @@ -58,23 +55,3 @@ function_trace=false function_trace_start=0 simulate_stalls=false -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt index 9c60e1316..8a03d8929 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1347543 # Simulator instruction rate (inst/s) -host_mem_usage 179988 # Number of bytes of host memory used -host_seconds 65.56 # Real time elapsed on the host -host_tick_rate 1347535 # Simulator tick rate (ticks/s) +host_inst_rate 842354 # Simulator instruction rate (inst/s) +host_mem_usage 152996 # Number of bytes of host memory used +host_seconds 104.87 # Real time elapsed on the host +host_tick_rate 421175511 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340674 # Number of instructions simulated -sim_seconds 0.000088 # Number of seconds simulated -sim_ticks 88340673 # Number of ticks simulated +sim_seconds 0.044170 # Number of seconds simulated +sim_ticks 44170336500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 88340674 # number of cpu cycles simulated diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr index eb1796ead..f33d007a7 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini index 0e1a3c9f1..2f49c7692 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini @@ -1,33 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -38,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -182,11 +156,11 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing egid=100 env= euid=100 -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin output=cout diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out index 0dc85858d..c1faaa3e6 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -27,11 +24,11 @@ responder_set=false [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex input=cin output=cout env= -cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing system=system uid=100 euid=100 @@ -50,7 +47,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -179,23 +176,3 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt index 9a9778162..939083267 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,35 +1,35 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 704446 # Simulator instruction rate (inst/s) -host_mem_usage 275648 # Number of bytes of host memory used -host_seconds 125.40 # Real time elapsed on the host -host_tick_rate 9716991 # Simulator tick rate (ticks/s) +host_inst_rate 562157 # Simulator instruction rate (inst/s) +host_mem_usage 158620 # Number of bytes of host memory used +host_seconds 157.15 # Real time elapsed on the host +host_tick_rate 396922606 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340674 # Number of instructions simulated -sim_seconds 0.001219 # Number of seconds simulated -sim_ticks 1218558003 # Number of ticks simulated +sim_seconds 0.062375 # Number of seconds simulated +sim_ticks 62374966500 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3613.021476 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2613.021476 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 3130.058422 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2130.058422 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 20215873 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 219545250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 190198000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 60765 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 158780250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 129433000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 60765 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 4540.238491 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3540.238491 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 3436.431765 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2436.431765 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 14469799 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 651878362 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 493396000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.009825 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 143578 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 508300362 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 349818000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 143578 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.cpu.dcache.avg_refs 169.742404 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 4264.514136 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3264.514136 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 3345.326241 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2345.326241 # average overall mshr miss latency system.cpu.dcache.demand_hits 34685672 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 871423612 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 683594000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.005857 # miss rate for demand accesses system.cpu.dcache.demand_misses 204343 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 667080612 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 479251000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 204343 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 4264.514136 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3264.514136 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_miss_latency 3345.326241 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2345.326241 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 34685672 # number of overall hits -system.cpu.dcache.overall_miss_latency 871423612 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 683594000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.005857 # miss rate for overall accesses system.cpu.dcache.overall_misses 204343 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 667080612 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 479251000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 204343 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,22 +76,22 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 200247 # number of replacements system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4056.438323 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4082.118898 # Cycle average of tags in use system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 28900000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 307192000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 147714 # number of writebacks system.cpu.icache.ReadReq_accesses 88340675 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2932.969818 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1932.969818 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 2831.355644 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1831.355644 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 88264239 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 224184481 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 216417500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000865 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 147748481 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 139981500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000865 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.cpu.icache.avg_refs 1154.746965 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 88340675 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2932.969818 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1932.969818 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 2831.355644 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1831.355644 # average overall mshr miss latency system.cpu.icache.demand_hits 88264239 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 224184481 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 216417500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000865 # miss rate for demand accesses system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 147748481 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 139981500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000865 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 88340675 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2932.969818 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1932.969818 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_miss_latency 2831.355644 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1831.355644 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 88264239 # number of overall hits -system.cpu.icache.overall_miss_latency 224184481 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 216417500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000865 # miss rate for overall accesses system.cpu.icache.overall_misses 76436 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 147748481 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 139981500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000865 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 74391 # number of replacements system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1796.106842 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1880.010701 # Cycle average of tags in use system.cpu.icache.total_refs 88264239 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 280779 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3650.218185 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1972.851350 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 2532.769537 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1531.091909 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 112101 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 615711503 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 427222500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.600750 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 168678 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 332776620 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 258261521 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.600750 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 168678 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses) @@ -159,8 +159,8 @@ system.cpu.l2cache.Writeback_miss_rate 0.002965 # mi system.cpu.l2cache.Writeback_misses 438 # number of Writeback misses system.cpu.l2cache.Writeback_mshr_miss_rate 0.002965 # mshr miss rate for Writeback accesses system.cpu.l2cache.Writeback_mshr_misses 438 # number of Writeback MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 1.537705 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked @@ -168,29 +168,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 280779 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3650.218185 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1972.851350 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 2532.769537 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1531.091909 # average overall mshr miss latency system.cpu.l2cache.demand_hits 112101 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 615711503 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 427222500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.600750 # miss rate for demand accesses system.cpu.l2cache.demand_misses 168678 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 332776620 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 258261521 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.600750 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 168678 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 428493 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3640.764345 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1972.851350 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_miss_latency 2526.209820 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1531.091909 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 259377 # number of overall hits -system.cpu.l2cache.overall_miss_latency 615711503 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 427222500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.394676 # miss rate for overall accesses system.cpu.l2cache.overall_misses 169116 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 332776620 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 258261521 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.393654 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 168678 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -207,12 +207,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 135910 # number of replacements system.cpu.l2cache.sampled_refs 168678 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 30401.731729 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 32002.173981 # Cycle average of tags in use system.cpu.l2cache.total_refs 259377 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 667816000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 30452104000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 115911 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1218558003 # number of cpu cycles simulated +system.cpu.numCycles 62374966500 # number of cpu cycles simulated system.cpu.num_insts 88340674 # Number of instructions executed system.cpu.num_refs 35224019 # Number of memory references system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr index eb1796ead..f33d007a7 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 567f53165..9e383ca33 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -23,7 +23,7 @@ activity=0 backComSize=5 choiceCtrBits=2 choicePredictorSize=8192 -clock=1 +clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out index bf1cbf0ac..4a5aeccf1 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out @@ -167,7 +167,7 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL [system.cpu] type=DerivO3CPU -clock=1 +clock=500 phase=0 numThreads=1 cpu_id=0 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt index 3521e50a1..227b79a7b 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 929108954 # Number of BTB hits -global.BPredUnit.BTBLookups 938262248 # Number of BTB lookups -global.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 21205625 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 887467305 # Number of conditional branches predicted -global.BPredUnit.lookups 962390884 # Number of BP lookups -global.BPredUnit.usedRAS 21400461 # Number of times the RAS was used to get a target. -host_inst_rate 41899 # Simulator instruction rate (inst/s) -host_mem_usage 150980 # Number of bytes of host memory used -host_seconds 41434.26 # Real time elapsed on the host -host_tick_rate 599461 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 138710917 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 68670490 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 815007661 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 388931456 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 264221270 # Number of BTB hits +global.BPredUnit.BTBLookups 273071573 # Number of BTB lookups +global.BPredUnit.RASInCorrect 122 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 19541079 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 228439261 # Number of conditional branches predicted +global.BPredUnit.lookups 295748685 # Number of BP lookups +global.BPredUnit.usedRAS 20371548 # Number of times the RAS was used to get a target. +host_inst_rate 108663 # Simulator instruction rate (inst/s) +host_mem_usage 154628 # Number of bytes of host memory used +host_seconds 15976.47 # Real time elapsed on the host +host_tick_rate 25821276 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 80477635 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 37646176 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 533254174 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 186471924 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1736043781 # Number of instructions simulated -sim_seconds 0.024838 # Number of seconds simulated -sim_ticks 24838210102 # Number of ticks simulated +sim_seconds 0.412533 # Number of seconds simulated +sim_ticks 412532848500 # Number of ticks simulated system.cpu.commit.COM:branches 214632552 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 66487461 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 78248119 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 7112101736 +system.cpu.commit.COM:committed_per_cycle.samples 772086758 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 6522703166 9171.27% - 1 208562151 293.25% - 2 123042509 173.00% - 3 62023833 87.21% - 4 51435586 72.32% - 5 40600313 57.09% - 6 22309158 31.37% - 7 14937559 21.00% - 8 66487461 93.48% + 0 242551958 3141.51% + 1 161050324 2085.91% + 2 101638189 1316.41% + 3 63812257 826.49% + 4 43982002 569.65% + 5 37612088 487.15% + 6 28299494 366.53% + 7 14892327 192.88% + 8 78248119 1013.46% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 445666361 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 606571343 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 21205131 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 19540581 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 2701603860 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 358953852 # The number of squashed insts skipped by commit system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 14.307364 # CPI: Cycles Per Instruction -system.cpu.cpi_total 14.307364 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 489384352 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 5253.286413 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5452.839977 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 474368420 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 78882991559 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.030683 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 15015932 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 7713263 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 39820285465 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.014922 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 7302669 # number of ReadReq MSHR misses +system.cpu.cpi 0.475256 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.475256 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 463286594 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3710.591477 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2550.415742 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 454594407 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 32253155000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.018762 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 8692187 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 1395111 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 18610577500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.015751 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 7297076 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 8690.039906 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 14121.575874 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 155407108 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 46243126214 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.033108 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 5321394 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 3438755 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 26585829481 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.011713 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1882639 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 985.727671 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 3841.099983 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 68.563354 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 637482 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 65141 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 628383647 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 250213094 # number of cycles access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 6275.157749 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 8072.319138 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 157494886 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 20291450500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.020118 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 3233616 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1350145 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 15203979000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.011718 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1883471 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 1064.957356 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 500 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 66.672421 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 75157 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 5468 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 80039000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 2734000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 650112854 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 6152.535381 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 7229.601331 # average overall mshr miss latency -system.cpu.dcache.demand_hits 629775528 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 125126117773 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.031283 # miss rate for demand accesses -system.cpu.dcache.demand_misses 20337326 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 11152018 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 66406114946 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.014129 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 9185308 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 624015096 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 4405.959540 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3683.283414 # average overall mshr miss latency +system.cpu.dcache.demand_hits 612089293 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 52544605500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.019111 # miss rate for demand accesses +system.cpu.dcache.demand_misses 11925803 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2745256 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 33814556500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.014712 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 9180547 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 650112854 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 6152.535381 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 7229.601331 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 624015096 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 4405.959540 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3683.283414 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 629775528 # number of overall hits -system.cpu.dcache.overall_miss_latency 125126117773 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.031283 # miss rate for overall accesses -system.cpu.dcache.overall_misses 20337326 # number of overall misses -system.cpu.dcache.overall_mshr_hits 11152018 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 66406114946 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.014129 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 9185308 # number of overall MSHR misses +system.cpu.dcache.overall_hits 612089293 # number of overall hits +system.cpu.dcache.overall_miss_latency 52544605500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.019111 # miss rate for overall accesses +system.cpu.dcache.overall_misses 11925803 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2745256 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 33814556500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.014712 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 9180547 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 9181212 # number of replacements -system.cpu.dcache.sampled_refs 9185308 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 9176451 # number of replacements +system.cpu.dcache.sampled_refs 9180547 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4093.052798 # Cycle average of tags in use -system.cpu.dcache.total_refs 629775528 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 39780000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 2244995 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 5295615421 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 511 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 51642597 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 5750899999 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 834310560 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 972356636 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 417727902 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 1635 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 9819120 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 962390884 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 341574441 # Number of cache lines fetched -system.cpu.fetch.Cycles 1454523625 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 5354005 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 6616091478 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 145044249 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.127810 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 341574441 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 950509415 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.878651 # Number of inst fetches per cycle +system.cpu.dcache.tagsinuse 4083.178096 # Cycle average of tags in use +system.cpu.dcache.total_refs 612089293 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 4996762000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 2245686 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 22551440 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 546 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 44940582 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 2380682647 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 322635695 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 423064703 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 52978940 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 1700 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 3834921 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 295748685 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 302488728 # Number of cache lines fetched +system.cpu.fetch.Cycles 741391553 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 441 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 2447585283 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 20057035 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.358455 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 302488728 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 284592818 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.966534 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 7529829639 +system.cpu.fetch.rateDist.samples 825065699 system.cpu.fetch.rateDist.min_value 0 - 0 6416880458 8521.95% - 1 35027129 46.52% - 2 21417088 28.44% - 3 34363919 45.64% - 4 372287950 494.42% - 5 53476407 71.02% - 6 32781145 43.54% - 7 26846633 35.65% - 8 536748910 712.83% + 0 386162878 4680.39% + 1 30694739 372.03% + 2 18778429 227.60% + 3 29987039 363.45% + 4 87656406 1062.42% + 5 50975460 617.84% + 6 28097158 340.54% + 7 26422023 320.24% + 8 166291567 2015.49% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 341574441 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 5436.849282 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 4708.305648 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 341573187 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 6817809 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1254 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 351 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 4251600 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_accesses 302488728 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 4286.486486 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 3340.579710 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 302487803 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 3965000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 925 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 28 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 2996500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 903 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 897 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets 4779 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 378264.880399 # Average number of references to valid blocks. +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 337221.630992 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 1 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 4779 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 341574441 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 5436.849282 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 4708.305648 # average overall mshr miss latency -system.cpu.icache.demand_hits 341573187 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 6817809 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses -system.cpu.icache.demand_misses 1254 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 351 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 4251600 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_accesses 302488728 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 4286.486486 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 3340.579710 # average overall mshr miss latency +system.cpu.icache.demand_hits 302487803 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 3965000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses +system.cpu.icache.demand_misses 925 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 28 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 2996500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 903 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 897 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 341574441 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 5436.849282 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 4708.305648 # average overall mshr miss latency +system.cpu.icache.overall_accesses 302488728 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 4286.486486 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 3340.579710 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 341573187 # number of overall hits -system.cpu.icache.overall_miss_latency 6817809 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses -system.cpu.icache.overall_misses 1254 # number of overall misses -system.cpu.icache.overall_mshr_hits 351 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 4251600 # number of overall MSHR miss cycles +system.cpu.icache.overall_hits 302487803 # number of overall hits +system.cpu.icache.overall_miss_latency 3965000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses +system.cpu.icache.overall_misses 925 # number of overall misses +system.cpu.icache.overall_mshr_hits 28 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 2996500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 903 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 897 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -216,79 +216,79 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.sampled_refs 903 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 897 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 719.119159 # Cycle average of tags in use -system.cpu.icache.total_refs 341573187 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 700.392428 # Cycle average of tags in use +system.cpu.icache.total_refs 302487803 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 17308380464 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 264199071 # Number of branches executed -system.cpu.iew.EXEC:nop 130726584 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.347587 # Inst execution rate -system.cpu.iew.EXEC:refs 833351854 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 181613826 # Number of stores executed +system.cpu.idleCycles 498 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 240658046 # Number of branches executed +system.cpu.iew.EXEC:nop 109011682 # number of nop insts executed +system.cpu.iew.EXEC:rate 2.343638 # Inst execution rate +system.cpu.iew.EXEC:refs 670450767 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 171332493 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1860973502 # num instructions consuming a value -system.cpu.iew.WB:count 2467010272 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.791148 # average fanout of values written-back +system.cpu.iew.WB:consumers 1329316260 # num instructions consuming a value +system.cpu.iew.WB:count 1919496913 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.807674 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1472305742 # num instructions producing a value -system.cpu.iew.WB:rate 0.327632 # insts written-back per cycle -system.cpu.iew.WB:sent 2471732034 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 22834368 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 4630364405 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 815007661 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 46 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 31860417 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 388931456 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 4520549939 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 651738028 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 279876672 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 2617267318 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 2938028 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1073654377 # num instructions producing a value +system.cpu.iew.WB:rate 2.326478 # insts written-back per cycle +system.cpu.iew.WB:sent 1925768214 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 21262198 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 271227 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 533254174 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 16376681 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 186471924 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2178733969 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 499118274 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 42707495 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1933655185 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 3473 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 161905 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 417727902 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 6385903 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 253 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 52978940 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 31539 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 122063096 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 39544757 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 151090 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 331862 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 34494542 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 128095 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 4644371 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 12 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 369341300 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 228026474 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 4644371 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 832035 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 22002333 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.069894 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.069894 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 2897143990 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 361683 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 9 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 87587813 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 25566942 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 361683 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 691850 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 20570348 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 2.104128 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.104128 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 1976362680 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 0 0.00% # Type of FU issued - IntAlu 1942173026 67.04% # Type of FU issued - IntMult 100 0.00% # Type of FU issued + IntAlu 1288510764 65.20% # Type of FU issued + IntMult 78 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 210 0.00% # Type of FU issued + FloatAdd 234 0.00% # Type of FU issued FloatCmp 15 0.00% # Type of FU issued - FloatCvt 140 0.00% # Type of FU issued - FloatMult 13 0.00% # Type of FU issued + FloatCvt 154 0.00% # Type of FU issued + FloatMult 14 0.00% # Type of FU issued FloatDiv 24 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 770673405 26.60% # Type of FU issued - MemWrite 184297057 6.36% # Type of FU issued + MemRead 513015840 25.96% # Type of FU issued + MemWrite 174835557 8.85% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 12298143 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.004245 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 18092397 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.009154 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 765509 6.22% # attempts to use FU when none available + IntAlu 2424231 13.40% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -297,84 +297,84 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 9714303 78.99% # attempts to use FU when none available - MemWrite 1818331 14.79% # attempts to use FU when none available + MemRead 11434785 63.20% # attempts to use FU when none available + MemWrite 4233381 23.40% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 7529829639 +system.cpu.iq.ISSUE:issued_per_cycle.samples 825065699 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 6294390011 8359.27% - 1 325228389 431.92% - 2 480486573 638.11% - 3 243738023 323.70% - 4 97825007 129.92% - 5 51561666 68.48% - 6 27659179 36.73% - 7 6861374 9.11% - 8 2079417 2.76% + 0 201043450 2436.70% + 1 117715520 1426.74% + 2 151671107 1838.29% + 3 100094924 1213.18% + 4 99857816 1210.30% + 5 89528622 1085.11% + 6 51943929 629.57% + 7 9400422 113.94% + 8 3809909 46.18% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.384756 # Inst issue rate -system.cpu.iq.iqInstsAdded 4389823309 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 2897143990 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 2623608231 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 10330579 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2673985156 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 9186210 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 7225.224344 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2102.004971 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 7015727 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 15682226609 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.236276 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 2170483 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 4562366056 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.236276 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 2170483 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 2244995 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 2215762 # number of Writeback hits -system.cpu.l2cache.Writeback_miss_rate 0.013021 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 29233 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 0.013021 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 29233 # number of Writeback MSHR misses +system.cpu.iq.ISSUE:rate 2.395400 # Inst issue rate +system.cpu.iq.iqInstsAdded 2069722245 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1976362680 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 42 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 325012863 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 1550012 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 175292310 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 9181444 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4578.076271 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1904.625556 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 7012219 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 9930877500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.236262 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 2169225 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 4131561371 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.236262 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 2169225 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 2245686 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2216531 # number of Writeback hits +system.cpu.l2cache.Writeback_miss_rate 0.012983 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 29155 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 0.012983 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 29155 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.253196 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 4.254400 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 9186210 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 7225.224344 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2102.004971 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 7015727 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 15682226609 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.236276 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 2170483 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 9181444 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4578.076271 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1904.625556 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 7012219 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 9930877500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.236262 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 2169225 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4562366056 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.236276 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 2170483 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 4131561371 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.236262 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 2169225 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 11431205 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 7129.205138 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2102.004971 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 11427130 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4517.361648 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1904.625556 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 9231489 # number of overall hits -system.cpu.l2cache.overall_miss_latency 15682226609 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.192431 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 2199716 # number of overall misses +system.cpu.l2cache.overall_hits 9228750 # number of overall hits +system.cpu.l2cache.overall_miss_latency 9930877500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.192383 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 2198380 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4562366056 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.189874 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 2170483 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 4131561371 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.189831 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 2169225 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -386,32 +386,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 2137715 # number of replacements -system.cpu.l2cache.sampled_refs 2170483 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 2136457 # number of replacements +system.cpu.l2cache.sampled_refs 2169225 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 32622.966749 # Cycle average of tags in use -system.cpu.l2cache.total_refs 9231489 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 513093000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 1039675 # number of writebacks -system.cpu.numCycles 7529829639 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 5035061268 # Number of cycles rename is blocking +system.cpu.l2cache.tagsinuse 31578.699946 # Cycle average of tags in use +system.cpu.l2cache.total_refs 9228750 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 29958824000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 1039499 # number of writebacks +system.cpu.numCycles 825065699 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 6100420 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 12523289 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 970889170 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 234469237 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 2022618 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 7453165021 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 5328451425 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 4004220538 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 843247999 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 417727902 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 262813407 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 2628017575 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 89893 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 51 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 1009480859 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 49 # count of temporary serializing insts renamed -system.cpu.timesIdled 6494671 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 4850719 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 338099779 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 9291025 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 1319 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 2964381647 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 2307795213 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 1730632745 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 411108509 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 52978940 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 16777593 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 354429782 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 458 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 47 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 42678716 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 45 # count of temporary serializing insts renamed +system.cpu.timesIdled 2 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 29 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini index ad57a5293..d1eaa2267 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini @@ -1,48 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -53,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -74,7 +33,7 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic egid=100 env= euid=100 @@ -100,14 +59,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out index 891519c26..19f234143 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -30,7 +28,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 input=cin output=cout env= -cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic system=system uid=100 euid=100 @@ -49,7 +47,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false width=1 @@ -57,51 +55,3 @@ function_trace=false function_trace_start=0 simulate_stalls=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt index 7422e3ae7..fbe8bb0a6 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 927424 # Simulator instruction rate (inst/s) -host_mem_usage 144704 # Number of bytes of host memory used -host_seconds 1962.19 # Real time elapsed on the host -host_tick_rate 927424 # Simulator tick rate (ticks/s) +host_inst_rate 929031 # Simulator instruction rate (inst/s) +host_mem_usage 148624 # Number of bytes of host memory used +host_seconds 1958.79 # Real time elapsed on the host +host_tick_rate 464515386 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780129 # Number of instructions simulated -sim_seconds 0.001820 # Number of seconds simulated -sim_ticks 1819780128 # Number of ticks simulated +sim_seconds 0.909890 # Number of seconds simulated +sim_ticks 909890064000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1819780129 # number of cpu cycles simulated diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr index 87866a2a5..d0a887867 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr @@ -1 +1,3 @@ warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. +warn: Increasing stack size by one page. diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini index 0a123d4a4..2f9e86a73 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini @@ -1,48 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -53,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -197,7 +156,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing egid=100 env= euid=100 @@ -223,14 +182,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out index 4692c5d40..7cc7b0b90 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -30,7 +28,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 input=cin output=cout env= -cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing system=system uid=100 euid=100 @@ -49,7 +47,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -178,51 +176,3 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt index 45b7beb7c..eb696cc14 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 486900 # Simulator instruction rate (inst/s) -host_mem_usage 1198232 # Number of bytes of host memory used -host_seconds 3737.50 # Real time elapsed on the host -host_tick_rate 8500130 # Simulator tick rate (ticks/s) +host_inst_rate 623968 # Simulator instruction rate (inst/s) +host_mem_usage 154076 # Number of bytes of host memory used +host_seconds 2916.46 # Real time elapsed on the host +host_tick_rate 423514548 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780129 # Number of instructions simulated -sim_seconds 0.031769 # Number of seconds simulated -sim_ticks 31769223012 # Number of ticks simulated +sim_seconds 1.235165 # Number of seconds simulated +sim_ticks 1235165291000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3121.340330 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2121.340330 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 2978.629098 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1978.629098 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 22543612099 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 21512892500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 15321198099 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 14290478500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3602.533807 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2602.533807 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 2992.340366 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 1992.340366 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 158839182 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 6806339173 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 5653488500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.011755 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1889320 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 4917019173 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3764168500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.011755 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1889320 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3221.115901 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2221.115901 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 2981.472133 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 1981.472133 # average overall mshr miss latency system.cpu.dcache.demand_hits 596212431 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 29349951272 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 27166381000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.015053 # miss rate for demand accesses system.cpu.dcache.demand_misses 9111734 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 20238217272 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 18054647000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.015053 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 9111734 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3221.115901 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2221.115901 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 2981.472133 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 1981.472133 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 596212431 # number of overall hits -system.cpu.dcache.overall_miss_latency 29349951272 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 27166381000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.015053 # miss rate for overall accesses system.cpu.dcache.overall_misses 9111734 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 20238217272 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 18054647000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.015053 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 9111734 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 9107638 # number of replacements system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4091.845274 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4078.615858 # Cycle average of tags in use system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 75264000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 20287970000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 2244708 # number of writebacks system.cpu.icache.ReadReq_accesses 1819780130 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4089.753117 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3089.753117 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 3779.301746 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2779.301746 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 1819779328 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 3279982 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 3031000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 2477982 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 2229000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1819780130 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4089.753117 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3089.753117 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 3779.301746 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2779.301746 # average overall mshr miss latency system.cpu.icache.demand_hits 1819779328 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 3279982 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 3031000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses system.cpu.icache.demand_misses 802 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2477982 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 2229000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 1819780130 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4089.753117 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3089.753117 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 3779.301746 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2779.301746 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1819779328 # number of overall hits -system.cpu.icache.overall_miss_latency 3279982 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 3031000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses system.cpu.icache.overall_misses 802 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2477982 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 2229000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,27 +138,27 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 1 # number of replacements system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 625.996248 # Cycle average of tags in use +system.cpu.icache.tagsinuse 611.013893 # Cycle average of tags in use system.cpu.icache.total_refs 1819779328 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 9112536 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3215.890455 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1919.394872 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 2722.045846 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1719.036352 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 6952383 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 6946815413 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 5880035500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.237053 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 2160153 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 4146186590 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 3713381532 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.237053 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 2160153 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 2244708 # number of WriteReqNoAck|Writeback accesses(hits+misses) -system.cpu.l2cache.WriteReqNoAck|Writeback_hits 2215611 # number of WriteReqNoAck|Writeback hits -system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate 0.012962 # miss rate for WriteReqNoAck|Writeback accesses -system.cpu.l2cache.WriteReqNoAck|Writeback_misses 29097 # number of WriteReqNoAck|Writeback misses -system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate 0.012962 # mshr miss rate for WriteReqNoAck|Writeback accesses -system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses 29097 # number of WriteReqNoAck|Writeback MSHR misses +system.cpu.l2cache.Writeback_accesses 2244708 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2215611 # number of Writeback hits +system.cpu.l2cache.Writeback_miss_rate 0.012962 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 29097 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 0.012962 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 29097 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 4.244141 # Average number of references to valid blocks. @@ -168,29 +168,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3215.890455 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1919.394872 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 2722.045846 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1719.036352 # average overall mshr miss latency system.cpu.l2cache.demand_hits 6952383 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 6946815413 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 5880035500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.237053 # miss rate for demand accesses system.cpu.l2cache.demand_misses 2160153 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4146186590 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 3713381532 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.237053 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 2160153 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 11357244 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3173.148527 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1919.394872 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 2685.867535 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1719.036352 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 9167994 # number of overall hits -system.cpu.l2cache.overall_miss_latency 6946815413 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 5880035500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.192762 # miss rate for overall accesses system.cpu.l2cache.overall_misses 2189250 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4146186590 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 3713381532 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.190200 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 2160153 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -207,12 +207,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 2127385 # number of replacements system.cpu.l2cache.sampled_refs 2160153 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 32563.117941 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 31158.106837 # Cycle average of tags in use system.cpu.l2cache.total_refs 9167994 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 748591000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 122436614000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 1038202 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 31769223012 # number of cpu cycles simulated +system.cpu.numCycles 1235165291000 # number of cpu cycles simulated system.cpu.num_insts 1819780129 # Number of instructions executed system.cpu.num_refs 606571345 # Number of memory references system.cpu.workload.PROG:num_syscalls 29 # Number of system calls diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr index 87866a2a5..d0a887867 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr @@ -1 +1,3 @@ warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. +warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 9795f2e42..04020c643 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -23,7 +23,7 @@ activity=0 backComSize=5 choiceCtrBits=2 choicePredictorSize=8192 -clock=1 +clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out index 504c6e888..50da468a0 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out @@ -167,7 +167,7 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL [system.cpu] type=DerivO3CPU -clock=1 +clock=500 phase=0 numThreads=1 cpu_id=0 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt index dba9e1470..8e2806190 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 13130842 # Number of BTB hits -global.BPredUnit.BTBLookups 17054746 # Number of BTB lookups -global.BPredUnit.RASInCorrect 1205 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1949700 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 14620230 # Number of conditional branches predicted -global.BPredUnit.lookups 19607486 # Number of BP lookups -global.BPredUnit.usedRAS 1766776 # Number of times the RAS was used to get a target. -host_inst_rate 70212 # Simulator instruction rate (inst/s) -host_mem_usage 153248 # Number of bytes of host memory used -host_seconds 1198.94 # Real time elapsed on the host -host_tick_rate 95357 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 19046664 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 5327434 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 34568849 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 10915344 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 14247678 # Number of BTB hits +global.BPredUnit.BTBLookups 18312009 # Number of BTB lookups +global.BPredUnit.RASInCorrect 1187 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1953985 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 15742663 # Number of conditional branches predicted +global.BPredUnit.lookups 20998495 # Number of BP lookups +global.BPredUnit.usedRAS 1857732 # Number of times the RAS was used to get a target. +host_inst_rate 58248 # Simulator instruction rate (inst/s) +host_mem_usage 156992 # Number of bytes of host memory used +host_seconds 1445.19 # Real time elapsed on the host +host_tick_rate 23712867 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 20592604 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 6080799 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 35412339 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 11200166 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 84179709 # Number of instructions simulated -sim_seconds 0.000114 # Number of seconds simulated -sim_ticks 114327081 # Number of ticks simulated +sim_seconds 0.034270 # Number of seconds simulated +sim_ticks 34269677000 # Number of ticks simulated system.cpu.commit.COM:branches 10240685 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 2895131 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 3363462 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 73926385 +system.cpu.commit.COM:committed_per_cycle.samples 59572652 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 37511035 5074.11% - 1 16507127 2232.91% - 2 8529257 1153.75% - 3 3749717 507.22% - 4 1879220 254.20% - 5 1361115 184.12% - 6 851721 115.21% - 7 642062 86.85% - 8 2895131 391.62% + 0 25280039 4243.56% + 1 15284536 2565.70% + 2 7326530 1229.85% + 3 3334393 559.72% + 4 2152142 361.26% + 5 1242273 208.53% + 6 890288 149.45% + 7 698989 117.33% + 8 3363462 564.60% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 20034413 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 26537108 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 1937238 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 1941454 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 58539227 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 63250167 # The number of squashed insts skipped by commit system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 1.358131 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.358131 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 23376895 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 5393.890593 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4863.252964 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 23375917 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5275225 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000042 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 978 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 472 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2460806 # number of ReadReq MSHR miss cycles +system.cpu.cpi 0.814203 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.814203 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 23612894 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 4229.600000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3389.648438 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 23612269 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2643500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000026 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 625 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 113 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1735500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 506 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 512 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 6579.789722 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6507.873418 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6492638 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 55697920 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.001302 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 8465 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 6727 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 11310684 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 3064.490759 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3618.087558 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6493474 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 23379000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001173 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 7629 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 5893 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 6281000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1738 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 2809.444444 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_mshr_misses 1736 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 13310.407754 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 9 # number of cycles access was blocked +system.cpu.dcache.avg_refs 13392.234431 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 25285 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 29877998 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 6456.967595 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 6137.027629 # average overall mshr miss latency -system.cpu.dcache.demand_hits 29868555 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 60973145 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000316 # miss rate for demand accesses -system.cpu.dcache.demand_misses 9443 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 7199 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 13771490 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_accesses 30113997 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3152.713836 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3566.058719 # average overall mshr miss latency +system.cpu.dcache.demand_hits 30105743 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 26022500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000274 # miss rate for demand accesses +system.cpu.dcache.demand_misses 8254 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 6006 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 8016500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000075 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2244 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 2248 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 29877998 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 6456.967595 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 6137.027629 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 30113997 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3152.713836 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3566.058719 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 29868555 # number of overall hits -system.cpu.dcache.overall_miss_latency 60973145 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000316 # miss rate for overall accesses -system.cpu.dcache.overall_misses 9443 # number of overall misses -system.cpu.dcache.overall_mshr_hits 7199 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 13771490 # number of overall MSHR miss cycles +system.cpu.dcache.overall_hits 30105743 # number of overall hits +system.cpu.dcache.overall_miss_latency 26022500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000274 # miss rate for overall accesses +system.cpu.dcache.overall_misses 8254 # number of overall misses +system.cpu.dcache.overall_mshr_hits 6006 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 8016500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000075 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2244 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 2248 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 160 # number of replacements -system.cpu.dcache.sampled_refs 2244 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 162 # number of replacements +system.cpu.dcache.sampled_refs 2248 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1415.957077 # Cycle average of tags in use -system.cpu.dcache.total_refs 29868555 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1463.572116 # Cycle average of tags in use +system.cpu.dcache.total_refs 30105743 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 106 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 5155486 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 12562 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3109369 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 165294506 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 40322652 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 28299602 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 8350763 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 41264 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 148646 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 19607486 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 19380281 # Number of cache lines fetched -system.cpu.fetch.Cycles 48705122 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 491925 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 170506876 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 2058666 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.238310 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 19380281 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 14897618 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.072348 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 6099480 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 13208 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3247204 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 173741531 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 23444029 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 28861256 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 8966698 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 40444 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 1167888 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 20998495 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 20206829 # Number of cache lines fetched +system.cpu.fetch.Cycles 51475298 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 3593 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 180749377 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 2035048 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.306371 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 20206829 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 16105410 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.637162 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 82277149 +system.cpu.fetch.rateDist.samples 68539351 system.cpu.fetch.rateDist.min_value 0 - 0 52952312 6435.85% - 1 3129610 380.37% - 2 1369966 166.51% - 3 2017219 245.17% - 4 3854384 468.46% - 5 1357405 164.98% - 6 1550178 188.41% - 7 1288552 156.61% - 8 14757523 1793.64% + 0 37270886 5437.88% + 1 3420236 499.02% + 2 1457458 212.65% + 3 2151808 313.95% + 4 4198050 612.50% + 5 1495508 218.20% + 6 1665097 242.94% + 7 1343985 196.09% + 8 15536323 2266.77% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 19380281 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3416.377011 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2534.518183 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 19366483 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 47139170 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000712 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 13798 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 3761 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 25438959 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000518 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 10037 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 20206829 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3070.200019 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2096.460002 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 20196480 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 31773500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000512 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 10349 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 236 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 21201500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000500 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 10113 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1929.509116 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1997.080985 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 19380281 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3416.377011 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2534.518183 # average overall mshr miss latency -system.cpu.icache.demand_hits 19366483 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 47139170 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000712 # miss rate for demand accesses -system.cpu.icache.demand_misses 13798 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 3761 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 25438959 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000518 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 10037 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 20206829 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3070.200019 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2096.460002 # average overall mshr miss latency +system.cpu.icache.demand_hits 20196480 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 31773500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000512 # miss rate for demand accesses +system.cpu.icache.demand_misses 10349 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 236 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 21201500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000500 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 10113 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 19380281 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3416.377011 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2534.518183 # average overall mshr miss latency +system.cpu.icache.overall_accesses 20206829 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3070.200019 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2096.460002 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 19366483 # number of overall hits -system.cpu.icache.overall_miss_latency 47139170 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000712 # miss rate for overall accesses -system.cpu.icache.overall_misses 13798 # number of overall misses -system.cpu.icache.overall_mshr_hits 3761 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 25438959 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000518 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 10037 # number of overall MSHR misses +system.cpu.icache.overall_hits 20196480 # number of overall hits +system.cpu.icache.overall_miss_latency 31773500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000512 # miss rate for overall accesses +system.cpu.icache.overall_misses 10349 # number of overall misses +system.cpu.icache.overall_mshr_hits 236 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 21201500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000500 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 10113 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,162 +215,162 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 8123 # number of replacements -system.cpu.icache.sampled_refs 10037 # Sample count of references to valid blocks. +system.cpu.icache.replacements 8192 # number of replacements +system.cpu.icache.sampled_refs 10113 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1498.249784 # Cycle average of tags in use -system.cpu.icache.total_refs 19366483 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1564.702526 # Cycle average of tags in use +system.cpu.icache.total_refs 20196480 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 32049933 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 12923262 # Number of branches executed -system.cpu.iew.EXEC:nop 13162253 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.241494 # Inst execution rate -system.cpu.iew.EXEC:refs 31990682 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 7220394 # Number of stores executed +system.cpu.idleCycles 2998 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 13347594 # Number of branches executed +system.cpu.iew.EXEC:nop 13508406 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.523954 # Inst execution rate +system.cpu.iew.EXEC:refs 32463851 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 7352116 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 91915926 # num instructions consuming a value -system.cpu.iew.WB:count 100065162 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.718590 # average fanout of values written-back +system.cpu.iew.WB:consumers 95064439 # num instructions consuming a value +system.cpu.iew.WB:count 103132878 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.721353 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 66049838 # num instructions producing a value -system.cpu.iew.WB:rate 1.216196 # insts written-back per cycle -system.cpu.iew.WB:sent 100916733 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 2084205 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 596692 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 34568849 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 437 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 864110 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 10915344 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 150440832 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 24770288 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2226727 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 102146587 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 177017 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 68574976 # num instructions producing a value +system.cpu.iew.WB:rate 1.504725 # insts written-back per cycle +system.cpu.iew.WB:sent 104172184 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 2117203 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 606505 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 35412339 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 444 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 632938 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 11200166 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 155150547 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 25111735 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2600272 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 104450796 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 226857 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 827 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 8350763 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 211777 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 8966698 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 304686 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 3149 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 865223 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 1107 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 1001916 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 10875 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 167324 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 9618 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 14534436 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 4412649 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 167324 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 194984 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1889221 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.736306 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.736306 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 104373314 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 88969 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 9698 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 15377926 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 4697471 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 88969 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 207130 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1910073 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.228195 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.228195 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 107051068 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 7 0.00% # Type of FU issued - IntAlu 64752207 62.04% # Type of FU issued - IntMult 471285 0.45% # Type of FU issued + IntAlu 66598699 62.21% # Type of FU issued + IntMult 478232 0.45% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 2789912 2.67% # Type of FU issued - FloatCmp 115515 0.11% # Type of FU issued - FloatCvt 2364267 2.27% # Type of FU issued - FloatMult 305289 0.29% # Type of FU issued - FloatDiv 755087 0.72% # Type of FU issued + FloatAdd 2814666 2.63% # Type of FU issued + FloatCmp 115604 0.11% # Type of FU issued + FloatCvt 2391391 2.23% # Type of FU issued + FloatMult 308778 0.29% # Type of FU issued + FloatDiv 755076 0.71% # Type of FU issued FloatSqrt 324 0.00% # Type of FU issued - MemRead 25418322 24.35% # Type of FU issued - MemWrite 7401099 7.09% # Type of FU issued + MemRead 26034990 24.32% # Type of FU issued + MemWrite 7553301 7.06% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 1952486 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.018707 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 2233247 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.020862 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 163325 8.36% # attempts to use FU when none available + IntAlu 352978 15.81% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 1017 0.05% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 12505 0.64% # attempts to use FU when none available - FloatMult 2432 0.12% # attempts to use FU when none available - FloatDiv 905685 46.39% # attempts to use FU when none available + FloatAdd 856 0.04% # attempts to use FU when none available + FloatCmp 8 0.00% # attempts to use FU when none available + FloatCvt 3654 0.16% # attempts to use FU when none available + FloatMult 2325 0.10% # attempts to use FU when none available + FloatDiv 987087 44.20% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 774173 39.65% # attempts to use FU when none available - MemWrite 93349 4.78% # attempts to use FU when none available + MemRead 766963 34.34% # attempts to use FU when none available + MemWrite 119376 5.35% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 82277149 +system.cpu.iq.ISSUE:issued_per_cycle.samples 68539351 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 35738506 4343.67% - 1 18264427 2219.87% - 2 12740961 1548.54% - 3 6961052 846.05% - 4 4806764 584.22% - 5 2441659 296.76% - 6 994924 120.92% - 7 291934 35.48% - 8 36922 4.49% + 0 25564605 3729.92% + 1 14833050 2164.17% + 2 10859904 1584.48% + 3 6945297 1013.33% + 4 5154135 752.00% + 5 2881350 420.39% + 6 1567848 228.75% + 7 633355 92.41% + 8 99807 14.56% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.268558 # Inst issue rate -system.cpu.iq.iqInstsAdded 137278142 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 104373314 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 437 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 52505275 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 293840 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 48 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 49588547 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 12278 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4378.207161 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2293.937242 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 7195 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 22254427 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.413993 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 5083 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 11660083 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.413993 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 5083 # number of ReadReq MSHR misses +system.cpu.iq.ISSUE:rate 1.561892 # Inst issue rate +system.cpu.iq.iqInstsAdded 141641697 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 107051068 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 444 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 56891185 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 501220 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 55 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 52161048 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 12360 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 3103.922717 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1864.884465 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 7236 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 15904500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.414563 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 5124 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 9555668 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.414563 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 5124 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 106 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 106 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.436356 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.432865 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 12278 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4378.207161 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2293.937242 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 7195 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 22254427 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.413993 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 5083 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 12360 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 3103.922717 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1864.884465 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 7236 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 15904500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.414563 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 5124 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 11660083 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.413993 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 5083 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 9555668 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.414563 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 5124 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 12384 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4378.207161 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2293.937242 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 12466 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 3103.922717 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1864.884465 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 7301 # number of overall hits -system.cpu.l2cache.overall_miss_latency 22254427 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.410449 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 5083 # number of overall misses +system.cpu.l2cache.overall_hits 7342 # number of overall hits +system.cpu.l2cache.overall_miss_latency 15904500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.411038 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 5124 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 11660083 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.410449 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 5083 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 9555668 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.411038 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 5124 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -383,31 +383,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 5083 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 5124 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3292.223620 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7301 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3431.784338 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7342 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 82277149 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 2387077 # Number of cycles rename is blocking +system.cpu.numCycles 68539351 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 2079138 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1473927 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 41553511 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1059964 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 61 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 206590907 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 160246119 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 117849091 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 27232157 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 8350763 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 2654523 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 49421730 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 99118 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 461 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 5497153 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 451 # count of temporary serializing insts renamed -system.cpu.timesIdled 10204 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 1661115 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 25239317 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1954833 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 215732838 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 167129936 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 122925813 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 28288722 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 8966698 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 3960770 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 54498452 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 4706 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 484 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 9920797 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 473 # count of temporary serializing insts renamed +system.cpu.timesIdled 2 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini index 789f77815..24a71167b 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini @@ -1,33 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -38,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -59,7 +33,7 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic egid=100 env= euid=100 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out index b4087eb1c..296e0472f 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -31,7 +28,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf input=cin output=cout env= -cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic system=system uid=100 euid=100 @@ -50,7 +47,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false width=1 @@ -58,23 +55,3 @@ function_trace=false function_trace_start=0 simulate_stalls=false -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt index 2cd5a06bf..b11bd8cad 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1013473 # Simulator instruction rate (inst/s) -host_mem_usage 151596 # Number of bytes of host memory used -host_seconds 90.68 # Real time elapsed on the host -host_tick_rate 1013469 # Simulator tick rate (ticks/s) +host_inst_rate 754988 # Simulator instruction rate (inst/s) +host_mem_usage 150624 # Number of bytes of host memory used +host_seconds 121.73 # Real time elapsed on the host +host_tick_rate 377492666 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903057 # Number of instructions simulated -sim_seconds 0.000092 # Number of seconds simulated -sim_ticks 91903056 # Number of ticks simulated +sim_seconds 0.045952 # Number of seconds simulated +sim_ticks 45951528000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 91903057 # number of cpu cycles simulated diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out index 00387ae5c..98777e0af 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out @@ -66,7 +66,7 @@ The rand generator seed was at utemp() : 1 I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 - 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46 + 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 @@ -103,7 +103,7 @@ The rand generator seed was at utemp() : 1 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 - 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48 + 40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr index eb1796ead..f33d007a7 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini index e2265235e..cd04983c0 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -1,33 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -38,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -182,7 +156,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing egid=100 env= euid=100 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out index fcf06c7db..3089af658 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -31,7 +28,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf input=cin output=cout env= -cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing system=system uid=100 euid=100 @@ -50,7 +47,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -179,23 +176,3 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt index 5cdae9c4a..b45fb965e 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 607322 # Simulator instruction rate (inst/s) -host_mem_usage 157212 # Number of bytes of host memory used -host_seconds 151.33 # Real time elapsed on the host -host_tick_rate 1013960 # Simulator tick rate (ticks/s) +host_inst_rate 335846 # Simulator instruction rate (inst/s) +host_mem_usage 156240 # Number of bytes of host memory used +host_seconds 273.71 # Real time elapsed on the host +host_tick_rate 216396349 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903057 # Number of instructions simulated -sim_seconds 0.000153 # Number of seconds simulated -sim_ticks 153438012 # Number of ticks simulated +sim_seconds 0.059229 # Number of seconds simulated +sim_ticks 59229023000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3701.356540 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2701.356540 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 3629.746835 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2629.746835 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 19995724 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1754443 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 1720500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 474 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1280443 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1246500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 474 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3869.070366 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2869.070366 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 3602.116705 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2602.116705 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 6499355 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 6763135 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 6296500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1748 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 5015135 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 4548500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3833.293429 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2833.293429 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 3608.010801 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2608.010801 # average overall mshr miss latency system.cpu.dcache.demand_hits 26495079 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 8517578 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 8017000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses system.cpu.dcache.demand_misses 2222 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 6295578 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5795000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 2222 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3833.293429 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2833.293429 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 3608.010801 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2608.010801 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 26495079 # number of overall hits -system.cpu.dcache.overall_miss_latency 8517578 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 8017000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses system.cpu.dcache.overall_misses 2222 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 6295578 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5795000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 2222 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.sampled_refs 2222 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1398.130089 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1441.710869 # Cycle average of tags in use system.cpu.dcache.total_refs 26495079 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 104 # number of writebacks system.cpu.icache.ReadReq_accesses 91903058 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3117.603760 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2117.603760 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 3077.908343 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2077.908343 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 91894548 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 26530808 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 26193000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 18020808 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 17683000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 91903058 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3117.603760 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2117.603760 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 3077.908343 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2077.908343 # average overall mshr miss latency system.cpu.icache.demand_hits 91894548 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 26530808 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 26193000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 18020808 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 17683000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 91903058 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3117.603760 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2117.603760 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 3077.908343 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2077.908343 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 91894548 # number of overall hits -system.cpu.icache.overall_miss_latency 26530808 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 26193000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses system.cpu.icache.overall_misses 8510 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 18020808 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 17683000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 6681 # number of replacements system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1374.520503 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1418.735069 # Cycle average of tags in use system.cpu.icache.total_refs 91894548 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 10732 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2892.483207 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1885.503778 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 2703.820319 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1702.820319 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 5968 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 13779790 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 12881000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.443906 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 4764 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 8982540 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 8112236 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.443906 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 4764 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses) @@ -164,29 +164,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 10732 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2892.483207 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1885.503778 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 2703.820319 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1702.820319 # average overall mshr miss latency system.cpu.l2cache.demand_hits 5968 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 13779790 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 12881000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.443906 # miss rate for demand accesses system.cpu.l2cache.demand_misses 4764 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 8982540 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 8112236 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.443906 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 4764 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 10836 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2892.483207 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1885.503778 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 2703.820319 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1702.820319 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 6072 # number of overall hits -system.cpu.l2cache.overall_miss_latency 13779790 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 12881000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.439646 # miss rate for overall accesses system.cpu.l2cache.overall_misses 4764 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 8982540 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 8112236 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.439646 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 4764 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -203,12 +203,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 4764 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3073.845977 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 3173.029647 # Cycle average of tags in use system.cpu.l2cache.total_refs 6072 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 153438012 # number of cpu cycles simulated +system.cpu.numCycles 59229023000 # number of cpu cycles simulated system.cpu.num_insts 91903057 # Number of instructions executed system.cpu.num_refs 26537109 # Number of memory references system.cpu.workload.PROG:num_syscalls 389 # Number of system calls diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out index 00387ae5c..98777e0af 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out @@ -66,7 +66,7 @@ The rand generator seed was at utemp() : 1 I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 - 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46 + 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 @@ -103,7 +103,7 @@ The rand generator seed was at utemp() : 1 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 - 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48 + 40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr index eb1796ead..f33d007a7 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. From ee188e88cd1f8c81e624cf5cfc29657a262fe531 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Fri, 27 Apr 2007 11:53:14 -0700 Subject: [PATCH 29/68] whack the old list of outstanding issues, and put the new list at the top --HG-- extra : convert_revision : af893f11c43bf0033886c2fda0c0421403f041c2 --- RELEASE_NOTES | 28 ++++++++++++---------------- 1 file changed, 12 insertions(+), 16 deletions(-) diff --git a/RELEASE_NOTES b/RELEASE_NOTES index 47507ba3b..1deb3b629 100644 --- a/RELEASE_NOTES +++ b/RELEASE_NOTES @@ -1,3 +1,15 @@ +Outstanding issues for 2.0 release: +-------------------- +1. Better statistics for the caches. +2. Clean up more SimObject parameter stuff +3. Checkpoint/switchover testing +4. FS mode doesn't work under Cygwin +5. memtest regression crashes under Cygwin +6. Make repository public +7. Testing +8. Validation +9. Testing + Apr. XX, 2007: m5_2.0_beta3 -------------------- New Features @@ -11,18 +23,6 @@ Bug fixes since beta 2: 5. Several compile fixes, including gcc 4.1 6. Many other minor fixes and enhancements -Outstanding issues for 2.0 release: --------------------- -1. Better statistics for the caches. -2. Clean up more SimObject parameter stuff -3. Checkpoint/switchover testing -4. FS mode doesn't work under Cygwin -5. memtest regression crashes under Cygwin -6. Make repository public -7. Testing -8. Validation -9. Testing - Nov. 28, 2006: m5_2.0_beta2 -------------------- Bug fixes since beta 1: @@ -35,10 +35,6 @@ Bug fixes since beta 1: 7. Single config file for all SpecCPU2000 benchmarks 8. Several other minor bug fixes and enhancements -Outstading issues for 2.0 release: -1. Simulator performance fixes for memory system/caches -2. Multiprocessor linux boot using the detailed O3 CPU model - Aug. 25, 2006: m5_2.0_beta patch 1 -------------------- Handful of minor bug fixes for m5_2.0_beta, From b5037ad82b954a86102cc03325a12c755c59f347 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Fri, 27 Apr 2007 12:15:25 -0700 Subject: [PATCH 30/68] Actually move the time two minutes into the future to make sure that we get the result that we want --HG-- extra : convert_revision : d3e1aca921705fe8c8b955229c2afcd2aa9b36ea --- util/make_release.py | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/util/make_release.py b/util/make_release.py index 250ee56ac..09629a78a 100755 --- a/util/make_release.py +++ b/util/make_release.py @@ -33,6 +33,7 @@ import os import re import shutil import sys +import time from glob import glob from os import system @@ -42,9 +43,10 @@ def mkdir(*args): path = joinpath(*args) os.mkdir(path) -def touch(*args): +def touch(*args, **kwargs): + when = kwargs.get('when', None) path = joinpath(*args) - os.utime(path, None) + os.utime(path, when) def rmtree(*args): path = joinpath(*args) @@ -110,12 +112,17 @@ mkdir(encumbered_dir) system('bk export -tplain -w -r+ %s' % release_dir) -# make sure scons doesn't try to run flex unnecessarily -touch(release_dir, 'src/encumbered/eio/exolex.cc') -# make sure scons doesn't try to rebuild the de.msg file since it +# move the time forward on some files by a couple of minutes so we can +# avoid building things unnecessarily +when = int(time.time()) + 120 + +# make sure scons doesn't try to run flex unnecessarily +touch(release_dir, 'src/encumbered/eio/exolex.cc', when=(when, when)) + +# make sure libelf doesn't try to rebuild the de.msg file since it # might fail on non linux machines -touch(release_dir, 'ext/libelf/po/de.msg') +touch(release_dir, 'ext/libelf/po/de.msg', when=(when, when)) # get rid of non-shipping code rmtree(release_dir, 'src/encumbered/dev') From 71b6499c126632766606fe227a99e06b79ddcc79 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Fri, 27 Apr 2007 16:36:19 -0400 Subject: [PATCH 31/68] Updates for clock changes. --HG-- extra : convert_revision : 88699ba98a738a62204ae4182f7ee5dcab9285eb --- .../ref/sparc/linux/simple-atomic/config.ini | 2 +- .../ref/sparc/linux/simple-atomic/config.out | 2 +- .../ref/sparc/linux/simple-atomic/m5stats.txt | 12 +- .../ref/sparc/linux/simple-atomic/stderr | 1 - .../ref/sparc/linux/simple-atomic/stdout | 6 +- .../ref/sparc/linux/simple-timing/config.ini | 2 +- .../ref/sparc/linux/simple-timing/config.out | 2 +- .../ref/sparc/linux/simple-timing/m5stats.txt | 110 ++++++++--------- .../ref/sparc/linux/simple-timing/stderr | 1 - .../ref/sparc/linux/simple-timing/stdout | 6 +- .../ref/sparc/linux/simple-atomic/config.ini | 2 +- .../ref/sparc/linux/simple-atomic/config.out | 2 +- .../ref/sparc/linux/simple-atomic/m5stats.txt | 12 +- .../ref/sparc/linux/simple-atomic/stderr | 1 - .../ref/sparc/linux/simple-atomic/stdout | 6 +- .../ref/sparc/linux/simple-timing/config.ini | 2 +- .../ref/sparc/linux/simple-timing/config.out | 2 +- .../ref/sparc/linux/simple-timing/m5stats.txt | 112 ++++++++--------- .../ref/sparc/linux/simple-timing/stderr | 1 - .../ref/sparc/linux/simple-timing/stdout | 6 +- .../ref/sparc/linux/simple-atomic/config.ini | 2 +- .../ref/sparc/linux/simple-atomic/config.out | 2 +- .../ref/sparc/linux/simple-atomic/m5stats.txt | 12 +- .../ref/sparc/linux/simple-atomic/stderr | 1 - .../ref/sparc/linux/simple-atomic/stdout | 6 +- .../ref/sparc/linux/simple-timing/config.ini | 2 +- .../ref/sparc/linux/simple-timing/config.out | 2 +- .../ref/sparc/linux/simple-timing/m5stats.txt | 114 +++++++++--------- .../ref/sparc/linux/simple-timing/stderr | 1 - .../ref/sparc/linux/simple-timing/stdout | 6 +- .../ref/sparc/linux/simple-atomic/config.ini | 2 +- .../ref/sparc/linux/simple-atomic/config.out | 2 +- .../ref/sparc/linux/simple-atomic/m5stats.txt | 12 +- .../ref/sparc/linux/simple-atomic/stderr | 1 - .../ref/sparc/linux/simple-atomic/stdout | 6 +- .../ref/sparc/linux/simple-timing/config.ini | 2 +- .../ref/sparc/linux/simple-timing/config.out | 2 +- .../ref/sparc/linux/simple-timing/m5stats.txt | 108 ++++++++--------- .../ref/sparc/linux/simple-timing/stderr | 1 - .../ref/sparc/linux/simple-timing/stdout | 6 +- 40 files changed, 286 insertions(+), 294 deletions(-) diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini index 1cf7e8a9b..0a5320e76 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini @@ -12,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.out b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.out index f6ace951d..24b104442 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.out +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.out @@ -47,7 +47,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false width=1 diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt index 6cf88af9d..c58a162a3 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 713136 # Simulator instruction rate (inst/s) -host_mem_usage 148308 # Number of bytes of host memory used -host_seconds 2088.68 # Real time elapsed on the host -host_tick_rate 713136 # Simulator tick rate (ticks/s) +host_inst_rate 687229 # Simulator instruction rate (inst/s) +host_mem_usage 149588 # Number of bytes of host memory used +host_seconds 2167.42 # Real time elapsed on the host +host_tick_rate 343614381 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489514860 # Number of instructions simulated -sim_seconds 0.001490 # Number of seconds simulated -sim_ticks 1489514859 # Number of ticks simulated +sim_seconds 0.744757 # Number of seconds simulated +sim_ticks 744757429500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1489514860 # number of cpu cycles simulated diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr index e74a68c71..6fe2fe04f 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr @@ -2,6 +2,5 @@ warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0xb4000 length 0x10. warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x0 length 0x0. -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout index 3f5dab90b..bf28090fa 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout @@ -36,9 +36,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 21 2007 00:46:54 -M5 started Wed Mar 21 00:47:20 2007 +M5 compiled Apr 27 2007 14:35:32 +M5 started Fri Apr 27 14:35:40 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic tests/run.py long/00.gzip/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1489514859 because target called exit() +Exiting @ tick 744757429500 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini index 75db6656a..52243641a 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -12,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.out b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.out index 11cb72660..bcc607b12 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.out +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.out @@ -47,7 +47,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false // width not specified diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt index f83fd185e..5a976b1e5 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 531377 # Simulator instruction rate (inst/s) -host_mem_usage 154376 # Number of bytes of host memory used -host_seconds 2803.12 # Real time elapsed on the host -host_tick_rate 1212716 # Simulator tick rate (ticks/s) +host_inst_rate 510352 # Simulator instruction rate (inst/s) +host_mem_usage 155048 # Number of bytes of host memory used +host_seconds 2918.60 # Real time elapsed on the host +host_tick_rate 353062922 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489514860 # Number of instructions simulated -sim_seconds 0.003399 # Number of seconds simulated -sim_ticks 3399390003 # Number of ticks simulated +sim_seconds 1.030450 # Number of seconds simulated +sim_ticks 1030449926500 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 402511688 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 2848.782706 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1848.782706 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 2729.300186 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1729.300186 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 402318208 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 551182478 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 528065000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 193480 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 357702478 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 334585000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 193480 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 3103.285714 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2103.285714 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 3071.428571 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2071.428571 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 21723 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 21500 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 14723 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 14500 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 166846642 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3023.717816 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2023.717816 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 2724.587576 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 1724.587576 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 166586897 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 785395584 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 707698000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.001557 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 259745 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 525650584 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 447953000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.001557 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 259745 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 569358330 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2949.038694 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 1949.038694 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 2726.599371 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 1726.599371 # average overall mshr miss latency system.cpu.dcache.demand_hits 568905105 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1336578062 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 1235763000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000796 # miss rate for demand accesses system.cpu.dcache.demand_misses 453225 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 883353062 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 782538000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000796 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 453225 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 569358330 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2949.038694 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 1949.038694 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 2726.599371 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 1726.599371 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 568905105 # number of overall hits -system.cpu.dcache.overall_miss_latency 1336578062 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 1235763000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000796 # miss rate for overall accesses system.cpu.dcache.overall_misses 453225 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 883353062 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 782538000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000796 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 453225 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 449136 # number of replacements system.cpu.dcache.sampled_refs 453232 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4068.114109 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.694265 # Cycle average of tags in use system.cpu.dcache.total_refs 568906424 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 33495000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 112631000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 316447 # number of writebacks system.cpu.icache.ReadReq_accesses 1489514861 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3979.992714 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2979.992714 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 3687.613843 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2687.613843 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 1489513763 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 4370032 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 4049000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 1098 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 3272032 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 2951000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 1098 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1489514861 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3979.992714 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2979.992714 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 3687.613843 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2687.613843 # average overall mshr miss latency system.cpu.icache.demand_hits 1489513763 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 4370032 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 4049000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses system.cpu.icache.demand_misses 1098 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 3272032 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 2951000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 1098 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 1489514861 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3979.992714 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2979.992714 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 3687.613843 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2687.613843 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1489513763 # number of overall hits -system.cpu.icache.overall_miss_latency 4370032 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 4049000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses system.cpu.icache.overall_misses 1098 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 3272032 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 2951000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 1098 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -148,19 +148,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 115 # number of replacements system.cpu.icache.sampled_refs 1098 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 865.251814 # Cycle average of tags in use +system.cpu.icache.tagsinuse 891.763656 # Cycle average of tags in use system.cpu.icache.total_refs 1489513763 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 454330 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3215.864263 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1941.261615 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 2631.120103 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1629.899651 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 427145 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 87423270 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 71527000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.059835 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 27185 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 52773197 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 44308822 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.059835 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 27185 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 316447 # number of Writeback accesses(hits+misses) @@ -178,29 +178,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 454330 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3215.864263 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1941.261615 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 2631.120103 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1629.899651 # average overall mshr miss latency system.cpu.l2cache.demand_hits 427145 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 87423270 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 71527000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.059835 # miss rate for demand accesses system.cpu.l2cache.demand_misses 27185 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 52773197 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 44308822 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.059835 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 27185 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 770777 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3214.799956 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1941.261615 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 2630.249320 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1629.899651 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 743583 # number of overall hits -system.cpu.l2cache.overall_miss_latency 87423270 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 71527000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.035281 # miss rate for overall accesses system.cpu.l2cache.overall_misses 27194 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 52773197 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 44308822 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.035270 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 27185 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -217,12 +217,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 2632 # number of replacements system.cpu.l2cache.sampled_refs 27185 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 23773.580402 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 24268.399126 # Cycle average of tags in use system.cpu.l2cache.total_refs 743583 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 2531 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 3399390003 # number of cpu cycles simulated +system.cpu.numCycles 1030449926500 # number of cpu cycles simulated system.cpu.num_insts 1489514860 # Number of instructions executed system.cpu.num_refs 569359656 # Number of memory references system.cpu.workload.PROG:num_syscalls 19 # Number of system calls diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr index e74a68c71..6fe2fe04f 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr @@ -2,6 +2,5 @@ warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0xb4000 length 0x10. warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x0 length 0x0. -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout index 8d54e9042..6f0bc150a 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout @@ -36,9 +36,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 29 2007 03:54:03 -M5 started Thu Mar 29 03:54:23 2007 +M5 compiled Apr 27 2007 14:35:32 +M5 started Fri Apr 27 14:35:40 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing tests/run.py long/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 3399390003 because target called exit() +Exiting @ tick 1030449926500 because target called exit() diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini index 73a28200e..368feb9a9 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini @@ -12,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.out b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.out index 2b86e6bfb..24228b2bd 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.out +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.out @@ -47,7 +47,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false width=1 diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt index 41e6bfc52..7e603ae8c 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 624449 # Simulator instruction rate (inst/s) -host_mem_usage 148644 # Number of bytes of host memory used -host_seconds 2753.78 # Real time elapsed on the host -host_tick_rate 624449 # Simulator tick rate (ticks/s) +host_inst_rate 658093 # Simulator instruction rate (inst/s) +host_mem_usage 149896 # Number of bytes of host memory used +host_seconds 2613.00 # Real time elapsed on the host +host_tick_rate 329046277 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1719594534 # Number of instructions simulated -sim_seconds 0.001720 # Number of seconds simulated -sim_ticks 1719594533 # Number of ticks simulated +sim_seconds 0.859797 # Number of seconds simulated +sim_ticks 859797266500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1719594534 # number of cpu cycles simulated diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr index 9c09fd847..cf178f133 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr @@ -2,6 +2,5 @@ warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0xa2000 length 0x10. warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x0 length 0x0. -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout index 6711761e8..f52ad5eac 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout @@ -25,9 +25,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 23 2007 22:37:06 -M5 started Fri Mar 23 22:37:22 2007 +M5 compiled Apr 27 2007 14:35:32 +M5 started Fri Apr 27 15:11:49 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic tests/run.py long/10.mcf/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1719594533 because target called exit() +Exiting @ tick 859797266500 because target called exit() diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini index dfb81664a..6e102e359 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -12,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out index e5ed0b288..970fa6992 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out @@ -47,7 +47,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false // width not specified diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt index b11288b2d..988dc8a7f 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 446147 # Simulator instruction rate (inst/s) -host_mem_usage 154148 # Number of bytes of host memory used -host_seconds 3854.32 # Real time elapsed on the host -host_tick_rate 13681801 # Simulator tick rate (ticks/s) +host_inst_rate 462859 # Simulator instruction rate (inst/s) +host_mem_usage 155288 # Number of bytes of host memory used +host_seconds 3715.16 # Real time elapsed on the host +host_tick_rate 345995852 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1719594534 # Number of instructions simulated -sim_seconds 0.052734 # Number of seconds simulated -sim_ticks 52734070003 # Number of ticks simulated +sim_seconds 1.285430 # Number of seconds simulated +sim_ticks 1285429818500 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 607807189 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3420.154300 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2420.154300 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 3129.930590 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2129.930590 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 594739458 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 44693656366 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 40901091000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.021500 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 13067731 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 31625925366 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 27833360000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.021500 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 13067731 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 15448 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 3631.818182 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2631.818182 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 3090.909091 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2090.909091 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 15437 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 39950 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 34000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.000712 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 11 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 28950 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 23000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.000712 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 11 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 166970997 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3255.499606 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2255.499606 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 2764.531806 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 1764.531806 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 165264000 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 5557128061 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 4719047500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.010223 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1706997 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 3850131061 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3012050500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.010223 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1706997 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 774778186 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3401.130933 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2401.130933 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 3087.714271 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2087.714271 # average overall mshr miss latency system.cpu.dcache.demand_hits 760003458 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 50250784427 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 45620138500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.019070 # miss rate for demand accesses system.cpu.dcache.demand_misses 14774728 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 35476056427 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 30845410500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.019070 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 14774728 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 774778186 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3401.130933 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2401.130933 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 3087.714271 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2087.714271 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 760003458 # number of overall hits -system.cpu.dcache.overall_miss_latency 50250784427 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 45620138500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.019070 # miss rate for overall accesses system.cpu.dcache.overall_misses 14774728 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 35476056427 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 30845410500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.019070 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 14774728 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 14770643 # number of replacements system.cpu.dcache.sampled_refs 14774739 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.978951 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.607725 # Cycle average of tags in use system.cpu.dcache.total_refs 760018895 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 35437000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 1932183000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 4191356 # number of writebacks system.cpu.icache.ReadReq_accesses 1719594535 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4032.295228 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3032.295228 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 3753.607103 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2753.607103 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 1719593634 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 3633098 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 3382000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 901 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 2732098 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 2481000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 901 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1719594535 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4032.295228 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3032.295228 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 3753.607103 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2753.607103 # average overall mshr miss latency system.cpu.icache.demand_hits 1719593634 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 3633098 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 3382000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses system.cpu.icache.demand_misses 901 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2732098 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 2481000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 901 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 1719594535 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4032.295228 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3032.295228 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 3753.607103 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2753.607103 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1719593634 # number of overall hits -system.cpu.icache.overall_miss_latency 3633098 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 3382000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses system.cpu.icache.overall_misses 901 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2732098 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 2481000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 901 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -148,19 +148,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 31 # number of replacements system.cpu.icache.sampled_refs 901 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 750.163929 # Cycle average of tags in use +system.cpu.icache.tagsinuse 737.434314 # Cycle average of tags in use system.cpu.icache.total_refs 1719593634 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 14775639 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3097.556051 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1926.730191 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 2607.028468 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1605.780536 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 8592784 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 19151739918 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 16118879000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.418449 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 6182855 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 11912693395 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 9928308213 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.418449 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 6182855 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 4191356 # number of Writeback accesses(hits+misses) @@ -178,29 +178,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 14775639 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3097.556051 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1926.730191 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 2607.028468 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1605.780536 # average overall mshr miss latency system.cpu.l2cache.demand_hits 8592784 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 19151739918 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 16118879000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.418449 # miss rate for demand accesses system.cpu.l2cache.demand_misses 6182855 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 11912693395 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 9928308213 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.418449 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 6182855 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 18966995 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3083.976361 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1926.730191 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 2595.599252 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1605.780536 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 12756915 # number of overall hits -system.cpu.l2cache.overall_miss_latency 19151739918 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 16118879000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.327415 # miss rate for overall accesses system.cpu.l2cache.overall_misses 6210080 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 11912693395 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 9928308213 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.325980 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 6182855 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -217,12 +217,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 6150087 # number of replacements system.cpu.l2cache.sampled_refs 6182855 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 27594.660688 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 26097.875810 # Cycle average of tags in use system.cpu.l2cache.total_refs 12756915 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 12316534000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 390549075000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 1069081 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 52734070003 # number of cpu cycles simulated +system.cpu.numCycles 1285429818500 # number of cpu cycles simulated system.cpu.num_insts 1719594534 # Number of instructions executed system.cpu.num_refs 774793634 # Number of memory references system.cpu.workload.PROG:num_syscalls 632 # Number of system calls diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr index 9c09fd847..cf178f133 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr @@ -2,6 +2,5 @@ warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0xa2000 length 0x10. warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x0 length 0x0. -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout index 7d97093d4..d1c7d6062 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout @@ -25,9 +25,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 29 2007 15:41:48 -M5 started Thu Mar 29 15:42:11 2007 +M5 compiled Apr 27 2007 14:35:32 +M5 started Fri Apr 27 15:24:20 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing tests/run.py long/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 52734070003 because target called exit() +Exiting @ tick 1285429818500 because target called exit() diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini index 7dbc37b58..7932bf16f 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini @@ -12,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out index ee1fc877f..b69343874 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out @@ -47,7 +47,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false width=1 diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt index 323b8a93c..37d044e8d 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 638506 # Simulator instruction rate (inst/s) -host_mem_usage 150340 # Number of bytes of host memory used -host_seconds 213.38 # Real time elapsed on the host -host_tick_rate 638505 # Simulator tick rate (ticks/s) +host_inst_rate 644632 # Simulator instruction rate (inst/s) +host_mem_usage 151548 # Number of bytes of host memory used +host_seconds 211.36 # Real time elapsed on the host +host_tick_rate 322315545 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136246936 # Number of instructions simulated -sim_seconds 0.000136 # Number of seconds simulated -sim_ticks 136246935 # Number of ticks simulated +sim_seconds 0.068123 # Number of seconds simulated +sim_ticks 68123467500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 136246936 # number of cpu cycles simulated diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr index c0f1c1fbb..08cfb2451 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr @@ -2,7 +2,6 @@ warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x1838c0 length 0x10. warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x0 length 0x0. -0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. warn: ignoring syscall time(4026527856, 4026528256, ...) diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout index 8e5f7bf90..794510e19 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 21 2007 00:48:18 -M5 started Wed Mar 21 00:48:40 2007 +M5 compiled Apr 27 2007 14:35:32 +M5 started Fri Apr 27 15:55:23 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic tests/run.py long/50.vortex/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 136246935 because target called exit() +Exiting @ tick 68123467500 because target called exit() diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini index 770dac1b9..1bc14e993 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -12,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out index 30db17922..cb469d872 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out @@ -47,7 +47,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false // width not specified diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt index 78f34213e..4e8db9778 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 473146 # Simulator instruction rate (inst/s) -host_mem_usage 156372 # Number of bytes of host memory used -host_seconds 287.96 # Real time elapsed on the host -host_tick_rate 4801122 # Simulator tick rate (ticks/s) +host_inst_rate 466766 # Simulator instruction rate (inst/s) +host_mem_usage 157052 # Number of bytes of host memory used +host_seconds 291.90 # Real time elapsed on the host +host_tick_rate 335938336 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136246936 # Number of instructions simulated -sim_seconds 0.001383 # Number of seconds simulated -sim_ticks 1382530003 # Number of ticks simulated +sim_seconds 0.098059 # Number of seconds simulated +sim_ticks 98059078500 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3575.086285 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2575.086285 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 3241.706786 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2241.706786 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 37185812 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 162627100 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 147462000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 45489 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 117138100 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 101973000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 45489 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 3413.933333 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2413.933333 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 3166.666667 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2166.666667 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 15901 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 51209 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 47500 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.000942 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 15 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 36209 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 32500 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.000942 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 15 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 4579.703729 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3579.703729 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 3588.938331 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2588.938331 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 20759130 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 481665760 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 377463000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.005041 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 105174 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 376491760 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 272289000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.005041 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 105174 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 4276.384116 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3276.384116 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 3484.100277 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2484.100277 # average overall mshr miss latency system.cpu.dcache.demand_hits 57944942 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 644292860 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 524925000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002593 # miss rate for demand accesses system.cpu.dcache.demand_misses 150663 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 493629860 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 374262000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002593 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 150663 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 4276.384116 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3276.384116 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 3484.100277 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2484.100277 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 57944942 # number of overall hits -system.cpu.dcache.overall_miss_latency 644292860 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 524925000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002593 # miss rate for overall accesses system.cpu.dcache.overall_misses 150663 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 493629860 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 374262000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002593 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 150663 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 146582 # number of replacements system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4060.510189 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4090.058697 # Cycle average of tags in use system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 33018000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 224414000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 107279 # number of writebacks system.cpu.icache.ReadReq_accesses 136246937 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2909.600795 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1909.600795 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 2800.327765 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1800.327765 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 136059913 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 544165179 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 523728500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.001373 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 357141179 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 336704500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.001373 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 136246937 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2909.600795 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1909.600795 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 2800.327765 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1800.327765 # average overall mshr miss latency system.cpu.icache.demand_hits 136059913 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 544165179 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 523728500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.001373 # miss rate for demand accesses system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 357141179 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 336704500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.001373 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 136246937 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2909.600795 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1909.600795 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 2800.327765 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1800.327765 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 136059913 # number of overall hits -system.cpu.icache.overall_miss_latency 544165179 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 523728500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.001373 # miss rate for overall accesses system.cpu.icache.overall_misses 187024 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 357141179 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 336704500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.001373 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -148,19 +148,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 184976 # number of replacements system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1952.728312 # Cycle average of tags in use +system.cpu.icache.tagsinuse 2008.440865 # Cycle average of tags in use system.cpu.icache.total_refs 136059913 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 1000315000 # Cycle when the warmup percentage was hit. +system.cpu.icache.warmup_cycle 69827484000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 337636 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3564.034868 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1961.482636 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 2644.770157 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1643.366085 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 202957 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 480000652 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 356195000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.398888 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 134679 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 264170520 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 221326901 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.398888 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 134679 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 107279 # number of Writeback accesses(hits+misses) @@ -178,29 +178,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 337636 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3564.034868 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1961.482636 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 2644.770157 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1643.366085 # average overall mshr miss latency system.cpu.l2cache.demand_hits 202957 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 480000652 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 356195000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.398888 # miss rate for demand accesses system.cpu.l2cache.demand_misses 134679 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 264170520 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 221326901 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.398888 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 134679 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 444915 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3550.642088 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1961.482636 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 2634.831752 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1643.366085 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 309728 # number of overall hits -system.cpu.l2cache.overall_miss_latency 480000652 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 356195000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.303849 # miss rate for overall accesses system.cpu.l2cache.overall_misses 135187 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 264170520 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 221326901 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.302707 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 134679 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -217,12 +217,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 101911 # number of replacements system.cpu.l2cache.sampled_refs 134679 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 30685.350019 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 32141.182824 # Cycle average of tags in use system.cpu.l2cache.total_refs 309728 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 319451000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 20627583000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 82918 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1382530003 # number of cpu cycles simulated +system.cpu.numCycles 98059078500 # number of cpu cycles simulated system.cpu.num_insts 136246936 # Number of instructions executed system.cpu.num_refs 58111522 # Number of memory references system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr index c0f1c1fbb..08cfb2451 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr @@ -2,7 +2,6 @@ warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x1838c0 length 0x10. warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x0 length 0x0. -0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. warn: ignoring syscall time(4026527856, 4026528256, ...) diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout index dc2b61804..08ec05c3a 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 29 2007 03:55:17 -M5 started Thu Mar 29 03:55:38 2007 +M5 compiled Apr 27 2007 14:35:32 +M5 started Fri Apr 27 15:58:57 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing tests/run.py long/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1382530003 because target called exit() +Exiting @ tick 98059078500 because target called exit() diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini index 2a1613fa1..5aa5f86fe 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini @@ -12,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out index d24c09793..f078d661c 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out @@ -47,7 +47,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false width=1 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt index 45fd6b479..5532c6dba 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 676464 # Simulator instruction rate (inst/s) -host_mem_usage 149916 # Number of bytes of host memory used -host_seconds 285.95 # Real time elapsed on the host -host_tick_rate 676463 # Simulator tick rate (ticks/s) +host_inst_rate 668374 # Simulator instruction rate (inst/s) +host_mem_usage 150556 # Number of bytes of host memory used +host_seconds 289.41 # Real time elapsed on the host +host_tick_rate 334186387 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193435973 # Number of instructions simulated -sim_seconds 0.000193 # Number of seconds simulated -sim_ticks 193435972 # Number of ticks simulated +sim_seconds 0.096718 # Number of seconds simulated +sim_ticks 96717986000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 193435973 # number of cpu cycles simulated diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr index 94662b6e8..18e13818c 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr @@ -2,7 +2,6 @@ warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x11e394 length 0x10. warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x0 length 0x0. -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout index 7c0e5ba5f..2cdcc205c 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout @@ -18,11 +18,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 12 2007 16:53:49 -M5 started Mon Mar 12 17:37:07 2007 +M5 compiled Apr 27 2007 14:35:32 +M5 started Fri Apr 27 16:03:50 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic tests/run.py long/70.twolf/sparc/linux/simple-atomic Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second -Exiting @ tick 193435972 because target called exit() +Exiting @ tick 96717986000 because target called exit() diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini index 0e057cbbe..ec76ab996 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -12,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out index 5f60c76d0..dbecb5fa5 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out @@ -47,7 +47,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false // width not specified diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt index 2fbdef851..2c6679b72 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 471554 # Simulator instruction rate (inst/s) -host_mem_usage 155352 # Number of bytes of host memory used -host_seconds 410.21 # Real time elapsed on the host -host_tick_rate 766692 # Simulator tick rate (ticks/s) +host_inst_rate 490451 # Simulator instruction rate (inst/s) +host_mem_usage 156012 # Number of bytes of host memory used +host_seconds 394.40 # Real time elapsed on the host +host_tick_rate 342594746 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193435973 # Number of instructions simulated -sim_seconds 0.000315 # Number of seconds simulated -sim_ticks 314505003 # Number of ticks simulated +sim_seconds 0.135121 # Number of seconds simulated +sim_ticks 135120940500 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 57734138 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3705.925703 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2705.925703 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 3786.144578 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2786.144578 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 57733640 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1845551 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 1885500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 498 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1347551 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1387500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 22406 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 3995 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2995 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 3500 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2500 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 22405 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 3995 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 3500 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.000045 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 1 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 2995 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 2500 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.000045 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 1 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 18976414 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3678.678637 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2678.678637 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 3587.016575 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2587.016575 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 18975328 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3995045 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 3895500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000057 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1086 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 2909045 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2809500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000057 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1086 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 76710552 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3687.244949 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2687.244949 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 3649.621212 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2649.621212 # average overall mshr miss latency system.cpu.dcache.demand_hits 76708968 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 5840596 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 5781000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses system.cpu.dcache.demand_misses 1584 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4256596 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4197000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 1584 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 76710552 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3687.244949 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2687.244949 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 3649.621212 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2649.621212 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 76708968 # number of overall hits -system.cpu.dcache.overall_miss_latency 5840596 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 5781000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses system.cpu.dcache.overall_misses 1584 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4256596 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4197000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 1584 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 26 # number of replacements system.cpu.dcache.sampled_refs 1585 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1216.403972 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1237.515646 # Cycle average of tags in use system.cpu.dcache.total_refs 76731373 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 23 # number of writebacks system.cpu.icache.ReadReq_accesses 193435974 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3138.680633 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2138.680633 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 3066.269971 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2066.269971 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 193423706 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 38505334 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 37617000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000063 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 12268 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 26237334 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 25349000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000063 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 12268 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 193435974 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3138.680633 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2138.680633 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 3066.269971 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2066.269971 # average overall mshr miss latency system.cpu.icache.demand_hits 193423706 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 38505334 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 37617000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000063 # miss rate for demand accesses system.cpu.icache.demand_misses 12268 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 26237334 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 25349000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000063 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 12268 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 193435974 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3138.680633 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2138.680633 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 3066.269971 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2066.269971 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 193423706 # number of overall hits -system.cpu.icache.overall_miss_latency 38505334 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 37617000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000063 # miss rate for overall accesses system.cpu.icache.overall_misses 12268 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 26237334 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 25349000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000063 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 12268 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -148,19 +148,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 10342 # number of replacements system.cpu.icache.sampled_refs 12268 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1567.271345 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1591.858190 # Cycle average of tags in use system.cpu.icache.total_refs 193423706 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 13852 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2847.598413 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1846.400619 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 2720.824463 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1719.824463 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 8685 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 14713541 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 14058500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.373015 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 5167 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 9540352 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 8886333 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.373015 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 5167 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 23 # number of Writeback accesses(hits+misses) @@ -174,29 +174,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 13852 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2847.598413 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1846.400619 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 2720.824463 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1719.824463 # average overall mshr miss latency system.cpu.l2cache.demand_hits 8685 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 14713541 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 14058500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.373015 # miss rate for demand accesses system.cpu.l2cache.demand_misses 5167 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 9540352 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 8886333 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.373015 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 5167 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 13875 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2847.598413 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1846.400619 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 2720.824463 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1719.824463 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 8708 # number of overall hits -system.cpu.l2cache.overall_miss_latency 14713541 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 14058500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.372396 # miss rate for overall accesses system.cpu.l2cache.overall_misses 5167 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 9540352 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 8886333 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.372396 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 5167 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -213,12 +213,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 5167 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3448.701925 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 3507.285738 # Cycle average of tags in use system.cpu.l2cache.total_refs 8708 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 314505003 # number of cpu cycles simulated +system.cpu.numCycles 135120940500 # number of cpu cycles simulated system.cpu.num_insts 193435973 # Number of instructions executed system.cpu.num_refs 76732959 # Number of memory references system.cpu.workload.PROG:num_syscalls 396 # Number of system calls diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr index 6e24f6d54..18e13818c 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr @@ -2,7 +2,6 @@ warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x11e394 length 0x10. warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x0 length 0x0. -0: system.remote_gdb.listener: listening for remote gdb on port 7002 warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout index d50dfc3c4..eb4e3bbfa 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout @@ -18,11 +18,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 29 2007 16:12:35 -M5 started Thu Mar 29 16:13:01 2007 +M5 compiled Apr 27 2007 14:35:32 +M5 started Fri Apr 27 16:08:41 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing tests/run.py long/70.twolf/sparc/linux/simple-timing Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second -Exiting @ tick 314505003 because target called exit() +Exiting @ tick 135120940500 because target called exit() From 69d259b6ae97b9f6803a34c794baec752977d611 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Fri, 27 Apr 2007 13:59:17 -0700 Subject: [PATCH 32/68] gcc 4.1 claims that mem_data might be used uninitialized, though I don't believe that's true. Placate it anyway. --HG-- extra : convert_revision : dcd9427af14f0e7a33510054bee4ecbe73e050be --- src/arch/sparc/isa/formats/mem/swap.isa | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/sparc/isa/formats/mem/swap.isa b/src/arch/sparc/isa/formats/mem/swap.isa index b71542a2b..f3d15670f 100644 --- a/src/arch/sparc/isa/formats/mem/swap.isa +++ b/src/arch/sparc/isa/formats/mem/swap.isa @@ -39,7 +39,7 @@ def template SwapExecute {{ Addr EA; %(fp_enable_check)s; %(op_decl)s; - uint64_t mem_data; + uint64_t mem_data = 0; %(op_rd)s; %(ea_code)s; From e77aa3d21215de75aeeb0961a2440b87a01d3dc6 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 30 Apr 2007 13:07:05 -0400 Subject: [PATCH 33/68] make ping actually end --HG-- extra : convert_revision : 6932d050a821abc7871bc73051688a986dcea364 --- configs/boot/ping-client.rcS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/boot/ping-client.rcS b/configs/boot/ping-client.rcS index 260ff42e0..a147fb245 100644 --- a/configs/boot/ping-client.rcS +++ b/configs/boot/ping-client.rcS @@ -21,5 +21,5 @@ echo "100000" > /proc/sys/net/core/netdev_max_backlog echo -n "waiting for server..." netcat -c -l -p 8000 -ping $SERVER +ping -c 5 $SERVER /sbin/m5 exit From 6e60d5c12f6cb8043657fd28638a81ce215dd92b Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 30 Apr 2007 13:08:21 -0400 Subject: [PATCH 34/68] add a udp stream benchmark and a udp loopback benchmark --HG-- extra : convert_revision : 9300c67a1258e57436eba6cbdbed8fdf93fb6e59 --- configs/boot/netperf-stream-udp-client.rcS | 45 ++++++++++++++++++++++ configs/boot/netperf-stream-udp-local.rcS | 22 +++++++++++ configs/common/Benchmarks.py | 5 ++- 3 files changed, 71 insertions(+), 1 deletion(-) create mode 100644 configs/boot/netperf-stream-udp-client.rcS create mode 100644 configs/boot/netperf-stream-udp-local.rcS diff --git a/configs/boot/netperf-stream-udp-client.rcS b/configs/boot/netperf-stream-udp-client.rcS new file mode 100644 index 000000000..91268ea50 --- /dev/null +++ b/configs/boot/netperf-stream-udp-client.rcS @@ -0,0 +1,45 @@ +#!/bin/sh +SERVER=10.0.0.1 +CLIENT=10.0.0.2 + +echo "setting up network..." +ifconfig lo 127.0.0.1 +ifconfig eth0 $CLIENT txqueuelen 1000 + +echo "0" > /proc/sys/net/ipv4/tcp_timestamps +echo "0" > /proc/sys/net/ipv4/tcp_sack +echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_rmem +echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_wmem +echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_mem +echo "262143" > /proc/sys/net/core/rmem_max +echo "262143" > /proc/sys/net/core/wmem_max +echo "262143" > /proc/sys/net/core/rmem_default +echo "262143" > /proc/sys/net/core/wmem_default +echo "262143" > /proc/sys/net/core/optmem_max +echo "100000" > /proc/sys/net/core/netdev_max_backlog + +echo -n "waiting for server..." +netcat -c -l -p 8000 + +BINARY=/benchmarks/netperf-bin/netperf +TEST="UDP_STREAM" +SHORT_ARGS="-l 2 -- -m 4096" +#LONG_ARGS="-k16384,0 -K16384,0 -- -m 65536 -M 65536 -s 262144 -S 262144" + + +SHORT="$BINARY -H $SERVER -t $TEST $SHORT_ARGS" +LONG="$BINARY -H $SERVER -t $TEST $LONG_ARGS" + +echo "starting test..." +echo "netperf warmup" +echo $SHORT +eval $SHORT + +#echo "netperf benchmark" +#echo $LONG +#/sbin/m5 ivlb 1 +#/sbin/m5 resetstats +#/sbin/m5 dumpresetstats 200000000 2000000000 +#/sbin/m5 checkpoint 200000000 2000000000 +#eval $LONG +/sbin/m5 exit diff --git a/configs/boot/netperf-stream-udp-local.rcS b/configs/boot/netperf-stream-udp-local.rcS new file mode 100644 index 000000000..ccd7654e2 --- /dev/null +++ b/configs/boot/netperf-stream-udp-local.rcS @@ -0,0 +1,22 @@ +#!/bin/sh +SERVER=127.0.0.1 +CLIENT=127.0.0.1 + +echo "setting up network..." +ifconfig lo 127.0.0.1 + +BINARY=/benchmarks/netperf-bin/netperf +TEST="UDP_STREAM" +SHORT_ARGS="-l 2 -- -m 4096" + +echo "running netserver..." +/benchmarks/netperf-bin/netserver + + +SHORT="$BINARY -H $SERVER -t $TEST $SHORT_ARGS" + +echo "starting test..." +echo $SHORT +eval $SHORT + +/sbin/m5 exit diff --git a/configs/common/Benchmarks.py b/configs/common/Benchmarks.py index eda0e80f9..9ec0f97b1 100644 --- a/configs/common/Benchmarks.py +++ b/configs/common/Benchmarks.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -61,6 +61,9 @@ Benchmarks = { 'NetperfStream': [SysConfig('netperf-stream-client.rcS'), SysConfig('netperf-server.rcS')], + 'NetperfStreamUdp': [SysConfig('netperf-stream-udp-client.rcS'), + SysConfig('netperf-server.rcS')], + 'NetperfUdpLocal': [SysConfig('netperf-stream-udp-local.rcS')], 'NetperfStreamNT': [SysConfig('netperf-stream-nt-client.rcS'), SysConfig('netperf-server.rcS')], 'NetperfMaerts': [SysConfig('netperf-maerts-client.rcS'), From ae4208f3a32bc829283a9998aa6f6fcebea7ca77 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 30 Apr 2007 13:09:13 -0400 Subject: [PATCH 35/68] add the ability for the ethernet device to check if the link is busy --HG-- extra : convert_revision : 0dc0c4c4546869261f4508ad22a6a85aecf3c334 --- src/dev/etherint.hh | 3 +++ src/dev/etherlink.hh | 1 + 2 files changed, 4 insertions(+) diff --git a/src/dev/etherint.hh b/src/dev/etherint.hh index dfc224ecc..430f45d66 100644 --- a/src/dev/etherint.hh +++ b/src/dev/etherint.hh @@ -63,6 +63,9 @@ class EtherInt : public SimObject bool sendPacket(EthPacketPtr packet) { return peer ? peer->recvPacket(packet) : true; } virtual bool recvPacket(EthPacketPtr packet) = 0; + + bool askBusy() {return peer->isBusy(); } + virtual bool isBusy() { return false; } }; #endif // __DEV_ETHERINT_HH__ diff --git a/src/dev/etherlink.hh b/src/dev/etherlink.hh index bb2854810..a16d6d799 100644 --- a/src/dev/etherlink.hh +++ b/src/dev/etherlink.hh @@ -114,6 +114,7 @@ class EtherLink : public SimObject Interface(const std::string &name, Link *txlink, Link *rxlink); bool recvPacket(EthPacketPtr packet) { return txlink->transmit(packet); } void sendDone() { peer->sendDone(); } + bool isBusy() { return txlink->busy(); } }; Link *link[2]; From 58b9047194774ae6ee3cd7c2ef52cc867c8e718e Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 30 Apr 2007 13:13:03 -0400 Subject: [PATCH 36/68] fix console printing bug --HG-- extra : convert_revision : 5481b72b22e7a2cf3367d777309bc30201f3b1fc --- src/dev/uart8250.cc | 20 +++++++++++++++----- src/dev/uart8250.hh | 1 + 2 files changed, 16 insertions(+), 5 deletions(-) diff --git a/src/dev/uart8250.cc b/src/dev/uart8250.cc index ddee33695..d178bd1af 100644 --- a/src/dev/uart8250.cc +++ b/src/dev/uart8250.cc @@ -68,6 +68,7 @@ Uart8250::IntrEvent::process() DPRINTF(Uart, "UART InterEvent, interrupting\n"); uart->platform->postConsoleInt(); uart->status |= intrBit; + uart->lastTxInt = curTick; } else DPRINTF(Uart, "UART InterEvent, not interrupting\n"); @@ -153,13 +154,13 @@ Uart8250::read(PacketPtr pkt) if (status & RX_INT) /* Rx data interrupt has a higher priority */ pkt->set(IIR_RXID); - else if (status & TX_INT) + else if (status & TX_INT) { pkt->set(IIR_TXID); - else + //Tx interrupts are cleared on IIR reads + status &= ~TX_INT; + } else pkt->set(IIR_NOPEND); - //Tx interrupts are cleared on IIR reads - status &= ~TX_INT; break; case 0x3: // Line Control Register (LCR) pkt->set(LCR); @@ -222,7 +223,16 @@ Uart8250::write(PacketPtr pkt) if (UART_IER_THRI & IER) { DPRINTF(Uart, "IER: IER_THRI set, scheduling TX intrrupt\n"); - txIntrEvent.scheduleIntr(); + if (curTick - lastTxInt > + (Tick)((Clock::Float::s / 2e9) * 450)) { + DPRINTF(Uart, "-- Interrupting Immediately... %d,%d\n", + curTick, lastTxInt); + txIntrEvent.process(); + } else { + DPRINTF(Uart, "-- Delaying interrupt... %d,%d\n", + curTick, lastTxInt); + txIntrEvent.scheduleIntr(); + } } else { diff --git a/src/dev/uart8250.hh b/src/dev/uart8250.hh index c28200592..c9c878aed 100644 --- a/src/dev/uart8250.hh +++ b/src/dev/uart8250.hh @@ -74,6 +74,7 @@ class Uart8250 : public Uart protected: uint8_t IER, DLAB, LCR, MCR; + Tick lastTxInt; class IntrEvent : public Event { From 7baf29c9d0ea2f4c6ad026d1420f25d1143a07ac Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 30 Apr 2007 13:18:44 -0400 Subject: [PATCH 37/68] fix igbe bug --HG-- extra : convert_revision : 01ffc08f5c1ec827a42f60562ae7e10176ffdb7f --- src/dev/i8254xGBe.cc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc index 3d08bca1e..6acd06132 100644 --- a/src/dev/i8254xGBe.cc +++ b/src/dev/i8254xGBe.cc @@ -710,7 +710,7 @@ IGbE::RxDescCache::pktComplete() DPRINTF(EthernetDesc, "Checking UDP checksum\n"); status |= RXDS_UDPCS; desc->csum = htole(cksum(udp)); - if (cksum(tcp) != 0) { + if (cksum(udp) != 0) { DPRINTF(EthernetDesc, "Checksum is bad!!\n"); err |= RXDE_TCPE; } @@ -927,11 +927,13 @@ IGbE::TxDescCache::pktComplete() if (TxdOp::txsm(desc)) { if (isTcp) { TcpPtr tcp(ip); + assert(tcp); tcp->sum(0); tcp->sum(cksum(tcp)); DPRINTF(EthernetDesc, "Calculated TCP checksum\n"); } else { UdpPtr udp(ip); + assert(udp); udp->sum(0); udp->sum(cksum(udp)); DPRINTF(EthernetDesc, "Calculated UDP checksum\n"); @@ -1028,7 +1030,7 @@ IGbE::TxDescCache::hasOutstandingEvents() void IGbE::restartClock() { - if (!tickEvent.scheduled() && (rxTick || txTick) && getState() == + if (!tickEvent.scheduled() && (rxTick || txTick || txFifoTick) && getState() == SimObject::Running) tickEvent.schedule((curTick/cycles(1)) * cycles(1) + cycles(1)); } From cd617b7d388e0762e5de370d676ea239c7e7413b Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 30 Apr 2007 14:10:40 -0400 Subject: [PATCH 38/68] update refs for uart device changes --HG-- extra : convert_revision : 4bea6652993cf147d9f1e88b1eb1f9796431121a --- .../tsunami-simple-atomic-dual/m5stats.txt | 152 +++++++++--------- .../linux/tsunami-simple-atomic-dual/stderr | 6 +- .../linux/tsunami-simple-atomic-dual/stdout | 11 +- .../linux/tsunami-simple-atomic/m5stats.txt | 100 ++++++------ .../alpha/linux/tsunami-simple-atomic/stderr | 2 +- .../alpha/linux/tsunami-simple-atomic/stdout | 11 +- .../tsunami-simple-timing-dual/m5stats.txt | 64 ++++---- .../linux/tsunami-simple-timing-dual/stderr | 4 +- .../linux/tsunami-simple-timing-dual/stdout | 11 +- .../linux/tsunami-simple-timing/m5stats.txt | 54 +++---- .../alpha/linux/tsunami-simple-timing/stderr | 4 +- .../alpha/linux/tsunami-simple-timing/stdout | 11 +- .../twosys-tsunami-simple-atomic/config.ini | 4 +- .../twosys-tsunami-simple-atomic/config.out | 4 +- .../twosys-tsunami-simple-atomic/m5stats.txt | 88 +++++----- .../linux/twosys-tsunami-simple-atomic/stderr | 8 +- .../linux/twosys-tsunami-simple-atomic/stdout | 12 +- 17 files changed, 276 insertions(+), 270 deletions(-) diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt index 1c69cf2f2..2a3b3163d 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt @@ -1,89 +1,89 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 242742 # Simulator instruction rate (inst/s) -host_mem_usage 197416 # Number of bytes of host memory used -host_seconds 260.02 # Real time elapsed on the host -host_tick_rate 14386097 # Simulator tick rate (ticks/s) +host_inst_rate 674184 # Simulator instruction rate (inst/s) +host_mem_usage 251408 # Number of bytes of host memory used +host_seconds 93.63 # Real time elapsed on the host +host_tick_rate 39952215 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 63117303 # Number of instructions simulated +sim_insts 63122441 # Number of instructions simulated sim_seconds 1.870326 # Number of seconds simulated -sim_ticks 3740652145 # Number of ticks simulated +sim_ticks 3740651174 # Number of ticks simulated system.cpu0.dtb.accesses 698037 # DTB accesses system.cpu0.dtb.acv 251 # DTB access violations -system.cpu0.dtb.hits 15070122 # DTB hits +system.cpu0.dtb.hits 15071957 # DTB hits system.cpu0.dtb.misses 7805 # DTB misses system.cpu0.dtb.read_accesses 508987 # DTB read accesses system.cpu0.dtb.read_acv 152 # DTB read access violations -system.cpu0.dtb.read_hits 9141132 # DTB read hits +system.cpu0.dtb.read_hits 9142249 # DTB read hits system.cpu0.dtb.read_misses 7079 # DTB read misses system.cpu0.dtb.write_accesses 189050 # DTB write accesses system.cpu0.dtb.write_acv 99 # DTB write access violations -system.cpu0.dtb.write_hits 5928990 # DTB write hits +system.cpu0.dtb.write_hits 5929708 # DTB write hits system.cpu0.dtb.write_misses 726 # DTB write misses -system.cpu0.idle_fraction 0.984722 # Percentage of idle cycles -system.cpu0.itb.accesses 3856317 # ITB accesses +system.cpu0.idle_fraction 0.984720 # Percentage of idle cycles +system.cpu0.itb.accesses 3857497 # ITB accesses system.cpu0.itb.acv 127 # ITB acv -system.cpu0.itb.hits 3852832 # ITB hits +system.cpu0.itb.hits 3854012 # ITB hits system.cpu0.itb.misses 3485 # ITB misses -system.cpu0.kern.callpal 183079 # number of callpals executed +system.cpu0.kern.callpal 183119 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal_wripir 111 0.06% 0.06% # number of callpals executed system.cpu0.kern.callpal_wrmces 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal_wrfen 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal_swpctx 3761 2.05% 2.12% # number of callpals executed +system.cpu0.kern.callpal_swpctx 3759 2.05% 2.12% # number of callpals executed system.cpu0.kern.callpal_tbi 38 0.02% 2.14% # number of callpals executed system.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal_swpipl 167848 91.68% 93.82% # number of callpals executed +system.cpu0.kern.callpal_swpipl 167881 91.68% 93.82% # number of callpals executed system.cpu0.kern.callpal_rdps 6134 3.35% 97.17% # number of callpals executed system.cpu0.kern.callpal_wrkgp 1 0.00% 97.17% # number of callpals executed system.cpu0.kern.callpal_wrusp 3 0.00% 97.17% # number of callpals executed -system.cpu0.kern.callpal_rdusp 7 0.00% 97.18% # number of callpals executed +system.cpu0.kern.callpal_rdusp 7 0.00% 97.17% # number of callpals executed system.cpu0.kern.callpal_whami 2 0.00% 97.18% # number of callpals executed -system.cpu0.kern.callpal_rti 4664 2.55% 99.73% # number of callpals executed +system.cpu0.kern.callpal_rti 4673 2.55% 99.73% # number of callpals executed system.cpu0.kern.callpal_callsys 357 0.19% 99.92% # number of callpals executed system.cpu0.kern.callpal_imb 142 0.08% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 196899 # number of hwrei instructions executed +system.cpu0.kern.inst.hwrei 196948 # number of hwrei instructions executed system.cpu0.kern.inst.quiesce 6163 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 174663 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 70908 40.60% 40.60% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_21 234 0.13% 40.73% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_22 1908 1.09% 41.82% # number of times we switched to this ipl +system.cpu0.kern.ipl_count 174714 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 70932 40.60% 40.60% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_21 243 0.14% 40.74% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_22 1908 1.09% 41.83% # number of times we switched to this ipl system.cpu0.kern.ipl_count_30 8 0.00% 41.83% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 101605 58.17% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 141224 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 69541 49.24% 49.24% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_21 234 0.17% 49.41% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count_31 101623 58.17% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 141281 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 69565 49.24% 49.24% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_30 8 0.01% 50.76% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 69533 49.24% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 3740651730 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 3706247513 99.08% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 38699 0.00% 99.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_good_30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_31 69557 49.23% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 3740650759 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 3706243742 99.08% 99.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 40220 0.00% 99.08% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks_22 164088 0.00% 99.09% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks_30 1899 0.00% 99.09% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 34199531 0.91% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used 0.808551 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_0 0.980721 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_ticks_31 34200810 0.91% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used 0.808642 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_0 0.980728 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.684346 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_31 0.684461 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.mode_good_kernel 1155 system.cpu0.kern.mode_good_user 1156 system.cpu0.kern.mode_good_idle 0 -system.cpu0.kern.mode_switch_kernel 7081 # number of protection mode switches +system.cpu0.kern.mode_switch_kernel 7088 # number of protection mode switches system.cpu0.kern.mode_switch_user 1156 # number of protection mode switches system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good 0.280563 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.163113 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good 0.280325 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.162951 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 3738737730 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_kernel 3738736759 99.95% 99.95% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_user 1913998 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3762 # number of times the context was actually changed +system.cpu0.kern.swap_context 3760 # number of times the context was actually changed system.cpu0.kern.syscall 226 # number of syscalls executed system.cpu0.kern.syscall_2 6 2.65% 2.65% # number of syscalls executed system.cpu0.kern.syscall_3 19 8.41% 11.06% # number of syscalls executed @@ -115,36 +115,36 @@ system.cpu0.kern.syscall_98 2 0.88% 97.35% # nu system.cpu0.kern.syscall_132 2 0.88% 98.23% # number of syscalls executed system.cpu0.kern.syscall_144 2 0.88% 99.12% # number of syscalls executed system.cpu0.kern.syscall_147 2 0.88% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.015278 # Percentage of non-idle cycles -system.cpu0.numCycles 57148679 # number of cpu cycles simulated -system.cpu0.num_insts 57145067 # Number of instructions executed -system.cpu0.num_refs 15309549 # Number of memory references +system.cpu0.not_idle_fraction 0.015280 # Percentage of non-idle cycles +system.cpu0.numCycles 57155598 # number of cpu cycles simulated +system.cpu0.num_insts 57151986 # Number of instructions executed +system.cpu0.num_refs 15311384 # Number of memory references system.cpu1.dtb.accesses 323622 # DTB accesses system.cpu1.dtb.acv 116 # DTB access violations -system.cpu1.dtb.hits 1925621 # DTB hits +system.cpu1.dtb.hits 1925043 # DTB hits system.cpu1.dtb.misses 3692 # DTB misses system.cpu1.dtb.read_accesses 220342 # DTB read accesses system.cpu1.dtb.read_acv 58 # DTB read access violations -system.cpu1.dtb.read_hits 1169530 # DTB read hits +system.cpu1.dtb.read_hits 1169160 # DTB read hits system.cpu1.dtb.read_misses 3277 # DTB read misses system.cpu1.dtb.write_accesses 103280 # DTB write accesses system.cpu1.dtb.write_acv 58 # DTB write access violations -system.cpu1.dtb.write_hits 756091 # DTB write hits +system.cpu1.dtb.write_hits 755883 # DTB write hits system.cpu1.dtb.write_misses 415 # DTB write misses system.cpu1.idle_fraction 0.998403 # Percentage of idle cycles -system.cpu1.itb.accesses 1471328 # ITB accesses +system.cpu1.itb.accesses 1471216 # ITB accesses system.cpu1.itb.acv 57 # ITB acv -system.cpu1.itb.hits 1469789 # ITB hits +system.cpu1.itb.hits 1469677 # ITB hits system.cpu1.itb.misses 1539 # ITB misses -system.cpu1.kern.callpal 32276 # number of callpals executed +system.cpu1.kern.callpal 32267 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu1.kern.callpal_wripir 8 0.02% 0.03% # number of callpals executed system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal_swpctx 473 1.47% 1.50% # number of callpals executed -system.cpu1.kern.callpal_tbi 15 0.05% 1.55% # number of callpals executed +system.cpu1.kern.callpal_swpctx 472 1.46% 1.50% # number of callpals executed +system.cpu1.kern.callpal_tbi 15 0.05% 1.54% # number of callpals executed system.cpu1.kern.callpal_wrent 7 0.02% 1.57% # number of callpals executed -system.cpu1.kern.callpal_swpipl 26366 81.69% 83.26% # number of callpals executed +system.cpu1.kern.callpal_swpipl 26358 81.69% 83.25% # number of callpals executed system.cpu1.kern.callpal_rdps 2589 8.02% 91.28% # number of callpals executed system.cpu1.kern.callpal_wrkgp 1 0.00% 91.28% # number of callpals executed system.cpu1.kern.callpal_wrusp 4 0.01% 91.29% # number of callpals executed @@ -155,42 +155,42 @@ system.cpu1.kern.callpal_callsys 158 0.49% 99.88% # nu system.cpu1.kern.callpal_imb 38 0.12% 100.00% # number of callpals executed system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 39700 # number of hwrei instructions executed +system.cpu1.kern.inst.hwrei 39691 # number of hwrei instructions executed system.cpu1.kern.inst.quiesce 2208 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 30993 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 10390 33.52% 33.52% # number of times we switched to this ipl +system.cpu1.kern.ipl_count 30985 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 10388 33.53% 33.53% # number of times we switched to this ipl system.cpu1.kern.ipl_count_22 1907 6.15% 39.68% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_30 111 0.36% 40.03% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 18585 59.97% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 22667 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 10380 45.79% 45.79% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_count_30 111 0.36% 40.04% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_31 18579 59.96% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 22663 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 10378 45.79% 45.79% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good_22 1907 8.41% 54.21% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good_30 111 0.49% 54.70% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 10269 45.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 3740237217 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 3718223353 99.41% 99.41% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_good_31 10267 45.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 3740237191 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 3718224753 99.41% 99.41% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks_22 164002 0.00% 99.42% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks_30 28353 0.00% 99.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 21821509 0.58% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used 0.731359 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_0 0.999038 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_ticks_31 21820083 0.58% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used 0.731418 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_0 0.999037 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.552542 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_31 0.552613 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.mode_good_kernel 613 system.cpu1.kern.mode_good_user 580 system.cpu1.kern.mode_good_idle 33 -system.cpu1.kern.mode_switch_kernel 1035 # number of protection mode switches +system.cpu1.kern.mode_switch_kernel 1034 # number of protection mode switches system.cpu1.kern.mode_switch_user 580 # number of protection mode switches system.cpu1.kern.mode_switch_idle 2048 # number of protection mode switches -system.cpu1.kern.mode_switch_good 0.334698 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.592271 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good 0.334790 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.592843 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_idle 0.016113 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 2788269 0.07% 0.07% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_kernel 2786521 0.07% 0.07% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks_user 1016578 0.03% 0.10% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 3735959544 99.90% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 474 # number of times the context was actually changed +system.cpu1.kern.mode_ticks_idle 3735960321 99.90% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 473 # number of times the context was actually changed system.cpu1.kern.syscall 100 # number of syscalls executed system.cpu1.kern.syscall_2 2 2.00% 2.00% # number of syscalls executed system.cpu1.kern.syscall_3 11 11.00% 13.00% # number of syscalls executed @@ -210,9 +210,9 @@ system.cpu1.kern.syscall_74 8 8.00% 97.00% # nu system.cpu1.kern.syscall_90 1 1.00% 98.00% # number of syscalls executed system.cpu1.kern.syscall_132 2 2.00% 100.00% # number of syscalls executed system.cpu1.not_idle_fraction 0.001597 # Percentage of non-idle cycles -system.cpu1.numCycles 5973832 # number of cpu cycles simulated -system.cpu1.num_insts 5972236 # Number of instructions executed -system.cpu1.num_refs 1937415 # Number of memory references +system.cpu1.numCycles 5972051 # number of cpu cycles simulated +system.cpu1.num_insts 5970455 # Number of instructions executed +system.cpu1.num_refs 1936828 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr index 2dc23577d..111ccf4f1 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr @@ -1,7 +1,7 @@ Warning: rounding error > tolerance 0.002000 rounded to 0 -Listening for system connection on port 3457 -0: system.remote_gdb.listener: listening for remote gdb on port 7001 -0: system.remote_gdb.listener: listening for remote gdb on port 7002 +Listening for system connection on port 3456 +0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 +0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001 warn: Entering event queue @ 0. Starting simulation... warn: 195723: Trying to launch CPU number 1! diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout index fe4bfd9cb..9ec0f1c3f 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout @@ -5,9 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2007 03:02:42 -M5 started Sun Apr 22 03:06:34 2007 -M5 executing on zed -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual +M5 compiled Apr 30 2007 13:38:38 +M5 started Mon Apr 30 13:53:05 2007 +M5 executing on zeep +command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 2000000000 ticks per second -Exiting @ tick 3740652145 because m5_exit instruction encountered + 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 +Exiting @ tick 3740651174 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt index 2514bef95..de848de68 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt @@ -1,84 +1,84 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 424352 # Simulator instruction rate (inst/s) -host_mem_usage 197360 # Number of bytes of host memory used -host_seconds 141.39 # Real time elapsed on the host -host_tick_rate 25861787 # Simulator tick rate (ticks/s) +host_inst_rate 1069072 # Simulator instruction rate (inst/s) +host_mem_usage 251484 # Number of bytes of host memory used +host_seconds 56.13 # Real time elapsed on the host +host_tick_rate 65146530 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 60000671 # Number of instructions simulated -sim_seconds 1.828353 # Number of seconds simulated -sim_ticks 3656706837 # Number of ticks simulated +sim_insts 60007301 # Number of instructions simulated +sim_seconds 1.828354 # Number of seconds simulated +sim_ticks 3656708271 # Number of ticks simulated system.cpu.dtb.accesses 1020787 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 16052251 # DTB hits +system.cpu.dtb.hits 16053817 # DTB hits system.cpu.dtb.misses 11471 # DTB misses system.cpu.dtb.read_accesses 728856 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 9702902 # DTB read hits +system.cpu.dtb.read_hits 9703849 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.write_accesses 291931 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_hits 6349349 # DTB write hits +system.cpu.dtb.write_hits 6349968 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses -system.cpu.idle_fraction 0.983590 # Percentage of idle cycles -system.cpu.itb.accesses 4978040 # ITB accesses +system.cpu.idle_fraction 0.983588 # Percentage of idle cycles +system.cpu.itb.accesses 4979206 # ITB accesses system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 4973034 # ITB hits +system.cpu.itb.hits 4974200 # ITB hits system.cpu.itb.misses 5006 # ITB misses -system.cpu.kern.callpal 192107 # number of callpals executed +system.cpu.kern.callpal 192138 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_swpctx 4180 2.18% 2.18% # number of callpals executed -system.cpu.kern.callpal_tbi 54 0.03% 2.21% # number of callpals executed +system.cpu.kern.callpal_swpctx 4177 2.17% 2.18% # number of callpals executed +system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal_wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal_swpipl 175185 91.19% 93.40% # number of callpals executed -system.cpu.kern.callpal_rdps 6770 3.52% 96.93% # number of callpals executed -system.cpu.kern.callpal_wrkgp 1 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal_wrusp 7 0.00% 96.93% # number of callpals executed +system.cpu.kern.callpal_swpipl 175209 91.19% 93.40% # number of callpals executed +system.cpu.kern.callpal_rdps 6770 3.52% 96.92% # number of callpals executed +system.cpu.kern.callpal_wrkgp 1 0.00% 96.92% # number of callpals executed +system.cpu.kern.callpal_wrusp 7 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal_rdusp 9 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal_whami 2 0.00% 96.94% # number of callpals executed -system.cpu.kern.callpal_rti 5192 2.70% 99.64% # number of callpals executed +system.cpu.kern.callpal_whami 2 0.00% 96.93% # number of callpals executed +system.cpu.kern.callpal_rti 5202 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 211235 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6241 # number of quiesce instructions executed -system.cpu.kern.ipl_count 182476 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 74792 40.99% 40.99% # number of times we switched to this ipl -system.cpu.kern.ipl_count_21 233 0.13% 41.11% # number of times we switched to this ipl +system.cpu.kern.inst.hwrei 211276 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6240 # number of quiesce instructions executed +system.cpu.kern.ipl_count 182520 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 74815 40.99% 40.99% # number of times we switched to this ipl +system.cpu.kern.ipl_count_21 243 0.13% 41.12% # number of times we switched to this ipl system.cpu.kern.ipl_count_22 1865 1.02% 42.14% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 105586 57.86% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 148948 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 73425 49.30% 49.30% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_21 233 0.16% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 1865 1.25% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 73425 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 3656706422 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 3622173235 99.06% 99.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 38530 0.00% 99.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_count_31 105597 57.86% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 149004 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 73448 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_22 1865 1.25% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_31 73448 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 3656707856 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 3622172407 99.06% 99.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 40220 0.00% 99.06% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks_22 160390 0.00% 99.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 34334267 0.94% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used 0.816261 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_0 0.981723 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_ticks_31 34334839 0.94% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used 0.816371 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used_0 0.981728 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.695405 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used_31 0.695550 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.mode_good_kernel 1907 system.cpu.kern.mode_good_user 1736 system.cpu.kern.mode_good_idle 171 -system.cpu.kern.mode_switch_kernel 5941 # number of protection mode switches +system.cpu.kern.mode_switch_kernel 5948 # number of protection mode switches system.cpu.kern.mode_switch_user 1736 # number of protection mode switches system.cpu.kern.mode_switch_idle 2097 # number of protection mode switches -system.cpu.kern.mode_switch_good 0.390219 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.320990 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good 0.389940 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.320612 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 53661287 1.47% 1.47% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_kernel 53668047 1.47% 1.47% # number of ticks spent at the given mode system.cpu.kern.mode_ticks_user 2930128 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 3600115005 98.45% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4181 # number of times the context was actually changed +system.cpu.kern.mode_ticks_idle 3600109679 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.cpu.kern.syscall 326 # number of syscalls executed system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed @@ -110,10 +110,10 @@ system.cpu.kern.syscall_98 2 0.61% 97.55% # nu system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed -system.cpu.not_idle_fraction 0.016410 # Percentage of non-idle cycles -system.cpu.numCycles 60005861 # number of cpu cycles simulated -system.cpu.num_insts 60000671 # Number of instructions executed -system.cpu.num_refs 16300569 # Number of memory references +system.cpu.not_idle_fraction 0.016412 # Percentage of non-idle cycles +system.cpu.numCycles 60012491 # number of cpu cycles simulated +system.cpu.num_insts 60007301 # Number of instructions executed +system.cpu.num_refs 16302128 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr index bffa97023..969291745 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr @@ -1,5 +1,5 @@ Warning: rounding error > tolerance 0.002000 rounded to 0 Listening for system connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout index 802d081ea..c3a1cb464 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout @@ -5,9 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2007 03:02:42 -M5 started Sun Apr 22 03:06:33 2007 -M5 executing on zed -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic +M5 compiled Apr 30 2007 13:38:38 +M5 started Mon Apr 30 13:52:08 2007 +M5 executing on zeep +command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 2000000000 ticks per second -Exiting @ tick 3656706837 because m5_exit instruction encountered + 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 +Exiting @ tick 3656708271 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt index b2e9ad6be..24b2c4738 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 93328 # Simulator instruction rate (inst/s) -host_mem_usage 194108 # Number of bytes of host memory used -host_seconds 698.07 # Real time elapsed on the host -host_tick_rate 5697629 # Simulator tick rate (ticks/s) +host_inst_rate 249273 # Simulator instruction rate (inst/s) +host_mem_usage 249952 # Number of bytes of host memory used +host_seconds 261.36 # Real time elapsed on the host +host_tick_rate 15217956 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 65149483 # Number of instructions simulated +sim_insts 65149861 # Number of instructions simulated sim_seconds 1.988682 # Number of seconds simulated -sim_ticks 3977364188 # Number of ticks simulated +sim_ticks 3977364868 # Number of ticks simulated system.cpu0.dtb.accesses 676531 # DTB accesses system.cpu0.dtb.acv 306 # DTB access violations -system.cpu0.dtb.hits 12726689 # DTB hits +system.cpu0.dtb.hits 12726821 # DTB hits system.cpu0.dtb.misses 8261 # DTB misses system.cpu0.dtb.read_accesses 494241 # DTB read accesses system.cpu0.dtb.read_acv 184 # DTB read access violations -system.cpu0.dtb.read_hits 7906502 # DTB read hits +system.cpu0.dtb.read_hits 7906586 # DTB read hits system.cpu0.dtb.read_misses 7534 # DTB read misses system.cpu0.dtb.write_accesses 182290 # DTB write accesses system.cpu0.dtb.write_acv 122 # DTB write access violations -system.cpu0.dtb.write_hits 4820187 # DTB write hits +system.cpu0.dtb.write_hits 4820235 # DTB write hits system.cpu0.dtb.write_misses 727 # DTB write misses -system.cpu0.idle_fraction 0.930926 # Percentage of idle cycles -system.cpu0.itb.accesses 3412074 # ITB accesses +system.cpu0.idle_fraction 0.930925 # Percentage of idle cycles +system.cpu0.itb.accesses 3412128 # ITB accesses system.cpu0.itb.acv 161 # ITB acv -system.cpu0.itb.hits 3408241 # ITB hits +system.cpu0.itb.hits 3408295 # ITB hits system.cpu0.itb.misses 3833 # ITB misses -system.cpu0.kern.callpal 142537 # number of callpals executed +system.cpu0.kern.callpal 142543 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal_wripir 572 0.40% 0.40% # number of callpals executed system.cpu0.kern.callpal_wrmces 1 0.00% 0.40% # number of callpals executed @@ -34,7 +34,7 @@ system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.40% # nu system.cpu0.kern.callpal_swpctx 2878 2.02% 2.42% # number of callpals executed system.cpu0.kern.callpal_tbi 47 0.03% 2.46% # number of callpals executed system.cpu0.kern.callpal_wrent 7 0.00% 2.46% # number of callpals executed -system.cpu0.kern.callpal_swpipl 127687 89.58% 92.04% # number of callpals executed +system.cpu0.kern.callpal_swpipl 127693 89.58% 92.04% # number of callpals executed system.cpu0.kern.callpal_rdps 6611 4.64% 96.68% # number of callpals executed system.cpu0.kern.callpal_wrkgp 1 0.00% 96.68% # number of callpals executed system.cpu0.kern.callpal_wrusp 3 0.00% 96.68% # number of callpals executed @@ -44,14 +44,14 @@ system.cpu0.kern.callpal_rti 4215 2.96% 99.65% # nu system.cpu0.kern.callpal_callsys 355 0.25% 99.90% # number of callpals executed system.cpu0.kern.callpal_imb 147 0.10% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 157722 # number of hwrei instructions executed +system.cpu0.kern.inst.hwrei 157728 # number of hwrei instructions executed system.cpu0.kern.inst.quiesce 6621 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 134525 # number of times we switched to this ipl +system.cpu0.kern.ipl_count 134531 # number of times we switched to this ipl system.cpu0.kern.ipl_count_0 53714 39.93% 39.93% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_21 131 0.10% 40.03% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_21 131 0.10% 40.02% # number of times we switched to this ipl system.cpu0.kern.ipl_count_22 2009 1.49% 41.52% # number of times we switched to this ipl system.cpu0.kern.ipl_count_30 482 0.36% 41.88% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 78189 58.12% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 78195 58.12% 100.00% # number of times we switched to this ipl system.cpu0.kern.ipl_good 108736 # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_0 53298 49.02% 49.02% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_21 131 0.12% 49.14% # number of times we switched to this ipl from a different ipl @@ -59,17 +59,17 @@ system.cpu0.kern.ipl_good_22 2009 1.85% 50.98% # nu system.cpu0.kern.ipl_good_30 482 0.44% 51.43% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_31 52816 48.57% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_ticks 3976579702 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 3843539628 96.65% 96.65% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 3843537444 96.65% 96.65% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks_21 123584 0.00% 96.66% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks_22 1875640 0.05% 96.70% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks_30 1201752 0.03% 96.73% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 129839098 3.27% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used 0.808296 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_ticks_31 129841282 3.27% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used 0.808260 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_0 0.992255 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.675491 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_31 0.675440 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.mode_good_kernel 1191 system.cpu0.kern.mode_good_user 1191 system.cpu0.kern.mode_good_idle 0 @@ -80,8 +80,8 @@ system.cpu0.kern.mode_switch_good 0.301863 # fr system.cpu0.kern.mode_switch_good_kernel 0.177761 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 3965298428 99.76% 99.76% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 9599262 0.24% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_kernel 3965299112 99.76% 99.76% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 9599258 0.24% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 2879 # number of times the context was actually changed system.cpu0.kern.syscall 216 # number of syscalls executed @@ -115,10 +115,10 @@ system.cpu0.kern.syscall_98 2 0.93% 97.69% # nu system.cpu0.kern.syscall_132 2 0.93% 98.61% # number of syscalls executed system.cpu0.kern.syscall_144 1 0.46% 99.07% # number of syscalls executed system.cpu0.kern.syscall_147 2 0.93% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.069074 # Percentage of non-idle cycles +system.cpu0.not_idle_fraction 0.069075 # Percentage of non-idle cycles system.cpu0.numCycles 3976579942 # number of cpu cycles simulated -system.cpu0.num_insts 50251013 # Number of instructions executed -system.cpu0.num_refs 12958414 # Number of memory references +system.cpu0.num_insts 50251391 # Number of instructions executed +system.cpu0.num_refs 12958546 # Number of memory references system.cpu1.dtb.accesses 346252 # DTB accesses system.cpu1.dtb.acv 67 # DTB access violations system.cpu1.dtb.hits 4740978 # DTB hits @@ -167,11 +167,11 @@ system.cpu1.kern.ipl_good_0 29502 48.36% 48.36% # nu system.cpu1.kern.ipl_good_22 2001 3.28% 51.64% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good_30 572 0.94% 52.58% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good_31 28930 47.42% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 3977362404 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 3855394306 96.93% 96.93% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks 3977363084 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 3855395406 96.93% 96.93% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks_22 1873360 0.05% 96.98% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks_30 1461344 0.04% 97.02% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 118633394 2.98% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 118632974 2.98% 100.00% # number of cycles we spent at this ipl system.cpu1.kern.ipl_used 0.779686 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_0 0.968454 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl @@ -189,7 +189,7 @@ system.cpu1.kern.mode_switch_good_user 1 # fr system.cpu1.kern.mode_switch_good_idle 0.163427 # fraction of useful protection mode switches system.cpu1.kern.mode_ticks_kernel 64042452 1.61% 1.61% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks_user 5753306 0.14% 1.75% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 3907566638 98.25% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 3907567318 98.25% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 2290 # number of times the context was actually changed system.cpu1.kern.syscall 110 # number of syscalls executed system.cpu1.kern.syscall_2 1 0.91% 0.91% # number of syscalls executed @@ -214,7 +214,7 @@ system.cpu1.kern.syscall_92 2 1.82% 97.27% # nu system.cpu1.kern.syscall_132 2 1.82% 99.09% # number of syscalls executed system.cpu1.kern.syscall_144 1 0.91% 100.00% # number of syscalls executed system.cpu1.not_idle_fraction 0.025425 # Percentage of non-idle cycles -system.cpu1.numCycles 3977364188 # number of cpu cycles simulated +system.cpu1.numCycles 3977364868 # number of cpu cycles simulated system.cpu1.num_insts 14898470 # Number of instructions executed system.cpu1.num_refs 4770918 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr index 8aa8d4104..9d86a655e 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr @@ -1,7 +1,7 @@ Warning: rounding error > tolerance 0.002000 rounded to 0 Listening for system connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb on port 7000 -0: system.remote_gdb.listener: listening for remote gdb on port 7001 +0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 +0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001 warn: Entering event queue @ 0. Starting simulation... warn: 1082476: Trying to launch CPU number 1! diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout index 933603fb1..ebf8b13c8 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout @@ -5,9 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2007 03:02:42 -M5 started Sun Apr 22 03:17:05 2007 -M5 executing on zed -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual +M5 compiled Apr 30 2007 13:38:38 +M5 started Mon Apr 30 13:57:20 2007 +M5 executing on zeep +command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 2000000000 ticks per second -Exiting @ tick 3977364188 because m5_exit instruction encountered + 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 +Exiting @ tick 3977364868 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt index c26624f69..7947c3d76 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 133073 # Simulator instruction rate (inst/s) -host_mem_usage 193848 # Number of bytes of host memory used -host_seconds 451.52 # Real time elapsed on the host -host_tick_rate 8600063 # Simulator tick rate (ticks/s) +host_inst_rate 374146 # Simulator instruction rate (inst/s) +host_mem_usage 249416 # Number of bytes of host memory used +host_seconds 160.59 # Real time elapsed on the host +host_tick_rate 24179677 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 60085145 # Number of instructions simulated +sim_insts 60085523 # Number of instructions simulated sim_seconds 1.941556 # Number of seconds simulated -sim_ticks 3883111644 # Number of ticks simulated +sim_ticks 3883112324 # Number of ticks simulated system.cpu.dtb.accesses 1020793 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 16070587 # DTB hits +system.cpu.dtb.hits 16070719 # DTB hits system.cpu.dtb.misses 11472 # DTB misses system.cpu.dtb.read_accesses 728862 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 9714704 # DTB read hits +system.cpu.dtb.read_hits 9714788 # DTB read hits system.cpu.dtb.read_misses 10330 # DTB read misses system.cpu.dtb.write_accesses 291931 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_hits 6355883 # DTB write hits +system.cpu.dtb.write_hits 6355931 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.idle_fraction 0.921464 # Percentage of idle cycles -system.cpu.itb.accesses 4985774 # ITB accesses +system.cpu.itb.accesses 4985828 # ITB accesses system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 4980764 # ITB hits +system.cpu.itb.hits 4980818 # ITB hits system.cpu.itb.misses 5010 # ITB misses -system.cpu.kern.callpal 193469 # number of callpals executed +system.cpu.kern.callpal 193475 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed @@ -33,7 +33,7 @@ system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal_swpctx 4148 2.14% 2.15% # number of callpals executed system.cpu.kern.callpal_tbi 54 0.03% 2.17% # number of callpals executed system.cpu.kern.callpal_wrent 7 0.00% 2.18% # number of callpals executed -system.cpu.kern.callpal_swpipl 176495 91.23% 93.40% # number of callpals executed +system.cpu.kern.callpal_swpipl 176501 91.23% 93.40% # number of callpals executed system.cpu.kern.callpal_rdps 6860 3.55% 96.95% # number of callpals executed system.cpu.kern.callpal_wrkgp 1 0.00% 96.95% # number of callpals executed system.cpu.kern.callpal_wrusp 7 0.00% 96.95% # number of callpals executed @@ -43,28 +43,28 @@ system.cpu.kern.callpal_rti 5186 2.68% 99.64% # nu system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 212596 # number of hwrei instructions executed +system.cpu.kern.inst.hwrei 212602 # number of hwrei instructions executed system.cpu.kern.inst.quiesce 6154 # number of quiesce instructions executed -system.cpu.kern.ipl_count 183774 # number of times we switched to this ipl +system.cpu.kern.ipl_count 183780 # number of times we switched to this ipl system.cpu.kern.ipl_count_0 75067 40.85% 40.85% # number of times we switched to this ipl system.cpu.kern.ipl_count_21 131 0.07% 40.92% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 1961 1.07% 41.99% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 106615 58.01% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count_22 1961 1.07% 41.98% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 106621 58.02% 100.00% # number of times we switched to this ipl system.cpu.kern.ipl_good 149492 # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_0 73700 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_21 131 0.09% 49.39% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_22 1961 1.31% 50.70% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_31 73700 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 3883109860 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 3755985580 96.73% 96.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks 3883110540 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 3755984220 96.73% 96.73% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks_21 112456 0.00% 96.73% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks_22 918754 0.02% 96.75% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 126093070 3.25% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used 0.813456 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_ticks_31 126095110 3.25% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used 0.813429 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_0 0.981790 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.691272 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used_31 0.691233 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.mode_good_kernel 1897 system.cpu.kern.mode_good_user 1742 system.cpu.kern.mode_good_idle 155 @@ -75,9 +75,9 @@ system.cpu.kern.mode_switch_good 0.389448 # fr system.cpu.kern.mode_switch_good_kernel 0.319629 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_idle 0.075061 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 112874078 2.91% 2.91% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_kernel 112876118 2.91% 2.91% # number of ticks spent at the given mode system.cpu.kern.mode_ticks_user 15210360 0.39% 3.30% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 3755025414 96.70% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 3755024054 96.70% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4149 # number of times the context was actually changed system.cpu.kern.syscall 326 # number of syscalls executed system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed @@ -111,9 +111,9 @@ system.cpu.kern.syscall_132 4 1.23% 98.77% # nu system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed system.cpu.not_idle_fraction 0.078536 # Percentage of non-idle cycles -system.cpu.numCycles 3883111644 # number of cpu cycles simulated -system.cpu.num_insts 60085145 # Number of instructions executed -system.cpu.num_refs 16318523 # Number of memory references +system.cpu.numCycles 3883112324 # number of cpu cycles simulated +system.cpu.num_insts 60085523 # Number of instructions executed +system.cpu.num_refs 16318655 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr index 738a31460..969291745 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr @@ -1,5 +1,5 @@ Warning: rounding error > tolerance 0.002000 rounded to 0 -Listening for system connection on port 3457 -0: system.remote_gdb.listener: listening for remote gdb on port 7002 +Listening for system connection on port 3456 +0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout index 2f1756e4d..427d90ea3 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout @@ -5,9 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2007 03:02:42 -M5 started Sun Apr 22 03:17:05 2007 -M5 executing on zed -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing +M5 compiled Apr 30 2007 13:38:38 +M5 started Mon Apr 30 13:54:39 2007 +M5 executing on zeep +command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 2000000000 ticks per second -Exiting @ tick 3883111644 because m5_exit instruction encountered + 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 +Exiting @ tick 3883112324 because m5_exit instruction encountered diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini index c10da1360..a14d4767e 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini @@ -14,7 +14,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=drivesys.physmem -readfile=/z/hsul/work/m5/newmem/configs/boot/netperf-server.rcS +readfile=/z/saidi/work/m5.newmem/configs/boot/netperf-server.rcS symbolfile= system_rev=1024 system_type=34 @@ -693,7 +693,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=testsys.physmem -readfile=/z/hsul/work/m5/newmem/configs/boot/netperf-stream-client.rcS +readfile=/z/saidi/work/m5.newmem/configs/boot/netperf-stream-client.rcS symbolfile= system_rev=1024 system_type=34 diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out index 4c39b0d8d..f9fd380da 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out @@ -18,7 +18,7 @@ kernel=/dist/m5/system/binaries/vmlinux console=/dist/m5/system/binaries/console pal=/dist/m5/system/binaries/ts_osfpal boot_osflags=root=/dev/hda1 console=ttyS0 -readfile=/z/hsul/work/m5/newmem/configs/boot/netperf-stream-client.rcS +readfile=/z/saidi/work/m5.newmem/configs/boot/netperf-stream-client.rcS symbolfile= init_param=0 system_type=34 @@ -632,7 +632,7 @@ kernel=/dist/m5/system/binaries/vmlinux console=/dist/m5/system/binaries/console pal=/dist/m5/system/binaries/ts_osfpal boot_osflags=root=/dev/hda1 console=ttyS0 -readfile=/z/hsul/work/m5/newmem/configs/boot/netperf-server.rcS +readfile=/z/saidi/work/m5.newmem/configs/boot/netperf-server.rcS symbolfile= init_param=0 system_type=34 diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt index 87f656822..b190ca80a 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt @@ -140,60 +140,60 @@ drivesys.tsunami.ethernet.txPPS 25 # Pa drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -host_inst_rate 17087768 # Simulator instruction rate (inst/s) -host_mem_usage 406052 # Number of bytes of host memory used -host_seconds 16.00 # Real time elapsed on the host -host_tick_rate 12499419683 # Simulator tick rate (ticks/s) +host_inst_rate 50427764 # Simulator instruction rate (inst/s) +host_mem_usage 465972 # Number of bytes of host memory used +host_seconds 5.44 # Real time elapsed on the host +host_tick_rate 36752487576 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 273411112 # Number of instructions simulated +sim_insts 274409387 # Number of instructions simulated sim_seconds 0.200001 # Number of seconds simulated sim_ticks 200000789468 # Number of ticks simulated testsys.cpu.dtb.accesses 335402 # DTB accesses testsys.cpu.dtb.acv 161 # DTB access violations -testsys.cpu.dtb.hits 1163686 # DTB hits +testsys.cpu.dtb.hits 1163325 # DTB hits testsys.cpu.dtb.misses 3815 # DTB misses testsys.cpu.dtb.read_accesses 225414 # DTB read accesses testsys.cpu.dtb.read_acv 80 # DTB read access violations -testsys.cpu.dtb.read_hits 658686 # DTB read hits +testsys.cpu.dtb.read_hits 658458 # DTB read hits testsys.cpu.dtb.read_misses 3287 # DTB read misses testsys.cpu.dtb.write_accesses 109988 # DTB write accesses testsys.cpu.dtb.write_acv 81 # DTB write access violations -testsys.cpu.dtb.write_hits 505000 # DTB write hits +testsys.cpu.dtb.write_hits 504867 # DTB write hits testsys.cpu.dtb.write_misses 528 # DTB write misses testsys.cpu.idle_fraction 0.999999 # Percentage of idle cycles -testsys.cpu.itb.accesses 1249822 # ITB accesses +testsys.cpu.itb.accesses 1249840 # ITB accesses testsys.cpu.itb.acv 69 # ITB acv -testsys.cpu.itb.hits 1248325 # ITB hits +testsys.cpu.itb.hits 1248343 # ITB hits testsys.cpu.itb.misses 1497 # ITB misses -testsys.cpu.kern.callpal 13126 # number of callpals executed -testsys.cpu.kern.callpal_swpctx 440 3.35% 3.35% # number of callpals executed -testsys.cpu.kern.callpal_tbi 20 0.15% 3.50% # number of callpals executed -testsys.cpu.kern.callpal_swpipl 11077 84.39% 87.89% # number of callpals executed -testsys.cpu.kern.callpal_rdps 359 2.74% 90.63% # number of callpals executed -testsys.cpu.kern.callpal_wrusp 3 0.02% 90.65% # number of callpals executed +testsys.cpu.kern.callpal 13124 # number of callpals executed +testsys.cpu.kern.callpal_swpctx 438 3.34% 3.34% # number of callpals executed +testsys.cpu.kern.callpal_tbi 20 0.15% 3.49% # number of callpals executed +testsys.cpu.kern.callpal_swpipl 11076 84.40% 87.88% # number of callpals executed +testsys.cpu.kern.callpal_rdps 359 2.74% 90.62% # number of callpals executed +testsys.cpu.kern.callpal_wrusp 3 0.02% 90.64% # number of callpals executed testsys.cpu.kern.callpal_rdusp 3 0.02% 90.67% # number of callpals executed -testsys.cpu.kern.callpal_rti 1040 7.92% 98.60% # number of callpals executed +testsys.cpu.kern.callpal_rti 1041 7.93% 98.60% # number of callpals executed testsys.cpu.kern.callpal_callsys 140 1.07% 99.66% # number of callpals executed testsys.cpu.kern.callpal_imb 44 0.34% 100.00% # number of callpals executed testsys.cpu.kern.inst.arm 0 # number of arm instructions executed -testsys.cpu.kern.inst.hwrei 19056 # number of hwrei instructions executed +testsys.cpu.kern.inst.hwrei 19055 # number of hwrei instructions executed testsys.cpu.kern.inst.quiesce 377 # number of quiesce instructions executed -testsys.cpu.kern.ipl_count 12505 # number of times we switched to this ipl +testsys.cpu.kern.ipl_count 12506 # number of times we switched to this ipl testsys.cpu.kern.ipl_count_0 5061 40.47% 40.47% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count_21 183 1.46% 41.94% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count_22 205 1.64% 43.57% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count_31 7056 56.43% 100.00% # number of times we switched to this ipl -testsys.cpu.kern.ipl_good 10498 # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_count_21 184 1.47% 41.94% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count_22 205 1.64% 43.58% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count_31 7056 56.42% 100.00% # number of times we switched to this ipl +testsys.cpu.kern.ipl_good 10499 # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good_0 5055 48.15% 48.15% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good_21 183 1.74% 49.90% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good_21 184 1.75% 49.90% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good_22 205 1.95% 51.85% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good_31 5055 48.15% 100.00% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_ticks 199569923781 # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks_0 199569307594 100.00% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks_21 30857 0.00% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks 199569922466 # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks_0 199569307215 100.00% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks_21 31026 0.00% 100.00% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks_31 567700 0.00% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_used 0.839504 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_ticks_31 566595 0.00% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_used 0.839517 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used_0 0.998814 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl @@ -201,17 +201,17 @@ testsys.cpu.kern.ipl_used_31 0.716412 # fr testsys.cpu.kern.mode_good_kernel 654 testsys.cpu.kern.mode_good_user 649 testsys.cpu.kern.mode_good_idle 5 -testsys.cpu.kern.mode_switch_kernel 1100 # number of protection mode switches +testsys.cpu.kern.mode_switch_kernel 1099 # number of protection mode switches testsys.cpu.kern.mode_switch_user 649 # number of protection mode switches testsys.cpu.kern.mode_switch_idle 381 # number of protection mode switches -testsys.cpu.kern.mode_switch_good 0.614085 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good_kernel 0.594545 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good 0.614373 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good_kernel 0.595086 # fraction of useful protection mode switches testsys.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches testsys.cpu.kern.mode_switch_good_idle 0.013123 # fraction of useful protection mode switches -testsys.cpu.kern.mode_ticks_kernel 1821815 2.16% 2.16% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks_user 1065606 1.26% 3.43% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks_idle 81402910 96.57% 100.00% # number of ticks spent at the given mode -testsys.cpu.kern.swap_context 440 # number of times the context was actually changed +testsys.cpu.kern.mode_ticks_kernel 1821131 2.16% 2.16% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks_user 1065606 1.26% 3.42% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks_idle 81402279 96.58% 100.00% # number of ticks spent at the given mode +testsys.cpu.kern.swap_context 438 # number of times the context was actually changed testsys.cpu.kern.syscall 83 # number of syscalls executed testsys.cpu.kern.syscall_2 3 3.61% 3.61% # number of syscalls executed testsys.cpu.kern.syscall_3 7 8.43% 12.05% # number of syscalls executed @@ -235,9 +235,9 @@ testsys.cpu.kern.syscall_104 1 1.20% 93.98% # nu testsys.cpu.kern.syscall_105 3 3.61% 97.59% # number of syscalls executed testsys.cpu.kern.syscall_118 2 2.41% 100.00% # number of syscalls executed testsys.cpu.not_idle_fraction 0.000001 # Percentage of non-idle cycles -testsys.cpu.numCycles 3566766 # number of cpu cycles simulated -testsys.cpu.num_insts 3565200 # Number of instructions executed -testsys.cpu.num_refs 1173985 # Number of memory references +testsys.cpu.numCycles 3566068 # number of cpu cycles simulated +testsys.cpu.num_insts 3564502 # Number of instructions executed +testsys.cpu.num_refs 1173608 # Number of memory references testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -383,12 +383,12 @@ drivesys.tsunami.ethernet.totalSwi 0 # to drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -host_inst_rate 45169521229 # Simulator instruction rate (inst/s) -host_mem_usage 406052 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 123213356 # Simulator tick rate (ticks/s) +host_inst_rate 105949570270 # Simulator instruction rate (inst/s) +host_mem_usage 465972 # Number of bytes of host memory used +host_seconds 0.00 # Real time elapsed on the host +host_tick_rate 285395062 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 273411112 # Number of instructions simulated +sim_insts 274409387 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated sim_ticks 785978 # Number of ticks simulated testsys.cpu.dtb.accesses 0 # DTB accesses diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr index 5d8bcbd75..8fb9590c3 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr @@ -1,6 +1,6 @@ -Listening for testsys connection on port 3457 -Listening for drivesys connection on port 3458 -0: testsys.remote_gdb.listener: listening for remote gdb on port 7002 -0: drivesys.remote_gdb.listener: listening for remote gdb on port 7003 +Listening for testsys connection on port 3456 +Listening for drivesys connection on port 3457 +0: testsys.remote_gdb.listener: listening for remote gdb #0 on port 7000 +0: drivesys.remote_gdb.listener: listening for remote gdb #1 on port 7001 warn: Entering event queue @ 0. Starting simulation... warn: Obsolete M5 instruction ivlb encountered. diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout index 20cc93dd8..4fb87de69 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout @@ -5,9 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2007 03:02:42 -M5 started Sun Apr 22 03:24:38 2007 -M5 executing on zed -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic +M5 compiled Apr 30 2007 13:38:38 +M5 started Mon Apr 30 14:01:42 2007 +M5 executing on zeep +command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 4300236341073 because checkpoint + 0: testsys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 + 0: drivesys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 +Exiting @ tick 4300236342388 because checkpoint From 3ae12a549e697db5a1c5baa723441435ebfeba98 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 30 Apr 2007 14:22:18 -0400 Subject: [PATCH 39/68] update release notes a bit --HG-- extra : convert_revision : e99661b971a1cbb2be6cabb68c1a4dcc7c4792ba --- RELEASE_NOTES | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/RELEASE_NOTES b/RELEASE_NOTES index 1deb3b629..1c781ac29 100644 --- a/RELEASE_NOTES +++ b/RELEASE_NOTES @@ -10,7 +10,7 @@ Outstanding issues for 2.0 release: 8. Validation 9. Testing -Apr. XX, 2007: m5_2.0_beta3 +May XX, 2007: m5_2.0_beta3 -------------------- New Features 1. Some support for SPARC full-system simulation @@ -19,9 +19,13 @@ Bug fixes since beta 2: 1. Many SPARC linux syscall emulation support fixes 2. Multiprocessor linux boot using the detailed O3 CPU module 3. Simulator performance and memory leak fixes -4. Fix issues with remote debugging -5. Several compile fixes, including gcc 4.1 -6. Many other minor fixes and enhancements +4. Fixed issue where console could stop printing in ALPHA_FS +5. Fix issues with remote debugging +6. Several compile fixes, including gcc 4.1 +7. Reworking of trace facitities (parameter names changed, variadic macros removed) +8. Scons script cleanups +9. Some support for compiling with Intel CC +10. Many other minor fixes and enhancements Nov. 28, 2006: m5_2.0_beta2 -------------------- From 8d56145d7b6f759456993b63692165d4b510adda Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 30 Apr 2007 22:49:21 -0400 Subject: [PATCH 40/68] always skip the debugprintf function (DebugPrintf traceflag shouldn't matter). Otherwise, when you turn on debugprintf alters the execution --HG-- extra : convert_revision : 1c9a665e3b7234cacf06c31d2e7886244a9e82bc --- src/kern/linux/events.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/kern/linux/events.cc b/src/kern/linux/events.cc index ba52e040a..4a3fd9f47 100644 --- a/src/kern/linux/events.cc +++ b/src/kern/linux/events.cc @@ -51,8 +51,8 @@ DebugPrintkEvent::process(ThreadContext *tc) TheISA::Arguments args(tc); Printk(args); - SkipFuncEvent::process(tc); } + SkipFuncEvent::process(tc); } } // namespace linux From ccdf60f7b2023a63b7ead9404ec90e590d921cb3 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 1 May 2007 12:32:30 -0400 Subject: [PATCH 41/68] initialize lastTxInt to 0 --HG-- extra : convert_revision : 4c5e9c2145b12fdeba91f3fdd8963c35abe326c2 --- src/dev/uart8250.cc | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/src/dev/uart8250.cc b/src/dev/uart8250.cc index d178bd1af..50307aad4 100644 --- a/src/dev/uart8250.cc +++ b/src/dev/uart8250.cc @@ -101,14 +101,11 @@ Uart8250::IntrEvent::scheduleIntr() Uart8250::Uart8250(Params *p) - : Uart(p), txIntrEvent(this, TX_INT), rxIntrEvent(this, RX_INT) + : Uart(p), IER(0), DLAB(0), LCR(0), MCR(0), lastTxInt(0), + txIntrEvent(this, TX_INT), rxIntrEvent(this, RX_INT) { pioSize = 8; - IER = 0; - DLAB = 0; - LCR = 0; - MCR = 0; } Tick From 8371f03e0df1b8b30f750e9b5c04ad67d706c656 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 1 May 2007 13:23:40 -0400 Subject: [PATCH 42/68] update for dprintk and not initializing lastTxInt --HG-- extra : convert_revision : c81ea950a919349a6e82f61ba591d3fbde4627b3 --- .../twosys-tsunami-simple-atomic/m5stats.txt | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt index b190ca80a..8ef183435 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt @@ -140,12 +140,12 @@ drivesys.tsunami.ethernet.txPPS 25 # Pa drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -host_inst_rate 50427764 # Simulator instruction rate (inst/s) -host_mem_usage 465972 # Number of bytes of host memory used -host_seconds 5.44 # Real time elapsed on the host -host_tick_rate 36752487576 # Simulator tick rate (ticks/s) +host_inst_rate 36787265 # Simulator instruction rate (inst/s) +host_mem_usage 407784 # Number of bytes of host memory used +host_seconds 7.46 # Real time elapsed on the host +host_tick_rate 26810828297 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 274409387 # Number of instructions simulated +sim_insts 274411697 # Number of instructions simulated sim_seconds 0.200001 # Number of seconds simulated sim_ticks 200000789468 # Number of ticks simulated testsys.cpu.dtb.accesses 335402 # DTB accesses @@ -383,12 +383,12 @@ drivesys.tsunami.ethernet.totalSwi 0 # to drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -host_inst_rate 105949570270 # Simulator instruction rate (inst/s) -host_mem_usage 465972 # Number of bytes of host memory used +host_inst_rate 80923531996 # Simulator instruction rate (inst/s) +host_mem_usage 407784 # Number of bytes of host memory used host_seconds 0.00 # Real time elapsed on the host -host_tick_rate 285395062 # Simulator tick rate (ticks/s) +host_tick_rate 216582530 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 274409387 # Number of instructions simulated +sim_insts 274411697 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated sim_ticks 785978 # Number of ticks simulated testsys.cpu.dtb.accesses 0 # DTB accesses From 39743d35a3dbe5b46e5051ade5394518cef8de9e Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 1 May 2007 18:12:58 -0400 Subject: [PATCH 43/68] fix flushAddr so it doesn't modify an iterator that has been deleted --HG-- extra : convert_revision : 8b7e4948974517b13616ab782aa7e84471b24f10 --- src/arch/alpha/tlb.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc index 3ab65e664..2dfff8c5f 100644 --- a/src/arch/alpha/tlb.cc +++ b/src/arch/alpha/tlb.cc @@ -213,7 +213,7 @@ TLB::flushAddr(Addr addr, uint8_t asn) if (i == lookupTable.end()) return; - while (i->first == vaddr.vpn()) { + while (i != lookupTable.end() && i->first == vaddr.vpn()) { int index = i->second; PTE *pte = &table[index]; assert(pte->valid); @@ -225,10 +225,10 @@ TLB::flushAddr(Addr addr, uint8_t asn) // invalidate this entry pte->valid = false; - lookupTable.erase(i); + lookupTable.erase(i++); + } else { + ++i; } - - ++i; } } From 3f2b039c98e57cdcd22376552d77603e6233c371 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 1 May 2007 18:14:16 -0400 Subject: [PATCH 44/68] change the way dprintf works so the cache accesses required to fulfill the dprintf aren't show in between the Cycle: name: printing and the actual formatted string being printed --HG-- extra : convert_revision : 8876ba938ba971f854bab490c9af10db039a2e83 --- src/kern/linux/events.cc | 11 +++++------ src/kern/linux/events.hh | 8 ++------ src/kern/linux/printk.cc | 13 +++---------- src/kern/linux/printk.hh | 4 +++- 4 files changed, 13 insertions(+), 23 deletions(-) diff --git a/src/kern/linux/events.cc b/src/kern/linux/events.cc index 4a3fd9f47..42fa63a27 100644 --- a/src/kern/linux/events.cc +++ b/src/kern/linux/events.cc @@ -37,6 +37,7 @@ #include "kern/system_events.hh" #include "sim/system.hh" +#include namespace Linux { @@ -44,13 +45,11 @@ void DebugPrintkEvent::process(ThreadContext *tc) { if (DTRACE(DebugPrintf)) { - if (!raw) { - StringWrap name(tc->getSystemPtr()->name() + ".dprintk"); - DPRINTFN(""); - } - + std::stringstream ss; TheISA::Arguments args(tc); - Printk(args); + Printk(ss, args); + StringWrap name(tc->getSystemPtr()->name() + ".dprintk"); + DPRINTFN("%s", ss.str()); } SkipFuncEvent::process(tc); } diff --git a/src/kern/linux/events.hh b/src/kern/linux/events.hh index b0510c18f..e36a72dde 100644 --- a/src/kern/linux/events.hh +++ b/src/kern/linux/events.hh @@ -38,13 +38,9 @@ namespace Linux { class DebugPrintkEvent : public SkipFuncEvent { - private: - bool raw; - public: - DebugPrintkEvent(PCEventQueue *q, const std::string &desc, Addr addr, - bool r = false) - : SkipFuncEvent(q, desc, addr), raw(r) {} + DebugPrintkEvent(PCEventQueue *q, const std::string &desc, Addr addr) + : SkipFuncEvent(q, desc, addr) {} virtual void process(ThreadContext *xc); }; diff --git a/src/kern/linux/printk.cc b/src/kern/linux/printk.cc index 0e9fd6620..866353e31 100644 --- a/src/kern/linux/printk.cc +++ b/src/kern/linux/printk.cc @@ -32,22 +32,18 @@ #include #include -#include "base/trace.hh" #include "arch/arguments.hh" +#include "base/trace.hh" +#include "kern/linux/printk.hh" using namespace std; void -Printk(TheISA::Arguments args) +Printk(stringstream &out, TheISA::Arguments args) { - std::ostream &out = Trace::output(); char *p = (char *)args++; - ios::fmtflags saved_flags = out.flags(); - char old_fill = out.fill(); - int old_precision = out.precision(); - while (*p) { switch (*p) { case '%': { @@ -258,8 +254,5 @@ Printk(TheISA::Arguments args) } } - out.flags(saved_flags); - out.fill(old_fill); - out.precision(old_precision); } diff --git a/src/kern/linux/printk.hh b/src/kern/linux/printk.hh index 17d59b765..20dfb430f 100644 --- a/src/kern/linux/printk.hh +++ b/src/kern/linux/printk.hh @@ -34,8 +34,10 @@ #include "arch/isa_specific.hh" +#include + class TheISA::Arguments; -void Printk(TheISA::Arguments args); +void Printk(std::stringstream &out, TheISA::Arguments args); #endif // __PRINTK_HH__ From 0dfc29a023ff407846ea4f200547e2b2d9de9c1a Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 7 May 2007 14:42:03 -0400 Subject: [PATCH 45/68] fix partial writes with a functional memory hack figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached configs/common/FSConfig.py: src/mem/bridge.cc: src/mem/bridge.hh: src/python/m5/objects/Bridge.py: fix partial writes with a functional memory hack src/mem/bus.cc: src/mem/bus.hh: src/python/m5/objects/Bus.py: figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached src/mem/packet.cc: fix WriteInvalidateResp to not be a request that needs a response since it isn't src/mem/port.hh: by default return 0 for deviceBlockSize instead of panicing. This makes finding the block size the bus should use easier --HG-- extra : convert_revision : 3fcfe95f9f392ef76f324ee8bd1d7f6de95c1a64 --- configs/common/FSConfig.py | 2 +- src/mem/bridge.cc | 45 +++++++++++++++----- src/mem/bridge.hh | 51 +++++++++++++++++++++-- src/mem/bus.cc | 73 +++++++++++++++++++++++++-------- src/mem/bus.hh | 22 ++++++++-- src/mem/packet.cc | 2 +- src/mem/port.hh | 6 +-- src/python/m5/objects/Bridge.py | 2 + src/python/m5/objects/Bus.py | 1 + 9 files changed, 165 insertions(+), 39 deletions(-) diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py index be3f5ff79..289a7a5f4 100644 --- a/configs/common/FSConfig.py +++ b/configs/common/FSConfig.py @@ -61,7 +61,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None): self.readfile = mdesc.script() self.iobus = Bus(bus_id=0) self.membus = Bus(bus_id=1) - self.bridge = Bridge() + self.bridge = Bridge(fix_partial_write_b=True) self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) self.bridge.side_a = self.iobus.port self.bridge.side_b = self.membus.port diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc index b787f79ca..b25d135e2 100644 --- a/src/mem/bridge.cc +++ b/src/mem/bridge.cc @@ -43,20 +43,24 @@ Bridge::BridgePort::BridgePort(const std::string &_name, Bridge *_bridge, BridgePort *_otherPort, - int _delay, int _queueLimit) + int _delay, int _queueLimit, + bool fix_partial_write) : Port(_name), bridge(_bridge), otherPort(_otherPort), - delay(_delay), outstandingResponses(0), - queueLimit(_queueLimit), sendEvent(this) + delay(_delay), fixPartialWrite(fix_partial_write), + outstandingResponses(0), queueLimit(_queueLimit), sendEvent(this) { } Bridge::Bridge(const std::string &n, int qsa, int qsb, - Tick _delay, int write_ack) + Tick _delay, int write_ack, bool fix_partial_write_a, + bool fix_partial_write_b) : MemObject(n), - portA(n + "-portA", this, &portB, _delay, qsa), - portB(n + "-portB", this, &portA, _delay, qsa), + portA(n + "-portA", this, &portB, _delay, qsa, fix_partial_write_a), + portB(n + "-portB", this, &portA, _delay, qsa, fix_partial_write_b), ackWrites(write_ack) { + if (ackWrites) + panic("No support for acknowledging writes\n"); } Port * @@ -82,7 +86,10 @@ Bridge::init() { // Make sure that both sides are connected to. if (portA.getPeer() == NULL || portB.getPeer() == NULL) - panic("Both ports of bus bridge are not connected to a bus.\n"); + fatal("Both ports of bus bridge are not connected to a bus.\n"); + + if (portA.peerBlockSize() != portB.peerBlockSize()) + fatal("Busses don't have the same block size... Not supported.\n"); } @@ -107,8 +114,10 @@ Bridge::BridgePort::recvTiming(PacketPtr pkt) bool Bridge::BridgePort::queueForSendTiming(PacketPtr pkt) { - if (queueFull()) + if (queueFull()) { + DPRINTF(BusBridge, "Queue full, returning false\n"); return false; + } if (pkt->isResponse()) { // This is a response for a request we forwarded earlier. The @@ -149,6 +158,7 @@ Bridge::BridgePort::trySend() assert(!sendQueue.empty()); bool was_full = queueFull(); + int pbs = peerBlockSize(); PacketBuffer *buf = sendQueue.front(); @@ -156,10 +166,18 @@ Bridge::BridgePort::trySend() PacketPtr pkt = buf->pkt; + pkt->flags &= ~SNOOP_COMMIT; //CLear it if it was set + + if (pkt->cmd == MemCmd::WriteInvalidateReq && fixPartialWrite && + pkt->getOffset(pbs) && pkt->getSize() != pbs) { + buf->partialWriteFix(this); + pkt = buf->pkt; + } + DPRINTF(BusBridge, "trySend: origSrc %d dest %d addr 0x%x\n", buf->origSrc, pkt->getDest(), pkt->getAddr()); - pkt->flags &= ~SNOOP_COMMIT; //CLear it if it was set + if (sendTiming(pkt)) { // send successful sendQueue.pop_front(); @@ -191,6 +209,7 @@ Bridge::BridgePort::trySend() } else { DPRINTF(BusBridge, " unsuccessful\n"); + buf->undoPartialWriteFix(); } } @@ -248,6 +267,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Bridge) Param queue_size_b; Param delay; Param write_ack; + Param fix_partial_write_a; + Param fix_partial_write_b; END_DECLARE_SIM_OBJECT_PARAMS(Bridge) @@ -256,14 +277,16 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Bridge) INIT_PARAM(queue_size_a, "The size of the queue for data coming into side a"), INIT_PARAM(queue_size_b, "The size of the queue for data coming into side b"), INIT_PARAM(delay, "The miminum delay to cross this bridge"), - INIT_PARAM(write_ack, "Acknowledge any writes that are received.") + INIT_PARAM(write_ack, "Acknowledge any writes that are received."), + INIT_PARAM(fix_partial_write_a, "Fixup any partial block writes that are received"), + INIT_PARAM(fix_partial_write_b, "Fixup any partial block writes that are received") END_INIT_SIM_OBJECT_PARAMS(Bridge) CREATE_SIM_OBJECT(Bridge) { return new Bridge(getInstanceName(), queue_size_a, queue_size_b, delay, - write_ack); + write_ack, fix_partial_write_a, fix_partial_write_b); } REGISTER_SIM_OBJECT("Bridge", Bridge) diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh index f7d0d12d0..d1154eda0 100644 --- a/src/mem/bridge.hh +++ b/src/mem/bridge.hh @@ -66,6 +66,8 @@ class Bridge : public MemObject /** Minimum delay though this bridge. */ Tick delay; + bool fixPartialWrite; + class PacketBuffer : public Packet::SenderState { public: @@ -75,10 +77,13 @@ class Bridge : public MemObject short origSrc; bool expectResponse; + bool partialWriteFixed; + PacketPtr oldPkt; + PacketBuffer(PacketPtr _pkt, Tick t) : ready(t), pkt(_pkt), origSenderState(_pkt->senderState), origSrc(_pkt->getSrc()), - expectResponse(_pkt->needsResponse()) + expectResponse(_pkt->needsResponse()), partialWriteFixed(false) { if (!pkt->isResponse()) pkt->senderState = this; @@ -89,7 +94,46 @@ class Bridge : public MemObject assert(pkt->senderState == this); pkt->setDest(origSrc); pkt->senderState = origSenderState; + if (partialWriteFixed) + delete oldPkt; } + + void partialWriteFix(Port *port) + { + assert(!partialWriteFixed); + assert(expectResponse); + + int pbs = port->peerBlockSize(); + partialWriteFixed = true; + PacketDataPtr data; + + data = new uint8_t[pbs]; + PacketPtr funcPkt = new Packet(pkt->req, MemCmd::ReadReq, + Packet::Broadcast, pbs); + + funcPkt->dataStatic(data); + port->sendFunctional(funcPkt); + assert(funcPkt->result == Packet::Success); + delete funcPkt; + + oldPkt = pkt; + memcpy(data + oldPkt->getOffset(pbs), pkt->getPtr(), + pkt->getSize()); + pkt = new Packet(oldPkt->req, MemCmd::WriteInvalidateReq, + Packet::Broadcast, pbs); + pkt->dataDynamicArray(data); + pkt->senderState = oldPkt->senderState; + } + + void undoPartialWriteFix() + { + if (!partialWriteFixed) + return; + delete pkt; + pkt = oldPkt; + partialWriteFixed = false; + } + }; /** @@ -140,7 +184,7 @@ class Bridge : public MemObject /** Constructor for the BusPort.*/ BridgePort(const std::string &_name, Bridge *_bridge, BridgePort *_otherPort, - int _delay, int _queueLimit); + int _delay, int _queueLimit, bool fix_partial_write); protected: @@ -182,7 +226,8 @@ class Bridge : public MemObject virtual void init(); - Bridge(const std::string &n, int qsa, int qsb, Tick _delay, int write_ack); + Bridge(const std::string &n, int qsa, int qsb, Tick _delay, int write_ack, + bool fix_partial_write_a, bool fix_partial_write_b); }; #endif //__MEM_BUS_HH__ diff --git a/src/mem/bus.cc b/src/mem/bus.cc index b0636ecc2..6682ade55 100644 --- a/src/mem/bus.cc +++ b/src/mem/bus.cc @@ -48,6 +48,7 @@ Bus::getPort(const std::string &if_name, int idx) if (defaultPort == NULL) { defaultPort = new BusPort(csprintf("%s-default",name()), this, defaultId); + cachedBlockSizeValid = false; return defaultPort; } else fatal("Default port already set\n"); @@ -68,6 +69,7 @@ Bus::getPort(const std::string &if_name, int idx) assert(maxId < std::numeric_limits::max()); BusPort *bp = new BusPort(csprintf("%s-p%d", name(), id), this, id); interfaces[id] = bp; + cachedBlockSizeValid = false; return bp; } @@ -182,6 +184,7 @@ Bus::recvTiming(PacketPtr pkt) if (tickNextIdle > curTick || (retryList.size() && (!inRetry || pktPort != retryList.front()))) { addToRetryList(pktPort); + DPRINTF(Bus, "recvTiming: Bus is busy, returning false\n"); return false; } @@ -207,11 +210,12 @@ Bus::recvTiming(PacketPtr pkt) inRetry = false; } occupyBus(pkt); + DPRINTF(Bus, "recvTiming: Packet sucessfully sent\n"); return true; } } else { //Snoop didn't succeed - DPRINTF(Bus, "Adding a retry to RETRY list %d\n", + DPRINTF(Bus, "Adding1 a retry to RETRY list %d\n", pktPort->getId()); addToRetryList(pktPort); return false; @@ -239,13 +243,14 @@ Bus::recvTiming(PacketPtr pkt) } // Packet not successfully sent. Leave or put it on the retry list. - DPRINTF(Bus, "Adding a retry to RETRY list %d\n", + DPRINTF(Bus, "Adding2 a retry to RETRY list %d\n", pktPort->getId()); addToRetryList(pktPort); return false; } else { //Forwarding up from responder, just return true; + DPRINTF(Bus, "recvTiming: can we be here?\n"); return true; } } @@ -253,12 +258,12 @@ Bus::recvTiming(PacketPtr pkt) void Bus::recvRetry(int id) { - DPRINTF(Bus, "Received a retry\n"); + DPRINTF(Bus, "Received a retry from %s\n", id == -1 ? "self" : interfaces[id]->getPeer()->name()); // If there's anything waiting, and the bus isn't busy... if (retryList.size() && curTick >= tickNextIdle) { //retryingPort = retryList.front(); inRetry = true; - DPRINTF(Bus, "Sending a retry\n"); + DPRINTF(Bus, "Sending a retry to %s\n", retryList.front()->getPeer()->name()); retryList.front()->sendRetry(); // If inRetry is still true, sendTiming wasn't called if (inRetry) @@ -267,18 +272,20 @@ Bus::recvRetry(int id) retryList.pop_front(); inRetry = false; - //Bring tickNextIdle up to the present - while (tickNextIdle < curTick) + if (id != -1) { + //Bring tickNextIdle up to the present + while (tickNextIdle < curTick) + tickNextIdle += clock; + + //Burn a cycle for the missed grant. tickNextIdle += clock; - //Burn a cycle for the missed grant. - tickNextIdle += clock; - - if (!busIdle.scheduled()) { - busIdle.schedule(tickNextIdle); - } else { - busIdle.reschedule(tickNextIdle); - } + if (!busIdle.scheduled()) { + busIdle.schedule(tickNextIdle); + } else { + busIdle.reschedule(tickNextIdle); + } + } // id != -1 } } //If we weren't able to drain before, we might be able to now. @@ -598,6 +605,37 @@ Bus::addressRanges(AddrRangeList &resp, AddrRangeList &snoop, int id) } } +int +Bus::findBlockSize(int id) +{ + if (cachedBlockSizeValid) + return cachedBlockSize; + + int max_bs = -1, tmp_bs; + range_map::iterator portIter; + std::vector::iterator snoopIter; + for (portIter = portMap.begin(); portIter != portMap.end(); portIter++) { + tmp_bs = interfaces[portIter->second]->peerBlockSize(); + if (tmp_bs > max_bs) + max_bs = tmp_bs; + } + for (snoopIter = portSnoopList.begin(); + snoopIter != portSnoopList.end(); snoopIter++) { + tmp_bs = interfaces[snoopIter->portId]->peerBlockSize(); + if (tmp_bs > max_bs) + max_bs = tmp_bs; + } + if (max_bs <= 0) + max_bs = defaultBlockSize; + + if (max_bs != 64) + warn_once("Blocksize found to not be 64... hmm... probably not.\n"); + cachedBlockSize = max_bs; + cachedBlockSizeValid = true; + return max_bs; +} + + unsigned int Bus::drain(Event * de) { @@ -618,6 +656,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Bus) Param clock; Param width; Param responder_set; + Param block_size; END_DECLARE_SIM_OBJECT_PARAMS(Bus) @@ -625,12 +664,14 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Bus) INIT_PARAM(bus_id, "a globally unique bus id"), INIT_PARAM(clock, "bus clock speed"), INIT_PARAM(width, "width of the bus (bits)"), - INIT_PARAM(responder_set, "Is a default responder set by the user") + INIT_PARAM(responder_set, "Is a default responder set by the user"), + INIT_PARAM(block_size, "Default blocksize if no device has one") END_INIT_SIM_OBJECT_PARAMS(Bus) CREATE_SIM_OBJECT(Bus) { - return new Bus(getInstanceName(), bus_id, clock, width, responder_set); + return new Bus(getInstanceName(), bus_id, clock, width, responder_set, + block_size); } REGISTER_SIM_OBJECT("Bus", Bus) diff --git a/src/mem/bus.hh b/src/mem/bus.hh index 0dd7547c5..f0dc67b12 100644 --- a/src/mem/bus.hh +++ b/src/mem/bus.hh @@ -133,6 +133,12 @@ class Bus : public MemObject /** Occupy the bus with transmitting the packet pkt */ void occupyBus(PacketPtr pkt); + /** Ask everyone on the bus what their size is + * @param id id of the busport that made the request + * @return the max of all the sizes + */ + int findBlockSize(int id); + /** Declaration of the buses port type, one will be instantiated for each of the interfaces connecting to the bus. */ class BusPort : public Port @@ -195,8 +201,11 @@ class Bus : public MemObject AddrRangeList &snoop) { bus->addressRanges(resp, snoop, id); } - // Hack to make translating port work without changes - virtual int deviceBlockSize() { return 32; } + // Ask the bus to ask everyone on the bus what their block size is and + // take the max of it. This might need to be changed a bit if we ever + // support multiple block sizes. + virtual int deviceBlockSize() + { return bus->findBlockSize(id); } }; @@ -256,6 +265,10 @@ class Bus : public MemObject /** Has the user specified their own default responder? */ bool responderSet; + int defaultBlockSize; + int cachedBlockSize; + bool cachedBlockSizeValid; + public: /** A function used to return the port associated with this bus object. */ @@ -267,11 +280,12 @@ class Bus : public MemObject unsigned int drain(Event *de); Bus(const std::string &n, int bus_id, int _clock, int _width, - bool responder_set) + bool responder_set, int dflt_blk_size) : MemObject(n), busId(bus_id), clock(_clock), width(_width), tickNextIdle(0), drainEvent(NULL), busIdle(this), inRetry(false), maxId(0), defaultPort(NULL), funcPort(NULL), funcPortId(-4), - responderSet(responder_set) + responderSet(responder_set), defaultBlockSize(dflt_blk_size), + cachedBlockSize(0), cachedBlockSizeValid(false) { //Both the width and clock period must be positive if (width <= 0) diff --git a/src/mem/packet.cc b/src/mem/packet.cc index 14d08db1b..2463a19ba 100644 --- a/src/mem/packet.cc +++ b/src/mem/packet.cc @@ -85,7 +85,7 @@ MemCmd::commandInfo[] = { SET5(IsWrite, IsInvalidate, IsRequest, HasData, NeedsResponse), WriteInvalidateResp, "WriteInvalidateReq" }, /* WriteInvalidateResp */ - { SET5(IsWrite, IsInvalidate, IsRequest, NeedsResponse, IsResponse), + { SET3(IsWrite, IsInvalidate, IsResponse), InvalidCmd, "WriteInvalidateResp" }, /* UpgradeReq */ { SET3(IsInvalidate, IsRequest, IsUpgrade), InvalidCmd, "UpgradeReq" }, diff --git a/src/mem/port.hh b/src/mem/port.hh index 6296b42ca..877e00293 100644 --- a/src/mem/port.hh +++ b/src/mem/port.hh @@ -161,10 +161,10 @@ class Port /** Called by a peer port in order to determine the block size of the device connected to this port. It sometimes doesn't make sense for - this function to be called, a DMA interface doesn't really have a - block size, so it is defaulted to a panic. + this function to be called, so it just returns 0. Anytthing that is + concerned with the size should just ignore that. */ - virtual int deviceBlockSize() { panic("??"); M5_DUMMY_RETURN } + virtual int deviceBlockSize() { return 0; } /** The peer port is requesting us to reply with a list of the ranges we are responsible for. diff --git a/src/python/m5/objects/Bridge.py b/src/python/m5/objects/Bridge.py index ee8e76bff..e123c2891 100644 --- a/src/python/m5/objects/Bridge.py +++ b/src/python/m5/objects/Bridge.py @@ -9,3 +9,5 @@ class Bridge(MemObject): queue_size_b = Param.Int(16, "The number of requests to buffer") delay = Param.Latency('0ns', "The latency of this bridge") write_ack = Param.Bool(False, "Should this bridge ack writes") + fix_partial_write_a = Param.Bool(False, "Should this bridge fixup partial block writes") + fix_partial_write_b = Param.Bool(False, "Should this bridge fixup partial block writes") diff --git a/src/python/m5/objects/Bus.py b/src/python/m5/objects/Bus.py index 8226fe8d2..48dbbe307 100644 --- a/src/python/m5/objects/Bus.py +++ b/src/python/m5/objects/Bus.py @@ -11,6 +11,7 @@ class Bus(MemObject): clock = Param.Clock("1GHz", "bus clock speed") width = Param.Int(64, "bus width (bytes)") responder_set = Param.Bool(False, "Did the user specify a default responder.") + block_size = Param.Int(64, "The default block size if one isn't set by a device attached to the bus.") if build_env['FULL_SYSTEM']: responder = BadAddr(pio_addr=0x0, pio_latency="1ps") default = Port(Self.responder.pio, "Default port for requests that aren't handled by a device.") From a38c79ec22918b02c529c930827e64e440984d29 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 7 May 2007 18:58:38 -0400 Subject: [PATCH 46/68] the bridge never returns false when recvTiming() is called on its ports now, it always returns true and nacks the packet if there isn't sufficient buffer space fix the timing cpu to handle receiving a nacked packet src/cpu/simple/timing.cc: make the timing cpu handle receiving a nacked packet src/mem/bridge.cc: src/mem/bridge.hh: the bridge never returns false when recvTiming() is called on its ports now, it always returns true and nacks the packet if there isn't sufficient buffer space --HG-- extra : convert_revision : 5e12d0cf6ce985a5f72bcb7ce26c83a76c34c50a --- src/cpu/simple/timing.cc | 24 ++++++++--- src/mem/bridge.cc | 93 ++++++++++++++++++++++++++++++---------- src/mem/bridge.hh | 16 ++++--- 3 files changed, 99 insertions(+), 34 deletions(-) diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 45da7c3eb..fa7bb4f86 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -574,10 +574,16 @@ TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) return true; } - else { - //Snooping a Coherence Request, do nothing - return true; + else if (pkt->result == Packet::Nacked) { + assert(cpu->_status == IcacheWaitResponse); + pkt->reinitNacked(); + if (!sendTiming(pkt)) { + cpu->_status = IcacheRetry; + cpu->ifetch_pkt = pkt; + } } + //Snooping a Coherence Request, do nothing + return true; } void @@ -663,10 +669,16 @@ TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) return true; } - else { - //Snooping a coherence req, do nothing - return true; + else if (pkt->result == Packet::Nacked) { + assert(cpu->_status == DcacheWaitResponse); + pkt->reinitNacked(); + if (!sendTiming(pkt)) { + cpu->_status = DcacheRetry; + cpu->dcache_pkt = pkt; + } } + //Snooping a Coherence Request, do nothing + return true; } void diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc index b25d135e2..e7d52b178 100644 --- a/src/mem/bridge.cc +++ b/src/mem/bridge.cc @@ -47,7 +47,8 @@ Bridge::BridgePort::BridgePort(const std::string &_name, bool fix_partial_write) : Port(_name), bridge(_bridge), otherPort(_otherPort), delay(_delay), fixPartialWrite(fix_partial_write), - outstandingResponses(0), queueLimit(_queueLimit), sendEvent(this) + outstandingResponses(0), queuedRequests(0), + queueLimit(_queueLimit), sendEvent(this) { } @@ -92,34 +93,70 @@ Bridge::init() fatal("Busses don't have the same block size... Not supported.\n"); } +bool +Bridge::BridgePort::queueFull() +{ + // use >= here because sendQueue could get larger because of + // nacks getting inserted + return queuedRequests + outstandingResponses >= queueLimit; +} /** Function called by the port when the bus is receiving a Timing * transaction.*/ bool Bridge::BridgePort::recvTiming(PacketPtr pkt) { - if (pkt->flags & SNOOP_COMMIT) { - DPRINTF(BusBridge, "recvTiming: src %d dest %d addr 0x%x\n", + if (!(pkt->flags & SNOOP_COMMIT)) + return true; + + + DPRINTF(BusBridge, "recvTiming: src %d dest %d addr 0x%x\n", pkt->getSrc(), pkt->getDest(), pkt->getAddr()); - return otherPort->queueForSendTiming(pkt); + if (pkt->isRequest() && otherPort->queueFull()) { + DPRINTF(BusBridge, "Remote queue full, nacking\n"); + nackRequest(pkt); + return true; } - else { - // Else it's just a snoop, properly return if we are blocking - return !queueFull(); + + if (pkt->needsResponse() && pkt->result != Packet::Nacked) + if (queueFull()) { + DPRINTF(BusBridge, "Local queue full, no space for response, nacking\n"); + DPRINTF(BusBridge, "queue size: %d outreq: %d outstanding resp: %d\n", + sendQueue.size(), queuedRequests, outstandingResponses); + nackRequest(pkt); + return true; + } else { + DPRINTF(BusBridge, "Request Needs response, reserving space\n"); + ++outstandingResponses; + } + + otherPort->queueForSendTiming(pkt); + + return true; +} + +void +Bridge::BridgePort::nackRequest(PacketPtr pkt) +{ + // Nack the packet + pkt->result = Packet::Nacked; + pkt->setDest(pkt->getSrc()); + + //put it on the list to send + Tick readyTime = curTick + delay; + PacketBuffer *buf = new PacketBuffer(pkt, readyTime, true); + if (sendQueue.empty()) { + sendEvent.schedule(readyTime); } + sendQueue.push_back(buf); } -bool +void Bridge::BridgePort::queueForSendTiming(PacketPtr pkt) { - if (queueFull()) { - DPRINTF(BusBridge, "Queue full, returning false\n"); - return false; - } - - if (pkt->isResponse()) { + if (pkt->isResponse() || pkt->result == Packet::Nacked) { // This is a response for a request we forwarded earlier. The // corresponding PacketBuffer should be stored in the packet's // senderState field. @@ -128,6 +165,13 @@ Bridge::BridgePort::queueForSendTiming(PacketPtr pkt) // set up new packet dest & senderState based on values saved // from original request buf->fixResponse(pkt); + + // Check if this packet was expecting a response (this is either it or + // its a nacked packet and we won't be seeing that response) + if (buf->expectResponse) + --outstandingResponses; + + DPRINTF(BusBridge, "restoring sender state: %#X, from packet buffer: %#X\n", pkt->senderState, buf); DPRINTF(BusBridge, " is response, new dest %d\n", pkt->getDest()); @@ -146,10 +190,8 @@ Bridge::BridgePort::queueForSendTiming(PacketPtr pkt) if (sendQueue.empty()) { sendEvent.schedule(readyTime); } - + ++queuedRequests; sendQueue.push_back(buf); - - return true; } void @@ -169,7 +211,8 @@ Bridge::BridgePort::trySend() pkt->flags &= ~SNOOP_COMMIT; //CLear it if it was set if (pkt->cmd == MemCmd::WriteInvalidateReq && fixPartialWrite && - pkt->getOffset(pbs) && pkt->getSize() != pbs) { + pkt->result != Packet::Nacked && pkt->getOffset(pbs) && + pkt->getSize() != pbs) { buf->partialWriteFix(this); pkt = buf->pkt; } @@ -184,10 +227,7 @@ Bridge::BridgePort::trySend() buf->pkt = NULL; // we no longer own packet, so it's not safe to look at it if (buf->expectResponse) { - // Must wait for response. We just need to count outstanding - // responses (in case we want to cap them); PacketBuffer - // pointer will be recovered on response. - ++outstandingResponses; + // Must wait for response DPRINTF(BusBridge, " successful: awaiting response (%d)\n", outstandingResponses); } else { @@ -196,13 +236,17 @@ Bridge::BridgePort::trySend() delete buf; } + if (!buf->nacked) + --queuedRequests; + // If there are more packets to send, schedule event to try again. if (!sendQueue.empty()) { buf = sendQueue.front(); + DPRINTF(BusBridge, "Scheduling next send\n"); sendEvent.schedule(std::max(buf->ready, curTick + 1)); } // Let things start sending again - if (was_full) { + if (was_full && !queueFull()) { DPRINTF(BusBridge, "Queue was full, sending retry\n"); otherPort->sendRetry(); } @@ -211,6 +255,8 @@ Bridge::BridgePort::trySend() DPRINTF(BusBridge, " unsuccessful\n"); buf->undoPartialWriteFix(); } + DPRINTF(BusBridge, "trySend: queue size: %d outreq: %d outstanding resp: %d\n", + sendQueue.size(), queuedRequests, outstandingResponses); } @@ -290,3 +336,4 @@ CREATE_SIM_OBJECT(Bridge) } REGISTER_SIM_OBJECT("Bridge", Bridge) + diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh index d1154eda0..1fa9cdffc 100644 --- a/src/mem/bridge.hh +++ b/src/mem/bridge.hh @@ -79,13 +79,16 @@ class Bridge : public MemObject bool partialWriteFixed; PacketPtr oldPkt; + bool nacked; - PacketBuffer(PacketPtr _pkt, Tick t) + PacketBuffer(PacketPtr _pkt, Tick t, bool nack = false) : ready(t), pkt(_pkt), origSenderState(_pkt->senderState), origSrc(_pkt->getSrc()), - expectResponse(_pkt->needsResponse()), partialWriteFixed(false) + expectResponse(_pkt->needsResponse() && !nack), + partialWriteFixed(false), nacked(nack) + { - if (!pkt->isResponse()) + if (!pkt->isResponse() && !nack) pkt->senderState = this; } @@ -144,6 +147,7 @@ class Bridge : public MemObject std::list sendQueue; int outstandingResponses; + int queuedRequests; /** Max queue size for outbound packets */ int queueLimit; @@ -151,12 +155,14 @@ class Bridge : public MemObject /** * Is this side blocked from accepting outbound packets? */ - bool queueFull() { return (sendQueue.size() == queueLimit); } + bool queueFull(); - bool queueForSendTiming(PacketPtr pkt); + void queueForSendTiming(PacketPtr pkt); void finishSend(PacketBuffer *buf); + void nackRequest(PacketPtr pkt); + /** * Handle send event, scheduled when the packet at the head of * the outbound queue is ready to transmit (for timing From aa095b63cd162c13112831f51045ab81eb643214 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 7 May 2007 19:19:00 -0400 Subject: [PATCH 47/68] update for partial write fix changes --HG-- extra : convert_revision : 066224dc7034206ea6c3578d41a9a5d75181f82c --- .../tsunami-simple-timing-dual/m5stats.txt | 256 +++++++++--------- .../linux/tsunami-simple-timing/m5stats.txt | 112 ++++---- 2 files changed, 184 insertions(+), 184 deletions(-) diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt index 24b2c4738..e0f0a0067 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt @@ -1,89 +1,89 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 249273 # Simulator instruction rate (inst/s) -host_mem_usage 249952 # Number of bytes of host memory used -host_seconds 261.36 # Real time elapsed on the host -host_tick_rate 15217956 # Simulator tick rate (ticks/s) +host_inst_rate 176514 # Simulator instruction rate (inst/s) +host_mem_usage 193420 # Number of bytes of host memory used +host_seconds 369.13 # Real time elapsed on the host +host_tick_rate 10780504 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 65149861 # Number of instructions simulated -sim_seconds 1.988682 # Number of seconds simulated -sim_ticks 3977364868 # Number of ticks simulated -system.cpu0.dtb.accesses 676531 # DTB accesses +sim_insts 65155632 # Number of instructions simulated +sim_seconds 1.989678 # Number of seconds simulated +sim_ticks 3979356760 # Number of ticks simulated +system.cpu0.dtb.accesses 676537 # DTB accesses system.cpu0.dtb.acv 306 # DTB access violations -system.cpu0.dtb.hits 12726821 # DTB hits -system.cpu0.dtb.misses 8261 # DTB misses -system.cpu0.dtb.read_accesses 494241 # DTB read accesses +system.cpu0.dtb.hits 12789393 # DTB hits +system.cpu0.dtb.misses 8263 # DTB misses +system.cpu0.dtb.read_accesses 494246 # DTB read accesses system.cpu0.dtb.read_acv 184 # DTB read access violations -system.cpu0.dtb.read_hits 7906586 # DTB read hits -system.cpu0.dtb.read_misses 7534 # DTB read misses -system.cpu0.dtb.write_accesses 182290 # DTB write accesses +system.cpu0.dtb.read_hits 7941036 # DTB read hits +system.cpu0.dtb.read_misses 7535 # DTB read misses +system.cpu0.dtb.write_accesses 182291 # DTB write accesses system.cpu0.dtb.write_acv 122 # DTB write access violations -system.cpu0.dtb.write_hits 4820235 # DTB write hits -system.cpu0.dtb.write_misses 727 # DTB write misses -system.cpu0.idle_fraction 0.930925 # Percentage of idle cycles -system.cpu0.itb.accesses 3412128 # ITB accesses +system.cpu0.dtb.write_hits 4848357 # DTB write hits +system.cpu0.dtb.write_misses 728 # DTB write misses +system.cpu0.idle_fraction 0.930790 # Percentage of idle cycles +system.cpu0.itb.accesses 3420080 # ITB accesses system.cpu0.itb.acv 161 # ITB acv -system.cpu0.itb.hits 3408295 # ITB hits -system.cpu0.itb.misses 3833 # ITB misses -system.cpu0.kern.callpal 142543 # number of callpals executed +system.cpu0.itb.hits 3416243 # ITB hits +system.cpu0.itb.misses 3837 # ITB misses +system.cpu0.kern.callpal 143414 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal_wripir 572 0.40% 0.40% # number of callpals executed +system.cpu0.kern.callpal_wripir 566 0.39% 0.40% # number of callpals executed system.cpu0.kern.callpal_wrmces 1 0.00% 0.40% # number of callpals executed system.cpu0.kern.callpal_wrfen 1 0.00% 0.40% # number of callpals executed system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.40% # number of callpals executed -system.cpu0.kern.callpal_swpctx 2878 2.02% 2.42% # number of callpals executed -system.cpu0.kern.callpal_tbi 47 0.03% 2.46% # number of callpals executed -system.cpu0.kern.callpal_wrent 7 0.00% 2.46% # number of callpals executed -system.cpu0.kern.callpal_swpipl 127693 89.58% 92.04% # number of callpals executed -system.cpu0.kern.callpal_rdps 6611 4.64% 96.68% # number of callpals executed -system.cpu0.kern.callpal_wrkgp 1 0.00% 96.68% # number of callpals executed -system.cpu0.kern.callpal_wrusp 3 0.00% 96.68% # number of callpals executed -system.cpu0.kern.callpal_rdusp 8 0.01% 96.69% # number of callpals executed -system.cpu0.kern.callpal_whami 2 0.00% 96.69% # number of callpals executed -system.cpu0.kern.callpal_rti 4215 2.96% 99.65% # number of callpals executed +system.cpu0.kern.callpal_swpctx 2893 2.02% 2.41% # number of callpals executed +system.cpu0.kern.callpal_tbi 47 0.03% 2.45% # number of callpals executed +system.cpu0.kern.callpal_wrent 7 0.00% 2.45% # number of callpals executed +system.cpu0.kern.callpal_swpipl 128466 89.58% 92.03% # number of callpals executed +system.cpu0.kern.callpal_rdps 6699 4.67% 96.70% # number of callpals executed +system.cpu0.kern.callpal_wrkgp 1 0.00% 96.70% # number of callpals executed +system.cpu0.kern.callpal_wrusp 3 0.00% 96.70% # number of callpals executed +system.cpu0.kern.callpal_rdusp 8 0.01% 96.71% # number of callpals executed +system.cpu0.kern.callpal_whami 2 0.00% 96.71% # number of callpals executed +system.cpu0.kern.callpal_rti 4216 2.94% 99.65% # number of callpals executed system.cpu0.kern.callpal_callsys 355 0.25% 99.90% # number of callpals executed system.cpu0.kern.callpal_imb 147 0.10% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 157728 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6621 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 134531 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 53714 39.93% 39.93% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_21 131 0.10% 40.02% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_22 2009 1.49% 41.52% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_30 482 0.36% 41.88% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 78195 58.12% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 108736 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 53298 49.02% 49.02% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.inst.hwrei 158606 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6630 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 135306 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 54074 39.96% 39.96% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_21 131 0.10% 40.06% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_22 2010 1.49% 41.55% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_30 482 0.36% 41.90% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 78609 58.10% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 109457 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 53658 49.02% 49.02% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_21 131 0.12% 49.14% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_22 2009 1.85% 50.98% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_30 482 0.44% 51.43% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 52816 48.57% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 3976579702 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 3843537444 96.65% 96.65% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 123584 0.00% 96.66% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 1875640 0.05% 96.70% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 1201752 0.03% 96.73% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 129841282 3.27% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used 0.808260 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_0 0.992255 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good_22 2010 1.84% 50.98% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_30 482 0.44% 51.42% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_31 53176 48.58% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 3978541594 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 3845416172 96.65% 96.65% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 119304 0.00% 96.66% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 1874808 0.05% 96.70% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 1202656 0.03% 96.73% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 129928654 3.27% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used 0.808959 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_0 0.992307 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.675440 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1191 -system.cpu0.kern.mode_good_user 1191 +system.cpu0.kern.ipl_used_31 0.676462 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1189 +system.cpu0.kern.mode_good_user 1189 system.cpu0.kern.mode_good_idle 0 -system.cpu0.kern.mode_switch_kernel 6700 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1191 # number of protection mode switches +system.cpu0.kern.mode_switch_kernel 6717 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1189 # number of protection mode switches system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good 0.301863 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.177761 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good 0.300784 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.177014 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 3965299112 99.76% 99.76% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 9599258 0.24% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_kernel 3967314670 99.76% 99.76% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 9570844 0.24% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2879 # number of times the context was actually changed +system.cpu0.kern.swap_context 2894 # number of times the context was actually changed system.cpu0.kern.syscall 216 # number of syscalls executed system.cpu0.kern.syscall_2 7 3.24% 3.24% # number of syscalls executed system.cpu0.kern.syscall_3 18 8.33% 11.57% # number of syscalls executed @@ -115,82 +115,82 @@ system.cpu0.kern.syscall_98 2 0.93% 97.69% # nu system.cpu0.kern.syscall_132 2 0.93% 98.61% # number of syscalls executed system.cpu0.kern.syscall_144 1 0.46% 99.07% # number of syscalls executed system.cpu0.kern.syscall_147 2 0.93% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.069075 # Percentage of non-idle cycles -system.cpu0.numCycles 3976579942 # number of cpu cycles simulated -system.cpu0.num_insts 50251391 # Number of instructions executed -system.cpu0.num_refs 12958546 # Number of memory references -system.cpu1.dtb.accesses 346252 # DTB accesses +system.cpu0.not_idle_fraction 0.069210 # Percentage of non-idle cycles +system.cpu0.numCycles 3978541834 # number of cpu cycles simulated +system.cpu0.num_insts 50446812 # Number of instructions executed +system.cpu0.num_refs 13021282 # Number of memory references +system.cpu1.dtb.accesses 346250 # DTB accesses system.cpu1.dtb.acv 67 # DTB access violations -system.cpu1.dtb.hits 4740978 # DTB hits -system.cpu1.dtb.misses 3345 # DTB misses -system.cpu1.dtb.read_accesses 235843 # DTB read accesses +system.cpu1.dtb.hits 4679272 # DTB hits +system.cpu1.dtb.misses 3343 # DTB misses +system.cpu1.dtb.read_accesses 235842 # DTB read accesses system.cpu1.dtb.read_acv 26 # DTB read access violations -system.cpu1.dtb.read_hits 2707473 # DTB read hits -system.cpu1.dtb.read_misses 2918 # DTB read misses -system.cpu1.dtb.write_accesses 110409 # DTB write accesses +system.cpu1.dtb.read_hits 2672655 # DTB read hits +system.cpu1.dtb.read_misses 2917 # DTB read misses +system.cpu1.dtb.write_accesses 110408 # DTB write accesses system.cpu1.dtb.write_acv 41 # DTB write access violations -system.cpu1.dtb.write_hits 2033505 # DTB write hits -system.cpu1.dtb.write_misses 427 # DTB write misses -system.cpu1.idle_fraction 0.974575 # Percentage of idle cycles -system.cpu1.itb.accesses 2097220 # ITB accesses +system.cpu1.dtb.write_hits 2006617 # DTB write hits +system.cpu1.dtb.write_misses 426 # DTB write misses +system.cpu1.idle_fraction 0.974905 # Percentage of idle cycles +system.cpu1.itb.accesses 2089153 # ITB accesses system.cpu1.itb.acv 23 # ITB acv -system.cpu1.itb.hits 2095948 # ITB hits +system.cpu1.itb.hits 2087881 # ITB hits system.cpu1.itb.misses 1272 # ITB misses -system.cpu1.kern.callpal 80965 # number of callpals executed +system.cpu1.kern.callpal 80102 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu1.kern.callpal_wripir 482 0.60% 0.60% # number of callpals executed system.cpu1.kern.callpal_wrmces 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal_wrfen 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal_swpctx 2289 2.83% 3.43% # number of callpals executed -system.cpu1.kern.callpal_tbi 7 0.01% 3.43% # number of callpals executed -system.cpu1.kern.callpal_wrent 7 0.01% 3.44% # number of callpals executed -system.cpu1.kern.callpal_swpipl 71577 88.40% 91.85% # number of callpals executed -system.cpu1.kern.callpal_rdps 2303 2.84% 94.69% # number of callpals executed -system.cpu1.kern.callpal_wrkgp 1 0.00% 94.69% # number of callpals executed -system.cpu1.kern.callpal_wrusp 4 0.00% 94.70% # number of callpals executed -system.cpu1.kern.callpal_rdusp 1 0.00% 94.70% # number of callpals executed -system.cpu1.kern.callpal_whami 3 0.00% 94.70% # number of callpals executed -system.cpu1.kern.callpal_rti 4092 5.05% 99.76% # number of callpals executed +system.cpu1.kern.callpal_wrfen 1 0.00% 0.61% # number of callpals executed +system.cpu1.kern.callpal_swpctx 2276 2.84% 3.45% # number of callpals executed +system.cpu1.kern.callpal_tbi 7 0.01% 3.46% # number of callpals executed +system.cpu1.kern.callpal_wrent 7 0.01% 3.46% # number of callpals executed +system.cpu1.kern.callpal_swpipl 70820 88.41% 91.88% # number of callpals executed +system.cpu1.kern.callpal_rdps 2215 2.77% 94.64% # number of callpals executed +system.cpu1.kern.callpal_wrkgp 1 0.00% 94.64% # number of callpals executed +system.cpu1.kern.callpal_wrusp 4 0.00% 94.65% # number of callpals executed +system.cpu1.kern.callpal_rdusp 1 0.00% 94.65% # number of callpals executed +system.cpu1.kern.callpal_whami 3 0.00% 94.65% # number of callpals executed +system.cpu1.kern.callpal_rti 4087 5.10% 99.76% # number of callpals executed system.cpu1.kern.callpal_callsys 162 0.20% 99.96% # number of callpals executed system.cpu1.kern.callpal_imb 33 0.04% 100.00% # number of callpals executed system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 88247 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 2815 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 78243 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 30463 38.93% 38.93% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_22 2001 2.56% 41.49% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_30 572 0.73% 42.22% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 45207 57.78% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 61005 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 29502 48.36% 48.36% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_22 2001 3.28% 51.64% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_30 572 0.94% 52.58% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 28930 47.42% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 3977363084 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 3855395406 96.93% 96.93% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 1873360 0.05% 96.98% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 1461344 0.04% 97.02% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 118632974 2.98% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used 0.779686 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_0 0.968454 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.hwrei 87377 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 2792 # number of quiesce instructions executed +system.cpu1.kern.ipl_count 77476 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 30110 38.86% 38.86% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_22 2002 2.58% 41.45% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_30 566 0.73% 42.18% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_31 44798 57.82% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 60300 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 29149 48.34% 48.34% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_22 2002 3.32% 51.66% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_30 566 0.94% 52.60% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_31 28583 47.40% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 3979354976 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 3857760682 96.94% 96.94% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 1872502 0.05% 96.99% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_30 1446416 0.04% 97.03% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 118275376 2.97% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used 0.778306 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_0 0.968084 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.639945 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good_kernel 1058 -system.cpu1.kern.mode_good_user 562 -system.cpu1.kern.mode_good_idle 496 -system.cpu1.kern.mode_switch_kernel 2397 # number of protection mode switches -system.cpu1.kern.mode_switch_user 562 # number of protection mode switches -system.cpu1.kern.mode_switch_idle 3035 # number of protection mode switches -system.cpu1.kern.mode_switch_good 0.353020 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.441385 # fraction of useful protection mode switches +system.cpu1.kern.ipl_used_31 0.638042 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good_kernel 1051 +system.cpu1.kern.mode_good_user 561 +system.cpu1.kern.mode_good_idle 490 +system.cpu1.kern.mode_switch_kernel 2388 # number of protection mode switches +system.cpu1.kern.mode_switch_user 561 # number of protection mode switches +system.cpu1.kern.mode_switch_idle 3025 # number of protection mode switches +system.cpu1.kern.mode_switch_good 0.351858 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.440117 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_idle 0.163427 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 64042452 1.61% 1.61% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 5753306 0.14% 1.75% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 3907567318 98.25% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2290 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good_idle 0.161983 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks_kernel 62784640 1.58% 1.58% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 5748262 0.14% 1.72% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 3910822066 98.28% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2277 # number of times the context was actually changed system.cpu1.kern.syscall 110 # number of syscalls executed system.cpu1.kern.syscall_2 1 0.91% 0.91% # number of syscalls executed system.cpu1.kern.syscall_3 12 10.91% 11.82% # number of syscalls executed @@ -213,10 +213,10 @@ system.cpu1.kern.syscall_90 1 0.91% 95.45% # nu system.cpu1.kern.syscall_92 2 1.82% 97.27% # number of syscalls executed system.cpu1.kern.syscall_132 2 1.82% 99.09% # number of syscalls executed system.cpu1.kern.syscall_144 1 0.91% 100.00% # number of syscalls executed -system.cpu1.not_idle_fraction 0.025425 # Percentage of non-idle cycles -system.cpu1.numCycles 3977364868 # number of cpu cycles simulated -system.cpu1.num_insts 14898470 # Number of instructions executed -system.cpu1.num_refs 4770918 # Number of memory references +system.cpu1.not_idle_fraction 0.025095 # Percentage of non-idle cycles +system.cpu1.numCycles 3979356760 # number of cpu cycles simulated +system.cpu1.num_insts 14708820 # Number of instructions executed +system.cpu1.num_refs 4709061 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt index 7947c3d76..88a94edf5 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt @@ -1,84 +1,84 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 374146 # Simulator instruction rate (inst/s) -host_mem_usage 249416 # Number of bytes of host memory used -host_seconds 160.59 # Real time elapsed on the host -host_tick_rate 24179677 # Simulator tick rate (ticks/s) +host_inst_rate 261150 # Simulator instruction rate (inst/s) +host_mem_usage 193084 # Number of bytes of host memory used +host_seconds 230.08 # Real time elapsed on the host +host_tick_rate 16884971 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 60085523 # Number of instructions simulated -sim_seconds 1.941556 # Number of seconds simulated -sim_ticks 3883112324 # Number of ticks simulated -system.cpu.dtb.accesses 1020793 # DTB accesses +sim_insts 60085806 # Number of instructions simulated +sim_seconds 1.942464 # Number of seconds simulated +sim_ticks 3884928812 # Number of ticks simulated +system.cpu.dtb.accesses 1020801 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 16070719 # DTB hits -system.cpu.dtb.misses 11472 # DTB misses -system.cpu.dtb.read_accesses 728862 # DTB read accesses +system.cpu.dtb.hits 16070687 # DTB hits +system.cpu.dtb.misses 11476 # DTB misses +system.cpu.dtb.read_accesses 728869 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 9714788 # DTB read hits -system.cpu.dtb.read_misses 10330 # DTB read misses -system.cpu.dtb.write_accesses 291931 # DTB write accesses +system.cpu.dtb.read_hits 9714773 # DTB read hits +system.cpu.dtb.read_misses 10333 # DTB read misses +system.cpu.dtb.write_accesses 291932 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_hits 6355931 # DTB write hits -system.cpu.dtb.write_misses 1142 # DTB write misses -system.cpu.idle_fraction 0.921464 # Percentage of idle cycles -system.cpu.itb.accesses 4985828 # ITB accesses +system.cpu.dtb.write_hits 6355914 # DTB write hits +system.cpu.dtb.write_misses 1143 # DTB write misses +system.cpu.idle_fraction 0.921526 # Percentage of idle cycles +system.cpu.itb.accesses 4986026 # ITB accesses system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 4980818 # ITB hits +system.cpu.itb.hits 4981016 # ITB hits system.cpu.itb.misses 5010 # ITB misses -system.cpu.kern.callpal 193475 # number of callpals executed +system.cpu.kern.callpal 193489 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_swpctx 4148 2.14% 2.15% # number of callpals executed +system.cpu.kern.callpal_swpctx 4146 2.14% 2.14% # number of callpals executed system.cpu.kern.callpal_tbi 54 0.03% 2.17% # number of callpals executed system.cpu.kern.callpal_wrent 7 0.00% 2.18% # number of callpals executed -system.cpu.kern.callpal_swpipl 176501 91.23% 93.40% # number of callpals executed -system.cpu.kern.callpal_rdps 6860 3.55% 96.95% # number of callpals executed +system.cpu.kern.callpal_swpipl 176515 91.23% 93.40% # number of callpals executed +system.cpu.kern.callpal_rdps 6861 3.55% 96.95% # number of callpals executed system.cpu.kern.callpal_wrkgp 1 0.00% 96.95% # number of callpals executed system.cpu.kern.callpal_wrusp 7 0.00% 96.95% # number of callpals executed system.cpu.kern.callpal_rdusp 9 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal_whami 2 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal_rti 5186 2.68% 99.64% # number of callpals executed +system.cpu.kern.callpal_rti 5187 2.68% 99.64% # number of callpals executed system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 212602 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6154 # number of quiesce instructions executed -system.cpu.kern.ipl_count 183780 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 75067 40.85% 40.85% # number of times we switched to this ipl +system.cpu.kern.inst.hwrei 212621 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6152 # number of quiesce instructions executed +system.cpu.kern.ipl_count 183796 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 75070 40.84% 40.84% # number of times we switched to this ipl system.cpu.kern.ipl_count_21 131 0.07% 40.92% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 1961 1.07% 41.98% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 106621 58.02% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 149492 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 73700 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count_22 1962 1.07% 41.98% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 106633 58.02% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 149499 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 73703 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_21 131 0.09% 49.39% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 1961 1.31% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 73700 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 3883110540 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 3755984220 96.73% 96.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_good_22 1962 1.31% 50.70% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_31 73703 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 3884927028 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 3757862392 96.73% 96.73% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks_21 112456 0.00% 96.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 918754 0.02% 96.75% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 126095110 3.25% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used 0.813429 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_ticks_22 918216 0.02% 96.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 126033964 3.24% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used 0.813396 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_0 0.981790 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.691233 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1897 -system.cpu.kern.mode_good_user 1742 -system.cpu.kern.mode_good_idle 155 -system.cpu.kern.mode_switch_kernel 5935 # number of protection mode switches -system.cpu.kern.mode_switch_user 1742 # number of protection mode switches +system.cpu.kern.ipl_used_31 0.691184 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1898 +system.cpu.kern.mode_good_user 1744 +system.cpu.kern.mode_good_idle 154 +system.cpu.kern.mode_switch_kernel 5934 # number of protection mode switches +system.cpu.kern.mode_switch_user 1744 # number of protection mode switches system.cpu.kern.mode_switch_idle 2065 # number of protection mode switches -system.cpu.kern.mode_switch_good 0.389448 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.319629 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good 0.389613 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.319852 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_idle 0.075061 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 112876118 2.91% 2.91% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 15210360 0.39% 3.30% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 3755024054 96.70% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4149 # number of times the context was actually changed +system.cpu.kern.mode_switch_good_idle 0.074576 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks_kernel 112858396 2.91% 2.91% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 15210848 0.39% 3.30% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 3756857776 96.70% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4147 # number of times the context was actually changed system.cpu.kern.syscall 326 # number of syscalls executed system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed @@ -110,10 +110,10 @@ system.cpu.kern.syscall_98 2 0.61% 97.55% # nu system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed -system.cpu.not_idle_fraction 0.078536 # Percentage of non-idle cycles -system.cpu.numCycles 3883112324 # number of cpu cycles simulated -system.cpu.num_insts 60085523 # Number of instructions executed -system.cpu.num_refs 16318655 # Number of memory references +system.cpu.not_idle_fraction 0.078474 # Percentage of non-idle cycles +system.cpu.numCycles 3884928812 # number of cpu cycles simulated +system.cpu.num_insts 60085806 # Number of instructions executed +system.cpu.num_refs 16318611 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). From ee70d8cfc430e38b84945e8b9ea870585b98f87c Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 9 May 2007 12:01:31 -0400 Subject: [PATCH 48/68] bit_val was being used directly in the statement in return. If type B had fewer bits than last, bit_val << last would get the wrong answer. src/base/bitfield.hh: bit_val was being used directly in the statement in return. If type B had fewer bits than last, bit_val << last would get the wrong answer. --HG-- extra : convert_revision : cbc43ccd139f82ebbd65f30af5d05b87c4edac64 --- src/base/bitfield.hh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/base/bitfield.hh b/src/base/bitfield.hh index 69cce2245..518bad6b8 100644 --- a/src/base/bitfield.hh +++ b/src/base/bitfield.hh @@ -96,8 +96,9 @@ inline T insertBits(T val, int first, int last, B bit_val) { + T t_bit_val = bit_val; T bmask = mask(first - last + 1) << last; - return ((bit_val << last) & bmask) | (val & ~bmask); + return ((t_bit_val << last) & bmask) | (val & ~bmask); } /** From 37b45e3c8cb2aef57e1d5dd8efd46705b8d46c16 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 9 May 2007 15:37:46 -0400 Subject: [PATCH 49/68] fix the translating ports so it can add a page on a fault --HG-- extra : convert_revision : 56f6f2cbf4e92b7f2dd8c9453831fab86d83ef80 --- src/arch/sparc/process.cc | 1 + src/arch/x86/process.cc | 1 + src/cpu/thread_state.cc | 5 +-- src/mem/translating_port.cc | 17 ++++++--- src/mem/translating_port.hh | 13 ++++++- src/sim/faults.cc | 17 +-------- src/sim/process.cc | 27 ++++++++++++- src/sim/process.hh | 27 ++----------- src/sim/process_impl.hh | 75 +++++++++++++++++++++++++++++++++++++ 9 files changed, 134 insertions(+), 49 deletions(-) create mode 100644 src/sim/process_impl.hh diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc index e4774ab54..d595664a0 100644 --- a/src/arch/sparc/process.cc +++ b/src/arch/sparc/process.cc @@ -39,6 +39,7 @@ #include "base/misc.hh" #include "cpu/thread_context.hh" #include "mem/page_table.hh" +#include "sim/process_impl.hh" #include "mem/translating_port.hh" #include "sim/system.hh" diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc index e6d1e4921..af7494598 100644 --- a/src/arch/x86/process.cc +++ b/src/arch/x86/process.cc @@ -95,6 +95,7 @@ #include "cpu/thread_context.hh" #include "mem/page_table.hh" #include "mem/translating_port.hh" +#include "sim/process_impl.hh" #include "sim/system.hh" using namespace std; diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc index 4b65ca4b8..be8f822f2 100644 --- a/src/cpu/thread_state.cc +++ b/src/cpu/thread_state.cc @@ -169,9 +169,8 @@ ThreadState::getMemPort() return port; /* Use this port to for syscall emulation writes to memory. */ - port = new TranslatingPort(csprintf("%s-%d-funcport", - baseCpu->name(), tid), - process->pTable, false); + port = new TranslatingPort(csprintf("%s-%d-funcport", baseCpu->name(), tid), + process, TranslatingPort::NextPage); connectToMemFunc(port); diff --git a/src/mem/translating_port.cc b/src/mem/translating_port.cc index d2c854086..54de6625e 100644 --- a/src/mem/translating_port.cc +++ b/src/mem/translating_port.cc @@ -34,12 +34,14 @@ #include "mem/port.hh" #include "mem/translating_port.hh" #include "mem/page_table.hh" +#include "sim/process.hh" using namespace TheISA; TranslatingPort::TranslatingPort(const std::string &_name, - PageTable *p_table, bool alloc) - : FunctionalPort(_name), pTable(p_table), allocating(alloc) + Process *p, AllocType alloc) + : FunctionalPort(_name), pTable(p->pTable), process(p), + allocating(alloc) { } TranslatingPort::~TranslatingPort() @@ -81,13 +83,18 @@ TranslatingPort::tryWriteBlob(Addr addr, uint8_t *p, int size) for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) { if (!pTable->translate(gen.addr(), paddr)) { - if (allocating) { + if (allocating == Always) { pTable->allocate(roundDown(gen.addr(), VMPageSize), VMPageSize); - pTable->translate(gen.addr(), paddr); + } else if (allocating == NextPage) { + // check if we've accessed the next page on the stack + if (!process->checkAndAllocNextPage(gen.addr())) + panic("Page table fault when accessing virtual address %#x " + "during functional write\n", gen.addr()); } else { return false; } + pTable->translate(gen.addr(), paddr); } Port::writeBlob(paddr, p + prevSize, gen.size()); @@ -113,7 +120,7 @@ TranslatingPort::tryMemsetBlob(Addr addr, uint8_t val, int size) for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) { if (!pTable->translate(gen.addr(), paddr)) { - if (allocating) { + if (allocating == Always) { pTable->allocate(roundDown(gen.addr(), VMPageSize), VMPageSize); pTable->translate(gen.addr(), paddr); diff --git a/src/mem/translating_port.hh b/src/mem/translating_port.hh index 7354278ba..76c7947be 100644 --- a/src/mem/translating_port.hh +++ b/src/mem/translating_port.hh @@ -35,16 +35,25 @@ #include "mem/port.hh" class PageTable; +class Process; class TranslatingPort : public FunctionalPort { + public: + enum AllocType { + Always, + Never, + NextPage + }; + private: PageTable *pTable; - bool allocating; + Process *process; + AllocType allocating; public: TranslatingPort(const std::string &_name, - PageTable *p_table, bool alloc = false); + Process *p, AllocType alloc); virtual ~TranslatingPort(); bool tryReadBlob(Addr addr, uint8_t *p, int size); diff --git a/src/sim/faults.cc b/src/sim/faults.cc index b09bbc177..fe62874d7 100644 --- a/src/sim/faults.cc +++ b/src/sim/faults.cc @@ -61,21 +61,8 @@ void PageTableFault::invoke(ThreadContext *tc) { Process *p = tc->getProcessPtr(); - // We've accessed the next page of the stack, so extend the stack - // to cover it. - if(vaddr < p->stack_min && vaddr >= p->stack_min - TheISA::PageBytes) - { - p->stack_min -= TheISA::PageBytes; - if(p->stack_base - p->stack_min > 8*1024*1024) - fatal("Over max stack size for one thread\n"); - p->pTable->allocate(p->stack_min, TheISA::PageBytes); - warn("Increasing stack size by one page."); - } - // Otherwise, we have an unexpected page fault. Report that fact, - // and what address was accessed to cause the fault. - else - { + if (!p->checkAndAllocNextPage(vaddr)) panic("Page table fault when accessing virtual address %#x\n", vaddr); - } + } #endif diff --git a/src/sim/process.cc b/src/sim/process.cc index 68239fa52..8b273d591 100644 --- a/src/sim/process.cc +++ b/src/sim/process.cc @@ -47,6 +47,7 @@ #include "mem/translating_port.hh" #include "sim/builder.hh" #include "sim/process.hh" +#include "sim/process_impl.hh" #include "sim/stats.hh" #include "sim/syscall_emul.hh" #include "sim/system.hh" @@ -182,7 +183,8 @@ Process::startup() Port *mem_port; mem_port = system->physmem->getPort("functional"); - initVirtMem = new TranslatingPort("process init port", pTable, true); + initVirtMem = new TranslatingPort("process init port", this, + TranslatingPort::Always); mem_port->setPeer(initVirtMem); initVirtMem->setPeer(mem_port); } @@ -250,6 +252,29 @@ Process::sim_fd(int tgt_fd) return fd_map[tgt_fd]; } +bool +Process::checkAndAllocNextPage(Addr vaddr) +{ + // if this is an initial write we might not have + if (vaddr >= stack_min && vaddr < stack_base) { + pTable->allocate(roundDown(vaddr, VMPageSize), VMPageSize); + return true; + } + + // We've accessed the next page of the stack, so extend the stack + // to cover it. + if(vaddr < stack_min && vaddr >= stack_min - TheISA::PageBytes) + { + stack_min -= TheISA::PageBytes; + if(stack_base - stack_min > 8*1024*1024) + fatal("Over max stack size for one thread\n"); + pTable->allocate(stack_min, TheISA::PageBytes); + warn("Increasing stack size by one page."); + return true; + } + return false; +} + void Process::serialize(std::ostream &os) { diff --git a/src/sim/process.hh b/src/sim/process.hh index dd64fa607..fa46b9c95 100644 --- a/src/sim/process.hh +++ b/src/sim/process.hh @@ -45,7 +45,6 @@ #include #include "base/statistics.hh" -#include "mem/translating_port.hh" #include "sim/host.hh" #include "sim/sim_object.hh" @@ -60,28 +59,6 @@ namespace TheISA class RemoteGDB; } -//This needs to be templated for cases where 32 bit pointers are needed. -template -void -copyStringArray(std::vector &strings, - AddrType array_ptr, AddrType data_ptr, - TranslatingPort* memPort) -{ - AddrType data_ptr_swap; - for (int i = 0; i < strings.size(); ++i) { - data_ptr_swap = htog(data_ptr); - memPort->writeBlob(array_ptr, (uint8_t*)&data_ptr_swap, - sizeof(AddrType)); - memPort->writeString(data_ptr, strings[i].c_str()); - array_ptr += sizeof(AddrType); - data_ptr += strings[i].size() + 1; - } - // add NULL terminator - data_ptr = 0; - - memPort->writeBlob(array_ptr, (uint8_t*)&data_ptr, sizeof(AddrType)); -} - class Process : public SimObject { public: @@ -194,6 +171,10 @@ class Process : public SimObject virtual void syscall(int64_t callnum, ThreadContext *tc) = 0; + // check if the this addr is on the next available page and allocate it + // if it's not we'll panic + bool checkAndAllocNextPage(Addr vaddr); + void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); }; diff --git a/src/sim/process_impl.hh b/src/sim/process_impl.hh new file mode 100644 index 000000000..a3519fe39 --- /dev/null +++ b/src/sim/process_impl.hh @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2001-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + * Steve Reinhardt + */ + +#ifndef __SIM_PROCESS_IMPL_HH__ +#define __SIM_PROCESS_IMPL_HH__ + +// +// The purpose of this code is to fake the loader & syscall mechanism +// when there's no OS: thus there's no reason to use it in FULL_SYSTEM +// mode when we do have an OS. +// +#include "config/full_system.hh" + +#if !FULL_SYSTEM + +#include +#include + +#include "mem/translating_port.hh" + + +//This needs to be templated for cases where 32 bit pointers are needed. +template +void +copyStringArray(std::vector &strings, + AddrType array_ptr, AddrType data_ptr, + TranslatingPort* memPort) +{ + AddrType data_ptr_swap; + for (int i = 0; i < strings.size(); ++i) { + data_ptr_swap = htog(data_ptr); + memPort->writeBlob(array_ptr, (uint8_t*)&data_ptr_swap, + sizeof(AddrType)); + memPort->writeString(data_ptr, strings[i].c_str()); + array_ptr += sizeof(AddrType); + data_ptr += strings[i].size() + 1; + } + // add NULL terminator + data_ptr = 0; + + memPort->writeBlob(array_ptr, (uint8_t*)&data_ptr, sizeof(AddrType)); +} + + +#endif // !FULL_SYSTEM + +#endif From 3c608bf76535dc1f08a9563b417b5c6fadeab3ff Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 9 May 2007 18:20:24 -0400 Subject: [PATCH 50/68] add a backoff algorithm when nacks are received by devices add seperate response buffers and request queue sizes in bus bridge add delay to respond to a nack in the bus bridge src/dev/i8254xGBe.cc: src/dev/ide_ctrl.cc: src/dev/ns_gige.cc: src/dev/pcidev.hh: src/dev/sinic.cc: add backoff delay parameters src/dev/io_device.cc: src/dev/io_device.hh: add a backoff algorithm when nacks are received. src/mem/bridge.cc: src/mem/bridge.hh: add seperate response buffers and request queue sizes add a new parameters to specify how long before a nack in ready to go after a packet that needs to be nacked is received src/mem/cache/cache_impl.hh: assert on the src/mem/tport.cc: add a friendly assert to make sure the packet was inserted into the list --HG-- extra : convert_revision : 3595ad932015a4ce2bb72772da7850ad91bd09b1 --- src/dev/i8254xGBe.cc | 6 ++ src/dev/ide_ctrl.cc | 6 ++ src/dev/io_device.cc | 90 ++++++++++++++++++++++----- src/dev/io_device.hh | 25 +++++++- src/dev/ns_gige.cc | 6 ++ src/dev/pcidev.hh | 2 +- src/dev/sinic.cc | 6 ++ src/mem/bridge.cc | 118 +++++++++++++++++++++++++----------- src/mem/bridge.hh | 43 ++++++++++--- src/mem/cache/cache_impl.hh | 8 +++ src/mem/tport.cc | 1 + 11 files changed, 250 insertions(+), 61 deletions(-) diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc index 6acd06132..e54249dee 100644 --- a/src/dev/i8254xGBe.cc +++ b/src/dev/i8254xGBe.cc @@ -1460,6 +1460,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(IGbE) SimObjectParam system; SimObjectParam platform; + Param min_backoff_delay; + Param max_backoff_delay; SimObjectParam configdata; Param pci_bus; Param pci_dev; @@ -1481,6 +1483,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(IGbE) INIT_PARAM(system, "System pointer"), INIT_PARAM(platform, "Platform pointer"), + INIT_PARAM(min_backoff_delay, "Minimum delay after receving a nack packed"), + INIT_PARAM(max_backoff_delay, "Maximum delay after receving a nack packed"), INIT_PARAM(configdata, "PCI Config data"), INIT_PARAM(pci_bus, "PCI bus ID"), INIT_PARAM(pci_dev, "PCI device number"), @@ -1505,6 +1509,8 @@ CREATE_SIM_OBJECT(IGbE) params->name = getInstanceName(); params->platform = platform; params->system = system; + params->min_backoff_delay = min_backoff_delay; + params->max_backoff_delay = max_backoff_delay; params->configData = configdata; params->busNum = pci_bus; params->deviceNum = pci_dev; diff --git a/src/dev/ide_ctrl.cc b/src/dev/ide_ctrl.cc index 1afad529f..921ba1cd0 100644 --- a/src/dev/ide_ctrl.cc +++ b/src/dev/ide_ctrl.cc @@ -751,6 +751,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController) SimObjectParam system; SimObjectParam platform; + Param min_backoff_delay; + Param max_backoff_delay; SimObjectParam configdata; Param pci_bus; Param pci_dev; @@ -765,6 +767,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController) INIT_PARAM(system, "System pointer"), INIT_PARAM(platform, "Platform pointer"), + INIT_PARAM(min_backoff_delay, "Minimum delay after receving a nack packed"), + INIT_PARAM(max_backoff_delay, "Maximum delay after receving a nack packed"), INIT_PARAM(configdata, "PCI Config data"), INIT_PARAM(pci_bus, "PCI bus ID"), INIT_PARAM(pci_dev, "PCI device number"), @@ -781,6 +785,8 @@ CREATE_SIM_OBJECT(IdeController) params->name = getInstanceName(); params->platform = platform; params->system = system; + params->min_backoff_delay = min_backoff_delay; + params->max_backoff_delay = max_backoff_delay; params->configData = configdata; params->busNum = pci_bus; params->deviceNum = pci_dev; diff --git a/src/dev/io_device.cc b/src/dev/io_device.cc index a1285fefc..9384c4b92 100644 --- a/src/dev/io_device.cc +++ b/src/dev/io_device.cc @@ -93,7 +93,8 @@ BasicPioDevice::addressRanges(AddrRangeList &range_list) DmaPort::DmaPort(DmaDevice *dev, System *s) : Port(dev->name() + "-dmaport", dev), device(dev), sys(s), - pendingCount(0), actionInProgress(0), drainEvent(NULL) + pendingCount(0), actionInProgress(0), drainEvent(NULL), + backoffTime(0), inRetry(false), backoffEvent(this) { } bool @@ -104,12 +105,27 @@ DmaPort::recvTiming(PacketPtr pkt) if (pkt->result == Packet::Nacked) { DPRINTF(DMA, "Received nacked Pkt %#x with State: %#x Addr: %#x\n", pkt, pkt->senderState, pkt->getAddr()); + + if (backoffTime < device->minBackoffDelay) + backoffTime = device->minBackoffDelay; + else if (backoffTime < device->maxBackoffDelay) + backoffTime <<= 1; + + if (backoffEvent.scheduled()) + backoffEvent.reschedule(curTick + backoffTime); + else + backoffEvent.schedule(curTick + backoffTime); + + DPRINTF(DMA, "Backoff time set to %d ticks\n", backoffTime); + pkt->reinitNacked(); - sendDma(pkt, true); + queueDma(pkt, true); } else if (pkt->senderState) { DmaReqState *state; - DPRINTF(DMA, "Received response Pkt %#x with State: %#x Addr: %#x\n", - pkt, pkt->senderState, pkt->getAddr()); + backoffTime >>= 2; + + DPRINTF(DMA, "Received response Pkt %#x with State: %#x Addr: %#x size: %#x\n", + pkt, pkt->senderState, pkt->getAddr(), pkt->req->getSize()); state = dynamic_cast(pkt->senderState); pendingCount--; @@ -117,6 +133,7 @@ DmaPort::recvTiming(PacketPtr pkt) assert(state); state->numBytes += pkt->req->getSize(); + assert(state->totBytes >= state->numBytes); if (state->totBytes == state->numBytes) { state->completionEvent->process(); delete state; @@ -136,7 +153,8 @@ DmaPort::recvTiming(PacketPtr pkt) } DmaDevice::DmaDevice(Params *p) - : PioDevice(p), dmaPort(NULL) + : PioDevice(p), dmaPort(NULL), minBackoffDelay(p->min_backoff_delay), + maxBackoffDelay(p->max_backoff_delay) { } @@ -165,19 +183,31 @@ DmaPort::drain(Event *de) void DmaPort::recvRetry() { + assert(transmitList.size()); PacketPtr pkt = transmitList.front(); bool result = true; - while (result && transmitList.size()) { + do { DPRINTF(DMA, "Retry on Packet %#x with senderState: %#x\n", pkt, pkt->senderState); result = sendTiming(pkt); if (result) { DPRINTF(DMA, "-- Done\n"); transmitList.pop_front(); + inRetry = false; } else { + inRetry = true; DPRINTF(DMA, "-- Failed, queued\n"); } + } while (!backoffTime && result && transmitList.size()); + + if (transmitList.size() && backoffTime && !inRetry) { + DPRINTF(DMA, "Scheduling backoff for %d\n", curTick+backoffTime); + if (!backoffEvent.scheduled()) + backoffEvent.schedule(backoffTime+curTick); } + DPRINTF(DMA, "TransmitList: %d, backoffTime: %d inRetry: %d es: %d\n", + transmitList.size(), backoffTime, inRetry, + backoffEvent.scheduled()); } @@ -204,33 +234,61 @@ DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event, assert(pendingCount >= 0); pendingCount++; - sendDma(pkt); + queueDma(pkt); } } +void +DmaPort::queueDma(PacketPtr pkt, bool front) +{ + + if (front) + transmitList.push_front(pkt); + else + transmitList.push_back(pkt); + sendDma(); +} + void -DmaPort::sendDma(PacketPtr pkt, bool front) +DmaPort::sendDma() { // some kind of selction between access methods // more work is going to have to be done to make // switching actually work + assert(transmitList.size()); + PacketPtr pkt = transmitList.front(); System::MemoryMode state = sys->getMemoryMode(); if (state == System::Timing) { + if (backoffEvent.scheduled() || inRetry) { + DPRINTF(DMA, "Can't send immediately, waiting for retry or backoff timer\n"); + return; + } + DPRINTF(DMA, "Attempting to send Packet %#x with addr: %#x\n", pkt, pkt->getAddr()); - if (transmitList.size() || !sendTiming(pkt)) { - if (front) - transmitList.push_front(pkt); - else - transmitList.push_back(pkt); - DPRINTF(DMA, "-- Failed: queued\n"); - } else { - DPRINTF(DMA, "-- Done\n"); + + bool result; + do { + result = sendTiming(pkt); + if (result) { + transmitList.pop_front(); + DPRINTF(DMA, "-- Done\n"); + } else { + inRetry = true; + DPRINTF(DMA, "-- Failed: queued\n"); + } + } while (result && !backoffTime && transmitList.size()); + + if (transmitList.size() && backoffTime && !inRetry && + !backoffEvent.scheduled()) { + backoffEvent.schedule(backoffTime+curTick); } } else if (state == System::Atomic) { + transmitList.pop_front(); + Tick lat; lat = sendAtomic(pkt); assert(pkt->senderState); diff --git a/src/dev/io_device.hh b/src/dev/io_device.hh index cd7a5296a..bd150bfe4 100644 --- a/src/dev/io_device.hh +++ b/src/dev/io_device.hh @@ -107,6 +107,14 @@ class DmaPort : public Port * here.*/ Event *drainEvent; + /** time to wait between sending another packet, increases as NACKs are + * recived, decreases as responses are recived. */ + Tick backoffTime; + + /** If the port is currently waiting for a retry before it can send whatever + * it is that it's sending. */ + bool inRetry; + virtual bool recvTiming(PacketPtr pkt); virtual Tick recvAtomic(PacketPtr pkt) { panic("dma port shouldn't be used for pio access."); M5_DUMMY_RETURN } @@ -122,7 +130,11 @@ class DmaPort : public Port AddrRangeList &snoop) { resp.clear(); snoop.clear(); } - void sendDma(PacketPtr pkt, bool front = false); + void queueDma(PacketPtr pkt, bool front = false); + void sendDma(); + + /** event to give us a kick every time we backoff time is reached. */ + EventWrapper backoffEvent; public: DmaPort(DmaDevice *dev, System *s); @@ -249,8 +261,17 @@ class BasicPioDevice : public PioDevice class DmaDevice : public PioDevice { - protected: + public: + struct Params : public PioDevice::Params + { + Tick min_backoff_delay; + Tick max_backoff_delay; + }; + + protected: DmaPort *dmaPort; + Tick minBackoffDelay; + Tick maxBackoffDelay; public: DmaDevice(Params *p); diff --git a/src/dev/ns_gige.cc b/src/dev/ns_gige.cc index 86f56b62e..bec1fb848 100644 --- a/src/dev/ns_gige.cc +++ b/src/dev/ns_gige.cc @@ -2812,6 +2812,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE) SimObjectParam system; SimObjectParam platform; + Param min_backoff_delay; + Param max_backoff_delay; SimObjectParam configdata; Param pci_bus; Param pci_dev; @@ -2846,6 +2848,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE) INIT_PARAM(system, "System pointer"), INIT_PARAM(platform, "Platform pointer"), + INIT_PARAM(min_backoff_delay, "Minimum delay after receving a nack packed"), + INIT_PARAM(max_backoff_delay, "Maximum delay after receving a nack packed"), INIT_PARAM(configdata, "PCI Config data"), INIT_PARAM(pci_bus, "PCI bus ID"), INIT_PARAM(pci_dev, "PCI device number"), @@ -2884,6 +2888,8 @@ CREATE_SIM_OBJECT(NSGigE) params->name = getInstanceName(); params->platform = platform; params->system = system; + params->min_backoff_delay = min_backoff_delay; + params->max_backoff_delay = max_backoff_delay; params->configData = configdata; params->busNum = pci_bus; params->deviceNum = pci_dev; diff --git a/src/dev/pcidev.hh b/src/dev/pcidev.hh index 56e3ffb4a..5044e2932 100644 --- a/src/dev/pcidev.hh +++ b/src/dev/pcidev.hh @@ -105,7 +105,7 @@ class PciDev : public DmaDevice }; public: - struct Params : public PioDevice::Params + struct Params : public DmaDevice::Params { /** * A pointer to the object that contains the first 64 bytes of diff --git a/src/dev/sinic.cc b/src/dev/sinic.cc index f61c161aa..1a72652da 100644 --- a/src/dev/sinic.cc +++ b/src/dev/sinic.cc @@ -1635,6 +1635,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS_WNS(Sinic, SinicDevice) SimObjectParam system; SimObjectParam platform; + Param min_backoff_delay; + Param max_backoff_delay; SimObjectParam configdata; Param pci_bus; Param pci_dev; @@ -1678,6 +1680,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS_WNS(Sinic, SinicDevice) INIT_PARAM(system, "System pointer"), INIT_PARAM(platform, "Platform pointer"), + INIT_PARAM(min_backoff_delay, "Minimum delay after receving a nack packed"), + INIT_PARAM(max_backoff_delay, "Maximum delay after receving a nack packed"), INIT_PARAM(configdata, "PCI Config data"), INIT_PARAM(pci_bus, "PCI bus ID"), INIT_PARAM(pci_dev, "PCI device number"), @@ -1723,6 +1727,8 @@ CREATE_SIM_OBJECT_WNS(Sinic, SinicDevice) params->name = getInstanceName(); params->platform = platform; params->system = system; + params->min_backoff_delay = min_backoff_delay; + params->max_backoff_delay = max_backoff_delay; params->configData = configdata; params->busNum = pci_bus; params->deviceNum = pci_dev; diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc index e7d52b178..e89473be3 100644 --- a/src/mem/bridge.cc +++ b/src/mem/bridge.cc @@ -43,22 +43,22 @@ Bridge::BridgePort::BridgePort(const std::string &_name, Bridge *_bridge, BridgePort *_otherPort, - int _delay, int _queueLimit, - bool fix_partial_write) + int _delay, int _nack_delay, int _req_limit, + int _resp_limit, bool fix_partial_write) : Port(_name), bridge(_bridge), otherPort(_otherPort), - delay(_delay), fixPartialWrite(fix_partial_write), - outstandingResponses(0), queuedRequests(0), - queueLimit(_queueLimit), sendEvent(this) + delay(_delay), nackDelay(_nack_delay), fixPartialWrite(fix_partial_write), + outstandingResponses(0), queuedRequests(0), inRetry(false), + reqQueueLimit(_req_limit), respQueueLimit(_resp_limit), sendEvent(this) { } -Bridge::Bridge(const std::string &n, int qsa, int qsb, - Tick _delay, int write_ack, bool fix_partial_write_a, - bool fix_partial_write_b) - : MemObject(n), - portA(n + "-portA", this, &portB, _delay, qsa, fix_partial_write_a), - portB(n + "-portB", this, &portA, _delay, qsa, fix_partial_write_b), - ackWrites(write_ack) +Bridge::Bridge(Params *p) + : MemObject(p->name), + portA(p->name + "-portA", this, &portB, p->delay, p->nack_delay, + p->req_size_a, p->resp_size_a, p->fix_partial_write_a), + portB(p->name + "-portB", this, &portA, p->delay, p->nack_delay, + p->req_size_b, p->resp_size_b, p->fix_partial_write_b), + ackWrites(p->write_ack), _params(p) { if (ackWrites) panic("No support for acknowledging writes\n"); @@ -94,11 +94,17 @@ Bridge::init() } bool -Bridge::BridgePort::queueFull() +Bridge::BridgePort::respQueueFull() { - // use >= here because sendQueue could get larger because of - // nacks getting inserted - return queuedRequests + outstandingResponses >= queueLimit; + assert(outstandingResponses >= 0 && outstandingResponses <= respQueueLimit); + return outstandingResponses >= respQueueLimit; +} + +bool +Bridge::BridgePort::reqQueueFull() +{ + assert(queuedRequests >= 0 && queuedRequests <= reqQueueLimit); + return queuedRequests >= reqQueueLimit; } /** Function called by the port when the bus is receiving a Timing @@ -113,14 +119,14 @@ Bridge::BridgePort::recvTiming(PacketPtr pkt) DPRINTF(BusBridge, "recvTiming: src %d dest %d addr 0x%x\n", pkt->getSrc(), pkt->getDest(), pkt->getAddr()); - if (pkt->isRequest() && otherPort->queueFull()) { + if (pkt->isRequest() && otherPort->reqQueueFull()) { DPRINTF(BusBridge, "Remote queue full, nacking\n"); nackRequest(pkt); return true; } if (pkt->needsResponse() && pkt->result != Packet::Nacked) - if (queueFull()) { + if (respQueueFull()) { DPRINTF(BusBridge, "Local queue full, no space for response, nacking\n"); DPRINTF(BusBridge, "queue size: %d outreq: %d outstanding resp: %d\n", sendQueue.size(), queuedRequests, outstandingResponses); @@ -144,12 +150,41 @@ Bridge::BridgePort::nackRequest(PacketPtr pkt) pkt->setDest(pkt->getSrc()); //put it on the list to send - Tick readyTime = curTick + delay; + Tick readyTime = curTick + nackDelay; PacketBuffer *buf = new PacketBuffer(pkt, readyTime, true); + + // nothing on the list, add it and we're done if (sendQueue.empty()) { + assert(!sendEvent.scheduled()); sendEvent.schedule(readyTime); + sendQueue.push_back(buf); + return; } - sendQueue.push_back(buf); + + assert(sendEvent.scheduled() || inRetry); + + // does it go at the end? + if (readyTime >= sendQueue.back()->ready) { + sendQueue.push_back(buf); + return; + } + + // ok, somewhere in the middle, fun + std::list::iterator i = sendQueue.begin(); + std::list::iterator end = sendQueue.end(); + std::list::iterator begin = sendQueue.begin(); + bool done = false; + + while (i != end && !done) { + if (readyTime < (*i)->ready) { + if (i == begin) + sendEvent.reschedule(readyTime); + sendQueue.insert(i,buf); + done = true; + } + i++; + } + assert(done); } @@ -199,7 +234,6 @@ Bridge::BridgePort::trySend() { assert(!sendQueue.empty()); - bool was_full = queueFull(); int pbs = peerBlockSize(); PacketBuffer *buf = sendQueue.front(); @@ -245,15 +279,10 @@ Bridge::BridgePort::trySend() DPRINTF(BusBridge, "Scheduling next send\n"); sendEvent.schedule(std::max(buf->ready, curTick + 1)); } - // Let things start sending again - if (was_full && !queueFull()) { - DPRINTF(BusBridge, "Queue was full, sending retry\n"); - otherPort->sendRetry(); - } - } else { DPRINTF(BusBridge, " unsuccessful\n"); buf->undoPartialWriteFix(); + inRetry = true; } DPRINTF(BusBridge, "trySend: queue size: %d outreq: %d outstanding resp: %d\n", sendQueue.size(), queuedRequests, outstandingResponses); @@ -263,7 +292,12 @@ Bridge::BridgePort::trySend() void Bridge::BridgePort::recvRetry() { - trySend(); + inRetry = false; + Tick nextReady = sendQueue.front()->ready; + if (nextReady <= curTick) + trySend(); + else + sendEvent.schedule(nextReady); } /** Function called by the port when the bus is receiving a Atomic @@ -309,9 +343,12 @@ Bridge::BridgePort::getDeviceAddressRanges(AddrRangeList &resp, BEGIN_DECLARE_SIM_OBJECT_PARAMS(Bridge) - Param queue_size_a; - Param queue_size_b; + Param req_size_a; + Param req_size_b; + Param resp_size_a; + Param resp_size_b; Param delay; + Param nack_delay; Param write_ack; Param fix_partial_write_a; Param fix_partial_write_b; @@ -320,9 +357,12 @@ END_DECLARE_SIM_OBJECT_PARAMS(Bridge) BEGIN_INIT_SIM_OBJECT_PARAMS(Bridge) - INIT_PARAM(queue_size_a, "The size of the queue for data coming into side a"), - INIT_PARAM(queue_size_b, "The size of the queue for data coming into side b"), + INIT_PARAM(req_size_a, "The size of the queue for requests coming into side a"), + INIT_PARAM(req_size_b, "The size of the queue for requests coming into side b"), + INIT_PARAM(resp_size_a, "The size of the queue for responses coming into side a"), + INIT_PARAM(resp_size_b, "The size of the queue for responses coming into side b"), INIT_PARAM(delay, "The miminum delay to cross this bridge"), + INIT_PARAM(nack_delay, "The minimum delay to nack a packet"), INIT_PARAM(write_ack, "Acknowledge any writes that are received."), INIT_PARAM(fix_partial_write_a, "Fixup any partial block writes that are received"), INIT_PARAM(fix_partial_write_b, "Fixup any partial block writes that are received") @@ -331,8 +371,18 @@ END_INIT_SIM_OBJECT_PARAMS(Bridge) CREATE_SIM_OBJECT(Bridge) { - return new Bridge(getInstanceName(), queue_size_a, queue_size_b, delay, - write_ack, fix_partial_write_a, fix_partial_write_b); + Bridge::Params *p = new Bridge::Params; + p->name = getInstanceName(); + p->req_size_a = req_size_a; + p->req_size_b = req_size_b; + p->resp_size_a = resp_size_a; + p->resp_size_b = resp_size_b; + p->delay = delay; + p->nack_delay = nack_delay; + p->write_ack = write_ack; + p->fix_partial_write_a = fix_partial_write_a; + p->fix_partial_write_b = fix_partial_write_b; + return new Bridge(p); } REGISTER_SIM_OBJECT("Bridge", Bridge) diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh index 1fa9cdffc..cb5a6baed 100644 --- a/src/mem/bridge.hh +++ b/src/mem/bridge.hh @@ -66,6 +66,9 @@ class Bridge : public MemObject /** Minimum delay though this bridge. */ Tick delay; + /** Min delay to respond to a nack. */ + Tick nackDelay; + bool fixPartialWrite; class PacketBuffer : public Packet::SenderState { @@ -149,13 +152,20 @@ class Bridge : public MemObject int outstandingResponses; int queuedRequests; + /** If we're waiting for a retry to happen.*/ + bool inRetry; + /** Max queue size for outbound packets */ - int queueLimit; + int reqQueueLimit; + + /** Max queue size for reserved responses. */ + int respQueueLimit; /** * Is this side blocked from accepting outbound packets? */ - bool queueFull(); + bool respQueueFull(); + bool reqQueueFull(); void queueForSendTiming(PacketPtr pkt); @@ -186,11 +196,10 @@ class Bridge : public MemObject SendEvent sendEvent; public: - /** Constructor for the BusPort.*/ - BridgePort(const std::string &_name, - Bridge *_bridge, BridgePort *_otherPort, - int _delay, int _queueLimit, bool fix_partial_write); + BridgePort(const std::string &_name, Bridge *_bridge, + BridgePort *_otherPort, int _delay, int _nack_delay, + int _req_limit, int _resp_limit, bool fix_partial_write); protected: @@ -226,14 +235,32 @@ class Bridge : public MemObject bool ackWrites; public: + struct Params + { + std::string name; + int req_size_a; + int req_size_b; + int resp_size_a; + int resp_size_b; + Tick delay; + Tick nack_delay; + bool write_ack; + bool fix_partial_write_a; + bool fix_partial_write_b; + }; + + protected: + Params *_params; + + public: + const Params *params() const { return _params; } /** A function used to return the port associated with this bus object. */ virtual Port *getPort(const std::string &if_name, int idx = -1); virtual void init(); - Bridge(const std::string &n, int qsa, int qsb, Tick _delay, int write_ack, - bool fix_partial_write_a, bool fix_partial_write_b); + Bridge(Params *p); }; #endif //__MEM_BUS_HH__ diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 0a528aa5d..c70f10151 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -1192,6 +1192,8 @@ template bool Cache::CpuSidePort::recvTiming(PacketPtr pkt) { + assert(pkt->result != Packet::Nacked); + if (!pkt->req->isUncacheable() && pkt->isInvalidate() && !pkt->isRead() && !pkt->isWrite()) { @@ -1249,6 +1251,12 @@ template bool Cache::MemSidePort::recvTiming(PacketPtr pkt) { + // this needs to be fixed so that the cache updates the mshr and sends the + // packet back out on the link, but it probably won't happen so until this + // gets fixed, just panic when it does + if (pkt->result == Packet::Nacked) + panic("Need to implement cache resending nacked packets!\n"); + if (pkt->isRequest() && blocked) { DPRINTF(Cache,"Scheduling a retry while blocked\n"); diff --git a/src/mem/tport.cc b/src/mem/tport.cc index b384a0444..9a4bd7967 100644 --- a/src/mem/tport.cc +++ b/src/mem/tport.cc @@ -128,6 +128,7 @@ SimpleTimingPort::sendTiming(PacketPtr pkt, Tick time) } i++; } + assert(done); } void From ff55888575af9e661697882736741ea6d4613303 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 9 May 2007 22:23:01 -0400 Subject: [PATCH 51/68] undo my previous bus change, it can make the bus deadlock.. so it still constantly reschedules itself --HG-- extra : convert_revision : b5ef1aa0a6a2e32bd775d2dbcad9cd9505ad9b78 --- src/mem/bus.cc | 23 +++++++++-------------- 1 file changed, 9 insertions(+), 14 deletions(-) diff --git a/src/mem/bus.cc b/src/mem/bus.cc index 6682ade55..95d4e2873 100644 --- a/src/mem/bus.cc +++ b/src/mem/bus.cc @@ -171,8 +171,9 @@ bool Bus::recvTiming(PacketPtr pkt) { Port *port; - DPRINTF(Bus, "recvTiming: packet src %d dest %d addr 0x%x cmd %s\n", - pkt->getSrc(), pkt->getDest(), pkt->getAddr(), pkt->cmdString()); + DPRINTF(Bus, "recvTiming: packet src %d dest %d addr 0x%x cmd %s result %d\n", + pkt->getSrc(), pkt->getDest(), pkt->getAddr(), pkt->cmdString(), + pkt->result); BusPort *pktPort; if (pkt->getSrc() == defaultId) @@ -272,20 +273,14 @@ Bus::recvRetry(int id) retryList.pop_front(); inRetry = false; - if (id != -1) { - //Bring tickNextIdle up to the present - while (tickNextIdle < curTick) - tickNextIdle += clock; - - //Burn a cycle for the missed grant. + //Bring tickNextIdle up to the present + while (tickNextIdle < curTick) tickNextIdle += clock; - if (!busIdle.scheduled()) { - busIdle.schedule(tickNextIdle); - } else { - busIdle.reschedule(tickNextIdle); - } - } // id != -1 + //Burn a cycle for the missed grant. + tickNextIdle += clock; + + busIdle.reschedule(tickNextIdle, true); } } //If we weren't able to drain before, we might be able to now. From 9dfbea68a204ca93ef9d20a13dd2fe7288121c75 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 9 May 2007 22:34:54 -0400 Subject: [PATCH 52/68] update for new reschedule semantics --HG-- extra : convert_revision : 8c18b2513d638f67cc096e7f1483b47390a374ca --- src/dev/i8254xGBe.cc | 16 ++++------------ src/dev/io_device.cc | 5 +---- src/dev/ns_gige.cc | 5 +---- src/dev/sinic.cc | 5 +---- src/sim/eventq.hh | 17 ++++++++++++----- src/sim/pseudo_inst.cc | 10 ++-------- 6 files changed, 21 insertions(+), 37 deletions(-) diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc index e54249dee..680e31656 100644 --- a/src/dev/i8254xGBe.cc +++ b/src/dev/i8254xGBe.cc @@ -727,12 +727,8 @@ IGbE::RxDescCache::pktComplete() if (igbe->regs.rdtr.delay()) { DPRINTF(EthernetSM, "RXS: Scheduling DTR for %d\n", igbe->regs.rdtr.delay() * igbe->intClock()); - if (igbe->rdtrEvent.scheduled()) - igbe->rdtrEvent.reschedule(curTick + igbe->regs.rdtr.delay() * - igbe->intClock()); - else - igbe->rdtrEvent.schedule(curTick + igbe->regs.rdtr.delay() * - igbe->intClock()); + igbe->rdtrEvent.reschedule(curTick + igbe->regs.rdtr.delay() * + igbe->intClock(),true); } if (igbe->regs.radv.idv() && igbe->regs.rdtr.delay()) { @@ -946,12 +942,8 @@ IGbE::TxDescCache::pktComplete() DPRINTF(EthernetDesc, "Descriptor had IDE set\n"); if (igbe->regs.tidv.idv()) { DPRINTF(EthernetDesc, "setting tidv\n"); - if (igbe->tidvEvent.scheduled()) - igbe->tidvEvent.reschedule(curTick + igbe->regs.tidv.idv() * - igbe->intClock()); - else - igbe->tidvEvent.schedule(curTick + igbe->regs.tidv.idv() * - igbe->intClock()); + igbe->tidvEvent.reschedule(curTick + igbe->regs.tidv.idv() * + igbe->intClock(), true); } if (igbe->regs.tadv.idv() && igbe->regs.tidv.idv()) { diff --git a/src/dev/io_device.cc b/src/dev/io_device.cc index 9384c4b92..d430ace72 100644 --- a/src/dev/io_device.cc +++ b/src/dev/io_device.cc @@ -111,10 +111,7 @@ DmaPort::recvTiming(PacketPtr pkt) else if (backoffTime < device->maxBackoffDelay) backoffTime <<= 1; - if (backoffEvent.scheduled()) - backoffEvent.reschedule(curTick + backoffTime); - else - backoffEvent.schedule(curTick + backoffTime); + backoffEvent.reschedule(curTick + backoffTime, true); DPRINTF(DMA, "Backoff time set to %d ticks\n", backoffTime); diff --git a/src/dev/ns_gige.cc b/src/dev/ns_gige.cc index bec1fb848..d9985f808 100644 --- a/src/dev/ns_gige.cc +++ b/src/dev/ns_gige.cc @@ -2310,10 +2310,7 @@ NSGigE::transferDone() DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n"); - if (txEvent.scheduled()) - txEvent.reschedule(curTick + cycles(1)); - else - txEvent.schedule(curTick + cycles(1)); + txEvent.reschedule(curTick + cycles(1), true); } bool diff --git a/src/dev/sinic.cc b/src/dev/sinic.cc index 1a72652da..420761620 100644 --- a/src/dev/sinic.cc +++ b/src/dev/sinic.cc @@ -1199,10 +1199,7 @@ Device::transferDone() DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n"); - if (txEvent.scheduled()) - txEvent.reschedule(curTick + cycles(1)); - else - txEvent.schedule(curTick + cycles(1)); + txEvent.reschedule(curTick + cycles(1), true); } bool diff --git a/src/sim/eventq.hh b/src/sim/eventq.hh index a57e9077e..974313968 100644 --- a/src/sim/eventq.hh +++ b/src/sim/eventq.hh @@ -210,7 +210,8 @@ class Event : public Serializable, public FastAlloc void schedule(Tick t); /// Reschedule the event with the current priority - void reschedule(Tick t); + // always parameter means to schedule if not already scheduled + void reschedule(Tick t, bool always = false); /// Remove the event from the current schedule void deschedule(); @@ -402,16 +403,22 @@ Event::deschedule() } inline void -Event::reschedule(Tick t) +Event::reschedule(Tick t, bool always) { - assert(scheduled()); - clearFlags(Squashed); + assert(scheduled() || always); #if TRACING_ON when_scheduled = curTick; #endif _when = t; - queue->reschedule(this); + + if (scheduled()) { + clearFlags(Squashed); + queue->reschedule(this); + } else { + setFlags(Scheduled); + queue->schedule(this); + } } inline void diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc index 56a779674..10127aa5f 100644 --- a/src/sim/pseudo_inst.cc +++ b/src/sim/pseudo_inst.cc @@ -87,10 +87,7 @@ namespace PseudoInst Tick resume = curTick + Clock::Int::ns * ns; - if (quiesceEvent->scheduled()) - quiesceEvent->reschedule(resume); - else - quiesceEvent->schedule(resume); + quiesceEvent->reschedule(resume, true); DPRINTF(Quiesce, "%s: quiesceNs(%d) until %d\n", tc->getCpuPtr()->name(), ns, resume); @@ -110,10 +107,7 @@ namespace PseudoInst Tick resume = curTick + tc->getCpuPtr()->cycles(cycles); - if (quiesceEvent->scheduled()) - quiesceEvent->reschedule(resume); - else - quiesceEvent->schedule(resume); + quiesceEvent->reschedule(resume, true); DPRINTF(Quiesce, "%s: quiesceCycles(%d) until %d\n", tc->getCpuPtr()->name(), cycles, resume); From 69ea50c1635bc3dc455eeb29a6f7b0ff04e4ad0b Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 9 May 2007 22:39:43 -0400 Subject: [PATCH 53/68] couple of updates in the intel nic --HG-- extra : convert_revision : da68e5e6411000d9d5247f769ee528a443286c61 --- src/dev/i8254xGBe.cc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc index 680e31656..e0272c655 100644 --- a/src/dev/i8254xGBe.cc +++ b/src/dev/i8254xGBe.cc @@ -891,6 +891,7 @@ IGbE::TxDescCache::pktComplete() pktPtr = NULL; DPRINTF(EthernetDesc, "Partial Packet Descriptor Done\n"); + enableSm(); return; } @@ -971,6 +972,7 @@ IGbE::TxDescCache::pktComplete() DPRINTF(EthernetDesc, "used > WTHRESH, writing back descriptor\n"); writeback((igbe->cacheBlockSize()-1)>>4); } + enableSm(); igbe->checkDrain(); } @@ -1150,6 +1152,8 @@ IGbE::txStateMachine() return; } + DPRINTF(EthernetSM, "TXS: Nothing to do, stopping ticking\n"); + txTick = false; } bool From 4a37c48e8e74405c39899e4914656930869f8bd4 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 10 May 2007 00:08:22 -0400 Subject: [PATCH 54/68] add/update parameters for bus bridge --HG-- extra : convert_revision : 063f757fbfa2c613328ffa70e556f8926623fa91 --- src/python/m5/objects/Bridge.py | 7 +++++-- src/python/m5/objects/Device.py | 6 ++++++ 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/src/python/m5/objects/Bridge.py b/src/python/m5/objects/Bridge.py index e123c2891..33b24ad3c 100644 --- a/src/python/m5/objects/Bridge.py +++ b/src/python/m5/objects/Bridge.py @@ -5,9 +5,12 @@ class Bridge(MemObject): type = 'Bridge' side_a = Port('Side A port') side_b = Port('Side B port') - queue_size_a = Param.Int(16, "The number of requests to buffer") - queue_size_b = Param.Int(16, "The number of requests to buffer") + req_size_a = Param.Int(16, "The number of requests to buffer") + req_size_b = Param.Int(16, "The number of requests to buffer") + resp_size_a = Param.Int(16, "The number of requests to buffer") + resp_size_b = Param.Int(16, "The number of requests to buffer") delay = Param.Latency('0ns', "The latency of this bridge") + nack_delay = Param.Latency('0ns', "The latency of this bridge") write_ack = Param.Bool(False, "Should this bridge ack writes") fix_partial_write_a = Param.Bool(False, "Should this bridge fixup partial block writes") fix_partial_write_b = Param.Bool(False, "Should this bridge fixup partial block writes") diff --git a/src/python/m5/objects/Device.py b/src/python/m5/objects/Device.py index f4b873a60..90fbfb552 100644 --- a/src/python/m5/objects/Device.py +++ b/src/python/m5/objects/Device.py @@ -19,6 +19,12 @@ class DmaDevice(PioDevice): type = 'DmaDevice' abstract = True dma = Port(Self.pio.peerObj.port, "DMA port") + min_backoff_delay = Param.Latency('4ns', + "min time between a nack packet being received and the next request made by the device") + max_backoff_delay = Param.Latency('10us', + "max time between a nack packet being received and the next request made by the device") + + class IsaFake(BasicPioDevice): type = 'IsaFake' From 77fd734b997f6d63edf4a84447fc76b38088bfa3 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 10 May 2007 00:30:53 -0400 Subject: [PATCH 55/68] update for bus bridge updates --HG-- extra : convert_revision : 829b1f33c88f1708ce5ee84afb4cd8bda8a6576f --- .../tsunami-simple-timing-dual/config.ini | 27 +++- .../tsunami-simple-timing-dual/config.out | 27 +++- .../tsunami-simple-timing-dual/m5stats.txt | 139 +++++++++--------- .../linux/tsunami-simple-timing/config.ini | 27 +++- .../linux/tsunami-simple-timing/config.out | 27 +++- .../linux/tsunami-simple-timing/m5stats.txt | 103 +++++++------ 6 files changed, 196 insertions(+), 154 deletions(-) diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index b24dc5968..8e1ba179d 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -8,11 +8,11 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami boot_cpu_frequency=1 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/Users/ali/work/system/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/Users/ali/work/system/binaries/vmlinux mem_mode=timing -pal=/dist/m5/system/binaries/ts_osfpal +pal=/Users/ali/work/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -22,8 +22,13 @@ system_type=34 [system.bridge] type=Bridge delay=0 -queue_size_a=16 -queue_size_b=16 +fix_partial_write_a=false +fix_partial_write_b=true +nack_delay=0 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 write_ack=false side_a=system.iobus.port[0] side_b=system.membus.port[0] @@ -108,7 +113,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/Users/ali/work/system/disks/linux-latest.img read_only=true [system.disk2] @@ -127,7 +132,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/Users/ali/work/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -136,6 +141,7 @@ sys=system [system.iobus] type=Bus +block_size=64 bus_id=0 clock=2 responder_set=true @@ -146,6 +152,7 @@ port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio syst [system.membus] type=Bus children=responder +block_size=64 bus_id=1 clock=2 responder_set=false @@ -193,7 +200,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/Users/ali/work/system/disks/linux-latest.img read_only=true [system.tsunami] @@ -242,6 +249,8 @@ dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 intr_delay=20000 +max_backoff_delay=20000 +min_backoff_delay=8 pci_bus=0 pci_dev=1 pci_func=0 @@ -614,6 +623,8 @@ children=configdata config_latency=40 configdata=system.tsunami.ide.configdata disks=system.disk0 system.disk2 +max_backoff_delay=20000 +min_backoff_delay=8 pci_bus=0 pci_dev=0 pci_func=0 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out index b41d5083f..890030c19 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out @@ -14,9 +14,9 @@ type=LinuxAlphaSystem boot_cpu_frequency=1 physmem=system.physmem mem_mode=timing -kernel=/dist/m5/system/binaries/vmlinux -console=/dist/m5/system/binaries/console -pal=/dist/m5/system/binaries/ts_osfpal +kernel=/Users/ali/work/system/binaries/vmlinux +console=/Users/ali/work/system/binaries/console +pal=/Users/ali/work/system/binaries/ts_osfpal boot_osflags=root=/dev/hda1 console=ttyS0 readfile=tests/halt.sh symbolfile= @@ -30,6 +30,7 @@ bus_id=1 clock=2 width=64 responder_set=false +block_size=64 [system.intrctrl] type=IntrControl @@ -57,14 +58,19 @@ system=system [system.bridge] type=Bridge -queue_size_a=16 -queue_size_b=16 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 delay=0 +nack_delay=0 write_ack=false +fix_partial_write_a=false +fix_partial_write_b=true [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/Users/ali/work/system/disks/linux-latest.img read_only=true [system.disk0.image] @@ -82,7 +88,7 @@ delay=2000 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/Users/ali/work/system/disks/linux-bigswap2.img read_only=true [system.disk2.image] @@ -162,7 +168,7 @@ function_trace_start=0 [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/Users/ali/work/system/disks/linux-latest.img read_only=true [system.simple_disk] @@ -510,6 +516,8 @@ BAR5Size=0 type=NSGigE system=system platform=system.tsunami +min_backoff_delay=8 +max_backoff_delay=20000 configdata=system.tsunami.ethernet.configdata pci_bus=0 pci_dev=1 @@ -632,6 +640,8 @@ BAR5Size=0 type=IdeController system=system platform=system.tsunami +min_backoff_delay=8 +max_backoff_delay=20000 configdata=system.tsunami.ide.configdata pci_bus=0 pci_dev=0 @@ -646,4 +656,5 @@ bus_id=0 clock=2 width=64 responder_set=true +block_size=64 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt index 24b2c4738..e808b031d 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt @@ -1,31 +1,30 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 249273 # Simulator instruction rate (inst/s) -host_mem_usage 249952 # Number of bytes of host memory used -host_seconds 261.36 # Real time elapsed on the host -host_tick_rate 15217956 # Simulator tick rate (ticks/s) +host_inst_rate 159511 # Simulator instruction rate (inst/s) +host_seconds 408.44 # Real time elapsed on the host +host_tick_rate 9737848 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 65149861 # Number of instructions simulated -sim_seconds 1.988682 # Number of seconds simulated -sim_ticks 3977364868 # Number of ticks simulated +sim_insts 65151264 # Number of instructions simulated +sim_seconds 1.988681 # Number of seconds simulated +sim_ticks 3977362808 # Number of ticks simulated system.cpu0.dtb.accesses 676531 # DTB accesses system.cpu0.dtb.acv 306 # DTB access violations -system.cpu0.dtb.hits 12726821 # DTB hits +system.cpu0.dtb.hits 12726999 # DTB hits system.cpu0.dtb.misses 8261 # DTB misses system.cpu0.dtb.read_accesses 494241 # DTB read accesses system.cpu0.dtb.read_acv 184 # DTB read access violations -system.cpu0.dtb.read_hits 7906586 # DTB read hits +system.cpu0.dtb.read_hits 7906690 # DTB read hits system.cpu0.dtb.read_misses 7534 # DTB read misses system.cpu0.dtb.write_accesses 182290 # DTB write accesses system.cpu0.dtb.write_acv 122 # DTB write access violations -system.cpu0.dtb.write_hits 4820235 # DTB write hits +system.cpu0.dtb.write_hits 4820309 # DTB write hits system.cpu0.dtb.write_misses 727 # DTB write misses -system.cpu0.idle_fraction 0.930925 # Percentage of idle cycles -system.cpu0.itb.accesses 3412128 # ITB accesses +system.cpu0.idle_fraction 0.930953 # Percentage of idle cycles +system.cpu0.itb.accesses 3412195 # ITB accesses system.cpu0.itb.acv 161 # ITB acv -system.cpu0.itb.hits 3408295 # ITB hits +system.cpu0.itb.hits 3408362 # ITB hits system.cpu0.itb.misses 3833 # ITB misses -system.cpu0.kern.callpal 142543 # number of callpals executed +system.cpu0.kern.callpal 142550 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal_wripir 572 0.40% 0.40% # number of callpals executed system.cpu0.kern.callpal_wrmces 1 0.00% 0.40% # number of callpals executed @@ -34,7 +33,7 @@ system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.40% # nu system.cpu0.kern.callpal_swpctx 2878 2.02% 2.42% # number of callpals executed system.cpu0.kern.callpal_tbi 47 0.03% 2.46% # number of callpals executed system.cpu0.kern.callpal_wrent 7 0.00% 2.46% # number of callpals executed -system.cpu0.kern.callpal_swpipl 127693 89.58% 92.04% # number of callpals executed +system.cpu0.kern.callpal_swpipl 127700 89.58% 92.04% # number of callpals executed system.cpu0.kern.callpal_rdps 6611 4.64% 96.68% # number of callpals executed system.cpu0.kern.callpal_wrkgp 1 0.00% 96.68% # number of callpals executed system.cpu0.kern.callpal_wrusp 3 0.00% 96.68% # number of callpals executed @@ -44,44 +43,44 @@ system.cpu0.kern.callpal_rti 4215 2.96% 99.65% # nu system.cpu0.kern.callpal_callsys 355 0.25% 99.90% # number of callpals executed system.cpu0.kern.callpal_imb 147 0.10% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 157728 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6621 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 134531 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 53714 39.93% 39.93% # number of times we switched to this ipl +system.cpu0.kern.inst.hwrei 157735 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6620 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 134538 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 53716 39.93% 39.93% # number of times we switched to this ipl system.cpu0.kern.ipl_count_21 131 0.10% 40.02% # number of times we switched to this ipl system.cpu0.kern.ipl_count_22 2009 1.49% 41.52% # number of times we switched to this ipl system.cpu0.kern.ipl_count_30 482 0.36% 41.88% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 78195 58.12% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 108736 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 53298 49.02% 49.02% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count_31 78200 58.12% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 108740 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 53300 49.02% 49.02% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_21 131 0.12% 49.14% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_22 2009 1.85% 50.98% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_30 482 0.44% 51.43% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 52816 48.57% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_31 52818 48.57% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_ticks 3976579702 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 3843537444 96.65% 96.65% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 3843619308 96.66% 96.66% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks_21 123584 0.00% 96.66% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 1875640 0.05% 96.70% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 1201752 0.03% 96.73% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 129841282 3.27% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used 0.808260 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_0 0.992255 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_ticks_22 1873872 0.05% 96.71% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 1201752 0.03% 96.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 129761186 3.26% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used 0.808247 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_0 0.992256 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.675440 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1191 -system.cpu0.kern.mode_good_user 1191 +system.cpu0.kern.ipl_used_31 0.675422 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1193 +system.cpu0.kern.mode_good_user 1193 system.cpu0.kern.mode_good_idle 0 system.cpu0.kern.mode_switch_kernel 6700 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1191 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1193 # number of protection mode switches system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good 0.301863 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.177761 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good 0.302293 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.178060 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 3965299112 99.76% 99.76% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 9599258 0.24% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_kernel 3965295376 99.76% 99.76% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 9600934 0.24% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 2879 # number of times the context was actually changed system.cpu0.kern.syscall 216 # number of syscalls executed @@ -115,36 +114,36 @@ system.cpu0.kern.syscall_98 2 0.93% 97.69% # nu system.cpu0.kern.syscall_132 2 0.93% 98.61% # number of syscalls executed system.cpu0.kern.syscall_144 1 0.46% 99.07% # number of syscalls executed system.cpu0.kern.syscall_147 2 0.93% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.069075 # Percentage of non-idle cycles +system.cpu0.not_idle_fraction 0.069047 # Percentage of non-idle cycles system.cpu0.numCycles 3976579942 # number of cpu cycles simulated -system.cpu0.num_insts 50251391 # Number of instructions executed -system.cpu0.num_refs 12958546 # Number of memory references +system.cpu0.num_insts 50252314 # Number of instructions executed +system.cpu0.num_refs 12958725 # Number of memory references system.cpu1.dtb.accesses 346252 # DTB accesses system.cpu1.dtb.acv 67 # DTB access violations -system.cpu1.dtb.hits 4740978 # DTB hits +system.cpu1.dtb.hits 4740996 # DTB hits system.cpu1.dtb.misses 3345 # DTB misses system.cpu1.dtb.read_accesses 235843 # DTB read accesses system.cpu1.dtb.read_acv 26 # DTB read access violations -system.cpu1.dtb.read_hits 2707473 # DTB read hits +system.cpu1.dtb.read_hits 2707487 # DTB read hits system.cpu1.dtb.read_misses 2918 # DTB read misses system.cpu1.dtb.write_accesses 110409 # DTB write accesses system.cpu1.dtb.write_acv 41 # DTB write access violations -system.cpu1.dtb.write_hits 2033505 # DTB write hits +system.cpu1.dtb.write_hits 2033509 # DTB write hits system.cpu1.dtb.write_misses 427 # DTB write misses -system.cpu1.idle_fraction 0.974575 # Percentage of idle cycles -system.cpu1.itb.accesses 2097220 # ITB accesses +system.cpu1.idle_fraction 0.974578 # Percentage of idle cycles +system.cpu1.itb.accesses 2097175 # ITB accesses system.cpu1.itb.acv 23 # ITB acv -system.cpu1.itb.hits 2095948 # ITB hits +system.cpu1.itb.hits 2095903 # ITB hits system.cpu1.itb.misses 1272 # ITB misses -system.cpu1.kern.callpal 80965 # number of callpals executed +system.cpu1.kern.callpal 80960 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu1.kern.callpal_wripir 482 0.60% 0.60% # number of callpals executed system.cpu1.kern.callpal_wrmces 1 0.00% 0.60% # number of callpals executed system.cpu1.kern.callpal_wrfen 1 0.00% 0.60% # number of callpals executed system.cpu1.kern.callpal_swpctx 2289 2.83% 3.43% # number of callpals executed -system.cpu1.kern.callpal_tbi 7 0.01% 3.43% # number of callpals executed +system.cpu1.kern.callpal_tbi 7 0.01% 3.44% # number of callpals executed system.cpu1.kern.callpal_wrent 7 0.01% 3.44% # number of callpals executed -system.cpu1.kern.callpal_swpipl 71577 88.40% 91.85% # number of callpals executed +system.cpu1.kern.callpal_swpipl 71572 88.40% 91.85% # number of callpals executed system.cpu1.kern.callpal_rdps 2303 2.84% 94.69% # number of callpals executed system.cpu1.kern.callpal_wrkgp 1 0.00% 94.69% # number of callpals executed system.cpu1.kern.callpal_wrusp 4 0.00% 94.70% # number of callpals executed @@ -155,28 +154,28 @@ system.cpu1.kern.callpal_callsys 162 0.20% 99.96% # nu system.cpu1.kern.callpal_imb 33 0.04% 100.00% # number of callpals executed system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 88247 # number of hwrei instructions executed +system.cpu1.kern.inst.hwrei 88242 # number of hwrei instructions executed system.cpu1.kern.inst.quiesce 2815 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 78243 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 30463 38.93% 38.93% # number of times we switched to this ipl +system.cpu1.kern.ipl_count 78238 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 30461 38.93% 38.93% # number of times we switched to this ipl system.cpu1.kern.ipl_count_22 2001 2.56% 41.49% # number of times we switched to this ipl system.cpu1.kern.ipl_count_30 572 0.73% 42.22% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 45207 57.78% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 61005 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 29502 48.36% 48.36% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_count_31 45204 57.78% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 61001 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 29500 48.36% 48.36% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good_22 2001 3.28% 51.64% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good_30 572 0.94% 52.58% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 28930 47.42% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 3977363084 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 3855395406 96.93% 96.93% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 1873360 0.05% 96.98% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_good_31 28928 47.42% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 3977361024 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 3855399740 96.93% 96.93% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 1871566 0.05% 96.98% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks_30 1461344 0.04% 97.02% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 118632974 2.98% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used 0.779686 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_0 0.968454 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_ticks_31 118628374 2.98% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used 0.779685 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_0 0.968451 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.639945 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_31 0.639943 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.mode_good_kernel 1058 system.cpu1.kern.mode_good_user 562 system.cpu1.kern.mode_good_idle 496 @@ -187,9 +186,9 @@ system.cpu1.kern.mode_switch_good 0.353020 # fr system.cpu1.kern.mode_switch_good_kernel 0.441385 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_idle 0.163427 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 64042452 1.61% 1.61% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 5753306 0.14% 1.75% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 3907567318 98.25% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_kernel 64032120 1.61% 1.61% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 5754658 0.14% 1.75% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 3907574238 98.25% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 2290 # number of times the context was actually changed system.cpu1.kern.syscall 110 # number of syscalls executed system.cpu1.kern.syscall_2 1 0.91% 0.91% # number of syscalls executed @@ -213,10 +212,10 @@ system.cpu1.kern.syscall_90 1 0.91% 95.45% # nu system.cpu1.kern.syscall_92 2 1.82% 97.27% # number of syscalls executed system.cpu1.kern.syscall_132 2 1.82% 99.09% # number of syscalls executed system.cpu1.kern.syscall_144 1 0.91% 100.00% # number of syscalls executed -system.cpu1.not_idle_fraction 0.025425 # Percentage of non-idle cycles -system.cpu1.numCycles 3977364868 # number of cpu cycles simulated -system.cpu1.num_insts 14898470 # Number of instructions executed -system.cpu1.num_refs 4770918 # Number of memory references +system.cpu1.not_idle_fraction 0.025422 # Percentage of non-idle cycles +system.cpu1.numCycles 3977362808 # number of cpu cycles simulated +system.cpu1.num_insts 14898950 # Number of instructions executed +system.cpu1.num_refs 4770935 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index 9edee8632..65aa9c7e6 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -8,11 +8,11 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami boot_cpu_frequency=1 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/Users/ali/work/system/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/Users/ali/work/system/binaries/vmlinux mem_mode=timing -pal=/dist/m5/system/binaries/ts_osfpal +pal=/Users/ali/work/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -22,8 +22,13 @@ system_type=34 [system.bridge] type=Bridge delay=0 -queue_size_a=16 -queue_size_b=16 +fix_partial_write_a=false +fix_partial_write_b=true +nack_delay=0 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 write_ack=false side_a=system.iobus.port[0] side_b=system.membus.port[0] @@ -76,7 +81,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/Users/ali/work/system/disks/linux-latest.img read_only=true [system.disk2] @@ -95,7 +100,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/Users/ali/work/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -104,6 +109,7 @@ sys=system [system.iobus] type=Bus +block_size=64 bus_id=0 clock=2 responder_set=true @@ -114,6 +120,7 @@ port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio syst [system.membus] type=Bus children=responder +block_size=64 bus_id=1 clock=2 responder_set=false @@ -161,7 +168,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/Users/ali/work/system/disks/linux-latest.img read_only=true [system.tsunami] @@ -210,6 +217,8 @@ dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 intr_delay=20000 +max_backoff_delay=20000 +min_backoff_delay=8 pci_bus=0 pci_dev=1 pci_func=0 @@ -582,6 +591,8 @@ children=configdata config_latency=40 configdata=system.tsunami.ide.configdata disks=system.disk0 system.disk2 +max_backoff_delay=20000 +min_backoff_delay=8 pci_bus=0 pci_dev=0 pci_func=0 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out index ad8a29167..1034abd0e 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out @@ -14,9 +14,9 @@ type=LinuxAlphaSystem boot_cpu_frequency=1 physmem=system.physmem mem_mode=timing -kernel=/dist/m5/system/binaries/vmlinux -console=/dist/m5/system/binaries/console -pal=/dist/m5/system/binaries/ts_osfpal +kernel=/Users/ali/work/system/binaries/vmlinux +console=/Users/ali/work/system/binaries/console +pal=/Users/ali/work/system/binaries/ts_osfpal boot_osflags=root=/dev/hda1 console=ttyS0 readfile=tests/halt.sh symbolfile= @@ -30,6 +30,7 @@ bus_id=1 clock=2 width=64 responder_set=false +block_size=64 [system.intrctrl] type=IntrControl @@ -57,14 +58,19 @@ system=system [system.bridge] type=Bridge -queue_size_a=16 -queue_size_b=16 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 delay=0 +nack_delay=0 write_ack=false +fix_partial_write_a=false +fix_partial_write_b=true [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/Users/ali/work/system/disks/linux-latest.img read_only=true [system.disk0.image] @@ -82,7 +88,7 @@ delay=2000 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/Users/ali/work/system/disks/linux-bigswap2.img read_only=true [system.disk2.image] @@ -100,7 +106,7 @@ delay=2000 [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/Users/ali/work/system/disks/linux-latest.img read_only=true [system.simple_disk] @@ -479,6 +485,8 @@ BAR5Size=0 type=NSGigE system=system platform=system.tsunami +min_backoff_delay=8 +max_backoff_delay=20000 configdata=system.tsunami.ethernet.configdata pci_bus=0 pci_dev=1 @@ -601,6 +609,8 @@ BAR5Size=0 type=IdeController system=system platform=system.tsunami +min_backoff_delay=8 +max_backoff_delay=20000 configdata=system.tsunami.ide.configdata pci_bus=0 pci_dev=0 @@ -615,4 +625,5 @@ bus_id=0 clock=2 width=64 responder_set=true +block_size=64 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt index 7947c3d76..466fb2d27 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt @@ -1,84 +1,83 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 374146 # Simulator instruction rate (inst/s) -host_mem_usage 249416 # Number of bytes of host memory used -host_seconds 160.59 # Real time elapsed on the host -host_tick_rate 24179677 # Simulator tick rate (ticks/s) +host_inst_rate 233672 # Simulator instruction rate (inst/s) +host_seconds 257.14 # Real time elapsed on the host +host_tick_rate 15108417 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 60085523 # Number of instructions simulated -sim_seconds 1.941556 # Number of seconds simulated -sim_ticks 3883112324 # Number of ticks simulated -system.cpu.dtb.accesses 1020793 # DTB accesses +sim_insts 60085488 # Number of instructions simulated +sim_seconds 1.942464 # Number of seconds simulated +sim_ticks 3884928812 # Number of ticks simulated +system.cpu.dtb.accesses 1020784 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 16070719 # DTB hits -system.cpu.dtb.misses 11472 # DTB misses -system.cpu.dtb.read_accesses 728862 # DTB read accesses +system.cpu.dtb.hits 16070353 # DTB hits +system.cpu.dtb.misses 11466 # DTB misses +system.cpu.dtb.read_accesses 728853 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 9714788 # DTB read hits -system.cpu.dtb.read_misses 10330 # DTB read misses +system.cpu.dtb.read_hits 9714571 # DTB read hits +system.cpu.dtb.read_misses 10324 # DTB read misses system.cpu.dtb.write_accesses 291931 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_hits 6355931 # DTB write hits +system.cpu.dtb.write_hits 6355782 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses -system.cpu.idle_fraction 0.921464 # Percentage of idle cycles -system.cpu.itb.accesses 4985828 # ITB accesses +system.cpu.idle_fraction 0.921526 # Percentage of idle cycles +system.cpu.itb.accesses 4985698 # ITB accesses system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 4980818 # ITB hits +system.cpu.itb.hits 4980688 # ITB hits system.cpu.itb.misses 5010 # ITB misses -system.cpu.kern.callpal 193475 # number of callpals executed +system.cpu.kern.callpal 193483 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_swpctx 4148 2.14% 2.15% # number of callpals executed +system.cpu.kern.callpal_swpctx 4144 2.14% 2.14% # number of callpals executed system.cpu.kern.callpal_tbi 54 0.03% 2.17% # number of callpals executed system.cpu.kern.callpal_wrent 7 0.00% 2.18% # number of callpals executed -system.cpu.kern.callpal_swpipl 176501 91.23% 93.40% # number of callpals executed -system.cpu.kern.callpal_rdps 6860 3.55% 96.95% # number of callpals executed +system.cpu.kern.callpal_swpipl 176511 91.23% 93.40% # number of callpals executed +system.cpu.kern.callpal_rdps 6861 3.55% 96.95% # number of callpals executed system.cpu.kern.callpal_wrkgp 1 0.00% 96.95% # number of callpals executed system.cpu.kern.callpal_wrusp 7 0.00% 96.95% # number of callpals executed system.cpu.kern.callpal_rdusp 9 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal_whami 2 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal_rti 5186 2.68% 99.64% # number of callpals executed +system.cpu.kern.callpal_rti 5187 2.68% 99.64% # number of callpals executed system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 212602 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6154 # number of quiesce instructions executed -system.cpu.kern.ipl_count 183780 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 75067 40.85% 40.85% # number of times we switched to this ipl +system.cpu.kern.inst.hwrei 212605 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6153 # number of quiesce instructions executed +system.cpu.kern.ipl_count 183792 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 75069 40.84% 40.84% # number of times we switched to this ipl system.cpu.kern.ipl_count_21 131 0.07% 40.92% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 1961 1.07% 41.98% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 106621 58.02% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 149492 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 73700 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count_22 1962 1.07% 41.98% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 106630 58.02% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 149497 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 73702 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_21 131 0.09% 49.39% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 1961 1.31% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 73700 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 3883110540 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 3755984220 96.73% 96.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_good_22 1962 1.31% 50.70% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_31 73702 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 3884927028 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 3757863794 96.73% 96.73% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks_21 112456 0.00% 96.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 918754 0.02% 96.75% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 126095110 3.25% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used 0.813429 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_ticks_22 918216 0.02% 96.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 126032562 3.24% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used 0.813403 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_0 0.981790 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.691233 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1897 +system.cpu.kern.ipl_used_31 0.691194 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1895 system.cpu.kern.mode_good_user 1742 -system.cpu.kern.mode_good_idle 155 +system.cpu.kern.mode_good_idle 153 system.cpu.kern.mode_switch_kernel 5935 # number of protection mode switches system.cpu.kern.mode_switch_user 1742 # number of protection mode switches -system.cpu.kern.mode_switch_idle 2065 # number of protection mode switches -system.cpu.kern.mode_switch_good 0.389448 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.319629 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_idle 2062 # number of protection mode switches +system.cpu.kern.mode_switch_good 0.389157 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.319292 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_idle 0.075061 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 112876118 2.91% 2.91% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 15210360 0.39% 3.30% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 3755024054 96.70% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4149 # number of times the context was actually changed +system.cpu.kern.mode_switch_good_idle 0.074200 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks_kernel 112890486 2.91% 2.91% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 15209884 0.39% 3.30% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 3756826650 96.70% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4145 # number of times the context was actually changed system.cpu.kern.syscall 326 # number of syscalls executed system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed @@ -110,10 +109,10 @@ system.cpu.kern.syscall_98 2 0.61% 97.55% # nu system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed -system.cpu.not_idle_fraction 0.078536 # Percentage of non-idle cycles -system.cpu.numCycles 3883112324 # number of cpu cycles simulated -system.cpu.num_insts 60085523 # Number of instructions executed -system.cpu.num_refs 16318655 # Number of memory references +system.cpu.not_idle_fraction 0.078474 # Percentage of non-idle cycles +system.cpu.numCycles 3884928812 # number of cpu cycles simulated +system.cpu.num_insts 60085488 # Number of instructions executed +system.cpu.num_refs 16318244 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). From 634d2e9d83054d2ddae4333d4e28e9a04cfbfd84 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 10 May 2007 18:24:48 -0400 Subject: [PATCH 56/68] remove hit_latency and make latency do the right thing set the latency parameter in terms of a latency add caches to tsunami-simple configs configs/common/Caches.py: tests/configs/memtest.py: tests/configs/o3-timing-mp.py: tests/configs/o3-timing.py: tests/configs/simple-atomic-mp.py: tests/configs/simple-timing-mp.py: tests/configs/simple-timing.py: set the latency parameter in terms of a latency configs/common/FSConfig.py: give the bridge a default latency too src/mem/cache/cache_builder.cc: src/python/m5/objects/BaseCache.py: remove hit_latency and make latency do the right thing tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: add caches to tsunami-simple configs --HG-- extra : convert_revision : 37bef7c652e97c8cdb91f471fba62978f89019f1 --- configs/common/Caches.py | 6 +-- configs/common/FSConfig.py | 4 +- src/mem/cache/cache_builder.cc | 6 +-- src/python/m5/objects/BaseCache.py | 3 +- tests/configs/memtest.py | 4 +- tests/configs/o3-timing-mp.py | 4 +- tests/configs/o3-timing.py | 2 +- tests/configs/simple-atomic-mp.py | 4 +- tests/configs/simple-timing-mp.py | 4 +- tests/configs/simple-timing.py | 4 +- tests/configs/tsunami-simple-atomic-dual.py | 43 ++++++++++++++++++-- tests/configs/tsunami-simple-atomic.py | 43 +++++++++++++++++++- tests/configs/tsunami-simple-timing-dual.py | 44 ++++++++++++++++++++- tests/configs/tsunami-simple-timing.py | 44 ++++++++++++++++++++- 14 files changed, 184 insertions(+), 31 deletions(-) diff --git a/configs/common/Caches.py b/configs/common/Caches.py index 4692ef537..4bff2c8a4 100644 --- a/configs/common/Caches.py +++ b/configs/common/Caches.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -32,7 +32,7 @@ from m5.objects import * class L1Cache(BaseCache): assoc = 2 block_size = 64 - latency = 1 + latency = '1ns' mshrs = 10 tgts_per_mshr = 5 protocol = CoherenceProtocol(protocol='moesi') @@ -40,7 +40,7 @@ class L1Cache(BaseCache): class L2Cache(BaseCache): assoc = 8 block_size = 64 - latency = 10 + latency = '10ns' mshrs = 20 tgts_per_mshr = 12 diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py index 289a7a5f4..593baf169 100644 --- a/configs/common/FSConfig.py +++ b/configs/common/FSConfig.py @@ -61,7 +61,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None): self.readfile = mdesc.script() self.iobus = Bus(bus_id=0) self.membus = Bus(bus_id=1) - self.bridge = Bridge(fix_partial_write_b=True) + self.bridge = Bridge(fix_partial_write_b=True, delay='50ns', nack_delay='4ns') self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) self.bridge.side_a = self.iobus.port self.bridge.side_b = self.membus.port @@ -94,7 +94,7 @@ def makeSparcSystem(mem_mode, mdesc = None): self.readfile = mdesc.script() self.iobus = Bus(bus_id=0) self.membus = Bus(bus_id=1) - self.bridge = Bridge() + self.bridge = Bridge(fix_partial_write_b=True, delay='50ns', nack_delay='4ns') self.t1000 = T1000() self.t1000.attachOnChipIO(self.membus) self.t1000.attachIO(self.iobus) diff --git a/src/mem/cache/cache_builder.cc b/src/mem/cache/cache_builder.cc index 318b57d50..e887f711e 100644 --- a/src/mem/cache/cache_builder.cc +++ b/src/mem/cache/cache_builder.cc @@ -134,7 +134,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(BaseCache) Param prefetch_cache_check_push; Param prefetch_use_cpu_id; Param prefetch_data_accesses_only; - Param hit_latency; END_DECLARE_SIM_OBJECT_PARAMS(BaseCache) @@ -190,8 +189,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(BaseCache) INIT_PARAM_DFLT(prefetch_policy, "Type of prefetcher to use", "none"), INIT_PARAM_DFLT(prefetch_cache_check_push, "Check if in cash on push or pop of prefetch queue", true), INIT_PARAM_DFLT(prefetch_use_cpu_id, "Use the CPU ID to seperate calculations of prefetches", true), - INIT_PARAM_DFLT(prefetch_data_accesses_only, "Only prefetch on data not on instruction accesses", false), - INIT_PARAM_DFLT(hit_latency, "Hit Latecny for a succesful access", 1) + INIT_PARAM_DFLT(prefetch_data_accesses_only, "Only prefetch on data not on instruction accesses", false) END_INIT_SIM_OBJECT_PARAMS(BaseCache) @@ -211,7 +209,7 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache) BUILD_NULL_PREFETCHER(TAGS); \ } \ Cache::Params params(tags, mq, coh, base_params, \ - pf, prefetch_access, hit_latency, \ + pf, prefetch_access, latency, \ true, \ store_compressed, \ adaptive_compression, \ diff --git a/src/python/m5/objects/BaseCache.py b/src/python/m5/objects/BaseCache.py index 773a11bea..7df5215e4 100644 --- a/src/python/m5/objects/BaseCache.py +++ b/src/python/m5/objects/BaseCache.py @@ -9,7 +9,7 @@ class BaseCache(MemObject): "Use an adaptive compression scheme") assoc = Param.Int("associativity") block_size = Param.Int("block size in bytes") - latency = Param.Int("Latency") + latency = Param.Latency("Latency") compressed_bus = Param.Bool(False, "This cache connects to a compressed memory") compression_latency = Param.Latency('0ns', @@ -59,6 +59,5 @@ class BaseCache(MemObject): "Use the CPU ID to seperate calculations of prefetches") prefetch_data_accesses_only = Param.Bool(False, "Only prefetch on data not on instruction accesses") - hit_latency = Param.Int(1,"Hit Latency of the cache") cpu_side = Port("Port on side closer to CPU") mem_side = Port("Port on side closer to MEM") diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py index f56edef4a..15a4f8f05 100644 --- a/tests/configs/memtest.py +++ b/tests/configs/memtest.py @@ -34,7 +34,7 @@ from m5.objects import * # ==================== class L1(BaseCache): - latency = 1 + latency = '1ns' block_size = 64 mshrs = 12 tgts_per_mshr = 8 @@ -46,7 +46,7 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - latency = 10 + latency = '10ns' mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py index 1e414294c..1ac9bd2e4 100644 --- a/tests/configs/o3-timing-mp.py +++ b/tests/configs/o3-timing-mp.py @@ -35,7 +35,7 @@ m5.AddToPath('../configs/common') # ==================== class L1(BaseCache): - latency = 1 + latency = '1ns' block_size = 64 mshrs = 4 tgts_per_mshr = 8 @@ -47,7 +47,7 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - latency = 100 + latency = '10ns' mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py index d20a7e0c8..366a3eb0d 100644 --- a/tests/configs/o3-timing.py +++ b/tests/configs/o3-timing.py @@ -33,7 +33,7 @@ m5.AddToPath('../configs/common') class MyCache(BaseCache): assoc = 2 block_size = 64 - latency = 1 + latency = '1ns' mshrs = 10 tgts_per_mshr = 5 diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py index e8000cd0a..de0793d1c 100644 --- a/tests/configs/simple-atomic-mp.py +++ b/tests/configs/simple-atomic-mp.py @@ -34,7 +34,7 @@ from m5.objects import * # ==================== class L1(BaseCache): - latency = 1 + latency = '1ns' block_size = 64 mshrs = 4 tgts_per_mshr = 8 @@ -46,7 +46,7 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - latency = 100 + latency = '10ns' mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py index a263bcf57..1fd0e8c3c 100644 --- a/tests/configs/simple-timing-mp.py +++ b/tests/configs/simple-timing-mp.py @@ -34,7 +34,7 @@ from m5.objects import * # ==================== class L1(BaseCache): - latency = 1 + latency = '1ns' block_size = 64 mshrs = 4 tgts_per_mshr = 8 @@ -46,7 +46,7 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - latency = 100 + latency = '10ns' mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py index 6c4b8232f..0ed985a17 100644 --- a/tests/configs/simple-timing.py +++ b/tests/configs/simple-timing.py @@ -32,13 +32,13 @@ from m5.objects import * class MyCache(BaseCache): assoc = 2 block_size = 64 - latency = 1 + latency = '1ns' mshrs = 10 tgts_per_mshr = 5 cpu = TimingSimpleCPU(cpu_id=0) cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), - MyCache(size = '2MB')) + MyCache(size = '2MB', latency='10ns')) system = System(cpu = cpu, physmem = PhysicalMemory(), membus = Bus()) diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py index 7ed854f44..131095055 100644 --- a/tests/configs/tsunami-simple-atomic-dual.py +++ b/tests/configs/tsunami-simple-atomic-dual.py @@ -31,12 +31,49 @@ from m5.objects import * m5.AddToPath('../configs/common') import FSConfig +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = '1ns' + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + protocol = CoherenceProtocol(protocol='moesi') + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = '10ns' + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +#cpu cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ] +#the system system = FSConfig.makeLinuxAlphaSystem('atomic') + system.cpu = cpus +#create the l1/l2 bus +system.toL2Bus = Bus() + +#connect up the l2 cache +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port +system.l2c.mem_side = system.membus.port + +#connect up the cpu and l1s for c in cpus: - c.connectMemPorts(system.membus) + c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) + # connect cpu level-1 caches to shared level-2 cache + c.connectMemPorts(system.toL2Bus) + c.clock = '2GHz' root = Root(system=system) - -m5.ticks.setGlobalFrequency('2GHz') +m5.ticks.setGlobalFrequency('1THz') diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py index 4859f30cf..595b1aeda 100644 --- a/tests/configs/tsunami-simple-atomic.py +++ b/tests/configs/tsunami-simple-atomic.py @@ -31,10 +31,49 @@ from m5.objects import * m5.AddToPath('../configs/common') import FSConfig +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = '1ns' + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + protocol = CoherenceProtocol(protocol='moesi') + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = '10ns' + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +#cpu cpu = AtomicSimpleCPU(cpu_id=0) +#the system system = FSConfig.makeLinuxAlphaSystem('atomic') + system.cpu = cpu -cpu.connectMemPorts(system.membus) +#create the l1/l2 bus +system.toL2Bus = Bus() + +#connect up the l2 cache +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port +system.l2c.mem_side = system.membus.port + +#connect up the cpu and l1s +cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) +# connect cpu level-1 caches to shared level-2 cache +cpu.connectMemPorts(system.toL2Bus) +cpu.clock = '2GHz' root = Root(system=system) -m5.ticks.setGlobalFrequency('2GHz') +m5.ticks.setGlobalFrequency('1THz') + diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py index 0c8c3d523..47fba30ff 100644 --- a/tests/configs/tsunami-simple-timing-dual.py +++ b/tests/configs/tsunami-simple-timing-dual.py @@ -31,11 +31,51 @@ from m5.objects import * m5.AddToPath('../configs/common') import FSConfig +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = '1ns' + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + protocol = CoherenceProtocol(protocol='moesi') + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = '10ns' + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +#cpu cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ] +#the system system = FSConfig.makeLinuxAlphaSystem('timing') + system.cpu = cpus +#create the l1/l2 bus +system.toL2Bus = Bus() + +#connect up the l2 cache +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port +system.l2c.mem_side = system.membus.port + +#connect up the cpu and l1s for c in cpus: - c.connectMemPorts(system.membus) + c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) + # connect cpu level-1 caches to shared level-2 cache + c.connectMemPorts(system.toL2Bus) + c.clock = '2GHz' root = Root(system=system) -m5.ticks.setGlobalFrequency('2GHz') +m5.ticks.setGlobalFrequency('1THz') + + diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py index 9f532e3ae..999bde087 100644 --- a/tests/configs/tsunami-simple-timing.py +++ b/tests/configs/tsunami-simple-timing.py @@ -31,10 +31,50 @@ from m5.objects import * m5.AddToPath('../configs/common') import FSConfig + +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = '1ns' + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + protocol = CoherenceProtocol(protocol='moesi') + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = '10ns' + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +#cpu cpu = TimingSimpleCPU(cpu_id=0) +#the system system = FSConfig.makeLinuxAlphaSystem('timing') + system.cpu = cpu -cpu.connectMemPorts(system.membus) +#create the l1/l2 bus +system.toL2Bus = Bus() + +#connect up the l2 cache +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port +system.l2c.mem_side = system.membus.port + +#connect up the cpu and l1s +cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) +# connect cpu level-1 caches to shared level-2 cache +cpu.connectMemPorts(system.toL2Bus) +cpu.clock = '2GHz' root = Root(system=system) -m5.ticks.setGlobalFrequency('2GHz') +m5.ticks.setGlobalFrequency('1THz') + From d667ce01b488e505569d6dce253f97e4246851cf Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Fri, 11 May 2007 11:47:18 -0700 Subject: [PATCH 57/68] total should be the sum of the vector result of an operation, not sum the operands and then apply the operation. --HG-- extra : convert_revision : 06486e59b3dd9588b458ef45c341cc4f2554dc09 --- src/base/statistics.hh | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/src/base/statistics.hh b/src/base/statistics.hh index 761b30c2b..8d3f53d4c 100644 --- a/src/base/statistics.hh +++ b/src/base/statistics.hh @@ -2094,9 +2094,13 @@ class UnaryNode : public Node return vresult; } - Result total() const { - Op op; - return op(l->total()); + Result total() const + { + const VResult &vec = this->result(); + Result total = 0; + for (int i = 0; i < size(); i++) + total += vec[i]; + return total; } virtual size_t size() const { return l->size(); } @@ -2149,9 +2153,13 @@ class BinaryNode : public Node return vresult; } - Result total() const { - Op op; - return op(l->total(), r->total()); + Result total() const + { + const VResult &vec = this->result(); + Result total = 0; + for (int i = 0; i < size(); i++) + total += vec[i]; + return total; } virtual size_t size() const { From 113319a7da9fe442f4f765b76c5728974824f2cc Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Fri, 11 May 2007 11:48:58 -0700 Subject: [PATCH 58/68] Float should have a c++ param type --HG-- extra : convert_revision : 150bbe7f31aafb43a75195fc2a365fb3c0ec5673 --- src/python/m5/params.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/python/m5/params.py b/src/python/m5/params.py index da7ddd65e..88b162874 100644 --- a/src/python/m5/params.py +++ b/src/python/m5/params.py @@ -348,7 +348,7 @@ class UdpPort(CheckedInt): cxx_type = 'uint16_t'; size = 16; unsigned = True class Percent(CheckedInt): cxx_type = 'int'; min = 0; max = 100 class Float(ParamValue, float): - pass + cxx_type = 'double' class MemorySize(CheckedInt): cxx_type = 'uint64_t' From 011db5c8515804145202373440bad26fa21b30a7 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Fri, 11 May 2007 15:01:44 -0700 Subject: [PATCH 59/68] Move full CPU sim object stuff into the encumbered directory --HG-- extra : convert_revision : 788068dd4f4994d0016dba7e8705359d45a3a45c --- src/python/SConscript | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/python/SConscript b/src/python/SConscript index 3c5ab4da1..562278aa0 100644 --- a/src/python/SConscript +++ b/src/python/SConscript @@ -81,7 +81,6 @@ SimObject('m5/objects/Ethernet.py') SimObject('m5/objects/FUPool.py') SimObject('m5/objects/FastCPU.py') #SimObject('m5/objects/FreebsdSystem.py') -SimObject('m5/objects/FullCPU.py') SimObject('m5/objects/FuncUnit.py') SimObject('m5/objects/FuncUnitConfig.py') SimObject('m5/objects/FunctionalMemory.py') @@ -97,7 +96,6 @@ SimObject('m5/objects/O3CPU.py') SimObject('m5/objects/OzoneCPU.py') SimObject('m5/objects/Pci.py') SimObject('m5/objects/PhysicalMemory.py') -SimObject('m5/objects/PipeTrace.py') SimObject('m5/objects/Platform.py') SimObject('m5/objects/Process.py') SimObject('m5/objects/Repl.py') From af26532bbd1a97a1f423c2944361290f1b696193 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Sun, 13 May 2007 01:44:42 -0400 Subject: [PATCH 60/68] fix handling of atomic packets fix up code for counting requests and responses --HG-- extra : convert_revision : 0d70981ee41c5d9c36cad01bd505281a096f6119 --- src/mem/bridge.cc | 60 ++++++++++++++++++++++++++++++++++++++++------- src/mem/bridge.hh | 5 ++-- 2 files changed, 54 insertions(+), 11 deletions(-) diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc index e89473be3..f525ccb48 100644 --- a/src/mem/bridge.cc +++ b/src/mem/bridge.cc @@ -119,7 +119,14 @@ Bridge::BridgePort::recvTiming(PacketPtr pkt) DPRINTF(BusBridge, "recvTiming: src %d dest %d addr 0x%x\n", pkt->getSrc(), pkt->getDest(), pkt->getAddr()); - if (pkt->isRequest() && otherPort->reqQueueFull()) { + DPRINTF(BusBridge, "Local queue size: %d outreq: %d outresp: %d\n", + sendQueue.size(), queuedRequests, outstandingResponses); + DPRINTF(BusBridge, "Remove queue size: %d outreq: %d outresp: %d\n", + otherPort->sendQueue.size(), otherPort->queuedRequests, + otherPort->outstandingResponses); + + if (pkt->isRequest() && otherPort->reqQueueFull() && pkt->result != + Packet::Nacked) { DPRINTF(BusBridge, "Remote queue full, nacking\n"); nackRequest(pkt); return true; @@ -191,7 +198,7 @@ Bridge::BridgePort::nackRequest(PacketPtr pkt) void Bridge::BridgePort::queueForSendTiming(PacketPtr pkt) { - if (pkt->isResponse() || pkt->result == Packet::Nacked) { + if (pkt->isResponse() || pkt->result == Packet::Nacked) { // This is a response for a request we forwarded earlier. The // corresponding PacketBuffer should be stored in the packet's // senderState field. @@ -201,9 +208,9 @@ Bridge::BridgePort::queueForSendTiming(PacketPtr pkt) // from original request buf->fixResponse(pkt); - // Check if this packet was expecting a response (this is either it or - // its a nacked packet and we won't be seeing that response) - if (buf->expectResponse) + // Check if this packet was expecting a response and it's a nacked + // packet, in which case we will never being seeing it + if (buf->expectResponse && pkt->result == Packet::Nacked) --outstandingResponses; @@ -213,6 +220,13 @@ Bridge::BridgePort::queueForSendTiming(PacketPtr pkt) delete buf; } + + if (pkt->isRequest() && pkt->result != Packet::Nacked) { + ++queuedRequests; + } + + + Tick readyTime = curTick + delay; PacketBuffer *buf = new PacketBuffer(pkt, readyTime); DPRINTF(BusBridge, "old sender state: %#X, new sender state: %#X\n", @@ -225,7 +239,6 @@ Bridge::BridgePort::queueForSendTiming(PacketPtr pkt) if (sendQueue.empty()) { sendEvent.schedule(readyTime); } - ++queuedRequests; sendQueue.push_back(buf); } @@ -254,6 +267,8 @@ Bridge::BridgePort::trySend() DPRINTF(BusBridge, "trySend: origSrc %d dest %d addr 0x%x\n", buf->origSrc, pkt->getDest(), pkt->getAddr()); + bool wasReq = pkt->isRequest(); + bool wasNacked = pkt->result == Packet::Nacked; if (sendTiming(pkt)) { // send successful @@ -270,8 +285,12 @@ Bridge::BridgePort::trySend() delete buf; } - if (!buf->nacked) + if (!wasNacked) { + if (wasReq) --queuedRequests; + else + --outstandingResponses; + } // If there are more packets to send, schedule event to try again. if (!sendQueue.empty()) { @@ -305,7 +324,32 @@ Bridge::BridgePort::recvRetry() Tick Bridge::BridgePort::recvAtomic(PacketPtr pkt) { - return otherPort->sendAtomic(pkt) + delay; + int pbs = otherPort->peerBlockSize(); + Tick atomic_delay; + // fix partial atomic writes... similar to the timing code that does the + // same + if (pkt->cmd == MemCmd::WriteInvalidateReq && fixPartialWrite && + pkt->getOffset(pbs) && pkt->getSize() != pbs) { + PacketDataPtr data; + data = new uint8_t[pbs]; + PacketPtr funcPkt = new Packet(pkt->req, MemCmd::ReadReq, + Packet::Broadcast, pbs); + + funcPkt->dataStatic(data); + otherPort->sendFunctional(funcPkt); + assert(funcPkt->result == Packet::Success); + delete funcPkt; + memcpy(data + pkt->getOffset(pbs), pkt->getPtr(), + pkt->getSize()); + PacketPtr newPkt = new Packet(pkt->req, MemCmd::WriteInvalidateReq, + Packet::Broadcast, pbs); + pkt->dataDynamicArray(data); + atomic_delay = otherPort->sendAtomic(newPkt); + delete newPkt; + } else { + atomic_delay = otherPort->sendAtomic(pkt); + } + return atomic_delay + delay; } /** Function called by the port when the bus is receiving a Functional diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh index cb5a6baed..7df3c767f 100644 --- a/src/mem/bridge.hh +++ b/src/mem/bridge.hh @@ -82,16 +82,15 @@ class Bridge : public MemObject bool partialWriteFixed; PacketPtr oldPkt; - bool nacked; PacketBuffer(PacketPtr _pkt, Tick t, bool nack = false) : ready(t), pkt(_pkt), origSenderState(_pkt->senderState), origSrc(_pkt->getSrc()), expectResponse(_pkt->needsResponse() && !nack), - partialWriteFixed(false), nacked(nack) + partialWriteFixed(false) { - if (!pkt->isResponse() && !nack) + if (!pkt->isResponse() && !nack && pkt->result != Packet::Nacked) pkt->senderState = this; } From df3fc36fa9f7a5edfe27421684fbaffba35e4592 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sun, 13 May 2007 22:58:06 -0700 Subject: [PATCH 61/68] Split BaseCache::CacheEvent into RequestEvent and ResponseEvent. Compiles but not tested. --HG-- extra : convert_revision : 4e1e28c4b87721ccfcf35a5ea62c1fa324acbaf9 --- src/mem/cache/base_cache.cc | 198 +++++++++++++++++++----------------- src/mem/cache/base_cache.hh | 27 +++-- src/mem/cache/cache_impl.hh | 14 +-- 3 files changed, 122 insertions(+), 117 deletions(-) diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc index ed665dafb..60e8028e8 100644 --- a/src/mem/cache/base_cache.cc +++ b/src/mem/cache/base_cache.cc @@ -134,8 +134,7 @@ BaseCache::CachePort::recvRetry() isCpuSide && cache->doSlaveRequest()) { DPRINTF(CachePort, "%s has more responses/requests\n", name()); - BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this, false); - reqCpu->schedule(curTick + 1); + new BaseCache::RequestEvent(this, curTick + 1); } waitingOnRetry = false; } @@ -178,8 +177,7 @@ BaseCache::CachePort::recvRetry() { DPRINTF(CachePort, "%s has more requests\n", name()); //Still more to issue, rerequest in 1 cycle - BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this, false); - reqCpu->schedule(curTick + 1); + new BaseCache::RequestEvent(this, curTick + 1); } } else @@ -196,8 +194,7 @@ BaseCache::CachePort::recvRetry() { DPRINTF(CachePort, "%s has more requests\n", name()); //Still more to issue, rerequest in 1 cycle - BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this, false); - reqCpu->schedule(curTick + 1); + new BaseCache::RequestEvent(this, curTick + 1); } } if (waitingOnRetry) DPRINTF(CachePort, "%s STILL Waiting on retry\n", name()); @@ -228,99 +225,110 @@ BaseCache::CachePort::clearBlocked() } } -BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort, bool _newResponse) - : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort), - newResponse(_newResponse) +BaseCache::RequestEvent::RequestEvent(CachePort *_cachePort, Tick when) + : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort) +{ + this->setFlags(AutoDelete); + pkt = NULL; + schedule(when); +} + +void +BaseCache::RequestEvent::process() +{ + if (cachePort->waitingOnRetry) return; + //We have some responses to drain first + if (!cachePort->drainList.empty()) { + DPRINTF(CachePort, "%s trying to drain a response\n", cachePort->name()); + if (cachePort->sendTiming(cachePort->drainList.front())) { + DPRINTF(CachePort, "%s drains a response succesfully\n", cachePort->name()); + cachePort->drainList.pop_front(); + if (!cachePort->drainList.empty() || + !cachePort->isCpuSide && cachePort->cache->doMasterRequest() || + cachePort->isCpuSide && cachePort->cache->doSlaveRequest()) { + + DPRINTF(CachePort, "%s still has outstanding bus reqs\n", cachePort->name()); + this->schedule(curTick + 1); + } + } + else { + cachePort->waitingOnRetry = true; + DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name()); + } + } + else if (!cachePort->isCpuSide) + { //MSHR + DPRINTF(CachePort, "%s trying to send a MSHR request\n", cachePort->name()); + if (!cachePort->cache->doMasterRequest()) { + //This can happen if I am the owner of a block and see an upgrade + //while the block was in my WB Buffers. I just remove the + //wb and de-assert the masterRequest + return; + } + + pkt = cachePort->cache->getPacket(); + MSHR* mshr = (MSHR*) pkt->senderState; + //Copy the packet, it may be modified/destroyed elsewhere + PacketPtr copyPkt = new Packet(*pkt); + copyPkt->dataStatic(pkt->getPtr()); + mshr->pkt = copyPkt; + + bool success = cachePort->sendTiming(pkt); + DPRINTF(Cache, "Address %x was %s in sending the timing request\n", + pkt->getAddr(), success ? "succesful" : "unsuccesful"); + + cachePort->waitingOnRetry = !success; + if (cachePort->waitingOnRetry) { + DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name()); + } + + cachePort->cache->sendResult(pkt, mshr, success); + if (success && cachePort->cache->doMasterRequest()) + { + DPRINTF(CachePort, "%s still more MSHR requests to send\n", + cachePort->name()); + //Still more to issue, rerequest in 1 cycle + pkt = NULL; + this->schedule(curTick+1); + } + } + else + { + //CSHR + assert(cachePort->cache->doSlaveRequest()); + pkt = cachePort->cache->getCoherencePacket(); + MSHR* cshr = (MSHR*) pkt->senderState; + bool success = cachePort->sendTiming(pkt); + cachePort->cache->sendCoherenceResult(pkt, cshr, success); + cachePort->waitingOnRetry = !success; + if (cachePort->waitingOnRetry) + DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name()); + if (success && cachePort->cache->doSlaveRequest()) + { + DPRINTF(CachePort, "%s still more CSHR requests to send\n", + cachePort->name()); + //Still more to issue, rerequest in 1 cycle + pkt = NULL; + this->schedule(curTick+1); + } + } +} + +const char * +BaseCache::RequestEvent::description() +{ + return "Cache request event"; +} + +BaseCache::ResponseEvent::ResponseEvent(CachePort *_cachePort) + : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort) { - if (!newResponse) - this->setFlags(AutoDelete); pkt = NULL; } void -BaseCache::CacheEvent::process() +BaseCache::ResponseEvent::process() { - if (!newResponse) - { - if (cachePort->waitingOnRetry) return; - //We have some responses to drain first - if (!cachePort->drainList.empty()) { - DPRINTF(CachePort, "%s trying to drain a response\n", cachePort->name()); - if (cachePort->sendTiming(cachePort->drainList.front())) { - DPRINTF(CachePort, "%s drains a response succesfully\n", cachePort->name()); - cachePort->drainList.pop_front(); - if (!cachePort->drainList.empty() || - !cachePort->isCpuSide && cachePort->cache->doMasterRequest() || - cachePort->isCpuSide && cachePort->cache->doSlaveRequest()) { - - DPRINTF(CachePort, "%s still has outstanding bus reqs\n", cachePort->name()); - this->schedule(curTick + 1); - } - } - else { - cachePort->waitingOnRetry = true; - DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name()); - } - } - else if (!cachePort->isCpuSide) - { //MSHR - DPRINTF(CachePort, "%s trying to send a MSHR request\n", cachePort->name()); - if (!cachePort->cache->doMasterRequest()) { - //This can happen if I am the owner of a block and see an upgrade - //while the block was in my WB Buffers. I just remove the - //wb and de-assert the masterRequest - return; - } - - pkt = cachePort->cache->getPacket(); - MSHR* mshr = (MSHR*) pkt->senderState; - //Copy the packet, it may be modified/destroyed elsewhere - PacketPtr copyPkt = new Packet(*pkt); - copyPkt->dataStatic(pkt->getPtr()); - mshr->pkt = copyPkt; - - bool success = cachePort->sendTiming(pkt); - DPRINTF(Cache, "Address %x was %s in sending the timing request\n", - pkt->getAddr(), success ? "succesful" : "unsuccesful"); - - cachePort->waitingOnRetry = !success; - if (cachePort->waitingOnRetry) { - DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name()); - } - - cachePort->cache->sendResult(pkt, mshr, success); - if (success && cachePort->cache->doMasterRequest()) - { - DPRINTF(CachePort, "%s still more MSHR requests to send\n", - cachePort->name()); - //Still more to issue, rerequest in 1 cycle - pkt = NULL; - this->schedule(curTick+1); - } - } - else - { - //CSHR - assert(cachePort->cache->doSlaveRequest()); - pkt = cachePort->cache->getCoherencePacket(); - MSHR* cshr = (MSHR*) pkt->senderState; - bool success = cachePort->sendTiming(pkt); - cachePort->cache->sendCoherenceResult(pkt, cshr, success); - cachePort->waitingOnRetry = !success; - if (cachePort->waitingOnRetry) - DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name()); - if (success && cachePort->cache->doSlaveRequest()) - { - DPRINTF(CachePort, "%s still more CSHR requests to send\n", - cachePort->name()); - //Still more to issue, rerequest in 1 cycle - pkt = NULL; - this->schedule(curTick+1); - } - } - return; - } - //Else it's a response assert(cachePort->transmitList.size()); assert(cachePort->transmitList.front().first <= curTick); pkt = cachePort->transmitList.front().second; @@ -354,9 +362,9 @@ BaseCache::CacheEvent::process() } const char * -BaseCache::CacheEvent::description() +BaseCache::ResponseEvent::description() { - return "BaseCache timing event"; + return "Cache response event"; } void diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh index ee871c1c4..0f2baa306 100644 --- a/src/mem/cache/base_cache.hh +++ b/src/mem/cache/base_cache.hh @@ -117,13 +117,22 @@ class BaseCache : public MemObject std::list > transmitList; }; - struct CacheEvent : public Event + struct RequestEvent : public Event { CachePort *cachePort; PacketPtr pkt; - bool newResponse; - CacheEvent(CachePort *_cachePort, bool response); + RequestEvent(CachePort *_cachePort, Tick when); + void process(); + const char *description(); + }; + + struct ResponseEvent : public Event + { + CachePort *cachePort; + PacketPtr pkt; + + ResponseEvent(CachePort *_cachePort); void process(); const char *description(); }; @@ -132,8 +141,8 @@ class BaseCache : public MemObject CachePort *cpuSidePort; CachePort *memSidePort; - CacheEvent *sendEvent; - CacheEvent *memSendEvent; + ResponseEvent *sendEvent; + ResponseEvent *memSendEvent; private: void recvStatusChange(Port::Status status, bool isCpuSide) @@ -432,9 +441,7 @@ class BaseCache : public MemObject { if (!doMasterRequest() && !memSidePort->waitingOnRetry) { - BaseCache::CacheEvent * reqCpu = - new BaseCache::CacheEvent(memSidePort, false); - reqCpu->schedule(time); + new RequestEvent(memSidePort, time); } uint8_t flag = 1<waitingOnRetry) { - BaseCache::CacheEvent * reqCpu = - new BaseCache::CacheEvent(cpuSidePort, false); - reqCpu->schedule(time); + new RequestEvent(cpuSidePort, time); } uint8_t flag = 1< Port * Cache::getPort(const std::string &if_name, int idx) { - if (if_name == "") + if (if_name == "" || if_name == "cpu_side") { if (cpuSidePort == NULL) { cpuSidePort = new CpuSidePort(name() + "-cpu_side_port", this); - sendEvent = new CacheEvent(cpuSidePort, true); + sendEvent = new ResponseEvent(cpuSidePort); } return cpuSidePort; } @@ -1158,20 +1158,12 @@ Cache::getPort(const std::string &if_name, int idx) { return new CpuSidePort(name() + "-cpu_side_funcport", this); } - else if (if_name == "cpu_side") - { - if (cpuSidePort == NULL) { - cpuSidePort = new CpuSidePort(name() + "-cpu_side_port", this); - sendEvent = new CacheEvent(cpuSidePort, true); - } - return cpuSidePort; - } else if (if_name == "mem_side") { if (memSidePort != NULL) panic("Already have a mem side for this cache\n"); memSidePort = new MemSidePort(name() + "-mem_side_port", this); - memSendEvent = new CacheEvent(memSidePort, true); + memSendEvent = new ResponseEvent(memSidePort); return memSidePort; } else panic("Port name %s unrecognized\n", if_name); From fecae03a0be9a5afc7f9c3536a425f8176afbd3e Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sun, 13 May 2007 23:09:10 -0700 Subject: [PATCH 62/68] Eliminate unused PacketPtr from BaseCache's RequestEvent and ResponseEvent. Compiles but not tested. --HG-- extra : convert_revision : cc791e7adea5b0406e986a0076edba51856b9105 --- src/mem/cache/base_cache.cc | 10 +++------- src/mem/cache/base_cache.hh | 2 -- 2 files changed, 3 insertions(+), 9 deletions(-) diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc index 60e8028e8..3ed4b84d1 100644 --- a/src/mem/cache/base_cache.cc +++ b/src/mem/cache/base_cache.cc @@ -229,7 +229,6 @@ BaseCache::RequestEvent::RequestEvent(CachePort *_cachePort, Tick when) : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort) { this->setFlags(AutoDelete); - pkt = NULL; schedule(when); } @@ -266,7 +265,7 @@ BaseCache::RequestEvent::process() return; } - pkt = cachePort->cache->getPacket(); + PacketPtr pkt = cachePort->cache->getPacket(); MSHR* mshr = (MSHR*) pkt->senderState; //Copy the packet, it may be modified/destroyed elsewhere PacketPtr copyPkt = new Packet(*pkt); @@ -288,7 +287,6 @@ BaseCache::RequestEvent::process() DPRINTF(CachePort, "%s still more MSHR requests to send\n", cachePort->name()); //Still more to issue, rerequest in 1 cycle - pkt = NULL; this->schedule(curTick+1); } } @@ -296,7 +294,7 @@ BaseCache::RequestEvent::process() { //CSHR assert(cachePort->cache->doSlaveRequest()); - pkt = cachePort->cache->getCoherencePacket(); + PacketPtr pkt = cachePort->cache->getCoherencePacket(); MSHR* cshr = (MSHR*) pkt->senderState; bool success = cachePort->sendTiming(pkt); cachePort->cache->sendCoherenceResult(pkt, cshr, success); @@ -308,7 +306,6 @@ BaseCache::RequestEvent::process() DPRINTF(CachePort, "%s still more CSHR requests to send\n", cachePort->name()); //Still more to issue, rerequest in 1 cycle - pkt = NULL; this->schedule(curTick+1); } } @@ -323,7 +320,6 @@ BaseCache::RequestEvent::description() BaseCache::ResponseEvent::ResponseEvent(CachePort *_cachePort) : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort) { - pkt = NULL; } void @@ -331,7 +327,7 @@ BaseCache::ResponseEvent::process() { assert(cachePort->transmitList.size()); assert(cachePort->transmitList.front().first <= curTick); - pkt = cachePort->transmitList.front().second; + PacketPtr pkt = cachePort->transmitList.front().second; cachePort->transmitList.pop_front(); if (!cachePort->transmitList.empty()) { Tick time = cachePort->transmitList.front().first; diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh index 0f2baa306..e45e36fa0 100644 --- a/src/mem/cache/base_cache.hh +++ b/src/mem/cache/base_cache.hh @@ -120,7 +120,6 @@ class BaseCache : public MemObject struct RequestEvent : public Event { CachePort *cachePort; - PacketPtr pkt; RequestEvent(CachePort *_cachePort, Tick when); void process(); @@ -130,7 +129,6 @@ class BaseCache : public MemObject struct ResponseEvent : public Event { CachePort *cachePort; - PacketPtr pkt; ResponseEvent(CachePort *_cachePort); void process(); From ea4e6f2e3d4d0ce6473fd2be5d9307c1e6545f72 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 14 May 2007 16:14:59 -0400 Subject: [PATCH 63/68] add uglyiness to fix dmas src/dev/io_device.cc: extra printing and assertions src/mem/bridge.hh: deal with packets only satisfying part of a request by making many requests src/mem/cache/cache_impl.hh: make the cache try to satisfy a functional request from the cache above it before checking itself --HG-- extra : convert_revision : 1df52ab61d7967e14cc377c560495430a6af266a --- src/dev/io_device.cc | 16 +++++++++++++++- src/mem/bridge.hh | 20 +++++++++++++------- src/mem/cache/cache_impl.hh | 6 +++--- 3 files changed, 31 insertions(+), 11 deletions(-) diff --git a/src/dev/io_device.cc b/src/dev/io_device.cc index d430ace72..6528bd81c 100644 --- a/src/dev/io_device.cc +++ b/src/dev/io_device.cc @@ -218,6 +218,9 @@ DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event, DmaReqState *reqState = new DmaReqState(event, this, size); + + DPRINTF(DMA, "Starting DMA for addr: %#x size: %d sched: %d\n", addr, size, + event->scheduled()); for (ChunkGenerator gen(addr, size, peerBlockSize()); !gen.done(); gen.next()) { Request *req = new Request(gen.addr(), gen.size(), 0); @@ -231,6 +234,8 @@ DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event, assert(pendingCount >= 0); pendingCount++; + DPRINTF(DMA, "--Queuing DMA for addr: %#x size: %d\n", gen.addr(), + gen.size()); queueDma(pkt); } @@ -281,19 +286,28 @@ DmaPort::sendDma() if (transmitList.size() && backoffTime && !inRetry && !backoffEvent.scheduled()) { + DPRINTF(DMA, "-- Scheduling backoff timer for %d\n", + backoffTime+curTick); backoffEvent.schedule(backoffTime+curTick); } } else if (state == System::Atomic) { transmitList.pop_front(); Tick lat; + DPRINTF(DMA, "--Sending DMA for addr: %#x size: %d\n", + pkt->req->getPaddr(), pkt->req->getSize()); lat = sendAtomic(pkt); assert(pkt->senderState); DmaReqState *state = dynamic_cast(pkt->senderState); assert(state); - state->numBytes += pkt->req->getSize(); + + DPRINTF(DMA, "--Received response for DMA for addr: %#x size: %d nb: %d, tot: %d sched %d\n", + pkt->req->getPaddr(), pkt->req->getSize(), state->numBytes, + state->totBytes, state->completionEvent->scheduled()); + if (state->totBytes == state->numBytes) { + assert(!state->completionEvent->scheduled()); state->completionEvent->schedule(curTick + lat); delete state; delete pkt->req; diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh index 7df3c767f..5951eeb98 100644 --- a/src/mem/bridge.hh +++ b/src/mem/bridge.hh @@ -108,18 +108,24 @@ class Bridge : public MemObject assert(!partialWriteFixed); assert(expectResponse); - int pbs = port->peerBlockSize(); + Addr pbs = port->peerBlockSize(); + Addr blockAddr = pkt->getAddr() & ~(pbs-1); partialWriteFixed = true; PacketDataPtr data; data = new uint8_t[pbs]; - PacketPtr funcPkt = new Packet(pkt->req, MemCmd::ReadReq, - Packet::Broadcast, pbs); - - funcPkt->dataStatic(data); - port->sendFunctional(funcPkt); - assert(funcPkt->result == Packet::Success); + RequestPtr funcReq = new Request(blockAddr, 4, 0); + PacketPtr funcPkt = new Packet(funcReq, MemCmd::ReadReq, + Packet::Broadcast); + for (int x = 0; x < pbs; x+=4) { + funcReq->setPhys(blockAddr + x, 4, 0); + funcPkt->reinitFromRequest(); + funcPkt->dataStatic(data + x); + port->sendFunctional(funcPkt); + assert(funcPkt->result == Packet::Success); + } delete funcPkt; + delete funcReq; oldPkt = pkt; memcpy(data + oldPkt->getOffset(pbs), pkt->getPtr(), diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index c70f10151..db488d33d 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -1290,9 +1290,9 @@ template void Cache::MemSidePort::recvFunctional(PacketPtr pkt) { - if (checkFunctional(pkt)) { - myCache()->probe(pkt, false, cache->cpuSidePort); - } + myCache()->probe(pkt, false, cache->cpuSidePort); + if (pkt->result != Packet::Success) + checkFunctional(pkt); } From 57104ea5f9e94dc4fe664f91e60278e486111ae9 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 14 May 2007 16:37:00 -0400 Subject: [PATCH 64/68] couple more bug fixes for intel nic src/dev/i8254xGBe.cc: src/dev/i8254xGBe.hh: couple more bug fixes --HG-- extra : convert_revision : ae5b806528c1ec06f0091e1f6e50fc0721057ddb --- configs/boot/devtime.rcS | 5 +---- src/dev/i8254xGBe.cc | 29 +++++++++++++++++++++++++++-- src/dev/i8254xGBe.hh | 2 ++ 3 files changed, 30 insertions(+), 6 deletions(-) diff --git a/configs/boot/devtime.rcS b/configs/boot/devtime.rcS index 22a5469b8..4d1ca9407 100644 --- a/configs/boot/devtime.rcS +++ b/configs/boot/devtime.rcS @@ -1,7 +1,4 @@ -echo "switching cpus" -m5 switchcpu -echo "done" -insmod /modules/devtime.ko dataAddr=0x9000004 count=100 +insmod /modules/devtime.ko dataAddr=0x9000008 count=100 rmmod devtime insmod /modules/devtime.ko dataAddr=0x1a0000300 count=100 rmmod devtime diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc index e0272c655..baf13c49a 100644 --- a/src/dev/i8254xGBe.cc +++ b/src/dev/i8254xGBe.cc @@ -656,7 +656,7 @@ IGbE::RxDescCache::writePacket(EthPacketPtr packet) return false; pktPtr = packet; - + pktDone = false; igbe->dmaWrite(igbe->platform->pciToDma(unusedCache.front()->buf), packet->length, &pktEvent, packet->data); return true; @@ -683,8 +683,12 @@ IGbE::RxDescCache::pktComplete() uint8_t status = RXDS_DD | RXDS_EOP; uint8_t err = 0; + IpPtr ip(pktPtr); + if (ip) { + DPRINTF(EthernetDesc, "Proccesing Ip packet with Id=%d\n", ip->id()); + if (igbe->regs.rxcsum.ipofld()) { DPRINTF(EthernetDesc, "Checking IP checksum\n"); status |= RXDS_IPCS; @@ -715,7 +719,10 @@ IGbE::RxDescCache::pktComplete() err |= RXDE_TCPE; } } - } // if ip + } else { // if ip + DPRINTF(EthernetSM, "Proccesing Non-Ip packet\n"); + } + desc->status = htole(status); desc->errors = htole(err); @@ -912,10 +919,20 @@ IGbE::TxDescCache::pktComplete() DPRINTF(EthernetDesc, "TxDescriptor data d1: %#llx d2: %#llx\n", desc->d1, desc->d2); + if (DTRACE(EthernetDesc)) { + IpPtr ip(pktPtr); + if (ip) + DPRINTF(EthernetDesc, "Proccesing Ip packet with Id=%d\n", + ip->id()); + else + DPRINTF(EthernetSM, "Proccesing Non-Ip packet\n"); + } + // Checksums are only ofloaded for new descriptor types if (TxdOp::isData(desc) && ( TxdOp::ixsm(desc) || TxdOp::txsm(desc)) ) { DPRINTF(EthernetDesc, "Calculating checksums for packet\n"); IpPtr ip(pktPtr); + if (TxdOp::ixsm(desc)) { ip->sum(0); ip->sum(cksum(ip)); @@ -1192,6 +1209,7 @@ IGbE::rxStateMachine() // If the packet is done check for interrupts/descriptors/etc if (rxDescCache.packetDone()) { + rxDmaPacket = false; DPRINTF(EthernetSM, "RXS: Packet completed DMA to memory\n"); int descLeft = rxDescCache.descLeft(); switch (regs.rctl.rdmts()) { @@ -1236,6 +1254,12 @@ IGbE::rxStateMachine() return; } + if (rxDmaPacket) { + DPRINTF(EthernetSM, "RXS: stopping ticking until packet DMA completes\n"); + rxTick = false; + return; + } + if (!rxDescCache.descUnused()) { DPRINTF(EthernetSM, "RXS: No descriptors available in cache, stopping ticking\n"); rxTick = false; @@ -1262,6 +1286,7 @@ IGbE::rxStateMachine() rxFifo.pop(); DPRINTF(EthernetSM, "RXS: stopping ticking until packet DMA completes\n"); rxTick = false; + rxDmaPacket = true; } void diff --git a/src/dev/i8254xGBe.hh b/src/dev/i8254xGBe.hh index 2dec3b08c..b6da53b09 100644 --- a/src/dev/i8254xGBe.hh +++ b/src/dev/i8254xGBe.hh @@ -80,6 +80,8 @@ class IGbE : public PciDev bool txTick; bool txFifoTick; + bool rxDmaPacket; + // Event and function to deal with RDTR timer expiring void rdtrProcess() { rxDescCache.writeback(0); From f317227b4e5002b2c9d7c2e5068d317dcea5b0f9 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 15 May 2007 17:39:50 -0400 Subject: [PATCH 65/68] hopefully the final hacky change to make the bus bridge work ok cache blocks that get dmaed ARE NOT marked invalid in the caches so it's a performance issue here src/mem/bridge.cc: src/mem/bridge.hh: hopefully the final hacky change to make the bus bridge work ok --HG-- extra : convert_revision : 62cbc65c74d1a84199f0a376546ec19994c5899c --- configs/boot/netperf-stream-udp-client.rcS | 2 +- src/mem/bridge.cc | 44 +++++++------------ src/mem/bridge.hh | 51 +--------------------- 3 files changed, 18 insertions(+), 79 deletions(-) diff --git a/configs/boot/netperf-stream-udp-client.rcS b/configs/boot/netperf-stream-udp-client.rcS index 91268ea50..4acb4243a 100644 --- a/configs/boot/netperf-stream-udp-client.rcS +++ b/configs/boot/netperf-stream-udp-client.rcS @@ -23,7 +23,7 @@ netcat -c -l -p 8000 BINARY=/benchmarks/netperf-bin/netperf TEST="UDP_STREAM" -SHORT_ARGS="-l 2 -- -m 4096" +SHORT_ARGS="-l 2 -- -m 16384 -M 16384 -s 262144 -S 262144" #LONG_ARGS="-k16384,0 -K16384,0 -- -m 65536 -M 65536 -s 262144 -S 262144" diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc index f525ccb48..9509aea38 100644 --- a/src/mem/bridge.cc +++ b/src/mem/bridge.cc @@ -247,8 +247,6 @@ Bridge::BridgePort::trySend() { assert(!sendQueue.empty()); - int pbs = peerBlockSize(); - PacketBuffer *buf = sendQueue.front(); assert(buf->ready <= curTick); @@ -257,11 +255,15 @@ Bridge::BridgePort::trySend() pkt->flags &= ~SNOOP_COMMIT; //CLear it if it was set + // Ugly! @todo When multilevel coherence works this will be removed if (pkt->cmd == MemCmd::WriteInvalidateReq && fixPartialWrite && - pkt->result != Packet::Nacked && pkt->getOffset(pbs) && - pkt->getSize() != pbs) { - buf->partialWriteFix(this); - pkt = buf->pkt; + pkt->result != Packet::Nacked) { + PacketPtr funcPkt = new Packet(pkt->req, MemCmd::WriteReq, + Packet::Broadcast); + funcPkt->dataStatic(pkt->getPtr()); + sendFunctional(funcPkt); + pkt->cmd = MemCmd::WriteReq; + delete funcPkt; } DPRINTF(BusBridge, "trySend: origSrc %d dest %d addr 0x%x\n", @@ -300,7 +302,6 @@ Bridge::BridgePort::trySend() } } else { DPRINTF(BusBridge, " unsuccessful\n"); - buf->undoPartialWriteFix(); inRetry = true; } DPRINTF(BusBridge, "trySend: queue size: %d outreq: %d outstanding resp: %d\n", @@ -324,32 +325,18 @@ Bridge::BridgePort::recvRetry() Tick Bridge::BridgePort::recvAtomic(PacketPtr pkt) { - int pbs = otherPort->peerBlockSize(); - Tick atomic_delay; // fix partial atomic writes... similar to the timing code that does the - // same - if (pkt->cmd == MemCmd::WriteInvalidateReq && fixPartialWrite && - pkt->getOffset(pbs) && pkt->getSize() != pbs) { - PacketDataPtr data; - data = new uint8_t[pbs]; - PacketPtr funcPkt = new Packet(pkt->req, MemCmd::ReadReq, - Packet::Broadcast, pbs); + // same... will be removed once our code gets this right + if (pkt->cmd == MemCmd::WriteInvalidateReq && fixPartialWrite) { - funcPkt->dataStatic(data); + PacketPtr funcPkt = new Packet(pkt->req, MemCmd::WriteReq, + Packet::Broadcast); + funcPkt->dataStatic(pkt->getPtr()); otherPort->sendFunctional(funcPkt); - assert(funcPkt->result == Packet::Success); delete funcPkt; - memcpy(data + pkt->getOffset(pbs), pkt->getPtr(), - pkt->getSize()); - PacketPtr newPkt = new Packet(pkt->req, MemCmd::WriteInvalidateReq, - Packet::Broadcast, pbs); - pkt->dataDynamicArray(data); - atomic_delay = otherPort->sendAtomic(newPkt); - delete newPkt; - } else { - atomic_delay = otherPort->sendAtomic(pkt); + pkt->cmd = MemCmd::WriteReq; } - return atomic_delay + delay; + return delay + otherPort->sendAtomic(pkt); } /** Function called by the port when the bus is receiving a Functional @@ -431,3 +418,4 @@ CREATE_SIM_OBJECT(Bridge) REGISTER_SIM_OBJECT("Bridge", Bridge) + diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh index 5951eeb98..a47fe3c1e 100644 --- a/src/mem/bridge.hh +++ b/src/mem/bridge.hh @@ -80,14 +80,10 @@ class Bridge : public MemObject short origSrc; bool expectResponse; - bool partialWriteFixed; - PacketPtr oldPkt; - PacketBuffer(PacketPtr _pkt, Tick t, bool nack = false) : ready(t), pkt(_pkt), origSenderState(_pkt->senderState), origSrc(_pkt->getSrc()), - expectResponse(_pkt->needsResponse() && !nack), - partialWriteFixed(false) + expectResponse(_pkt->needsResponse() && !nack) { if (!pkt->isResponse() && !nack && pkt->result != Packet::Nacked) @@ -99,52 +95,7 @@ class Bridge : public MemObject assert(pkt->senderState == this); pkt->setDest(origSrc); pkt->senderState = origSenderState; - if (partialWriteFixed) - delete oldPkt; } - - void partialWriteFix(Port *port) - { - assert(!partialWriteFixed); - assert(expectResponse); - - Addr pbs = port->peerBlockSize(); - Addr blockAddr = pkt->getAddr() & ~(pbs-1); - partialWriteFixed = true; - PacketDataPtr data; - - data = new uint8_t[pbs]; - RequestPtr funcReq = new Request(blockAddr, 4, 0); - PacketPtr funcPkt = new Packet(funcReq, MemCmd::ReadReq, - Packet::Broadcast); - for (int x = 0; x < pbs; x+=4) { - funcReq->setPhys(blockAddr + x, 4, 0); - funcPkt->reinitFromRequest(); - funcPkt->dataStatic(data + x); - port->sendFunctional(funcPkt); - assert(funcPkt->result == Packet::Success); - } - delete funcPkt; - delete funcReq; - - oldPkt = pkt; - memcpy(data + oldPkt->getOffset(pbs), pkt->getPtr(), - pkt->getSize()); - pkt = new Packet(oldPkt->req, MemCmd::WriteInvalidateReq, - Packet::Broadcast, pbs); - pkt->dataDynamicArray(data); - pkt->senderState = oldPkt->senderState; - } - - void undoPartialWriteFix() - { - if (!partialWriteFixed) - return; - delete pkt; - pkt = oldPkt; - partialWriteFixed = false; - } - }; /** From 0934f259d66c7adcf8446e84a2ce7db739794064 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 15 May 2007 18:06:35 -0400 Subject: [PATCH 66/68] add an l2 cache option to se example config configs/common/Options.py: configs/example/fs.py: move l2 cache option to Options.py --HG-- extra : convert_revision : 5c0071c2827f7db6d56229d5276326364b50f0c8 --- configs/common/Options.py | 3 ++- configs/example/fs.py | 1 - configs/example/se.py | 11 +++++++++-- 3 files changed, 11 insertions(+), 4 deletions(-) diff --git a/configs/common/Options.py b/configs/common/Options.py index 69f48dc3b..4f2b317c0 100644 --- a/configs/common/Options.py +++ b/configs/common/Options.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -31,6 +31,7 @@ parser.add_option("-d", "--detailed", action="store_true") parser.add_option("-t", "--timing", action="store_true") parser.add_option("-n", "--num_cpus", type="int", default=1) parser.add_option("--caches", action="store_true") +parser.add_option("--l2cache", action="store_true") # Run duration options parser.add_option("-m", "--maxtick", type="int") diff --git a/configs/example/fs.py b/configs/example/fs.py index bd4637e95..76c12bd9e 100644 --- a/configs/example/fs.py +++ b/configs/example/fs.py @@ -51,7 +51,6 @@ parser.add_option("--kernel", action="store", type="string") parser.add_option("--script", action="store", type="string") # Benchmark options -parser.add_option("--l2cache", action="store_true") parser.add_option("--dual", action="store_true", help="Simulate two systems attached with an ethernet link") parser.add_option("-b", "--benchmark", action="store", type="string", diff --git a/configs/example/se.py b/configs/example/se.py index 0944a030e..b294480f6 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -104,7 +104,14 @@ for i in xrange(np): if options.caches: system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), L1Cache(size = '64kB')) - system.cpu[i].connectMemPorts(system.membus) + if options.l2cache: + system.l2 = L2Cache(size='2MB') + system.tol2bus = Bus() + system.l2.cpu_side = system.tol2bus.port + system.l2.mem_side = system.membus.port + system.cpu[i].connectMemPorts(system.tol2bus) + else: + system.cpu[i].connectMemPorts(system.membus) system.cpu[i].workload = process root = Root(system = system) From b85690e239616b703881b7734b0559f61f9eb75e Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 15 May 2007 19:25:35 -0400 Subject: [PATCH 67/68] update all the regresstion tests for release --HG-- extra : convert_revision : 47e420b5b27e196a6e7a6424540923623bb3c4d2 --- .../ref/alpha/tru64/o3-timing/config.ini | 11 +- .../ref/alpha/tru64/o3-timing/config.out | 11 +- .../ref/alpha/tru64/o3-timing/m5stats.txt | 552 +- .../ref/alpha/tru64/simple-atomic/config.ini | 1 + .../ref/alpha/tru64/simple-atomic/config.out | 1 + .../ref/alpha/tru64/simple-atomic/m5stats.txt | 8 +- .../ref/alpha/tru64/simple-timing/config.ini | 11 +- .../ref/alpha/tru64/simple-timing/config.out | 11 +- .../ref/alpha/tru64/simple-timing/m5stats.txt | 102 +- .../ref/sparc/linux/simple-atomic/config.ini | 1 + .../ref/sparc/linux/simple-atomic/config.out | 1 + .../ref/sparc/linux/simple-atomic/m5stats.txt | 8 +- .../ref/sparc/linux/simple-atomic/stdout | 4 +- .../ref/sparc/linux/simple-timing/config.ini | 11 +- .../ref/sparc/linux/simple-timing/config.out | 11 +- .../ref/sparc/linux/simple-timing/m5stats.txt | 110 +- .../ref/sparc/linux/simple-timing/stdout | 6 +- .../ref/sparc/linux/simple-atomic/config.ini | 1 + .../ref/sparc/linux/simple-atomic/config.out | 1 + .../ref/sparc/linux/simple-atomic/m5stats.txt | 8 +- .../ref/sparc/linux/simple-atomic/stdout | 4 +- .../ref/sparc/linux/simple-timing/config.ini | 11 +- .../ref/sparc/linux/simple-timing/config.out | 11 +- .../ref/sparc/linux/simple-timing/m5stats.txt | 112 +- .../ref/sparc/linux/simple-timing/stdout | 6 +- .../ref/alpha/tru64/o3-timing/config.ini | 11 +- .../ref/alpha/tru64/o3-timing/config.out | 11 +- .../ref/alpha/tru64/o3-timing/m5stats.txt | 556 +- .../30.eon/ref/alpha/tru64/o3-timing/stdout | 2 +- .../ref/alpha/tru64/simple-atomic/config.ini | 1 + .../ref/alpha/tru64/simple-atomic/config.out | 1 + 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.../ref/alpha/tru64/simple-timing/m5stats.txt | 104 +- .../ref/sparc/linux/simple-atomic/config.ini | 1 + .../ref/sparc/linux/simple-atomic/config.out | 1 + .../ref/sparc/linux/simple-atomic/m5stats.txt | 8 +- .../ref/sparc/linux/simple-atomic/stdout | 4 +- .../ref/sparc/linux/simple-timing/config.ini | 11 +- .../ref/sparc/linux/simple-timing/config.out | 11 +- .../ref/sparc/linux/simple-timing/m5stats.txt | 114 +- .../ref/sparc/linux/simple-timing/stdout | 6 +- .../ref/alpha/tru64/o3-timing/config.ini | 11 +- .../ref/alpha/tru64/o3-timing/config.out | 11 +- .../ref/alpha/tru64/o3-timing/m5stats.txt | 554 +- .../ref/alpha/tru64/simple-atomic/config.ini | 1 + .../ref/alpha/tru64/simple-atomic/config.out | 1 + .../ref/alpha/tru64/simple-atomic/m5stats.txt | 8 +- .../ref/alpha/tru64/simple-timing/config.ini | 11 +- .../ref/alpha/tru64/simple-timing/config.out | 11 +- .../ref/alpha/tru64/simple-timing/m5stats.txt | 104 +- .../ref/alpha/tru64/o3-timing/config.ini | 11 +- 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.../sparc/solaris/t1000-simple-atomic/stderr | 10126 +--------------- .../sparc/solaris/t1000-simple-atomic/stdout | 4 +- .../ref/alpha/linux/o3-timing/config.ini | 11 +- .../ref/alpha/linux/o3-timing/config.out | 11 +- .../ref/alpha/linux/o3-timing/m5stats.txt | 482 +- .../00.hello/ref/alpha/linux/o3-timing/stdout | 8 +- .../ref/alpha/linux/simple-atomic/config.ini | 1 + .../ref/alpha/linux/simple-atomic/config.out | 1 + .../ref/alpha/linux/simple-atomic/m5stats.txt | 8 +- .../ref/alpha/linux/simple-atomic/stdout | 6 +- .../ref/alpha/linux/simple-timing/config.ini | 11 +- .../ref/alpha/linux/simple-timing/config.out | 11 +- .../ref/alpha/linux/simple-timing/m5stats.txt | 100 +- .../ref/alpha/linux/simple-timing/stdout | 8 +- .../ref/alpha/tru64/o3-timing/config.ini | 11 +- .../ref/alpha/tru64/o3-timing/config.out | 11 +- .../ref/alpha/tru64/o3-timing/m5stats.txt | 458 +- .../00.hello/ref/alpha/tru64/o3-timing/stderr | 1 - .../00.hello/ref/alpha/tru64/o3-timing/stdout | 8 +- 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100 +- .../ref/sparc/linux/simple-timing/stdout | 8 +- .../tsunami-simple-atomic-dual/config.ini | 356 +- .../tsunami-simple-atomic-dual/config.out | 327 +- .../tsunami-simple-atomic-dual/m5stats.txt | 592 +- .../linux/tsunami-simple-atomic-dual/stderr | 10 +- .../linux/tsunami-simple-atomic-dual/stdout | 13 +- .../linux/tsunami-simple-atomic/config.ini | 260 +- .../linux/tsunami-simple-atomic/config.out | 241 +- .../linux/tsunami-simple-atomic/m5stats.txt | 299 +- .../alpha/linux/tsunami-simple-atomic/stderr | 4 +- .../alpha/linux/tsunami-simple-atomic/stdout | 13 +- .../tsunami-simple-timing-dual/config.ini | 363 +- .../tsunami-simple-timing-dual/config.out | 334 +- .../tsunami-simple-timing-dual/m5stats.txt | 868 +- .../linux/tsunami-simple-timing-dual/stderr | 10 +- .../linux/tsunami-simple-timing-dual/stdout | 13 +- .../linux/tsunami-simple-timing/config.ini | 267 +- .../linux/tsunami-simple-timing/config.out | 248 +- .../linux/tsunami-simple-timing/m5stats.txt | 404 +- .../alpha/linux/tsunami-simple-timing/stderr | 4 +- .../alpha/linux/tsunami-simple-timing/stdout | 13 +- .../ref/alpha/eio/simple-atomic/config.ini | 1 + .../ref/alpha/eio/simple-atomic/config.out | 1 + .../ref/alpha/eio/simple-atomic/m5stats.txt | 8 +- .../ref/alpha/eio/simple-atomic/stdout | 6 +- .../ref/alpha/eio/simple-timing/config.ini | 11 +- .../ref/alpha/eio/simple-timing/config.out | 11 +- .../ref/alpha/eio/simple-timing/m5stats.txt | 100 +- .../ref/alpha/eio/simple-timing/stdout | 8 +- .../ref/alpha/linux/memtest/config.ini | 29 +- .../ref/alpha/linux/memtest/config.out | 29 +- .../ref/alpha/linux/memtest/m5stats.txt | 1260 +- .../50.memtest/ref/alpha/linux/memtest/stderr | 146 +- .../50.memtest/ref/alpha/linux/memtest/stdout | 8 +- .../twosys-tsunami-simple-atomic/config.ini | 38 +- .../twosys-tsunami-simple-atomic/config.out | 38 +- .../twosys-tsunami-simple-atomic/m5stats.txt | 100 +- .../linux/twosys-tsunami-simple-atomic/stderr | 6 +- .../linux/twosys-tsunami-simple-atomic/stdout | 12 +- 185 files changed, 8398 insertions(+), 15583 deletions(-) diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 2192c0d45..4de44cbb3 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -91,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -267,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -306,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -339,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -363,6 +361,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out index 4c50c2a46..24d41aaa7 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -249,7 +250,7 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -280,14 +281,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -318,14 +318,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -356,7 +355,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -364,4 +362,5 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt index 7e02db19e..21eca8681 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 74294088 # Number of BTB hits -global.BPredUnit.BTBLookups 83217138 # Number of BTB lookups -global.BPredUnit.RASInCorrect 175 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 4320797 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 79655810 # Number of conditional branches predicted -global.BPredUnit.lookups 86600861 # Number of BP lookups -global.BPredUnit.usedRAS 1992384 # Number of times the RAS was used to get a target. -host_inst_rate 121760 # Simulator instruction rate (inst/s) -host_mem_usage 154560 # Number of bytes of host memory used -host_seconds 4644.82 # Real time elapsed on the host -host_tick_rate 28265671 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 20253948 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 12668807 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 134508955 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 44216516 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 65796417 # Number of BTB hits +global.BPredUnit.BTBLookups 73152793 # Number of BTB lookups +global.BPredUnit.RASInCorrect 162 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 4224786 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 70143727 # Number of conditional branches predicted +global.BPredUnit.lookups 75959317 # Number of BP lookups +global.BPredUnit.usedRAS 1707904 # Number of times the RAS was used to get a target. +host_inst_rate 95235 # Simulator instruction rate (inst/s) +host_mem_usage 154544 # Number of bytes of host memory used +host_seconds 5938.47 # Real time elapsed on the host +host_tick_rate 31305923 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 11533351 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 9283325 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 125815870 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 42503953 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated -sim_seconds 0.131289 # Number of seconds simulated -sim_ticks 131288904500 # Number of ticks simulated +sim_seconds 0.185909 # Number of seconds simulated +sim_ticks 185909249000 # Number of ticks simulated system.cpu.commit.COM:branches 62547159 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 25836005 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 21750592 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 248547939 +system.cpu.commit.COM:committed_per_cycle.samples 363164843 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 64112537 2579.48% - 1 73997996 2977.21% - 2 29649485 1192.91% - 3 7413919 298.29% - 4 16299890 655.80% - 5 20436719 822.24% - 6 3362671 135.29% - 7 7438717 299.29% - 8 25836005 1039.48% + 0 150226418 4136.59% + 1 99566964 2741.65% + 2 34056070 937.76% + 3 10333475 284.54% + 4 20301573 559.02% + 5 15829471 435.88% + 6 8882909 244.60% + 7 2217371 61.06% + 8 21750592 598.92% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 115049510 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 154862033 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 4320164 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 4224164 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 94497449 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 52370845 # The number of squashed insts skipped by commit system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.464286 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.464286 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 115538611 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 2723.249468 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2089.628248 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 114910502 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1710497500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.005436 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 628109 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 403470 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 469412000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001944 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 224639 # number of ReadReq MSHR misses +system.cpu.cpi 0.657443 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.657443 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 115591547 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3246.088003 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2434.144734 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 115095381 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 1610598500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.004292 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 496166 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 273177 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 542787500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001929 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 222989 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3076.718619 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2314.396461 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 38683248 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2363144500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.019469 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 768073 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 511246 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 594399500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006510 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 256827 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 539.249147 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 250 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 319.012661 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 1172 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 4 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 632000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 1000 # number of cycles access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 3474.707454 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2824.359825 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 38691611 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 2639770000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.019257 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 759710 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 502007 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 727846000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006532 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 257703 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 427.272727 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 0 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 319.928337 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 1210 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 2 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 517000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 154989932 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2917.701274 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2209.525699 # average overall mshr miss latency -system.cpu.dcache.demand_hits 153593750 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 4073642000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.009008 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1396182 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 914716 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1063811500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003106 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 481466 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 155042868 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3384.385481 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2643.342307 # average overall mshr miss latency +system.cpu.dcache.demand_hits 153786992 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 4250368500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.008100 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1255876 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 775184 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 1270633500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.003100 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 480692 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 154989932 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2917.701274 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2209.525699 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 155042868 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3384.385481 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2643.342307 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 153593750 # number of overall hits -system.cpu.dcache.overall_miss_latency 4073642000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.009008 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1396182 # number of overall misses -system.cpu.dcache.overall_mshr_hits 914716 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1063811500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003106 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 481466 # number of overall MSHR misses +system.cpu.dcache.overall_hits 153786992 # number of overall hits +system.cpu.dcache.overall_miss_latency 4250368500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.008100 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1255876 # number of overall misses +system.cpu.dcache.overall_mshr_hits 775184 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 1270633500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.003100 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 480692 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 477370 # number of replacements -system.cpu.dcache.sampled_refs 481466 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 476596 # number of replacements +system.cpu.dcache.sampled_refs 480692 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.510322 # Cycle average of tags in use -system.cpu.dcache.total_refs 153593750 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 24474000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 338333 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 34835558 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 676 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 4837262 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 747469994 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 87926948 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 115162373 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 14029871 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 2002 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 10623061 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 86600861 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 72219408 # Number of cache lines fetched -system.cpu.fetch.Cycles 200341434 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 435 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 760297798 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 4883794 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.329810 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 72219408 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 76286472 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.895514 # Number of inst fetches per cycle +system.cpu.dcache.tagsinuse 4095.610639 # Cycle average of tags in use +system.cpu.dcache.total_refs 153786992 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 28323000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 338024 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 44010110 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 636 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3910489 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 686828869 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 203536444 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 106139742 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 8653682 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 1958 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 9478548 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 75959317 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 65390933 # Number of cache lines fetched +system.cpu.fetch.Cycles 182129217 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 2901518 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 693889852 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 4411999 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.204291 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 65390933 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 67504321 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.866206 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 262577811 +system.cpu.fetch.rateDist.samples 371818526 system.cpu.fetch.rateDist.min_value 0 - 0 134455787 5120.61% - 1 11289278 429.94% - 2 12199345 464.60% - 3 11605085 441.97% - 4 7894720 300.66% - 5 3823699 145.62% - 6 3913283 149.03% - 7 3555410 135.40% - 8 73841204 2812.16% + 0 255080243 6860.34% + 1 9944321 267.45% + 2 12043396 323.91% + 3 10077209 271.02% + 4 7005486 188.41% + 5 3160802 85.01% + 6 3551742 95.52% + 7 3151910 84.77% + 8 67803417 1823.56% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 72219408 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4241.833509 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3311.810155 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 72218459 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 4025500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 949 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 43 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 3000500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000013 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 906 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 65390933 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5347.983454 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4573.991031 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 65389966 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 5171500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000015 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 967 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 75 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 4080000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 892 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 79711.323400 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 73307.136771 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 72219408 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4241.833509 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3311.810155 # average overall mshr miss latency -system.cpu.icache.demand_hits 72218459 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 4025500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses -system.cpu.icache.demand_misses 949 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 43 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 3000500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000013 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 906 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 65390933 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5347.983454 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4573.991031 # average overall mshr miss latency +system.cpu.icache.demand_hits 65389966 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 5171500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000015 # miss rate for demand accesses +system.cpu.icache.demand_misses 967 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 75 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 4080000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 892 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 72219408 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4241.833509 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3311.810155 # average overall mshr miss latency +system.cpu.icache.overall_accesses 65390933 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5347.983454 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4573.991031 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 72218459 # number of overall hits -system.cpu.icache.overall_miss_latency 4025500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses -system.cpu.icache.overall_misses 949 # number of overall misses -system.cpu.icache.overall_mshr_hits 43 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 3000500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000013 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 906 # number of overall MSHR misses +system.cpu.icache.overall_hits 65389966 # number of overall hits +system.cpu.icache.overall_miss_latency 5171500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000015 # miss rate for overall accesses +system.cpu.icache.overall_misses 967 # number of overall misses +system.cpu.icache.overall_mshr_hits 75 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 4080000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 892 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,63 +215,63 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 34 # number of replacements -system.cpu.icache.sampled_refs 906 # Sample count of references to valid blocks. +system.cpu.icache.replacements 33 # number of replacements +system.cpu.icache.sampled_refs 892 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 774.513861 # Cycle average of tags in use -system.cpu.icache.total_refs 72218459 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 761.711791 # Cycle average of tags in use +system.cpu.icache.total_refs 65389966 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 997 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 69153659 # Number of branches executed -system.cpu.iew.EXEC:nop 45896023 # number of nop insts executed -system.cpu.iew.EXEC:rate 2.341699 # Inst execution rate -system.cpu.iew.EXEC:refs 168426251 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 41748280 # Number of stores executed +system.cpu.idleCycles 2468 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 67136036 # Number of branches executed +system.cpu.iew.EXEC:nop 41949449 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.608660 # Inst execution rate +system.cpu.iew.EXEC:refs 164353457 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 41112797 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 525987328 # num instructions consuming a value -system.cpu.iew.WB:count 611675009 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.792003 # average fanout of values written-back +system.cpu.iew.WB:consumers 478961290 # num instructions consuming a value +system.cpu.iew.WB:count 594114153 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.812310 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 416583352 # num instructions producing a value -system.cpu.iew.WB:rate 2.329500 # insts written-back per cycle -system.cpu.iew.WB:sent 613682130 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 4878985 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 11826 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 134508955 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 2507193 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 44216516 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 696353635 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 126677971 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 11034988 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 614878076 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 389064913 # num instructions producing a value +system.cpu.iew.WB:rate 1.597861 # insts written-back per cycle +system.cpu.iew.WB:sent 594699658 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 4485637 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 10981 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 125815870 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 6586227 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 42503953 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 654225210 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 123240660 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4346710 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 598129643 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 518 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 14029871 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 4036 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 8653682 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 4417 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 4056 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 10594878 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 23131 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 2615 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 7105932 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 1847 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 1076564 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 5809 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 19459445 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 4403993 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 1076564 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 574744 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 4304241 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 2.153847 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.153847 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 625913064 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 296430 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 5860 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 10766360 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 2691430 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 296430 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 519296 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 3966341 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.521044 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.521044 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 602476353 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 0 0.00% # Type of FU issued - IntAlu 452893161 72.36% # Type of FU issued - IntMult 6537 0.00% # Type of FU issued + IntAlu 435905994 72.35% # Type of FU issued + IntMult 6492 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 27 0.00% # Type of FU issued FloatCmp 5 0.00% # Type of FU issued @@ -279,17 +279,17 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 4 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 130507417 20.85% # Type of FU issued - MemWrite 42505908 6.79% # Type of FU issued + MemRead 124769613 20.71% # Type of FU issued + MemWrite 41794213 6.94% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 6267821 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.010014 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 3485464 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.005785 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 5230779 83.45% # attempts to use FU when none available - IntMult 183 0.00% # attempts to use FU when none available + IntAlu 2980889 85.52% # attempts to use FU when none available + IntMult 104 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available FloatCmp 0 0.00% # attempts to use FU when none available @@ -297,80 +297,80 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 663118 10.58% # attempts to use FU when none available - MemWrite 373741 5.96% # attempts to use FU when none available + MemRead 331227 9.50% # attempts to use FU when none available + MemWrite 173244 4.97% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 262577811 +system.cpu.iq.ISSUE:issued_per_cycle.samples 371818526 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 49543053 1886.80% - 1 42653619 1624.42% - 2 65996372 2513.40% - 3 28722982 1093.88% - 4 36210264 1379.03% - 5 20379063 776.12% - 6 16095665 612.99% - 7 2026950 77.19% - 8 949843 36.17% + 0 125625601 3378.68% + 1 89616652 2410.23% + 2 55904072 1503.53% + 3 46310572 1245.52% + 4 27240019 732.62% + 5 12675210 340.90% + 6 11517465 309.76% + 7 2752555 74.03% + 8 176380 4.74% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 2.383724 # Inst issue rate -system.cpu.iq.iqInstsAdded 650457589 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 625913064 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 83477196 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 265708 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 44589775 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 482372 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 5974.559204 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2202.761362 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 456056 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 157226500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.054555 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 26316 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 57967868 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054555 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 26316 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 338333 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 338333 # number of Writeback hits +system.cpu.iq.ISSUE:rate 1.620351 # Inst issue rate +system.cpu.iq.iqInstsAdded 612275739 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 602476353 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 42659982 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 2623 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 5 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 21979774 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 481584 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 6174.721472 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2416.099471 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 455285 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 162389000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.054609 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 26299 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 63541000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054609 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 26299 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 338024 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 338024 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 30.186541 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 30.164987 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 482372 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 5974.559204 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2202.761362 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 456056 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 157226500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.054555 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 26316 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 481584 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 6174.721472 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2416.099471 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 455285 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 162389000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.054609 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 26299 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 57967868 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.054555 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 26316 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 63541000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.054609 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 26299 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 820705 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 5974.559204 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2202.761362 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 819608 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 6174.721472 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2416.099471 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 794389 # number of overall hits -system.cpu.l2cache.overall_miss_latency 157226500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.032065 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 26316 # number of overall misses +system.cpu.l2cache.overall_hits 793309 # number of overall hits +system.cpu.l2cache.overall_miss_latency 162389000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.032087 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 26299 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 57967868 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.032065 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 26316 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 63541000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.032087 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 26299 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -382,31 +382,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 932 # number of replacements -system.cpu.l2cache.sampled_refs 26316 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 931 # number of replacements +system.cpu.l2cache.sampled_refs 26299 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 25073.756706 # Cycle average of tags in use -system.cpu.l2cache.total_refs 794389 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 25071.267749 # Cycle average of tags in use +system.cpu.l2cache.total_refs 793309 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 904 # number of writebacks -system.cpu.numCycles 262577811 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 2682297 # Number of cycles rename is blocking +system.cpu.numCycles 371818526 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 11517489 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 30243185 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 96498295 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1942834 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 952429183 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 727912324 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 552445892 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 117213862 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 14029871 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 32153216 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 88591003 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 270 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 33 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 50706382 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 31 # count of temporary serializing insts renamed -system.cpu.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 32462126 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 206624315 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 21712 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 889109667 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 674900294 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 515718683 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 111518348 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 8653682 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 33504424 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 51863794 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 268 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 59569309 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 24 # count of temporary serializing insts renamed +system.cpu.timesIdled 32 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini index 27aeb9034..e7acc71a6 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out index a8a9148d5..589507187 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt index 7c260dd71..5453dc099 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 964119 # Simulator instruction rate (inst/s) -host_mem_usage 148524 # Number of bytes of host memory used -host_seconds 624.26 # Real time elapsed on the host -host_tick_rate 482059313 # Simulator tick rate (ticks/s) +host_inst_rate 963880 # Simulator instruction rate (inst/s) +host_mem_usage 148548 # Number of bytes of host memory used +host_seconds 624.41 # Real time elapsed on the host +host_tick_rate 481939681 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856965 # Number of instructions simulated sim_seconds 0.300928 # Number of seconds simulated diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini index f70ed5de3..f82815f7b 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out index d4c1bde6e..5cab10662 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt index 5fbf59915..9d4ab211d 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 642291 # Simulator instruction rate (inst/s) -host_mem_usage 153996 # Number of bytes of host memory used -host_seconds 937.05 # Real time elapsed on the host -host_tick_rate 404322160 # Simulator tick rate (ticks/s) +host_inst_rate 494073 # Simulator instruction rate (inst/s) +host_mem_usage 153964 # Number of bytes of host memory used +host_seconds 1218.16 # Real time elapsed on the host +host_tick_rate 624626994 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856965 # Number of instructions simulated -sim_seconds 0.378869 # Number of seconds simulated -sim_ticks 378869140000 # Number of ticks simulated +sim_seconds 0.760893 # Number of seconds simulated +sim_ticks 760892614000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 2584.255983 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1584.255983 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 12040.967639 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11040.967639 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 520035000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 2423028000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 318803000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2221796000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2608.788455 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 1608.788455 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 12166.766996 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11166.766996 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 39197158 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 663057500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 3092342000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.006442 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 254163 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 408894500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2838179000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2597.947935 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 1597.947935 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 12111.178208 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 11111.178208 # average overall mshr miss latency system.cpu.dcache.demand_hits 153509968 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1183092500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 5515370000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002958 # miss rate for demand accesses system.cpu.dcache.demand_misses 455395 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 727697500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5059975000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2597.947935 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 1597.947935 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 12111.178208 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 11111.178208 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 153509968 # number of overall hits -system.cpu.dcache.overall_miss_latency 1183092500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 5515370000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002958 # miss rate for overall accesses system.cpu.dcache.overall_misses 455395 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 727697500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5059975000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 451299 # number of replacements system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.423304 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.250869 # Cycle average of tags in use system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 102411000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 257148000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 325723 # number of writebacks system.cpu.icache.ReadReq_accesses 601856966 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3746.540881 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2746.540881 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13969.811321 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12969.811321 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 601856171 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 2978500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 11106000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 2183500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 10311000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 601856966 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3746.540881 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2746.540881 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13969.811321 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12969.811321 # average overall mshr miss latency system.cpu.icache.demand_hits 601856171 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 2978500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 11106000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses system.cpu.icache.demand_misses 795 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2183500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 10311000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 601856966 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3746.540881 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2746.540881 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13969.811321 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12969.811321 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 601856171 # number of overall hits -system.cpu.icache.overall_miss_latency 2978500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 11106000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses system.cpu.icache.overall_misses 795 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2183500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 10311000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 24 # number of replacements system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 674.110982 # Cycle average of tags in use +system.cpu.icache.tagsinuse 673.943506 # Cycle average of tags in use system.cpu.icache.total_refs 601856171 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 456190 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2564.564334 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1563.181738 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 430092 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 66930000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 339274000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.057209 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 26098 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 40795917 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 287078000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.057209 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 26098 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 325723 # number of Writeback accesses(hits+misses) @@ -164,29 +164,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2564.564334 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1563.181738 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 430092 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 66930000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 339274000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.057209 # miss rate for demand accesses system.cpu.l2cache.demand_misses 26098 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 40795917 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 287078000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.057209 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 26098 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 781913 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2564.564334 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1563.181738 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 755815 # number of overall hits -system.cpu.l2cache.overall_miss_latency 66930000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 339274000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.033377 # miss rate for overall accesses system.cpu.l2cache.overall_misses 26098 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 40795917 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 287078000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.033377 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 26098 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -203,12 +203,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 903 # number of replacements system.cpu.l2cache.sampled_refs 26098 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 24878.910085 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 24875.090462 # Cycle average of tags in use system.cpu.l2cache.total_refs 755815 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 883 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 378869140000 # number of cpu cycles simulated +system.cpu.numCycles 760892614000 # number of cpu cycles simulated system.cpu.num_insts 601856965 # Number of instructions executed system.cpu.num_refs 154862034 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini index 0a5320e76..144c9c7fe 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.out b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.out index 24b104442..9c608a7e6 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.out +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt index c58a162a3..bdafc8603 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 687229 # Simulator instruction rate (inst/s) -host_mem_usage 149588 # Number of bytes of host memory used -host_seconds 2167.42 # Real time elapsed on the host -host_tick_rate 343614381 # Simulator tick rate (ticks/s) +host_inst_rate 723585 # Simulator instruction rate (inst/s) +host_mem_usage 149576 # Number of bytes of host memory used +host_seconds 2058.52 # Real time elapsed on the host +host_tick_rate 361792205 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489514860 # Number of instructions simulated sim_seconds 0.744757 # Number of seconds simulated diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout index bf28090fa..b335083d4 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout @@ -36,8 +36,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 27 2007 14:35:32 -M5 started Fri Apr 27 14:35:40 2007 +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 13:02:33 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic tests/run.py long/00.gzip/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini index 52243641a..ad1db1010 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.out b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.out index bcc607b12..d8a055b90 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.out +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt index 5a976b1e5..fc8b89b1e 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 510352 # Simulator instruction rate (inst/s) -host_mem_usage 155048 # Number of bytes of host memory used -host_seconds 2918.60 # Real time elapsed on the host -host_tick_rate 353062922 # Simulator tick rate (ticks/s) +host_inst_rate 529254 # Simulator instruction rate (inst/s) +host_mem_usage 154916 # Number of bytes of host memory used +host_seconds 2814.36 # Real time elapsed on the host +host_tick_rate 733354350 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489514860 # Number of instructions simulated -sim_seconds 1.030450 # Number of seconds simulated -sim_ticks 1030449926500 # Number of ticks simulated +sim_seconds 2.063927 # Number of seconds simulated +sim_ticks 2063926516000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 402511688 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 2729.300186 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1729.300186 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 12044.273310 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11044.273310 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 402318208 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 528065000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 2330326000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 193480 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 334585000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2136846000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 193480 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 3071.428571 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2071.428571 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 12285.714286 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 11285.714286 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 21500 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 86000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 14500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 79000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 166846642 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2724.587576 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 1724.587576 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 12168.472925 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11168.472925 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 166586897 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 707698000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 3160700000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.001557 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 259745 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 447953000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2900955000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.001557 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 259745 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 569358330 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2726.599371 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 1726.599371 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 12115.452590 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 11115.452590 # average overall mshr miss latency system.cpu.dcache.demand_hits 568905105 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1235763000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 5491026000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000796 # miss rate for demand accesses system.cpu.dcache.demand_misses 453225 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 782538000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5037801000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000796 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 453225 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 569358330 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2726.599371 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 1726.599371 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 12115.452590 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 11115.452590 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 568905105 # number of overall hits -system.cpu.dcache.overall_miss_latency 1235763000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 5491026000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000796 # miss rate for overall accesses system.cpu.dcache.overall_misses 453225 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 782538000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5037801000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000796 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 453225 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 449136 # number of replacements system.cpu.dcache.sampled_refs 453232 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.694265 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.630445 # Cycle average of tags in use system.cpu.dcache.total_refs 568906424 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 112631000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 274426000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 316447 # number of writebacks system.cpu.icache.ReadReq_accesses 1489514861 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3687.613843 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2687.613843 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13859.744991 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12859.744991 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 1489513763 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 4049000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 15218000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 1098 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 2951000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 14120000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 1098 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1489514861 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3687.613843 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2687.613843 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13859.744991 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12859.744991 # average overall mshr miss latency system.cpu.icache.demand_hits 1489513763 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 4049000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 15218000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses system.cpu.icache.demand_misses 1098 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2951000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 14120000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 1098 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 1489514861 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3687.613843 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2687.613843 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13859.744991 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12859.744991 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1489513763 # number of overall hits -system.cpu.icache.overall_miss_latency 4049000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 15218000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses system.cpu.icache.overall_misses 1098 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2951000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 14120000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 1098 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -148,19 +148,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 115 # number of replacements system.cpu.icache.sampled_refs 1098 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 891.763656 # Cycle average of tags in use +system.cpu.icache.tagsinuse 891.684170 # Cycle average of tags in use system.cpu.icache.total_refs 1489513763 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 454330 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2631.120103 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1629.899651 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 427145 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 71527000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 353405000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.059835 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 27185 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 44308822 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 299035000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.059835 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 27185 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 316447 # number of Writeback accesses(hits+misses) @@ -178,29 +178,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 454330 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2631.120103 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1629.899651 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 427145 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 71527000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 353405000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.059835 # miss rate for demand accesses system.cpu.l2cache.demand_misses 27185 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 44308822 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 299035000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.059835 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 27185 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 770777 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2630.249320 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1629.899651 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 12995.697580 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 743583 # number of overall hits -system.cpu.l2cache.overall_miss_latency 71527000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 353405000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.035281 # miss rate for overall accesses system.cpu.l2cache.overall_misses 27194 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 44308822 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 299035000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.035270 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 27185 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -217,12 +217,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 2632 # number of replacements system.cpu.l2cache.sampled_refs 27185 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 24268.399126 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 24267.041661 # Cycle average of tags in use system.cpu.l2cache.total_refs 743583 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 2531 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1030449926500 # number of cpu cycles simulated +system.cpu.numCycles 2063926516000 # number of cpu cycles simulated system.cpu.num_insts 1489514860 # Number of instructions executed system.cpu.num_refs 569359656 # Number of memory references system.cpu.workload.PROG:num_syscalls 19 # Number of system calls diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout index 6f0bc150a..3741c6499 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout @@ -36,9 +36,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 27 2007 14:35:32 -M5 started Fri Apr 27 14:35:40 2007 +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 13:36:53 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing tests/run.py long/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1030449926500 because target called exit() +Exiting @ tick 2063926516000 because target called exit() diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini index 368feb9a9..9b8d69888 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.out b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.out index 24228b2bd..8a5c9fd62 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.out +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt index 7e603ae8c..530572b5d 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 658093 # Simulator instruction rate (inst/s) -host_mem_usage 149896 # Number of bytes of host memory used -host_seconds 2613.00 # Real time elapsed on the host -host_tick_rate 329046277 # Simulator tick rate (ticks/s) +host_inst_rate 686638 # Simulator instruction rate (inst/s) +host_mem_usage 149820 # Number of bytes of host memory used +host_seconds 2504.37 # Real time elapsed on the host +host_tick_rate 343319148 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1719594534 # Number of instructions simulated sim_seconds 0.859797 # Number of seconds simulated diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout index f52ad5eac..bd861b307 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout @@ -25,8 +25,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 27 2007 14:35:32 -M5 started Fri Apr 27 15:11:49 2007 +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 14:23:47 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic tests/run.py long/10.mcf/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini index 6e102e359..9beb527ea 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out index 970fa6992..5d5cc71c1 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt index 988dc8a7f..c95331047 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 462859 # Simulator instruction rate (inst/s) -host_mem_usage 155288 # Number of bytes of host memory used -host_seconds 3715.16 # Real time elapsed on the host -host_tick_rate 345995852 # Simulator tick rate (ticks/s) +host_inst_rate 480485 # Simulator instruction rate (inst/s) +host_mem_usage 155316 # Number of bytes of host memory used +host_seconds 3578.87 # Real time elapsed on the host +host_tick_rate 745845171 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1719594534 # Number of instructions simulated -sim_seconds 1.285430 # Number of seconds simulated -sim_ticks 1285429818500 # Number of ticks simulated +sim_seconds 2.669285 # Number of seconds simulated +sim_ticks 2669284585000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 607807189 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3129.930590 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2129.930590 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 12893.226605 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11893.226605 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 594739458 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 40901091000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 168485217000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.021500 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 13067731 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 27833360000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 155417486000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.021500 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 13067731 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 15448 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 3090.909091 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2090.909091 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 13090.909091 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 12090.909091 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 15437 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 34000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 144000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.000712 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 11 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 23000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 133000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.000712 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 11 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 166970997 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2764.531806 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 1764.531806 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 12404.292450 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11404.292450 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 165264000 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4719047500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 21174090000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.010223 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1706997 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 3012050500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 19467093000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.010223 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1706997 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 774778186 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3087.714271 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2087.714271 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 12836.737637 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 11836.737637 # average overall mshr miss latency system.cpu.dcache.demand_hits 760003458 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 45620138500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 189659307000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.019070 # miss rate for demand accesses system.cpu.dcache.demand_misses 14774728 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 30845410500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 174884579000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.019070 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 14774728 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 774778186 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3087.714271 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2087.714271 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 12836.737637 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 11836.737637 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 760003458 # number of overall hits -system.cpu.dcache.overall_miss_latency 45620138500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 189659307000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.019070 # miss rate for overall accesses system.cpu.dcache.overall_misses 14774728 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 30845410500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 174884579000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.019070 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 14774728 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 14770643 # number of replacements system.cpu.dcache.sampled_refs 14774739 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.607725 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.628585 # Cycle average of tags in use system.cpu.dcache.total_refs 760018895 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1932183000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 3913237000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 4191356 # number of writebacks system.cpu.icache.ReadReq_accesses 1719594535 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3753.607103 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2753.607103 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13991.120977 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12991.120977 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 1719593634 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 3382000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 12606000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 901 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 2481000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 11705000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 901 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1719594535 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3753.607103 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2753.607103 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13991.120977 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12991.120977 # average overall mshr miss latency system.cpu.icache.demand_hits 1719593634 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 3382000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 12606000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses system.cpu.icache.demand_misses 901 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2481000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 11705000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 901 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 1719594535 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3753.607103 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2753.607103 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13991.120977 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12991.120977 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1719593634 # number of overall hits -system.cpu.icache.overall_miss_latency 3382000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 12606000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses system.cpu.icache.overall_misses 901 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2481000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 11705000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 901 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -148,19 +148,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 31 # number of replacements system.cpu.icache.sampled_refs 901 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 737.434314 # Cycle average of tags in use +system.cpu.icache.tagsinuse 737.715884 # Cycle average of tags in use system.cpu.icache.total_refs 1719593634 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 14775639 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2607.028468 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1605.780536 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 12999.785859 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 10999.785859 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 8592784 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 16118879000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 80375791000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.418449 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 6182855 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 9928308213 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 68010081000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.418449 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 6182855 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 4191356 # number of Writeback accesses(hits+misses) @@ -178,29 +178,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 14775639 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2607.028468 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1605.780536 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 12999.785859 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 10999.785859 # average overall mshr miss latency system.cpu.l2cache.demand_hits 8592784 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 16118879000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 80375791000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.418449 # miss rate for demand accesses system.cpu.l2cache.demand_misses 6182855 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 9928308213 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 68010081000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.418449 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 6182855 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 18966995 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2595.599252 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1605.780536 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 12942.794779 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 10999.785859 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 12756915 # number of overall hits -system.cpu.l2cache.overall_miss_latency 16118879000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 80375791000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.327415 # miss rate for overall accesses system.cpu.l2cache.overall_misses 6210080 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 9928308213 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 68010081000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.325980 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 6182855 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -217,12 +217,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 6150087 # number of replacements system.cpu.l2cache.sampled_refs 6182855 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 26097.875810 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 26129.060966 # Cycle average of tags in use system.cpu.l2cache.total_refs 12756915 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 390549075000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 806915893000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 1069081 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1285429818500 # number of cpu cycles simulated +system.cpu.numCycles 2669284585000 # number of cpu cycles simulated system.cpu.num_insts 1719594534 # Number of instructions executed system.cpu.num_refs 774793634 # Number of memory references system.cpu.workload.PROG:num_syscalls 632 # Number of system calls diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout index d1c7d6062..272fc2ce1 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout @@ -25,9 +25,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 27 2007 14:35:32 -M5 started Fri Apr 27 15:24:20 2007 +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 15:05:32 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing tests/run.py long/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1285429818500 because target called exit() +Exiting @ tick 2669284585000 because target called exit() diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini index 29e352b0e..af33f850b 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -91,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -267,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -306,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -339,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -363,6 +361,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out index c04c0d11b..cea0c0402 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -249,7 +250,7 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -280,14 +281,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -318,14 +318,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -356,7 +355,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -364,4 +362,5 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt index ce046cea7..f3f9842a2 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,112 +1,112 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 38358431 # Number of BTB hits -global.BPredUnit.BTBLookups 50162851 # Number of BTB lookups -global.BPredUnit.RASInCorrect 1146 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 6112182 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 38942362 # Number of conditional branches predicted -global.BPredUnit.lookups 68824046 # Number of BP lookups -global.BPredUnit.usedRAS 14094584 # Number of times the RAS was used to get a target. -host_inst_rate 88313 # Simulator instruction rate (inst/s) -host_mem_usage 157144 # Number of bytes of host memory used -host_seconds 4252.75 # Real time elapsed on the host -host_tick_rate 26084457 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 79078987 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 58020753 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 131723270 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 96432918 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 36408912 # Number of BTB hits +global.BPredUnit.BTBLookups 43706931 # Number of BTB lookups +global.BPredUnit.RASInCorrect 1105 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 5391565 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 33884568 # Number of conditional branches predicted +global.BPredUnit.lookups 59377619 # Number of BP lookups +global.BPredUnit.usedRAS 11768977 # Number of times the RAS was used to get a target. +host_inst_rate 72337 # Simulator instruction rate (inst/s) +host_mem_usage 157124 # Number of bytes of host memory used +host_seconds 5192.02 # Real time elapsed on the host +host_tick_rate 28301038 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 55015552 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 43012918 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 120933927 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 90962569 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 375574812 # Number of instructions simulated -sim_seconds 0.110931 # Number of seconds simulated -sim_ticks 110930737500 # Number of ticks simulated -system.cpu.commit.COM:branches 44587533 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 15191652 # number cycles where commit BW limit reached +sim_insts 375574819 # Number of instructions simulated +sim_seconds 0.146939 # Number of seconds simulated +sim_ticks 146939447000 # Number of ticks simulated +system.cpu.commit.COM:branches 44587532 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 12019969 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 203296876 +system.cpu.commit.COM:committed_per_cycle.samples 280687503 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 83055980 4085.45% - 1 37801777 1859.44% - 2 20090473 988.23% - 3 18525905 911.27% - 4 11216575 551.73% - 5 8853752 435.51% - 6 5489461 270.02% - 7 3071301 151.07% - 8 15191652 747.26% + 0 153383398 5464.56% + 1 43042738 1533.48% + 2 19983570 711.95% + 3 20747693 739.17% + 4 12078292 430.31% + 5 11042042 393.39% + 6 5000100 178.14% + 7 3389701 120.76% + 8 12019969 428.23% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 398664587 # Number of instructions committed +system.cpu.commit.COM:count 398664594 # Number of instructions committed system.cpu.commit.COM:loads 100651995 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 174183397 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 6107953 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 398664587 # The number of committed instructions +system.cpu.commit.branchMispredicts 5387368 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 398664594 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 122897297 # The number of squashed insts skipped by commit -system.cpu.committedInsts 375574812 # Number of Instructions Simulated -system.cpu.committedInsts_total 375574812 # Number of Instructions Simulated -system.cpu.cpi 0.590725 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.590725 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 96817111 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 4478.552279 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3669.007021 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 96815619 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 6682000 # number of ReadReq miss cycles +system.cpu.commit.commitSquashedInsts 80492961 # The number of squashed insts skipped by commit +system.cpu.committedInsts 375574819 # Number of Instructions Simulated +system.cpu.committedInsts_total 375574819 # Number of Instructions Simulated +system.cpu.cpi 0.782478 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.782478 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 96341397 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5402.232747 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4689.672802 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 96339919 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 7984500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000015 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1492 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 495 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 3658000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 1478 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 500 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 4586500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 997 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 978 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 4580.037179 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3751.017852 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 73511046 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 44348500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000132 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 9683 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 6490 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 11977000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 5858.789942 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4984.052533 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 73511622 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 53356000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000124 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 9107 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 5909 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 15939000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 3193 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 3198 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 40650.755370 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 40673.261734 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 170337840 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 4566.487696 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3731.503580 # average overall mshr miss latency -system.cpu.dcache.demand_hits 170326665 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 51030500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000066 # miss rate for demand accesses -system.cpu.dcache.demand_misses 11175 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 6985 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 15635000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_accesses 169862126 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 5795.040151 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4915.110153 # average overall mshr miss latency +system.cpu.dcache.demand_hits 169851541 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 61340500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000062 # miss rate for demand accesses +system.cpu.dcache.demand_misses 10585 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 6409 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 20525500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 4190 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 4176 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 170337840 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 4566.487696 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3731.503580 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 169862126 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 5795.040151 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4915.110153 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 170326665 # number of overall hits -system.cpu.dcache.overall_miss_latency 51030500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000066 # miss rate for overall accesses -system.cpu.dcache.overall_misses 11175 # number of overall misses -system.cpu.dcache.overall_mshr_hits 6985 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 15635000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_hits 169851541 # number of overall hits +system.cpu.dcache.overall_miss_latency 61340500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000062 # miss rate for overall accesses +system.cpu.dcache.overall_misses 10585 # number of overall misses +system.cpu.dcache.overall_mshr_hits 6409 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 20525500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 4190 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 4176 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 787 # number of replacements -system.cpu.dcache.sampled_refs 4190 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 781 # number of replacements +system.cpu.dcache.sampled_refs 4176 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3304.118717 # Cycle average of tags in use -system.cpu.dcache.total_refs 170326665 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3294.483088 # Cycle average of tags in use +system.cpu.dcache.total_refs 169851541 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 642 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 19129336 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 4391 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 12122968 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 582055742 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 80258799 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 100428895 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 18564601 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 12469 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 3479847 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 68824046 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 70113587 # Number of cache lines fetched -system.cpu.fetch.Cycles 177754526 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1413 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 605291130 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 6551564 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.310212 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 70113587 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 52453015 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.728239 # Number of inst fetches per cycle +system.cpu.dcache.writebacks 637 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 7091571 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 4262 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 10528111 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 508290393 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 182764130 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 90473414 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 13191511 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 12840 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 358389 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 59377619 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 61063139 # Number of cache lines fetched +system.cpu.fetch.Cycles 154416855 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 2298760 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 522129068 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 5723447 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.202048 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 61063139 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 48177889 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.776680 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 221861478 +system.cpu.fetch.rateDist.samples 293879015 system.cpu.fetch.rateDist.min_value 0 - 0 114220541 5148.28% - 1 8239331 371.37% - 2 8549373 385.35% - 3 6969058 314.12% - 4 16046109 723.25% - 5 8875051 400.03% - 6 9195050 414.45% - 7 2819832 127.10% - 8 46947133 2116.06% + 0 200525300 6823.40% + 1 7846897 267.01% + 2 7291722 248.12% + 3 6200462 210.99% + 4 13845529 471.13% + 5 7438768 253.12% + 6 7492914 254.97% + 7 2335483 79.47% + 8 40901940 1391.80% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 70113587 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3851.773227 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2889.186432 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 70109583 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15422500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000057 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 4004 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 83 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11328500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000056 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 3921 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 61063139 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5151.654640 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4230.492813 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 61059120 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 20704500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000066 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 4019 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 123 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 16482000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000064 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 3896 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 17880.536343 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 15672.258727 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 70113587 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3851.773227 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2889.186432 # average overall mshr miss latency -system.cpu.icache.demand_hits 70109583 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15422500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000057 # miss rate for demand accesses -system.cpu.icache.demand_misses 4004 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 83 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11328500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000056 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 3921 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 61063139 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5151.654640 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4230.492813 # average overall mshr miss latency +system.cpu.icache.demand_hits 61059120 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 20704500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000066 # miss rate for demand accesses +system.cpu.icache.demand_misses 4019 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 123 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 16482000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000064 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 3896 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 70113587 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3851.773227 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2889.186432 # average overall mshr miss latency +system.cpu.icache.overall_accesses 61063139 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5151.654640 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4230.492813 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 70109583 # number of overall hits -system.cpu.icache.overall_miss_latency 15422500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000057 # miss rate for overall accesses -system.cpu.icache.overall_misses 4004 # number of overall misses -system.cpu.icache.overall_mshr_hits 83 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11328500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000056 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 3921 # number of overall MSHR misses +system.cpu.icache.overall_hits 61059120 # number of overall hits +system.cpu.icache.overall_miss_latency 20704500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000066 # miss rate for overall accesses +system.cpu.icache.overall_misses 4019 # number of overall misses +system.cpu.icache.overall_mshr_hits 123 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 16482000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000064 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 3896 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,162 +215,162 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 1998 # number of replacements -system.cpu.icache.sampled_refs 3921 # Sample count of references to valid blocks. +system.cpu.icache.replacements 1976 # number of replacements +system.cpu.icache.sampled_refs 3896 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1828.295849 # Cycle average of tags in use -system.cpu.icache.total_refs 70109583 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1822.947356 # Cycle average of tags in use +system.cpu.icache.total_refs 61059120 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles -2 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 52992725 # Number of branches executed -system.cpu.iew.EXEC:nop 29946505 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.944645 # Inst execution rate -system.cpu.iew.EXEC:refs 194719104 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 80042784 # Number of stores executed +system.cpu.idleCycles 6367 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 50329288 # Number of branches executed +system.cpu.iew.EXEC:nop 26718868 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.409679 # Inst execution rate +system.cpu.iew.EXEC:refs 190324589 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 79889528 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 297392817 # num instructions consuming a value -system.cpu.iew.WB:count 427980775 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.704330 # average fanout of values written-back +system.cpu.iew.WB:consumers 266244037 # num instructions consuming a value +system.cpu.iew.WB:count 411128901 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.717332 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 209462789 # num instructions producing a value -system.cpu.iew.WB:rate 1.929045 # insts written-back per cycle -system.cpu.iew.WB:sent 430386834 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 6770153 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 2285856 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 131723270 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 248 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 6165269 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 96432918 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 521561792 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 114676320 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 13198323 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 431441879 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 131901 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 190985280 # num instructions producing a value +system.cpu.iew.WB:rate 1.398973 # insts written-back per cycle +system.cpu.iew.WB:sent 411485990 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 6032644 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 1137801 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 120933927 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 222 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 6771454 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 90962569 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 479157588 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 110435061 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10298797 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 414275208 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 67 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 25295 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 18564601 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 554549 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 21083 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 13191511 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 115109 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 10646448 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 56371 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 7097511 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 3223 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 636490 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 215134 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 31071275 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 22901516 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 636490 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 1000963 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 5769190 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.692835 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.692835 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 444640202 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 404889 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 176320 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 20281932 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 17431167 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 404889 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 802823 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 5229821 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.277991 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.277991 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 424574005 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 33581 0.01% # Type of FU issued - IntAlu 177043734 39.82% # Type of FU issued - IntMult 2204532 0.50% # Type of FU issued + IntAlu 163144501 38.43% # Type of FU issued + IntMult 2125088 0.50% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 36105087 8.12% # Type of FU issued - FloatCmp 7997969 1.80% # Type of FU issued - FloatCvt 3013999 0.68% # Type of FU issued - FloatMult 17176525 3.86% # Type of FU issued - FloatDiv 1578480 0.36% # Type of FU issued + FloatAdd 34659405 8.16% # Type of FU issued + FloatCmp 7790033 1.83% # Type of FU issued + FloatCvt 2881594 0.68% # Type of FU issued + FloatMult 16618307 3.91% # Type of FU issued + FloatDiv 1566111 0.37% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 116850777 26.28% # Type of FU issued - MemWrite 82635518 18.58% # Type of FU issued + MemRead 113765764 26.80% # Type of FU issued + MemWrite 81989621 19.31% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 12556872 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.028241 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 9576176 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.022555 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 57761 0.46% # attempts to use FU when none available + IntAlu 12415 0.13% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 28133 0.22% # attempts to use FU when none available - FloatCmp 21849 0.17% # attempts to use FU when none available - FloatCvt 3461 0.03% # attempts to use FU when none available - FloatMult 3478872 27.70% # attempts to use FU when none available - FloatDiv 916669 7.30% # attempts to use FU when none available + FloatAdd 46832 0.49% # attempts to use FU when none available + FloatCmp 11338 0.12% # attempts to use FU when none available + FloatCvt 25702 0.27% # attempts to use FU when none available + FloatMult 2984764 31.17% # attempts to use FU when none available + FloatDiv 331535 3.46% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 6621449 52.73% # attempts to use FU when none available - MemWrite 1428678 11.38% # attempts to use FU when none available + MemRead 4942933 51.62% # attempts to use FU when none available + MemWrite 1220657 12.75% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 221861478 +system.cpu.iq.ISSUE:issued_per_cycle.samples 293879015 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 66879354 3014.46% - 1 37689855 1698.80% - 2 36617552 1650.47% - 3 29239458 1317.92% - 4 27293259 1230.19% - 5 13755301 620.00% - 6 5789291 260.94% - 7 3467682 156.30% - 8 1129726 50.92% + 0 129735390 4414.59% + 1 52072154 1771.89% + 2 39787134 1353.86% + 3 29621395 1007.95% + 4 21763636 740.56% + 5 12600620 428.77% + 6 4911147 167.11% + 7 2561440 87.16% + 8 826099 28.11% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 2.004134 # Inst issue rate -system.cpu.iq.iqInstsAdded 491615039 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 444640202 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 248 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 114649126 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 1134366 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 33 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 83844967 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 8108 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3327.551159 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1909.064236 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 729 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 24554000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.910089 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 7379 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 14086985 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.910089 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 7379 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 642 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 642 # number of Writeback hits +system.cpu.iq.ISSUE:rate 1.444724 # Inst issue rate +system.cpu.iq.iqInstsAdded 452438498 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 424574005 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 222 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 75756994 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 1109878 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 55099010 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 8070 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4677.770224 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2436.233855 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 715 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 34405000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.911400 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 7355 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 17918500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.911400 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 7355 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 637 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 637 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.185798 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.183821 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 8108 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3327.551159 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1909.064236 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 729 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 24554000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.910089 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 7379 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 8070 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4677.770224 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2436.233855 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 715 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 34405000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.911400 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 7355 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 14086985 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.910089 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 7379 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 17918500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.911400 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 7355 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 8750 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3327.551159 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1909.064236 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 8707 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4677.770224 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2436.233855 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1371 # number of overall hits -system.cpu.l2cache.overall_miss_latency 24554000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.843314 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 7379 # number of overall misses +system.cpu.l2cache.overall_hits 1352 # number of overall hits +system.cpu.l2cache.overall_miss_latency 34405000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.844723 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 7355 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 14086985 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.843314 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 7379 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 17918500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.844723 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 7355 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -383,30 +383,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 7379 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 7355 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 6669.459869 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1371 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 6644.823451 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1352 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 221861478 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 6569281 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 259532333 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1971772 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 86889182 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 8681438 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 731270765 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 559458182 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 360795698 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 96896401 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 18564601 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 12635219 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 101263365 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 306794 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 37801 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 32486829 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 267 # count of temporary serializing insts renamed -system.cpu.timesIdled 2 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.numCycles 293879015 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 3715266 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 259532341 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 115195 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 185747540 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2602652 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 654991501 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 496454048 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 320284080 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 87805227 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 13191511 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 3048084 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 60751739 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 371387 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 37057 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 7965999 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 243 # count of temporary serializing insts renamed +system.cpu.timesIdled 133 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout index 68b00def4..50ed34325 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout @@ -1,2 +1,2 @@ Eon, Version 1.1 -OO-style eon Time= 0.100000 +OO-style eon Time= 0.133333 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini index ba3b61431..58022eaf1 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out index de3317258..b7319250f 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt index 3892be109..2e2beec40 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 844104 # Simulator instruction rate (inst/s) +host_inst_rate 828868 # Simulator instruction rate (inst/s) host_mem_usage 151076 # Number of bytes of host memory used -host_seconds 472.29 # Real time elapsed on the host -host_tick_rate 422051705 # Simulator tick rate (ticks/s) +host_seconds 480.97 # Real time elapsed on the host +host_tick_rate 414433819 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664597 # Number of instructions simulated sim_seconds 0.199332 # Number of seconds simulated diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini index bc260bf15..ca3706b7b 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out index 0a9655414..c3af4f4b3 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt index 552adff15..28c7cc183 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,65 +1,65 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 557007 # Simulator instruction rate (inst/s) -host_mem_usage 156576 # Number of bytes of host memory used -host_seconds 715.73 # Real time elapsed on the host -host_tick_rate 396092779 # Simulator tick rate (ticks/s) +host_inst_rate 579996 # Simulator instruction rate (inst/s) +host_mem_usage 156556 # Number of bytes of host memory used +host_seconds 687.36 # Real time elapsed on the host +host_tick_rate 824955659 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 398664597 # Number of instructions simulated -sim_seconds 0.283494 # Number of seconds simulated -sim_ticks 283494379000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 94754489 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3630.526316 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2630.526316 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 94753539 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3449000 # number of ReadReq miss cycles +sim_insts 398664611 # Number of instructions simulated +sim_seconds 0.567040 # Number of seconds simulated +sim_ticks 567040254000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 94754490 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 13741.052632 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12741.052632 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 94753540 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 13054000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 950 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2499000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 12104000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3618.988132 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2618.988132 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 73517527 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 11588000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses 73520730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 13962.523423 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12962.523423 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 73517528 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 44708000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000044 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 3202 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 8386000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 41506000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 3202 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 40527.713391 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 168275218 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3621.628131 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2621.628131 # average overall mshr miss latency -system.cpu.dcache.demand_hits 168271066 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 15037000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 168275220 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 13911.849711 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12911.849711 # average overall mshr miss latency +system.cpu.dcache.demand_hits 168271068 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 57762000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses system.cpu.dcache.demand_misses 4152 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 10885000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 53610000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 168275218 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3621.628131 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2621.628131 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 168275220 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 13911.849711 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12911.849711 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 168271066 # number of overall hits -system.cpu.dcache.overall_miss_latency 15037000 # number of overall miss cycles +system.cpu.dcache.overall_hits 168271068 # number of overall hits +system.cpu.dcache.overall_miss_latency 57762000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_misses 4152 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 10885000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 53610000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,52 +76,52 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 764 # number of replacements system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3289.772430 # Cycle average of tags in use -system.cpu.dcache.total_refs 168271066 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3289.654807 # Cycle average of tags in use +system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 625 # number of writebacks -system.cpu.icache.ReadReq_accesses 398664598 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3633.814321 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2633.814321 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 398660925 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 13347000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 398664612 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 13745.167438 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12745.167438 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 398660939 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 50486000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 3673 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 9674000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 46813000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 3673 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 108538.231691 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 108538.235502 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 398664598 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3633.814321 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2633.814321 # average overall mshr miss latency -system.cpu.icache.demand_hits 398660925 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 13347000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 398664612 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 13745.167438 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12745.167438 # average overall mshr miss latency +system.cpu.icache.demand_hits 398660939 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 50486000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses system.cpu.icache.demand_misses 3673 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 9674000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 46813000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000009 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 3673 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 398664598 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3633.814321 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2633.814321 # average overall mshr miss latency +system.cpu.icache.overall_accesses 398664612 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 13745.167438 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12745.167438 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 398660925 # number of overall hits -system.cpu.icache.overall_miss_latency 13347000 # number of overall miss cycles +system.cpu.icache.overall_hits 398660939 # number of overall hits +system.cpu.icache.overall_miss_latency 50486000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses system.cpu.icache.overall_misses 3673 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 9674000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 46813000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 3673 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 1769 # number of replacements system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1795.510184 # Cycle average of tags in use -system.cpu.icache.total_refs 398660925 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1795.458615 # Cycle average of tags in use +system.cpu.icache.total_refs 398660939 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 7825 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2707.276275 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1705.023697 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 651 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 19422000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 93262000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.916805 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 7174 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12231840 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 78914000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.916805 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 7174 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses) @@ -164,29 +164,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2707.276275 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1705.023697 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 651 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 19422000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 93262000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.916805 # miss rate for demand accesses system.cpu.l2cache.demand_misses 7174 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 12231840 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 78914000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.916805 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 7174 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 8450 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2707.276275 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1705.023697 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1276 # number of overall hits -system.cpu.l2cache.overall_miss_latency 19422000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 93262000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.848994 # miss rate for overall accesses system.cpu.l2cache.overall_misses 7174 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 12231840 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 78914000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.848994 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 7174 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -203,14 +203,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 7174 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 6483.699084 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 6483.455048 # Cycle average of tags in use system.cpu.l2cache.total_refs 1276 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 283494379000 # number of cpu cycles simulated -system.cpu.num_insts 398664597 # Number of instructions executed -system.cpu.num_refs 174183399 # Number of memory references +system.cpu.numCycles 567040254000 # number of cpu cycles simulated +system.cpu.num_insts 398664611 # Number of instructions executed +system.cpu.num_refs 174183401 # Number of memory references system.cpu.workload.PROG:num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout index 1e8a0ac6f..f9d497506 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout @@ -1,2 +1,2 @@ Eon, Version 1.1 -OO-style eon Time= 0.283333 +OO-style eon Time= 0.566667 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini index dc1116a7e..1b858fca2 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out index ef449bf6d..0e4ea1cb5 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt index 5fa1b5726..0f58a9003 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 855453 # Simulator instruction rate (inst/s) -host_mem_usage 151192 # Number of bytes of host memory used -host_seconds 2348.45 # Real time elapsed on the host -host_tick_rate 427726617 # Simulator tick rate (ticks/s) +host_inst_rate 855891 # Simulator instruction rate (inst/s) +host_mem_usage 151228 # Number of bytes of host memory used +host_seconds 2347.25 # Real time elapsed on the host +host_tick_rate 427945543 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987607 # Number of instructions simulated sim_seconds 1.004494 # Number of seconds simulated diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini index 6f1f78d48..dd36bbf60 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out index 1c3b86ae3..676b65128 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt index afc2c695a..6aa1ee5aa 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 594701 # Simulator instruction rate (inst/s) -host_mem_usage 156660 # Number of bytes of host memory used -host_seconds 3378.14 # Real time elapsed on the host -host_tick_rate 405574512 # Simulator tick rate (ticks/s) +host_inst_rate 622738 # Simulator instruction rate (inst/s) +host_mem_usage 156744 # Number of bytes of host memory used +host_seconds 3226.05 # Real time elapsed on the host +host_tick_rate 852686846 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987607 # Number of instructions simulated -sim_seconds 1.370090 # Number of seconds simulated -sim_ticks 1370089513500 # Number of ticks simulated +sim_seconds 2.750814 # Number of seconds simulated +sim_ticks 2750814393000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3511.656558 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2511.656558 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 13971.031250 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12971.031250 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 509611834 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5120669500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 20372446000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3662477500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 18914254000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3914.581944 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2914.581944 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 13873.860351 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12873.860351 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 210722944 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 281662000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 998252000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000341 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 71952 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 209710000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 926300000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000341 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 71952 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 721864922 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3530.603329 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2530.603329 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 13966.461980 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12966.461980 # average overall mshr miss latency system.cpu.dcache.demand_hits 720334778 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 5402331500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 21370698000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002120 # miss rate for demand accesses system.cpu.dcache.demand_misses 1530144 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3872187500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 19840554000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002120 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 1530144 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3530.603329 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2530.603329 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 13966.461980 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12966.461980 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 720334778 # number of overall hits -system.cpu.dcache.overall_miss_latency 5402331500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 21370698000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002120 # miss rate for overall accesses system.cpu.dcache.overall_misses 1530144 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3872187500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 19840554000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002120 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 1530144 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 1526048 # number of replacements system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.457388 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.422371 # Cycle average of tags in use system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 325153000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 702832000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 74589 # number of writebacks system.cpu.icache.ReadReq_accesses 2008987608 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2952.765194 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1952.765194 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 12448.659872 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11448.659872 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 2008977012 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 31287500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 131906000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 10596 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 20691500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 121310000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 10596 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 2008987608 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2952.765194 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1952.765194 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 12448.659872 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11448.659872 # average overall mshr miss latency system.cpu.icache.demand_hits 2008977012 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 31287500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 131906000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses system.cpu.icache.demand_misses 10596 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 20691500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 121310000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 10596 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 2008987608 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2952.765194 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1952.765194 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 12448.659872 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11448.659872 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 2008977012 # number of overall hits -system.cpu.icache.overall_miss_latency 31287500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 131906000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses system.cpu.icache.overall_misses 10596 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 20691500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 121310000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 10596 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 9046 # number of replacements system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1478.638648 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1478.610505 # Cycle average of tags in use system.cpu.icache.total_refs 2008977012 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 1540740 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2545.120588 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1544.109658 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 33878 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 3835145500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 19589206000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.978012 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 1506862 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 2326760167 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 16575482000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.978012 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 1506862 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses) @@ -168,29 +168,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2545.120588 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1544.109658 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 33878 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3835145500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 19589206000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.978012 # miss rate for demand accesses system.cpu.l2cache.demand_misses 1506862 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2326760167 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 16575482000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.978012 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 1506862 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 1615329 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2543.307872 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1544.109658 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 12990.740986 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 107393 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3835145500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 19589206000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.933516 # miss rate for overall accesses system.cpu.l2cache.overall_misses 1507936 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2326760167 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 16575482000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.932851 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 1506862 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -207,12 +207,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 1474094 # number of replacements system.cpu.l2cache.sampled_refs 1506862 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 32754.836517 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 32753.638584 # Cycle average of tags in use system.cpu.l2cache.total_refs 107393 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 1084960000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 2394479000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 66804 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1370089513500 # number of cpu cycles simulated +system.cpu.numCycles 2750814393000 # number of cpu cycles simulated system.cpu.num_insts 2008987607 # Number of instructions executed system.cpu.num_refs 722390435 # Number of memory references system.cpu.workload.PROG:num_syscalls 39 # Number of system calls diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 6aa726853..8c32bfa79 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -91,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -267,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -306,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -339,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -363,6 +361,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out index e22560975..071b401c0 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -249,7 +250,7 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -280,14 +281,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -318,14 +318,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -356,7 +355,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -364,4 +362,5 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt index 91b29d8d9..bf6f402cd 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 7744324 # Number of BTB hits -global.BPredUnit.BTBLookups 13591046 # Number of BTB lookups -global.BPredUnit.RASInCorrect 32932 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 452723 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 10077718 # Number of conditional branches predicted -global.BPredUnit.lookups 15489897 # Number of BP lookups -global.BPredUnit.usedRAS 1844517 # Number of times the RAS was used to get a target. -host_inst_rate 108228 # Simulator instruction rate (inst/s) -host_mem_usage 159488 # Number of bytes of host memory used -host_seconds 735.41 # Real time elapsed on the host -host_tick_rate 23792996 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 12942665 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 11520420 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 21780362 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 15866784 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 7411086 # Number of BTB hits +global.BPredUnit.BTBLookups 13158968 # Number of BTB lookups +global.BPredUnit.RASInCorrect 32147 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 450892 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 9746581 # Number of conditional branches predicted +global.BPredUnit.lookups 14988034 # Number of BP lookups +global.BPredUnit.usedRAS 1776543 # Number of times the RAS was used to get a target. +host_inst_rate 99683 # Simulator instruction rate (inst/s) +host_mem_usage 159476 # Number of bytes of host memory used +host_seconds 798.45 # Real time elapsed on the host +host_tick_rate 35303213 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 9747985 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 9298064 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 21418262 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 15459606 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 79591756 # Number of instructions simulated -sim_seconds 0.017498 # Number of seconds simulated -sim_ticks 17497602000 # Number of ticks simulated +sim_seconds 0.028188 # Number of seconds simulated +sim_ticks 28187684500 # Number of ticks simulated system.cpu.commit.COM:branches 13754477 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 4260073 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 3230574 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 33996100 +system.cpu.commit.COM:committed_per_cycle.samples 55590975 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 8358440 2458.65% - 1 8230566 2421.03% - 2 4712162 1386.09% - 3 3108634 914.41% - 4 2121957 624.18% - 5 1131901 332.95% - 6 1374606 404.34% - 7 697761 205.25% - 8 4260073 1253.11% + 0 26501535 4767.24% + 1 10970497 1973.43% + 2 5466463 983.34% + 3 3506601 630.79% + 4 2372940 426.86% + 5 1558557 280.36% + 6 1098347 197.58% + 7 885461 159.28% + 8 3230574 581.13% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 20379399 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 35224018 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 356682 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 355366 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 6565781 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4551161 # The number of squashed insts skipped by commit system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.439684 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.439684 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 19603173 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 4020.633151 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2686.323277 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 19458721 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 580788500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.007369 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 144452 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 82734 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 165794500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.003148 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 61718 # number of ReadReq MSHR misses +system.cpu.cpi 0.708309 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.708309 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 20049834 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 4729.134904 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3349.390829 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 19907503 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 673102500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.007099 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 142331 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 80854 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 205910500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.003066 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 61477 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2642.114676 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3379.334983 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 13777457 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2208596500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.057202 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 835920 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 692465 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 484782500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009817 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 143455 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 3029.723364 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4119.889460 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 14053363 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 1696687500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.038322 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 560014 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 416536 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 591113500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.009818 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 143478 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 161.990993 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 165.699134 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 34216550 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2845.231198 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3170.870436 # average overall mshr miss latency -system.cpu.dcache.demand_hits 33236178 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 2789385000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.028652 # miss rate for demand accesses -system.cpu.dcache.demand_misses 980372 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 775199 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 650577000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.005996 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 205173 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 34663211 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3374.111014 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3888.775585 # average overall mshr miss latency +system.cpu.dcache.demand_hits 33960866 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 2369790000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.020262 # miss rate for demand accesses +system.cpu.dcache.demand_misses 702345 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 497390 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 797024000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.005913 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 204955 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 34216550 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2845.231198 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3170.870436 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 34663211 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3374.111014 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3888.775585 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 33236178 # number of overall hits -system.cpu.dcache.overall_miss_latency 2789385000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.028652 # miss rate for overall accesses -system.cpu.dcache.overall_misses 980372 # number of overall misses -system.cpu.dcache.overall_mshr_hits 775199 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 650577000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.005996 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 205173 # number of overall MSHR misses +system.cpu.dcache.overall_hits 33960866 # number of overall hits +system.cpu.dcache.overall_miss_latency 2369790000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.020262 # miss rate for overall accesses +system.cpu.dcache.overall_misses 702345 # number of overall misses +system.cpu.dcache.overall_mshr_hits 497390 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 797024000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.005913 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 204955 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 201077 # number of replacements -system.cpu.dcache.sampled_refs 205173 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 200859 # number of replacements +system.cpu.dcache.sampled_refs 204955 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4079.993551 # Cycle average of tags in use -system.cpu.dcache.total_refs 33236178 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 90338000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 147781 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1516721 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 98391 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3463978 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 98144908 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 14320248 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 17547399 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 999107 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 287801 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 611733 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 15489897 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 12778073 # Number of cache lines fetched -system.cpu.fetch.Cycles 31147667 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 14471 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 99913909 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 465674 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.442629 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 12778073 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 9588841 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.855074 # Number of inst fetches per cycle +system.cpu.dcache.tagsinuse 4080.110580 # Cycle average of tags in use +system.cpu.dcache.total_refs 33960866 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 144827000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 147753 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 583473 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 97307 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3380270 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 95203508 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 37386702 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 17614461 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 784542 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 292514 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 6340 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 14988034 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 12416477 # Number of cache lines fetched +system.cpu.fetch.Cycles 30119953 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 260035 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 96279919 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 467393 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.265861 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 12416477 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 9187629 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.707832 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 34995208 +system.cpu.fetch.rateDist.samples 56375518 system.cpu.fetch.rateDist.min_value 0 - 0 16625619 4750.83% - 1 1365816 390.29% - 2 1258616 359.65% - 3 1410956 403.19% - 4 3900976 1114.72% - 5 1678758 479.71% - 6 612174 174.93% - 7 1011089 288.92% - 8 7131204 2037.77% + 0 38672046 6859.72% + 1 1321940 234.49% + 2 1201428 213.11% + 3 1338454 237.42% + 4 3789980 672.27% + 5 1624217 288.11% + 6 592859 105.16% + 7 975150 172.97% + 8 6859444 1216.74% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 12778073 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2888.242687 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1894.538715 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 12690553 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 252779000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.006849 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 87520 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 654 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 164571000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.006798 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 86866 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 12416477 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3477.694454 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2488.876340 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 12330467 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 299116500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.006927 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 86010 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 1011 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 211552000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.006846 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 84999 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 146.093443 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 145.066024 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 12778073 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2888.242687 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1894.538715 # average overall mshr miss latency -system.cpu.icache.demand_hits 12690553 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 252779000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.006849 # miss rate for demand accesses -system.cpu.icache.demand_misses 87520 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 654 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 164571000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.006798 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 86866 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 12416477 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3477.694454 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2488.876340 # average overall mshr miss latency +system.cpu.icache.demand_hits 12330467 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 299116500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.006927 # miss rate for demand accesses +system.cpu.icache.demand_misses 86010 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 1011 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 211552000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.006846 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 84999 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 12778073 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2888.242687 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1894.538715 # average overall mshr miss latency +system.cpu.icache.overall_accesses 12416477 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3477.694454 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2488.876340 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 12690553 # number of overall hits -system.cpu.icache.overall_miss_latency 252779000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.006849 # miss rate for overall accesses -system.cpu.icache.overall_misses 87520 # number of overall misses -system.cpu.icache.overall_mshr_hits 654 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 164571000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.006798 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 86866 # number of overall MSHR misses +system.cpu.icache.overall_hits 12330467 # number of overall hits +system.cpu.icache.overall_miss_latency 299116500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.006927 # miss rate for overall accesses +system.cpu.icache.overall_misses 86010 # number of overall misses +system.cpu.icache.overall_mshr_hits 1011 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 211552000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.006846 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 84999 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,80 +215,80 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 84818 # number of replacements -system.cpu.icache.sampled_refs 86866 # Sample count of references to valid blocks. +system.cpu.icache.replacements 82951 # number of replacements +system.cpu.icache.sampled_refs 84999 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1921.828467 # Cycle average of tags in use -system.cpu.icache.total_refs 12690553 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 15230287000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tagsinuse 1918.432617 # Cycle average of tags in use +system.cpu.icache.total_refs 12330467 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 24669337000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 6484 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 14304724 # Number of branches executed -system.cpu.iew.EXEC:nop 9152219 # number of nop insts executed -system.cpu.iew.EXEC:rate 2.363053 # Inst execution rate -system.cpu.iew.EXEC:refs 36160680 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 15116998 # Number of stores executed +system.cpu.idleCycles 25301 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 14196900 # Number of branches executed +system.cpu.iew.EXEC:nop 9006488 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.455602 # Inst execution rate +system.cpu.iew.EXEC:refs 36045074 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 15052480 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 43283574 # num instructions consuming a value -system.cpu.iew.WB:count 82548148 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.757836 # average fanout of values written-back +system.cpu.iew.WB:consumers 39431808 # num instructions consuming a value +system.cpu.iew.WB:count 81784655 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.769564 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 32801872 # num instructions producing a value -system.cpu.iew.WB:rate 2.358841 # insts written-back per cycle -system.cpu.iew.WB:sent 82621578 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 398195 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 20355 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 21780362 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 4681 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 352010 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 15866784 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 94903979 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 21043682 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 752566 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 82695525 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 5889 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 30345313 # num instructions producing a value +system.cpu.iew.WB:rate 1.450712 # insts written-back per cycle +system.cpu.iew.WB:sent 81828309 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 387091 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 10156 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 21418262 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 4652 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 597409 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 15459606 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 92891480 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 20992594 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 333391 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 82060341 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 141 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 132 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 999107 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 7135 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 37 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 784542 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 478 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 1325562 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 2239 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 2 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 828061 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 554 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 16849 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1491 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1400963 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1022165 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 16849 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 105190 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 293005 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 2.274362 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.274362 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 83448091 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 19340 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1425 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1038863 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 614987 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 19340 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 103732 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 283359 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.411814 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.411814 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 82393732 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 0 0.00% # Type of FU issued - IntAlu 46687810 55.95% # Type of FU issued - IntMult 45238 0.05% # Type of FU issued + IntAlu 45892607 55.70% # Type of FU issued + IntMult 44107 0.05% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 120004 0.14% # Type of FU issued + FloatAdd 116900 0.14% # Type of FU issued FloatCmp 87 0.00% # Type of FU issued - FloatCvt 122290 0.15% # Type of FU issued + FloatCvt 120453 0.15% # Type of FU issued FloatMult 50 0.00% # Type of FU issued - FloatDiv 37770 0.05% # Type of FU issued + FloatDiv 37768 0.05% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 21206489 25.41% # Type of FU issued - MemWrite 15228353 18.25% # Type of FU issued + MemRead 21065064 25.57% # Type of FU issued + MemWrite 15116696 18.35% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 1422206 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.017043 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 898002 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.010899 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 169452 11.91% # attempts to use FU when none available + IntAlu 168043 18.71% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -297,84 +297,84 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 649726 45.68% # attempts to use FU when none available - MemWrite 603028 42.40% # attempts to use FU when none available + MemRead 309725 34.49% # attempts to use FU when none available + MemWrite 420234 46.80% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 34995208 +system.cpu.iq.ISSUE:issued_per_cycle.samples 56375518 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 5876071 1679.11% - 1 8518834 2434.29% - 2 6419045 1834.26% - 3 4436708 1267.80% - 4 4423684 1264.08% - 5 2554091 729.84% - 6 1512126 432.10% - 7 794096 226.92% - 8 460553 131.60% + 0 22612550 4011.06% + 1 13769796 2442.51% + 2 7834961 1389.78% + 3 4029672 714.79% + 4 3712649 658.56% + 5 1993297 353.57% + 6 1449259 257.07% + 7 434309 77.04% + 8 539025 95.61% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 2.384558 # Inst issue rate -system.cpu.iq.iqInstsAdded 85747079 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 83448091 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 4681 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 5951026 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 23998 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 98 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 4012087 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 291992 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3325.548649 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1922.235296 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 122257 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 564462000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.581300 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 169735 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 326270608 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.581300 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 169735 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 147781 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 147317 # number of Writeback hits -system.cpu.l2cache.Writeback_miss_rate 0.003140 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 464 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 0.003140 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 464 # number of Writeback MSHR misses +system.cpu.iq.ISSUE:rate 1.461516 # Inst issue rate +system.cpu.iq.iqInstsAdded 83880340 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 82393732 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 4652 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 4104955 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 35761 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 69 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2730801 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 289883 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4226.385671 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2218.670959 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 120272 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 716841500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.585102 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 169611 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 376311000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.585102 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 169611 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 147753 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 147292 # number of Writeback hits +system.cpu.l2cache.Writeback_miss_rate 0.003120 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 461 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 0.003120 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 461 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.588205 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.577516 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 291992 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3325.548649 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1922.235296 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 122257 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 564462000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.581300 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 169735 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 289883 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4226.385671 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2218.670959 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 120272 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 716841500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.585102 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 169611 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 326270608 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.581300 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 169735 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 376311000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.585102 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 169611 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 439773 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3316.482471 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1922.235296 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 437636 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4214.929559 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2218.670959 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 269574 # number of overall hits -system.cpu.l2cache.overall_miss_latency 564462000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.387016 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 170199 # number of overall misses +system.cpu.l2cache.overall_hits 267564 # number of overall hits +system.cpu.l2cache.overall_miss_latency 716841500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.388615 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 170072 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 326270608 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.385960 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 169735 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 376311000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.387562 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 169611 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -386,31 +386,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 136967 # number of replacements -system.cpu.l2cache.sampled_refs 169735 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 136843 # number of replacements +system.cpu.l2cache.sampled_refs 169611 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 32064.700481 # Cycle average of tags in use -system.cpu.l2cache.total_refs 269574 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 8508988000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 115938 # number of writebacks -system.cpu.numCycles 34995208 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 201241 # Number of cycles rename is blocking +system.cpu.l2cache.tagsinuse 32058.525051 # Cycle average of tags in use +system.cpu.l2cache.total_refs 267564 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 13792867000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 115936 # number of writebacks +system.cpu.numCycles 56375518 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 238131 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 31178 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 14721876 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1110145 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 117085470 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 96973574 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 58152082 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 17754494 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 999107 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 1242602 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 5605201 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 75888 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 4701 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 2792735 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 4699 # count of temporary serializing insts renamed -system.cpu.timesIdled 16 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 31030 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 37626801 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 240022 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 113729051 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 94390828 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 56605918 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 17378620 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 784542 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 281505 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4059037 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 65919 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 4656 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 641192 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 4654 # count of temporary serializing insts renamed +system.cpu.timesIdled 199 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini index 57d9578d2..5339d79af 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out index fbb08bf4b..bf2c5c795 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt index 8a03d8929..16fb6367e 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 842354 # Simulator instruction rate (inst/s) -host_mem_usage 152996 # Number of bytes of host memory used -host_seconds 104.87 # Real time elapsed on the host -host_tick_rate 421175511 # Simulator tick rate (ticks/s) +host_inst_rate 840697 # Simulator instruction rate (inst/s) +host_mem_usage 152968 # Number of bytes of host memory used +host_seconds 105.08 # Real time elapsed on the host +host_tick_rate 420346781 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340674 # Number of instructions simulated sim_seconds 0.044170 # Number of seconds simulated diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini index 2f49c7692..4c8661842 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out index c1faaa3e6..c0cb264bc 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt index 939083267..107c46644 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 562157 # Simulator instruction rate (inst/s) -host_mem_usage 158620 # Number of bytes of host memory used -host_seconds 157.15 # Real time elapsed on the host -host_tick_rate 396922606 # Simulator tick rate (ticks/s) +host_inst_rate 585395 # Simulator instruction rate (inst/s) +host_mem_usage 158604 # Number of bytes of host memory used +host_seconds 150.91 # Real time elapsed on the host +host_tick_rate 839295251 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340674 # Number of instructions simulated -sim_seconds 0.062375 # Number of seconds simulated -sim_ticks 62374966500 # Number of ticks simulated +sim_seconds 0.126657 # Number of seconds simulated +sim_ticks 126656575000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3130.058422 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2130.058422 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 12987.854851 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11987.854851 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 20215873 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 190198000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 789207000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 60765 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 129433000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 728442000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 60765 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3436.431765 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2436.431765 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 13826.199000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12826.199000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 14469799 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 493396000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 1985138000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.009825 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 143578 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 349818000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1841560000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 143578 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3345.326241 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2345.326241 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 13576.902561 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12576.902561 # average overall mshr miss latency system.cpu.dcache.demand_hits 34685672 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 683594000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 2774345000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.005857 # miss rate for demand accesses system.cpu.dcache.demand_misses 204343 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 479251000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 2570002000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 204343 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3345.326241 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2345.326241 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 13576.902561 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12576.902561 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 34685672 # number of overall hits -system.cpu.dcache.overall_miss_latency 683594000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 2774345000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.005857 # miss rate for overall accesses system.cpu.dcache.overall_misses 204343 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 479251000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 2570002000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 204343 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 200247 # number of replacements system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4082.118898 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4081.697925 # Cycle average of tags in use system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 307192000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 661090000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 147714 # number of writebacks system.cpu.icache.ReadReq_accesses 88340675 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2831.355644 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1831.355644 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 12197.393898 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11197.393898 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 88264239 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 216417500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 932320000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000865 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 139981500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 855884000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000865 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 88340675 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2831.355644 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1831.355644 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 12197.393898 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11197.393898 # average overall mshr miss latency system.cpu.icache.demand_hits 88264239 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 216417500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 932320000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000865 # miss rate for demand accesses system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 139981500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 855884000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000865 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 88340675 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2831.355644 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1831.355644 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 12197.393898 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11197.393898 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 88264239 # number of overall hits -system.cpu.icache.overall_miss_latency 216417500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 932320000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000865 # miss rate for overall accesses system.cpu.icache.overall_misses 76436 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 139981500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 855884000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000865 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 74391 # number of replacements system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1880.010701 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1878.885583 # Cycle average of tags in use system.cpu.icache.total_refs 88264239 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 280779 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2532.769537 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1531.091909 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 12999.768790 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 10999.768790 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 112101 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 427222500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 2192775000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.600750 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 168678 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 258261521 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1855419000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.600750 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 168678 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses) @@ -168,29 +168,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 280779 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2532.769537 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1531.091909 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 12999.768790 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 10999.768790 # average overall mshr miss latency system.cpu.l2cache.demand_hits 112101 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 427222500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 2192775000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.600750 # miss rate for demand accesses system.cpu.l2cache.demand_misses 168678 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 258261521 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 1855419000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.600750 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 168678 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 428493 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2526.209820 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1531.091909 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 12966.100192 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 10999.768790 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 259377 # number of overall hits -system.cpu.l2cache.overall_miss_latency 427222500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 2192775000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.394676 # miss rate for overall accesses system.cpu.l2cache.overall_misses 169116 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 258261521 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 1855419000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.393654 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 168678 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -207,12 +207,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 135910 # number of replacements system.cpu.l2cache.sampled_refs 168678 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 32002.173981 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 31979.717205 # Cycle average of tags in use system.cpu.l2cache.total_refs 259377 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 30452104000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 61925078000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 115911 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 62374966500 # number of cpu cycles simulated +system.cpu.numCycles 126656575000 # number of cpu cycles simulated system.cpu.num_insts 88340674 # Number of instructions executed system.cpu.num_refs 35224019 # Number of memory references system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini index 7932bf16f..da377104f 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out index b69343874..4d97fe26f 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt index 37d044e8d..9dd2e7465 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 644632 # Simulator instruction rate (inst/s) -host_mem_usage 151548 # Number of bytes of host memory used -host_seconds 211.36 # Real time elapsed on the host -host_tick_rate 322315545 # Simulator tick rate (ticks/s) +host_inst_rate 672762 # Simulator instruction rate (inst/s) +host_mem_usage 151516 # Number of bytes of host memory used +host_seconds 202.52 # Real time elapsed on the host +host_tick_rate 336380340 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136246936 # Number of instructions simulated sim_seconds 0.068123 # Number of seconds simulated diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout index 794510e19..13addb638 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 27 2007 14:35:32 -M5 started Fri Apr 27 15:55:23 2007 +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 16:40:43 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic tests/run.py long/50.vortex/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini index 1bc14e993..ff1b40886 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out index cb469d872..c2fb507ae 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt index 4e8db9778..bf74220de 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 466766 # Simulator instruction rate (inst/s) -host_mem_usage 157052 # Number of bytes of host memory used -host_seconds 291.90 # Real time elapsed on the host -host_tick_rate 335938336 # Simulator tick rate (ticks/s) +host_inst_rate 480067 # Simulator instruction rate (inst/s) +host_mem_usage 157016 # Number of bytes of host memory used +host_seconds 283.81 # Real time elapsed on the host +host_tick_rate 698858124 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136246936 # Number of instructions simulated -sim_seconds 0.098059 # Number of seconds simulated -sim_ticks 98059078500 # Number of ticks simulated +sim_seconds 0.198342 # Number of seconds simulated +sim_ticks 198341876000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3241.706786 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2241.706786 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 13005.210051 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12005.210051 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 37185812 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 147462000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 591594000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 45489 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 101973000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 546105000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 45489 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 3166.666667 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2166.666667 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 12800 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 11800 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 15901 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 47500 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 192000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.000942 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 15 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 32500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 177000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.000942 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 15 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3588.938331 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2588.938331 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 13928.024036 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12928.024036 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 20759130 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 377463000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 1464866000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.005041 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 105174 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 272289000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1359692000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.005041 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 105174 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3484.100277 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2484.100277 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 13649.402972 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12649.402972 # average overall mshr miss latency system.cpu.dcache.demand_hits 57944942 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 524925000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 2056460000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002593 # miss rate for demand accesses system.cpu.dcache.demand_misses 150663 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 374262000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 1905797000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002593 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 150663 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3484.100277 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2484.100277 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 13649.402972 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12649.402972 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 57944942 # number of overall hits -system.cpu.dcache.overall_miss_latency 524925000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 2056460000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002593 # miss rate for overall accesses system.cpu.dcache.overall_misses 150663 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 374262000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 1905797000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002593 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 150663 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 146582 # number of replacements system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4090.058697 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4089.719370 # Cycle average of tags in use system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 224414000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 500116000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 107279 # number of writebacks system.cpu.icache.ReadReq_accesses 136246937 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2800.327765 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1800.327765 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 12107.905937 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11107.905937 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 136059913 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 523728500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 2264469000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.001373 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 336704500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 2077445000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.001373 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 136246937 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2800.327765 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1800.327765 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 12107.905937 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11107.905937 # average overall mshr miss latency system.cpu.icache.demand_hits 136059913 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 523728500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 2264469000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.001373 # miss rate for demand accesses system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 336704500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 2077445000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.001373 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 136246937 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2800.327765 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1800.327765 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 12107.905937 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11107.905937 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 136059913 # number of overall hits -system.cpu.icache.overall_miss_latency 523728500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 2264469000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.001373 # miss rate for overall accesses system.cpu.icache.overall_misses 187024 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 336704500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 2077445000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.001373 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -148,19 +148,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 184976 # number of replacements system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 2008.440865 # Cycle average of tags in use +system.cpu.icache.tagsinuse 2007.901723 # Cycle average of tags in use system.cpu.icache.total_refs 136059913 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 69827484000 # Cycle when the warmup percentage was hit. +system.cpu.icache.warmup_cycle 141263674000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 337636 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2644.770157 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1643.366085 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 12999.502521 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 10999.502521 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 202957 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 356195000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 1750760000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.398888 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 134679 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 221326901 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1481402000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.398888 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 134679 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 107279 # number of Writeback accesses(hits+misses) @@ -178,29 +178,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 337636 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2644.770157 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1643.366085 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 12999.502521 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 10999.502521 # average overall mshr miss latency system.cpu.l2cache.demand_hits 202957 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 356195000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 1750760000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.398888 # miss rate for demand accesses system.cpu.l2cache.demand_misses 134679 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 221326901 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 1481402000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.398888 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 134679 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 444915 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2634.831752 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1643.366085 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 12950.653539 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 10999.502521 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 309728 # number of overall hits -system.cpu.l2cache.overall_miss_latency 356195000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 1750760000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.303849 # miss rate for overall accesses system.cpu.l2cache.overall_misses 135187 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 221326901 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 1481402000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.302707 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 134679 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -217,12 +217,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 101911 # number of replacements system.cpu.l2cache.sampled_refs 134679 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 32141.182824 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 32127.015431 # Cycle average of tags in use system.cpu.l2cache.total_refs 309728 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 20627583000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 41711518000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 82918 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 98059078500 # number of cpu cycles simulated +system.cpu.numCycles 198341876000 # number of cpu cycles simulated system.cpu.num_insts 136246936 # Number of instructions executed system.cpu.num_refs 58111522 # Number of memory references system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout index 08ec05c3a..c635e0e4b 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 27 2007 14:35:32 -M5 started Fri Apr 27 15:58:57 2007 +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 16:44:06 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing tests/run.py long/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 98059078500 because target called exit() +Exiting @ tick 198341876000 because target called exit() diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 9e383ca33..105e8c6e2 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -91,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -267,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -306,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -339,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -363,6 +361,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out index 4a5aeccf1..ea4848b9b 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -249,7 +250,7 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -280,14 +281,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -318,14 +318,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -356,7 +355,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -364,4 +362,5 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt index 227b79a7b..dccb62bee 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 264221270 # Number of BTB hits -global.BPredUnit.BTBLookups 273071573 # Number of BTB lookups -global.BPredUnit.RASInCorrect 122 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 19541079 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 228439261 # Number of conditional branches predicted -global.BPredUnit.lookups 295748685 # Number of BP lookups -global.BPredUnit.usedRAS 20371548 # Number of times the RAS was used to get a target. -host_inst_rate 108663 # Simulator instruction rate (inst/s) -host_mem_usage 154628 # Number of bytes of host memory used -host_seconds 15976.47 # Real time elapsed on the host -host_tick_rate 25821276 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 80477635 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 37646176 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 533254174 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 186471924 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 236329759 # Number of BTB hits +global.BPredUnit.BTBLookups 244099867 # Number of BTB lookups +global.BPredUnit.RASInCorrect 116 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 19342549 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 203388054 # Number of conditional branches predicted +global.BPredUnit.lookups 265702680 # Number of BP lookups +global.BPredUnit.usedRAS 19620183 # Number of times the RAS was used to get a target. +host_inst_rate 104740 # Simulator instruction rate (inst/s) +host_mem_usage 154596 # Number of bytes of host memory used +host_seconds 16574.74 # Real time elapsed on the host +host_tick_rate 38540500 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 53067106 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 26767467 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 497279728 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 174034666 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1736043781 # Number of instructions simulated -sim_seconds 0.412533 # Number of seconds simulated -sim_ticks 412532848500 # Number of ticks simulated +sim_seconds 0.638799 # Number of seconds simulated +sim_ticks 638798750000 # Number of ticks simulated system.cpu.commit.COM:branches 214632552 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 78248119 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 60317471 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 772086758 +system.cpu.commit.COM:committed_per_cycle.samples 1240430038 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 242551958 3141.51% - 1 161050324 2085.91% - 2 101638189 1316.41% - 3 63812257 826.49% - 4 43982002 569.65% - 5 37612088 487.15% - 6 28299494 366.53% - 7 14892327 192.88% - 8 78248119 1013.46% + 0 616961832 4973.77% + 1 236071207 1903.14% + 2 130159070 1049.31% + 3 77572840 625.37% + 4 40072787 323.06% + 5 42334502 341.29% + 6 22413470 180.69% + 7 14526859 117.11% + 8 60317471 486.26% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 445666361 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 606571343 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 19540581 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 19342064 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 358953852 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 213160886 # The number of squashed insts skipped by commit system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.475256 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.475256 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 463286594 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3710.591477 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2550.415742 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 454594407 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 32253155000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.018762 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 8692187 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 1395111 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 18610577500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.015751 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 7297076 # number of ReadReq MSHR misses +system.cpu.cpi 0.735925 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.735925 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 460303357 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3955.169300 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2868.381634 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 451791924 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 33664158500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.018491 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 8511433 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 1219244 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 20916781000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.015842 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 7292189 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 6275.157749 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 8072.319138 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 157494886 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 20291450500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.020118 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 3233616 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1350145 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 15203979000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.011718 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1883471 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 1064.957356 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 500 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 66.672421 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 75157 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 5468 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 80039000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 2734000 # number of cycles access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 6699.535635 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 8433.632873 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 157310932 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 22896132000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.021263 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 3417570 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1533904 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 15886147500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.011720 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1883666 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 1092.259997 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 571.397227 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 66.381046 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 62416 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 56970 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 68174500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 32552500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 624015096 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 4405.959540 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3683.283414 # average overall mshr miss latency -system.cpu.dcache.demand_hits 612089293 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 52544605500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.019111 # miss rate for demand accesses -system.cpu.dcache.demand_misses 11925803 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2745256 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 33814556500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.014712 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 9180547 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 621031859 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 4741.409697 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4010.844602 # average overall mshr miss latency +system.cpu.dcache.demand_hits 609102856 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 56560290500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.019208 # miss rate for demand accesses +system.cpu.dcache.demand_misses 11929003 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2753148 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 36802928500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.014775 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 9175855 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 624015096 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 4405.959540 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3683.283414 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 621031859 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 4741.409697 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4010.844602 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 612089293 # number of overall hits -system.cpu.dcache.overall_miss_latency 52544605500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.019111 # miss rate for overall accesses -system.cpu.dcache.overall_misses 11925803 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2745256 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 33814556500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.014712 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 9180547 # number of overall MSHR misses +system.cpu.dcache.overall_hits 609102856 # number of overall hits +system.cpu.dcache.overall_miss_latency 56560290500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.019208 # miss rate for overall accesses +system.cpu.dcache.overall_misses 11929003 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2753148 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 36802928500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.014775 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 9175855 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 9176451 # number of replacements -system.cpu.dcache.sampled_refs 9180547 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 9171759 # number of replacements +system.cpu.dcache.sampled_refs 9175855 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4083.178096 # Cycle average of tags in use -system.cpu.dcache.total_refs 612089293 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 4996762000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 2245686 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 22551440 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 546 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 44940582 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 2380682647 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 322635695 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 423064703 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 52978940 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 1700 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 3834921 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 295748685 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 302488728 # Number of cache lines fetched -system.cpu.fetch.Cycles 741391553 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 441 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 2447585283 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 20057035 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.358455 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 302488728 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 284592818 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.966534 # Number of inst fetches per cycle +system.cpu.dcache.tagsinuse 4081.309726 # Cycle average of tags in use +system.cpu.dcache.total_refs 609102856 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 8881811000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 2245633 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 27333658 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 501 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 42431183 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 2163062948 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 823856490 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 388659524 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 37167487 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 1638 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 580367 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 265702680 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 277957843 # Number of cache lines fetched +system.cpu.fetch.Cycles 672748425 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 10624598 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 2197044125 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 19810424 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.207971 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 277957843 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 255949942 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.719668 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 825065699 +system.cpu.fetch.rateDist.samples 1277597526 system.cpu.fetch.rateDist.min_value 0 - 0 386162878 4680.39% - 1 30694739 372.03% - 2 18778429 227.60% - 3 29987039 363.45% - 4 87656406 1062.42% - 5 50975460 617.84% - 6 28097158 340.54% - 7 26422023 320.24% - 8 166291567 2015.49% + 0 882806946 6909.90% + 1 27356477 214.12% + 2 16416749 128.50% + 3 27123610 212.30% + 4 80197027 627.72% + 5 46838848 366.62% + 6 25144427 196.81% + 7 24073126 188.42% + 8 147640316 1155.61% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 302488728 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4286.486486 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3340.579710 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 302487803 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 3965000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 277957843 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5447.729673 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4641.891892 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 277956896 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 5159000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 925 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 28 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 2996500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 947 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 59 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 4122000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 897 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 888 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 337221.630992 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 313014.522523 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 302488728 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4286.486486 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3340.579710 # average overall mshr miss latency -system.cpu.icache.demand_hits 302487803 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 3965000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 277957843 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5447.729673 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4641.891892 # average overall mshr miss latency +system.cpu.icache.demand_hits 277956896 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 5159000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses -system.cpu.icache.demand_misses 925 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 28 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2996500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 947 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 59 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 4122000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 897 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 888 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 302488728 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4286.486486 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3340.579710 # average overall mshr miss latency +system.cpu.icache.overall_accesses 277957843 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5447.729673 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4641.891892 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 302487803 # number of overall hits -system.cpu.icache.overall_miss_latency 3965000 # number of overall miss cycles +system.cpu.icache.overall_hits 277956896 # number of overall hits +system.cpu.icache.overall_miss_latency 5159000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses -system.cpu.icache.overall_misses 925 # number of overall misses -system.cpu.icache.overall_mshr_hits 28 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2996500 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 947 # number of overall misses +system.cpu.icache.overall_mshr_hits 59 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 4122000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 897 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 888 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -216,79 +216,79 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.sampled_refs 897 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 888 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 700.392428 # Cycle average of tags in use -system.cpu.icache.total_refs 302487803 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 691.554117 # Cycle average of tags in use +system.cpu.icache.total_refs 277956896 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 498 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 240658046 # Number of branches executed -system.cpu.iew.EXEC:nop 109011682 # number of nop insts executed -system.cpu.iew.EXEC:rate 2.343638 # Inst execution rate -system.cpu.iew.EXEC:refs 670450767 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 171332493 # Number of stores executed +system.cpu.idleCycles 973 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 231142223 # Number of branches executed +system.cpu.iew.EXEC:nop 101615397 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.460942 # Inst execution rate +system.cpu.iew.EXEC:refs 650877785 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 168419462 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1329316260 # num instructions consuming a value -system.cpu.iew.WB:count 1919496913 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.807674 # average fanout of values written-back +system.cpu.iew.WB:consumers 1210814193 # num instructions consuming a value +system.cpu.iew.WB:count 1847797148 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.819076 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1073654377 # num instructions producing a value -system.cpu.iew.WB:rate 2.326478 # insts written-back per cycle -system.cpu.iew.WB:sent 1925768214 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 21262198 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 271227 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 533254174 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 16376681 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 186471924 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2178733969 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 499118274 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 42707495 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1933655185 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 3473 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 991749121 # num instructions producing a value +system.cpu.iew.WB:rate 1.446306 # insts written-back per cycle +system.cpu.iew.WB:sent 1849274792 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 20085867 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 1985372 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 497279728 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 38 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 27992821 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 174034666 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2032941045 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 482458323 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 14098084 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1866495371 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 77 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 253 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 52978940 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 31539 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 1402 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 37167487 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 36044 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 331862 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 34494542 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 128095 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 409084 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 20784106 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 401249 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 361683 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 9 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 87587813 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 25566942 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 361683 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 691850 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 20570348 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 2.104128 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.104128 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 1976362680 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 306932 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 3 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 51613367 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 13129684 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 306932 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 672336 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 19413531 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.358835 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.358835 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 1880593455 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 0 0.00% # Type of FU issued - IntAlu 1288510764 65.20% # Type of FU issued + IntAlu 1224165146 65.09% # Type of FU issued IntMult 78 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 234 0.00% # Type of FU issued + FloatAdd 199 0.00% # Type of FU issued FloatCmp 15 0.00% # Type of FU issued - FloatCvt 154 0.00% # Type of FU issued - FloatMult 14 0.00% # Type of FU issued + FloatCvt 141 0.00% # Type of FU issued + FloatMult 13 0.00% # Type of FU issued FloatDiv 24 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 513015840 25.96% # Type of FU issued - MemWrite 174835557 8.85% # Type of FU issued + MemRead 487297898 25.91% # Type of FU issued + MemWrite 169129941 8.99% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 18092397 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009154 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 14841221 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.007892 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 2424231 13.40% # attempts to use FU when none available + IntAlu 753308 5.08% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -297,84 +297,84 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 11434785 63.20% # attempts to use FU when none available - MemWrite 4233381 23.40% # attempts to use FU when none available + MemRead 10126775 68.23% # attempts to use FU when none available + MemWrite 3961138 26.69% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 825065699 +system.cpu.iq.ISSUE:issued_per_cycle.samples 1277597526 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 201043450 2436.70% - 1 117715520 1426.74% - 2 151671107 1838.29% - 3 100094924 1213.18% - 4 99857816 1210.30% - 5 89528622 1085.11% - 6 51943929 629.57% - 7 9400422 113.94% - 8 3809909 46.18% + 0 550473495 4308.66% + 1 242915598 1901.35% + 2 174612702 1366.73% + 3 111937959 876.16% + 4 91216702 713.97% + 5 63235343 494.96% + 6 32411117 253.69% + 7 9228529 72.23% + 8 1566081 12.26% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 2.395400 # Inst issue rate -system.cpu.iq.iqInstsAdded 2069722245 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1976362680 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 42 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 325012863 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 1550012 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 175292310 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 9181444 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4578.076271 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1904.625556 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 7012219 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 9930877500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.236262 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 2169225 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 4131561371 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.236262 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 2169225 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 2245686 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 2216531 # number of Writeback hits -system.cpu.l2cache.Writeback_miss_rate 0.012983 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 29155 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 0.012983 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 29155 # number of Writeback MSHR misses +system.cpu.iq.ISSUE:rate 1.471976 # Inst issue rate +system.cpu.iq.iqInstsAdded 1931325610 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1880593455 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 179510503 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 87058 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 101093002 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 9176743 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 5323.405393 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2210.600583 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 7008183 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 11544124000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.236310 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 2168560 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 4793820000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.236310 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 2168560 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 2245633 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2216502 # number of Writeback hits +system.cpu.l2cache.Writeback_miss_rate 0.012972 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 29131 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 0.012972 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 29131 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.254400 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 4.253830 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 9181444 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4578.076271 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1904.625556 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 7012219 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9930877500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.236262 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 2169225 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 9176743 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 5323.405393 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2210.600583 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 7008183 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 11544124000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.236310 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 2168560 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4131561371 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.236262 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 2169225 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 4793820000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.236310 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 2168560 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 11427130 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4517.361648 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1904.625556 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 11422376 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 5252.842188 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2210.600583 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 9228750 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9930877500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.192383 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 2198380 # number of overall misses +system.cpu.l2cache.overall_hits 9224685 # number of overall hits +system.cpu.l2cache.overall_miss_latency 11544124000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.192402 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 2197691 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4131561371 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.189831 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 2169225 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 4793820000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.189852 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 2168560 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -386,32 +386,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 2136457 # number of replacements -system.cpu.l2cache.sampled_refs 2169225 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 2135792 # number of replacements +system.cpu.l2cache.sampled_refs 2168560 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 31578.699946 # Cycle average of tags in use -system.cpu.l2cache.total_refs 9228750 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 29958824000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 1039499 # number of writebacks -system.cpu.numCycles 825065699 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 6100420 # Number of cycles rename is blocking +system.cpu.l2cache.tagsinuse 31406.160078 # Cycle average of tags in use +system.cpu.l2cache.total_refs 9224685 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 53019662000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 1039396 # number of writebacks +system.cpu.numCycles 1277597526 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 16292159 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 4850719 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 338099779 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 9291025 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 1319 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 2964381647 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 2307795213 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 1730632745 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 411108509 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 52978940 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 16777593 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 354429782 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 458 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 47 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 42678716 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 45 # count of temporary serializing insts renamed -system.cpu.timesIdled 2 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 4365074 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 834284464 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 6221923 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 448 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 2711841153 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 2114466649 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 1591248178 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 378627043 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 37167487 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 11225904 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 215045215 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 469 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 45 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 21611838 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 43 # count of temporary serializing insts renamed +system.cpu.timesIdled 27 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 29 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini index d1eaa2267..ab96f2ec5 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out index 19f234143..fc081bf5e 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt index fbe8bb0a6..4bc7b8152 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 929031 # Simulator instruction rate (inst/s) -host_mem_usage 148624 # Number of bytes of host memory used -host_seconds 1958.79 # Real time elapsed on the host -host_tick_rate 464515386 # Simulator tick rate (ticks/s) +host_inst_rate 918892 # Simulator instruction rate (inst/s) +host_mem_usage 148632 # Number of bytes of host memory used +host_seconds 1980.41 # Real time elapsed on the host +host_tick_rate 459446111 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780129 # Number of instructions simulated sim_seconds 0.909890 # Number of seconds simulated diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini index 2f9e86a73..41806d538 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out index 7cc7b0b90..55a09db2b 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt index eb696cc14..009ee213d 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 623968 # Simulator instruction rate (inst/s) -host_mem_usage 154076 # Number of bytes of host memory used -host_seconds 2916.46 # Real time elapsed on the host -host_tick_rate 423514548 # Simulator tick rate (ticks/s) +host_inst_rate 637714 # Simulator instruction rate (inst/s) +host_mem_usage 154060 # Number of bytes of host memory used +host_seconds 2853.60 # Real time elapsed on the host +host_tick_rate 886477792 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780129 # Number of instructions simulated -sim_seconds 1.235165 # Number of seconds simulated -sim_ticks 1235165291000 # Number of ticks simulated +sim_seconds 2.529655 # Number of seconds simulated +sim_ticks 2529654621000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 2978.629098 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1978.629098 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 12378.042992 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11378.042992 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 21512892500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 89399351000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 14290478500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 82176937000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2992.340366 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 1992.340366 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 12836.520018 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11836.520018 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 158839182 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 5653488500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 24252294000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.011755 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1889320 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 3764168500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 22362974000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.011755 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1889320 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2981.472133 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 1981.472133 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 12473.108302 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 11473.108302 # average overall mshr miss latency system.cpu.dcache.demand_hits 596212431 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 27166381000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 113651645000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.015053 # miss rate for demand accesses system.cpu.dcache.demand_misses 9111734 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 18054647000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 104539911000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.015053 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 9111734 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2981.472133 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 1981.472133 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 12473.108302 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 11473.108302 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 596212431 # number of overall hits -system.cpu.dcache.overall_miss_latency 27166381000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 113651645000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.015053 # miss rate for overall accesses system.cpu.dcache.overall_misses 9111734 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 18054647000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 104539911000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.015053 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 9111734 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 9107638 # number of replacements system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4078.615858 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4078.970916 # Cycle average of tags in use system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 20287970000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 40631938000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 2244708 # number of writebacks system.cpu.icache.ReadReq_accesses 1819780130 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3779.301746 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2779.301746 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13987.531172 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12987.531172 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 1819779328 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 3031000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 11218000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 2229000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 10416000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1819780130 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3779.301746 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2779.301746 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13987.531172 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12987.531172 # average overall mshr miss latency system.cpu.icache.demand_hits 1819779328 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 3031000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 11218000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses system.cpu.icache.demand_misses 802 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2229000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 10416000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 1819780130 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3779.301746 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2779.301746 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13987.531172 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12987.531172 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1819779328 # number of overall hits -system.cpu.icache.overall_miss_latency 3031000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 11218000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses system.cpu.icache.overall_misses 802 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2229000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 10416000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 1 # number of replacements system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 611.013893 # Cycle average of tags in use +system.cpu.icache.tagsinuse 611.364745 # Cycle average of tags in use system.cpu.icache.total_refs 1819779328 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 9112536 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2722.045846 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1719.036352 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 12996.354425 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 10996.354425 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 6952383 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 5880035500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 28074114000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.237053 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 2160153 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 3713381532 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 23753808000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.237053 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 2160153 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 2244708 # number of Writeback accesses(hits+misses) @@ -168,29 +168,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2722.045846 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1719.036352 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 12996.354425 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 10996.354425 # average overall mshr miss latency system.cpu.l2cache.demand_hits 6952383 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 5880035500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 28074114000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.237053 # miss rate for demand accesses system.cpu.l2cache.demand_misses 2160153 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 3713381532 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 23753808000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.237053 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 2160153 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 11357244 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2685.867535 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1719.036352 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 12823.621788 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 10996.354425 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 9167994 # number of overall hits -system.cpu.l2cache.overall_miss_latency 5880035500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 28074114000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.192762 # miss rate for overall accesses system.cpu.l2cache.overall_misses 2189250 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 3713381532 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 23753808000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.190200 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 2160153 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -207,12 +207,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 2127385 # number of replacements system.cpu.l2cache.sampled_refs 2160153 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 31158.106837 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 31194.155037 # Cycle average of tags in use system.cpu.l2cache.total_refs 9167994 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 122436614000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 245730069000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 1038202 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1235165291000 # number of cpu cycles simulated +system.cpu.numCycles 2529654621000 # number of cpu cycles simulated system.cpu.num_insts 1819780129 # Number of instructions executed system.cpu.num_refs 606571345 # Number of memory references system.cpu.workload.PROG:num_syscalls 29 # Number of system calls diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 04020c643..72c4312d9 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -91,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -267,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -306,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -339,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -363,6 +361,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out index 50da468a0..e3bf50f10 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -249,7 +250,7 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -280,14 +281,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -318,14 +318,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -356,7 +355,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -364,4 +362,5 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt index 8e2806190..8dcfd61cf 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 14247678 # Number of BTB hits -global.BPredUnit.BTBLookups 18312009 # Number of BTB lookups -global.BPredUnit.RASInCorrect 1187 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1953985 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 15742663 # Number of conditional branches predicted -global.BPredUnit.lookups 20998495 # Number of BP lookups -global.BPredUnit.usedRAS 1857732 # Number of times the RAS was used to get a target. -host_inst_rate 58248 # Simulator instruction rate (inst/s) -host_mem_usage 156992 # Number of bytes of host memory used -host_seconds 1445.19 # Real time elapsed on the host -host_tick_rate 23712867 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 20592604 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 6080799 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 35412339 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 11200166 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 11874522 # Number of BTB hits +global.BPredUnit.BTBLookups 15445749 # Number of BTB lookups +global.BPredUnit.RASInCorrect 1158 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1931947 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 13190559 # Number of conditional branches predicted +global.BPredUnit.lookups 17824174 # Number of BP lookups +global.BPredUnit.usedRAS 1655464 # Number of times the RAS was used to get a target. +host_inst_rate 74830 # Simulator instruction rate (inst/s) +host_mem_usage 156844 # Number of bytes of host memory used +host_seconds 1124.95 # Real time elapsed on the host +host_tick_rate 39347975 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 14674251 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 4294265 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 31675298 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 10012759 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 84179709 # Number of instructions simulated -sim_seconds 0.034270 # Number of seconds simulated -sim_ticks 34269677000 # Number of ticks simulated +sim_seconds 0.044264 # Number of seconds simulated +sim_ticks 44264420500 # Number of ticks simulated system.cpu.commit.COM:branches 10240685 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3363462 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 2948022 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 59572652 +system.cpu.commit.COM:committed_per_cycle.samples 81602250 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 25280039 4243.56% - 1 15284536 2565.70% - 2 7326530 1229.85% - 3 3334393 559.72% - 4 2152142 361.26% - 5 1242273 208.53% - 6 890288 149.45% - 7 698989 117.33% - 8 3363462 564.60% + 0 44887304 5500.74% + 1 17052684 2089.73% + 2 8186225 1003.19% + 3 3991011 489.08% + 4 1764745 216.26% + 5 1325913 162.48% + 6 892255 109.34% + 7 554091 67.90% + 8 2948022 361.27% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 20034413 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 26537108 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 1941454 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 1919652 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 63250167 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 46410426 # The number of squashed insts skipped by commit system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.814203 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.814203 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 23612894 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 4229.600000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3389.648438 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 23612269 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2643500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000026 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 625 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 113 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1735500 # number of ReadReq MSHR miss cycles +system.cpu.cpi 1.051666 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.051666 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 23047695 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5314.424635 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4545.725646 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 23047078 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3279000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 617 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 114 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2286500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 512 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 503 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3064.490759 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3618.087558 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6493474 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 23379000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.001173 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 7629 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 5893 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 6281000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 3836.081210 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4946.808511 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6493764 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 28153000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001129 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 7339 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 5600 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 8602500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1736 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1739 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 13392.234431 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 13176.111508 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 30113997 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3152.713836 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3566.058719 # average overall mshr miss latency -system.cpu.dcache.demand_hits 30105743 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 26022500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000274 # miss rate for demand accesses -system.cpu.dcache.demand_misses 8254 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 6006 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 8016500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000075 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2248 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 29548798 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3950.729010 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4856.824264 # average overall mshr miss latency +system.cpu.dcache.demand_hits 29540842 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 31432000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000269 # miss rate for demand accesses +system.cpu.dcache.demand_misses 7956 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 5714 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 10889000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000076 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2242 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 30113997 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3152.713836 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3566.058719 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 29548798 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3950.729010 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4856.824264 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 30105743 # number of overall hits -system.cpu.dcache.overall_miss_latency 26022500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000274 # miss rate for overall accesses -system.cpu.dcache.overall_misses 8254 # number of overall misses -system.cpu.dcache.overall_mshr_hits 6006 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 8016500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000075 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2248 # number of overall MSHR misses +system.cpu.dcache.overall_hits 29540842 # number of overall hits +system.cpu.dcache.overall_miss_latency 31432000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000269 # miss rate for overall accesses +system.cpu.dcache.overall_misses 7956 # number of overall misses +system.cpu.dcache.overall_mshr_hits 5714 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 10889000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000076 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2242 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 162 # number of replacements -system.cpu.dcache.sampled_refs 2248 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 163 # number of replacements +system.cpu.dcache.sampled_refs 2242 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1463.572116 # Cycle average of tags in use -system.cpu.dcache.total_refs 30105743 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1457.683096 # Cycle average of tags in use +system.cpu.dcache.total_refs 29540842 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 106 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 6099480 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 13208 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3247204 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 173741531 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 23444029 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 28861256 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 8966698 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 40444 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1167888 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 20998495 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 20206829 # Number of cache lines fetched -system.cpu.fetch.Cycles 51475298 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 3593 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 180749377 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 2035048 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.306371 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 20206829 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 16105410 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.637162 # Number of inst fetches per cycle +system.cpu.dcache.writebacks 107 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 2294607 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 12777 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 2890400 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 151561971 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 53136009 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 26139582 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 6926673 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 40541 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 32053 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 17824174 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 18016265 # Number of cache lines fetched +system.cpu.fetch.Cycles 44691424 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 975254 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 154588435 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 2011658 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.201337 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 18016265 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 13529986 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.746191 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 68539351 +system.cpu.fetch.rateDist.samples 88528924 system.cpu.fetch.rateDist.min_value 0 - 0 37270886 5437.88% - 1 3420236 499.02% - 2 1457458 212.65% - 3 2151808 313.95% - 4 4198050 612.50% - 5 1495508 218.20% - 6 1665097 242.94% - 7 1343985 196.09% - 8 15536323 2266.77% + 0 61853767 6986.84% + 1 2838595 320.64% + 2 1299355 146.77% + 3 1865057 210.67% + 4 3537974 399.64% + 5 1231942 139.16% + 6 1400771 158.23% + 7 1171977 132.38% + 8 13329486 1505.66% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 20206829 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3070.200019 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2096.460002 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 20196480 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 31773500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000512 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 10349 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 236 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 21201500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000500 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 10113 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 18016265 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3877.692156 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2918.898279 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 18006143 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 39250000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000562 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 10122 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 301 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 28666500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000545 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 9821 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1997.080985 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1833.432746 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 20206829 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3070.200019 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2096.460002 # average overall mshr miss latency -system.cpu.icache.demand_hits 20196480 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 31773500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000512 # miss rate for demand accesses -system.cpu.icache.demand_misses 10349 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 236 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 21201500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000500 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 10113 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 18016265 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3877.692156 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2918.898279 # average overall mshr miss latency +system.cpu.icache.demand_hits 18006143 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 39250000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000562 # miss rate for demand accesses +system.cpu.icache.demand_misses 10122 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 301 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 28666500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000545 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 9821 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 20206829 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3070.200019 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2096.460002 # average overall mshr miss latency +system.cpu.icache.overall_accesses 18016265 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3877.692156 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2918.898279 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 20196480 # number of overall hits -system.cpu.icache.overall_miss_latency 31773500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000512 # miss rate for overall accesses -system.cpu.icache.overall_misses 10349 # number of overall misses -system.cpu.icache.overall_mshr_hits 236 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 21201500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000500 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 10113 # number of overall MSHR misses +system.cpu.icache.overall_hits 18006143 # number of overall hits +system.cpu.icache.overall_miss_latency 39250000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000562 # miss rate for overall accesses +system.cpu.icache.overall_misses 10122 # number of overall misses +system.cpu.icache.overall_mshr_hits 301 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 28666500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000545 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 9821 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,162 +215,162 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 8192 # number of replacements -system.cpu.icache.sampled_refs 10113 # Sample count of references to valid blocks. +system.cpu.icache.replacements 7904 # number of replacements +system.cpu.icache.sampled_refs 9821 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1564.702526 # Cycle average of tags in use -system.cpu.icache.total_refs 20196480 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1549.418815 # Cycle average of tags in use +system.cpu.icache.total_refs 18006143 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 2998 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 13347594 # Number of branches executed -system.cpu.iew.EXEC:nop 13508406 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.523954 # Inst execution rate -system.cpu.iew.EXEC:refs 32463851 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 7352116 # Number of stores executed +system.cpu.idleCycles 7902 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 12543861 # Number of branches executed +system.cpu.iew.EXEC:nop 11949352 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.130385 # Inst execution rate +system.cpu.iew.EXEC:refs 31528912 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 7145648 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 95064439 # num instructions consuming a value -system.cpu.iew.WB:count 103132878 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.721353 # average fanout of values written-back +system.cpu.iew.WB:consumers 87529341 # num instructions consuming a value +system.cpu.iew.WB:count 98214425 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.729574 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 68574976 # num instructions producing a value -system.cpu.iew.WB:rate 1.504725 # insts written-back per cycle -system.cpu.iew.WB:sent 104172184 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 2117203 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 606505 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 35412339 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 444 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 632938 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 11200166 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 155150547 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 25111735 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2600272 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 104450796 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 226857 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 63859133 # num instructions producing a value +system.cpu.iew.WB:rate 1.109405 # insts written-back per cycle +system.cpu.iew.WB:sent 99107976 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 2078247 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 190251 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 31675298 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 411 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 2578287 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 10012759 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 138313092 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 24383264 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1412890 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 100071797 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 38223 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 8966698 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 304686 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 20 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 6926673 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 64568 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 1001916 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 10875 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 828690 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 779 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 88969 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 9698 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 15377926 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 4697471 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 88969 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 207130 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1910073 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.228195 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.228195 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 107051068 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 84249 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 9673 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 11640885 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 3510064 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 84249 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 193948 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1884299 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.950872 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.950872 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 101484687 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 7 0.00% # Type of FU issued - IntAlu 66598699 62.21% # Type of FU issued - IntMult 478232 0.45% # Type of FU issued + IntAlu 62609480 61.69% # Type of FU issued + IntMult 467679 0.46% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 2814666 2.63% # Type of FU issued - FloatCmp 115604 0.11% # Type of FU issued - FloatCvt 2391391 2.23% # Type of FU issued - FloatMult 308778 0.29% # Type of FU issued - FloatDiv 755076 0.71% # Type of FU issued - FloatSqrt 324 0.00% # Type of FU issued - MemRead 26034990 24.32% # Type of FU issued - MemWrite 7553301 7.06% # Type of FU issued + FloatAdd 2780950 2.74% # Type of FU issued + FloatCmp 115557 0.11% # Type of FU issued + FloatCvt 2364134 2.33% # Type of FU issued + FloatMult 305451 0.30% # Type of FU issued + FloatDiv 755050 0.74% # Type of FU issued + FloatSqrt 320 0.00% # Type of FU issued + MemRead 24826231 24.46% # Type of FU issued + MemWrite 7259828 7.15% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 2233247 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.020862 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 1739512 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.017141 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 352978 15.81% # attempts to use FU when none available + IntAlu 236478 13.59% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 856 0.04% # attempts to use FU when none available - FloatCmp 8 0.00% # attempts to use FU when none available - FloatCvt 3654 0.16% # attempts to use FU when none available - FloatMult 2325 0.10% # attempts to use FU when none available - FloatDiv 987087 44.20% # attempts to use FU when none available + FloatAdd 1 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 223 0.01% # attempts to use FU when none available + FloatMult 1629 0.09% # attempts to use FU when none available + FloatDiv 705159 40.54% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 766963 34.34% # attempts to use FU when none available - MemWrite 119376 5.35% # attempts to use FU when none available + MemRead 710061 40.82% # attempts to use FU when none available + MemWrite 85961 4.94% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 68539351 +system.cpu.iq.ISSUE:issued_per_cycle.samples 88528924 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 25564605 3729.92% - 1 14833050 2164.17% - 2 10859904 1584.48% - 3 6945297 1013.33% - 4 5154135 752.00% - 5 2881350 420.39% - 6 1567848 228.75% - 7 633355 92.41% - 8 99807 14.56% + 0 43673541 4933.25% + 1 18286123 2065.55% + 2 11155754 1260.13% + 3 6962814 786.50% + 4 4628513 522.82% + 5 2073707 234.24% + 6 1255435 141.81% + 7 360879 40.76% + 8 132158 14.93% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.561892 # Inst issue rate -system.cpu.iq.iqInstsAdded 141641697 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 107051068 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 444 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 56891185 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 501220 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 55 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 52161048 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 12360 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3103.922717 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1864.884465 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 7236 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 15904500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.414563 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 5124 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 9555668 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.414563 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 5124 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 106 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 106 # number of Writeback hits +system.cpu.iq.ISSUE:rate 1.146345 # Inst issue rate +system.cpu.iq.iqInstsAdded 126363329 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 101484687 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 411 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 41115515 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 151595 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 22 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 37587907 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 12063 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4597.386006 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2450.176887 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 6975 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 23391500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.421786 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 5088 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 12466500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.421786 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 5088 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.432865 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.391903 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 12360 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3103.922717 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1864.884465 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 7236 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 15904500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.414563 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 5124 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 12063 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4597.386006 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2450.176887 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 6975 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 23391500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.421786 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 5088 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 9555668 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.414563 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 5124 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 12466500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.421786 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 5088 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 12466 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3103.922717 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1864.884465 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 12170 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4597.386006 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2450.176887 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 7342 # number of overall hits -system.cpu.l2cache.overall_miss_latency 15904500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.411038 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 5124 # number of overall misses +system.cpu.l2cache.overall_hits 7082 # number of overall hits +system.cpu.l2cache.overall_miss_latency 23391500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.418077 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 5088 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 9555668 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.411038 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 5124 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 12466500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.418077 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 5088 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -383,30 +383,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 5124 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 5088 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3431.784338 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7342 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3405.740601 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7082 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 68539351 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 2079138 # Number of cycles rename is blocking +system.cpu.numCycles 88528924 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 1217757 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1661115 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 25239317 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1954833 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 215732838 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 167129936 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 122925813 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 28288722 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 8966698 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 3960770 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 54498452 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 4706 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 484 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 9920797 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 473 # count of temporary serializing insts renamed -system.cpu.timesIdled 2 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 511469 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 54000366 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 581686 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 190129267 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 147303303 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 108348051 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 25314451 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 6926673 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1065045 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 39920690 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 4632 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 447 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 2624388 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 437 # count of temporary serializing insts renamed +system.cpu.timesIdled 98 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini index 24a71167b..3cb797e6a 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out index 296e0472f..47defa937 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt index b11bd8cad..acfa7c9dd 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 754988 # Simulator instruction rate (inst/s) -host_mem_usage 150624 # Number of bytes of host memory used -host_seconds 121.73 # Real time elapsed on the host -host_tick_rate 377492666 # Simulator tick rate (ticks/s) +host_inst_rate 935813 # Simulator instruction rate (inst/s) +host_mem_usage 150648 # Number of bytes of host memory used +host_seconds 98.21 # Real time elapsed on the host +host_tick_rate 467904361 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903057 # Number of instructions simulated sim_seconds 0.045952 # Number of seconds simulated diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini index cd04983c0..7edcc9166 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out index 3089af658..3ed492885 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt index b45fb965e..9f5824722 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 335846 # Simulator instruction rate (inst/s) -host_mem_usage 156240 # Number of bytes of host memory used -host_seconds 273.71 # Real time elapsed on the host -host_tick_rate 216396349 # Simulator tick rate (ticks/s) +host_inst_rate 651405 # Simulator instruction rate (inst/s) +host_mem_usage 156232 # Number of bytes of host memory used +host_seconds 141.08 # Real time elapsed on the host +host_tick_rate 840119018 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903057 # Number of instructions simulated -sim_seconds 0.059229 # Number of seconds simulated -sim_ticks 59229023000 # Number of ticks simulated +sim_seconds 0.118528 # Number of seconds simulated +sim_ticks 118527938000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3629.746835 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2629.746835 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 13776.371308 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12776.371308 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 19995724 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1720500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 6530000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 474 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1246500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 6056000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 474 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3602.116705 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2602.116705 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 13970.251716 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12970.251716 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 6499355 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 6296500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 24420000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1748 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 4548500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 22672000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3608.010801 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2608.010801 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 13928.892889 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12928.892889 # average overall mshr miss latency system.cpu.dcache.demand_hits 26495079 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 8017000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 30950000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses system.cpu.dcache.demand_misses 2222 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 5795000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 28728000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 2222 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3608.010801 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2608.010801 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 13928.892889 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12928.892889 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 26495079 # number of overall hits -system.cpu.dcache.overall_miss_latency 8017000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 30950000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses system.cpu.dcache.overall_misses 2222 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 5795000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 28728000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 2222 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.sampled_refs 2222 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1441.710869 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1441.614290 # Cycle average of tags in use system.cpu.dcache.total_refs 26495079 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 104 # number of writebacks system.cpu.icache.ReadReq_accesses 91903058 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3077.908343 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2077.908343 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 12615.981199 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11615.981199 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 91894548 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 26193000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 107362000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 17683000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 98852000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 91903058 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3077.908343 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2077.908343 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 12615.981199 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11615.981199 # average overall mshr miss latency system.cpu.icache.demand_hits 91894548 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 26193000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 107362000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 17683000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 98852000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 91903058 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3077.908343 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2077.908343 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 12615.981199 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11615.981199 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 91894548 # number of overall hits -system.cpu.icache.overall_miss_latency 26193000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 107362000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses system.cpu.icache.overall_misses 8510 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 17683000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 98852000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 6681 # number of replacements system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1418.735069 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1418.637331 # Cycle average of tags in use system.cpu.icache.total_refs 91894548 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 10732 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2703.820319 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1702.820319 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 5968 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 12881000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 61932000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.443906 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 4764 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 8112236 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 52404000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.443906 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 4764 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses) @@ -164,29 +164,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 10732 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2703.820319 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1702.820319 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 5968 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 12881000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 61932000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.443906 # miss rate for demand accesses system.cpu.l2cache.demand_misses 4764 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 8112236 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 52404000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.443906 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 4764 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 10836 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2703.820319 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1702.820319 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 6072 # number of overall hits -system.cpu.l2cache.overall_miss_latency 12881000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 61932000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.439646 # miss rate for overall accesses system.cpu.l2cache.overall_misses 4764 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 8112236 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 52404000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.439646 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 4764 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -203,12 +203,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 4764 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3173.029647 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 3172.809799 # Cycle average of tags in use system.cpu.l2cache.total_refs 6072 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 59229023000 # number of cpu cycles simulated +system.cpu.numCycles 118527938000 # number of cpu cycles simulated system.cpu.num_insts 91903057 # Number of instructions executed system.cpu.num_refs 26537109 # Number of memory references system.cpu.workload.PROG:num_syscalls 389 # Number of system calls diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini index 5aa5f86fe..3dcf027c2 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out index f078d661c..d448056f4 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt index 5532c6dba..c41d3b35f 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 668374 # Simulator instruction rate (inst/s) -host_mem_usage 150556 # Number of bytes of host memory used -host_seconds 289.41 # Real time elapsed on the host -host_tick_rate 334186387 # Simulator tick rate (ticks/s) +host_inst_rate 673586 # Simulator instruction rate (inst/s) +host_mem_usage 150548 # Number of bytes of host memory used +host_seconds 287.17 # Real time elapsed on the host +host_tick_rate 336792536 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193435973 # Number of instructions simulated sim_seconds 0.096718 # Number of seconds simulated diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout index 2cdcc205c..f878587c3 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout @@ -18,8 +18,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 27 2007 14:35:32 -M5 started Fri Apr 27 16:03:50 2007 +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 16:48:51 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic tests/run.py long/70.twolf/sparc/linux/simple-atomic Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini index ec76ab996..2a87cb78d 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out index dbecb5fa5..f79151c21 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt index 2c6679b72..0f4d2b473 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 490451 # Simulator instruction rate (inst/s) -host_mem_usage 156012 # Number of bytes of host memory used -host_seconds 394.40 # Real time elapsed on the host -host_tick_rate 342594746 # Simulator tick rate (ticks/s) +host_inst_rate 500598 # Simulator instruction rate (inst/s) +host_mem_usage 156000 # Number of bytes of host memory used +host_seconds 386.41 # Real time elapsed on the host +host_tick_rate 699597163 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193435973 # Number of instructions simulated -sim_seconds 0.135121 # Number of seconds simulated -sim_ticks 135120940500 # Number of ticks simulated +sim_seconds 0.270332 # Number of seconds simulated +sim_ticks 270331639000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 57734138 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3786.144578 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2786.144578 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 57733640 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1885500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 6972000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 498 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1387500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 6474000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 22406 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 3500 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2500 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 14000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 13000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 22405 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 3500 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 14000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.000045 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 1 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 2500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 13000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.000045 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 1 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 18976414 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3587.016575 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2587.016575 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 13987.108656 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12987.108656 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 18975328 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3895500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 15190000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000057 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1086 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 2809500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 14104000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000057 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1086 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 76710552 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3649.621212 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2649.621212 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 13991.161616 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12991.161616 # average overall mshr miss latency system.cpu.dcache.demand_hits 76708968 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 5781000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 22162000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses system.cpu.dcache.demand_misses 1584 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4197000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 20578000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 1584 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 76710552 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3649.621212 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2649.621212 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 13991.161616 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12991.161616 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 76708968 # number of overall hits -system.cpu.dcache.overall_miss_latency 5781000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 22162000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses system.cpu.dcache.overall_misses 1584 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4197000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 20578000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 1584 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 26 # number of replacements system.cpu.dcache.sampled_refs 1585 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1237.515646 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1237.473868 # Cycle average of tags in use system.cpu.dcache.total_refs 76731373 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 23 # number of writebacks system.cpu.icache.ReadReq_accesses 193435974 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3066.269971 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2066.269971 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 12584.365830 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11584.365830 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 193423706 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 37617000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 154385000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000063 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 12268 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 25349000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 142117000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000063 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 12268 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 193435974 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3066.269971 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2066.269971 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 12584.365830 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11584.365830 # average overall mshr miss latency system.cpu.icache.demand_hits 193423706 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 37617000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 154385000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000063 # miss rate for demand accesses system.cpu.icache.demand_misses 12268 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 25349000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 142117000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000063 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 12268 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 193435974 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3066.269971 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2066.269971 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 12584.365830 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11584.365830 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 193423706 # number of overall hits -system.cpu.icache.overall_miss_latency 37617000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 154385000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000063 # miss rate for overall accesses system.cpu.icache.overall_misses 12268 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 25349000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 142117000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000063 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 12268 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -148,19 +148,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 10342 # number of replacements system.cpu.icache.sampled_refs 12268 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1591.858190 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1591.809550 # Cycle average of tags in use system.cpu.icache.total_refs 193423706 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 13852 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2720.824463 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1719.824463 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 8685 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 14058500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 67171000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.373015 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 5167 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 8886333 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 56837000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.373015 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 5167 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 23 # number of Writeback accesses(hits+misses) @@ -174,29 +174,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 13852 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2720.824463 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1719.824463 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 8685 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 14058500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 67171000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.373015 # miss rate for demand accesses system.cpu.l2cache.demand_misses 5167 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 8886333 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 56837000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.373015 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 5167 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 13875 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2720.824463 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1719.824463 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 8708 # number of overall hits -system.cpu.l2cache.overall_miss_latency 14058500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 67171000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.372396 # miss rate for overall accesses system.cpu.l2cache.overall_misses 5167 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 8886333 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 56837000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.372396 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 5167 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -213,12 +213,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 5167 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3507.285738 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 3507.169610 # Cycle average of tags in use system.cpu.l2cache.total_refs 8708 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 135120940500 # number of cpu cycles simulated +system.cpu.numCycles 270331639000 # number of cpu cycles simulated system.cpu.num_insts 193435973 # Number of instructions executed system.cpu.num_refs 76732959 # Number of memory references system.cpu.workload.PROG:num_syscalls 396 # Number of system calls diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout index eb4e3bbfa..316a2c0d3 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout @@ -18,11 +18,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 27 2007 14:35:32 -M5 started Fri Apr 27 16:08:41 2007 +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 16:53:38 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing tests/run.py long/70.twolf/sparc/linux/simple-timing Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second -Exiting @ tick 135120940500 because target called exit() +Exiting @ tick 270331639000 because target called exit() diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini index a5e3f40d7..d0738b960 100644 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini @@ -33,9 +33,14 @@ symbolfile= [system.bridge] type=Bridge -delay=0 -queue_size_a=16 -queue_size_b=16 +delay=100 +fix_partial_write_a=false +fix_partial_write_b=true +nack_delay=8 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 write_ack=false side_a=system.iobus.port[14] side_b=system.membus.port[2] @@ -111,6 +116,7 @@ sys=system [system.iobus] type=Bus children=responder +block_size=64 bus_id=0 clock=2 responder_set=false @@ -137,6 +143,7 @@ pio=system.iobus.default [system.membus] type=Bus children=responder +block_size=64 bus_id=1 clock=2 responder_set=false diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.out b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.out index d7c3ccbd9..bc35fc4e7 100644 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.out +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.out @@ -69,6 +69,7 @@ bus_id=1 clock=2 width=64 responder_set=false +block_size=64 [system.intrctrl] type=IntrControl @@ -103,10 +104,15 @@ zero=true [system.bridge] type=Bridge -queue_size_a=16 -queue_size_b=16 -delay=0 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +delay=100 +nack_delay=8 write_ack=false +fix_partial_write_a=false +fix_partial_write_b=true [system.disk0.image.child] type=RawDiskImage @@ -361,6 +367,7 @@ bus_id=0 clock=2 width=64 responder_set=false +block_size=64 [system.iobus.responder] type=IsaFake diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt index 1e1ba049c..5229bd3a6 100644 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 571923 # Simulator instruction rate (inst/s) -host_mem_usage 373992 # Number of bytes of host memory used -host_seconds 3905.40 # Real time elapsed on the host -host_tick_rate 571972 # Simulator tick rate (ticks/s) +host_inst_rate 584673 # Simulator instruction rate (inst/s) +host_mem_usage 374168 # Number of bytes of host memory used +host_seconds 3820.23 # Real time elapsed on the host +host_tick_rate 584723 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks sim_insts 2233583679 # Number of instructions simulated sim_seconds 1.116889 # Number of seconds simulated diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr index d07f16195..cf3ec3bba 100644 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr @@ -3,10132 +3,10 @@ Warning: rounding error > tolerance Warning: rounding error > tolerance 0.002000 rounded to 0 warn: No kernel set for full system simulation. Assuming you know what you're doing... +Listening for t1000 connection on port 3456 Listening for t1000 connection on port 3457 -Listening for t1000 connection on port 3458 -0: system.remote_gdb.listener: listening for remote gdb on port 7001 +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: Ignoring write to SPARC ERROR regsiter warn: Ignoring write to SPARC ERROR regsiter warn: Don't know what interrupt to clear for console. -warn: Attempted to set the CWP to 31 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout index 0639edaa5..ef048f157 100644 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2007 12:26:45 -M5 started Fri Mar 30 12:26:47 2007 +M5 compiled May 15 2007 17:08:10 +M5 started Tue May 15 17:08:12 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic tests/run.py long/80.solaris-boot/sparc/solaris/t1000-simple-atomic Global frequency set at 2000000000 ticks per second diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 2a139492e..882c78529 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -91,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -267,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -306,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -339,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -363,6 +361,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out index 8155faf63..701034053 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -249,7 +250,7 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -280,14 +281,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -318,14 +318,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -356,7 +355,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -364,4 +362,5 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index 86aa4129f..c07021f5a 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 606 # Number of BTB hits -global.BPredUnit.BTBLookups 1858 # Number of BTB lookups -global.BPredUnit.RASInCorrect 54 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 415 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1270 # Number of conditional branches predicted -global.BPredUnit.lookups 2195 # Number of BP lookups -global.BPredUnit.usedRAS 306 # Number of times the RAS was used to get a target. -host_inst_rate 22780 # Simulator instruction rate (inst/s) +global.BPredUnit.BTBHits 524 # Number of BTB hits +global.BPredUnit.BTBLookups 1590 # Number of BTB lookups +global.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 422 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1093 # Number of conditional branches predicted +global.BPredUnit.lookups 1843 # Number of BP lookups +global.BPredUnit.usedRAS 241 # Number of times the RAS was used to get a target. +host_inst_rate 54565 # Simulator instruction rate (inst/s) host_mem_usage 154084 # Number of bytes of host memory used -host_seconds 0.25 # Real time elapsed on the host -host_tick_rate 14337041 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 31 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 138 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2061 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1230 # Number of stores inserted to the mem dependence unit. +host_seconds 0.10 # Real time elapsed on the host +host_tick_rate 44392410 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 17 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 127 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 1876 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1144 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5623 # Number of instructions simulated -sim_seconds 0.000004 # Number of seconds simulated -sim_ticks 3543500 # Number of ticks simulated +sim_seconds 0.000005 # Number of seconds simulated +sim_ticks 4588000 # Number of ticks simulated system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 121 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 104 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 6315 +system.cpu.commit.COM:committed_per_cycle.samples 8514 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 4255 6737.93% - 1 915 1448.93% - 2 408 646.08% - 3 162 256.53% - 4 140 221.69% - 5 91 144.10% - 6 121 191.61% - 7 102 161.52% - 8 121 191.61% + 0 6195 7276.25% + 1 1158 1360.11% + 2 469 550.86% + 3 176 206.72% + 4 131 153.86% + 5 99 116.28% + 6 109 128.02% + 7 73 85.74% + 8 104 122.15% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,69 +43,69 @@ system.cpu.commit.COM:loads 979 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 1791 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 341 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 350 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4458 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 3588 # The number of squashed insts skipped by commit system.cpu.committedInsts 5623 # Number of Instructions Simulated system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.260537 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.260537 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1516 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 4941.176471 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4361.386139 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1380 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 672000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.089710 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 136 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 440500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.066623 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses +system.cpu.cpi 1.635604 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.635604 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1475 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5928.571429 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5385 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1342 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 788500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.090169 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 133 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 33 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 538500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.067797 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3265.671642 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3819.444444 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 477 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 1094000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.412562 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 335 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 263 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 275000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.088670 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 72 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 4501.457726 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5116.438356 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 469 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 1544000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.422414 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 343 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 270 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 373500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 10.734104 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 10.468208 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2328 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3749.469214 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 4135.838150 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1857 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1766000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.202320 # miss rate for demand accesses -system.cpu.dcache.demand_misses 471 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 298 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 715500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.074313 # mshr miss rate for demand accesses +system.cpu.dcache.demand_accesses 2287 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 4900.210084 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 5271.676301 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1811 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 2332500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.208133 # miss rate for demand accesses +system.cpu.dcache.demand_misses 476 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 303 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 912000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.075645 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 173 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2328 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3749.469214 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 4135.838150 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 2287 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 4900.210084 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 5271.676301 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1857 # number of overall hits -system.cpu.dcache.overall_miss_latency 1766000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.202320 # miss rate for overall accesses -system.cpu.dcache.overall_misses 471 # number of overall misses -system.cpu.dcache.overall_mshr_hits 298 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 715500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.074313 # mshr miss rate for overall accesses +system.cpu.dcache.overall_hits 1811 # number of overall hits +system.cpu.dcache.overall_miss_latency 2332500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.208133 # miss rate for overall accesses +system.cpu.dcache.overall_misses 476 # number of overall misses +system.cpu.dcache.overall_mshr_hits 303 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 912000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.075645 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 173 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -121,89 +121,89 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 111.557376 # Cycle average of tags in use -system.cpu.dcache.total_refs 1857 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 112.670676 # Cycle average of tags in use +system.cpu.dcache.total_refs 1811 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 381 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 81 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 172 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12164 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 3741 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2151 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 772 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 244 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 43 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 2195 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1616 # Number of cache lines fetched -system.cpu.fetch.Cycles 3951 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 151 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13452 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 448 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.309678 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1616 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 912 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.897856 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 389 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 75 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 144 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 10499 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 6230 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 1848 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 682 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 228 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 48 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 1843 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1471 # Number of cache lines fetched +system.cpu.fetch.Cycles 3451 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 11450 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 455 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.200391 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1471 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 765 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.244971 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 7088 +system.cpu.fetch.rateDist.samples 9197 system.cpu.fetch.rateDist.min_value 0 - 0 4755 6708.52% - 1 197 277.93% - 2 177 249.72% - 3 163 229.97% - 4 234 330.14% - 5 170 239.84% - 6 198 279.35% - 7 114 160.84% - 8 1080 1523.70% + 0 7219 7849.30% + 1 167 181.58% + 2 147 159.83% + 3 129 140.26% + 4 200 217.46% + 5 139 151.14% + 6 181 196.80% + 7 99 107.64% + 8 916 995.98% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 1616 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4068.597561 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3148.089172 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1288 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1334500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.202970 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 328 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 988500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.194307 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 314 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 1471 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5375.757576 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4524.038462 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1141 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1774000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.224337 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 330 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 18 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 1411500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.212101 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 312 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4.101911 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.657051 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1616 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4068.597561 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3148.089172 # average overall mshr miss latency -system.cpu.icache.demand_hits 1288 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1334500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.202970 # miss rate for demand accesses -system.cpu.icache.demand_misses 328 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 14 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 988500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.194307 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 314 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 1471 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5375.757576 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4524.038462 # average overall mshr miss latency +system.cpu.icache.demand_hits 1141 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1774000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.224337 # miss rate for demand accesses +system.cpu.icache.demand_misses 330 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 18 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 1411500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.212101 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 312 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1616 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4068.597561 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3148.089172 # average overall mshr miss latency +system.cpu.icache.overall_accesses 1471 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5375.757576 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4524.038462 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1288 # number of overall hits -system.cpu.icache.overall_miss_latency 1334500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.202970 # miss rate for overall accesses -system.cpu.icache.overall_misses 328 # number of overall misses -system.cpu.icache.overall_mshr_hits 14 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 988500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.194307 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 314 # number of overall MSHR misses +system.cpu.icache.overall_hits 1141 # number of overall hits +system.cpu.icache.overall_miss_latency 1774000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.224337 # miss rate for overall accesses +system.cpu.icache.overall_misses 330 # number of overall misses +system.cpu.icache.overall_mshr_hits 18 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 1411500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.212101 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 312 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -216,78 +216,79 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 312 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 166.037293 # Cycle average of tags in use -system.cpu.icache.total_refs 1288 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 165.938349 # Cycle average of tags in use +system.cpu.icache.total_refs 1141 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 1203 # Number of branches executed -system.cpu.iew.EXEC:nop 41 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.125423 # Inst execution rate -system.cpu.iew.EXEC:refs 2585 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 989 # Number of stores executed +system.cpu.idleCycles 2475 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1148 # Number of branches executed +system.cpu.iew.EXEC:nop 40 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.837338 # Inst execution rate +system.cpu.iew.EXEC:refs 2524 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 977 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5598 # num instructions consuming a value -system.cpu.iew.WB:count 7767 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.741872 # average fanout of values written-back +system.cpu.iew.WB:consumers 5205 # num instructions consuming a value +system.cpu.iew.WB:count 7402 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.742747 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4153 # num instructions producing a value -system.cpu.iew.WB:rate 1.095796 # insts written-back per cycle -system.cpu.iew.WB:sent 7849 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 3 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2061 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 240 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1230 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 10115 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1596 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 554 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 7977 # Number of executed instructions +system.cpu.iew.WB:producers 3866 # num instructions producing a value +system.cpu.iew.WB:rate 0.804828 # insts written-back per cycle +system.cpu.iew.WB:sent 7467 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 374 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 1876 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 315 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1144 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9245 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1547 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 280 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 7701 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 772 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 682 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 57 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 50 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 68 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 63 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1082 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 418 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 68 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 284 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 109 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.793313 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.793313 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8531 # Type of FU issued +system.cpu.iew.lsq.thread.0.squashedLoads 897 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 332 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 63 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 263 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 111 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.611395 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.611395 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 7981 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 2 0.02% # Type of FU issued - IntAlu 5713 66.97% # Type of FU issued + (null) 2 0.03% # Type of FU issued + IntAlu 5322 66.68% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued + FloatAdd 2 0.03% # Type of FU issued FloatCmp 0 0.00% # Type of FU issued FloatCvt 0 0.00% # Type of FU issued FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1773 20.78% # Type of FU issued - MemWrite 1040 12.19% # Type of FU issued + MemRead 1662 20.82% # Type of FU issued + MemWrite 992 12.43% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 128 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.015004 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 106 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.013282 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 7 5.47% # attempts to use FU when none available + IntAlu 0 0.00% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -296,43 +297,43 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 78 60.94% # attempts to use FU when none available - MemWrite 43 33.59% # attempts to use FU when none available + MemRead 71 66.98% # attempts to use FU when none available + MemWrite 35 33.02% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 7088 +system.cpu.iq.ISSUE:issued_per_cycle.samples 9197 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 4068 5739.28% - 1 771 1087.75% - 2 763 1076.47% - 3 485 684.26% - 4 504 711.06% - 5 295 416.20% - 6 144 203.16% - 7 40 56.43% - 8 18 25.40% + 0 5952 6471.68% + 1 1107 1203.65% + 2 919 999.24% + 3 442 480.59% + 4 375 407.74% + 5 250 271.83% + 6 115 125.04% + 7 26 28.27% + 8 11 11.96% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.203584 # Inst issue rate -system.cpu.iq.iqInstsAdded 10051 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8531 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4086 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2494 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 485 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3318.556701 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1934.377320 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1609500 # number of ReadReq miss cycles +system.cpu.iq.ISSUE:rate 0.867783 # Inst issue rate +system.cpu.iq.iqInstsAdded 9183 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 7981 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 3171 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 22 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 5 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2045 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 483 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4639.751553 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2463.768116 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 2241000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 485 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 938173 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_misses 483 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1190000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 485 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 483 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -341,32 +342,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 485 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3318.556701 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1934.377320 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 483 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4639.751553 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2463.768116 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1609500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 2241000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 485 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 483 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 938173 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 1190000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 485 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 483 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 485 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3318.556701 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1934.377320 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 483 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4639.751553 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2463.768116 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1609500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 2241000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 485 # number of overall misses +system.cpu.l2cache.overall_misses 483 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 938173 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 1190000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 485 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 483 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -379,28 +380,29 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 485 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 483 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 277.255174 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 278.222582 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 7088 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 3 # Number of cycles rename is blocking +system.cpu.numCycles 9197 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 15 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 3933 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 65 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 14798 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11577 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8671 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 2005 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 772 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 115 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4620 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 260 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 396 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed +system.cpu.rename.RENAME:IdleCycles 6383 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 70 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 12854 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 10031 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 7485 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 1746 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 682 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 101 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 3434 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 270 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 380 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed +system.cpu.timesIdled 25 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout index eeba3846f..3ab3ef422 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:06 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:39 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 3543500 because target called exit() +Exiting @ tick 4588000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini index 26009ca4f..bf00075ce 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out index f8e40871a..117159126 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt index 0f64469e9..4e1bd9447 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 357156 # Simulator instruction rate (inst/s) -host_mem_usage 148180 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 171417285 # Simulator tick rate (ticks/s) +host_inst_rate 576538 # Simulator instruction rate (inst/s) +host_mem_usage 148208 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 276546720 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout index 5acc408a3..6848303a8 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:08 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:40 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 2820500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index 025531062..6daf0bd85 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out index fa1054e9e..7041702bf 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt index afdac247d..ad908bf47 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 215467 # Simulator instruction rate (inst/s) -host_mem_usage 153656 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 193088667 # Simulator tick rate (ticks/s) +host_inst_rate 280990 # Simulator instruction rate (inst/s) +host_mem_usage 153668 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 642654954 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated -sim_seconds 0.000005 # Number of seconds simulated -sim_ticks 5135000 # Number of ticks simulated +sim_seconds 0.000013 # Number of seconds simulated +sim_ticks 13168000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 979 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3750 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2750 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 887 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 345000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 1288000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.093973 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 253000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1196000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.093973 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 92 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3582.191781 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2582.191781 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 739 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 261500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 1022000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.089901 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 188500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 949000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 1791 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3675.757576 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2675.757576 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.demand_hits 1626 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 606500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 2310000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.092127 # miss rate for demand accesses system.cpu.dcache.demand_misses 165 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 441500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 2145000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.092127 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 165 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 1791 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3675.757576 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2675.757576 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1626 # number of overall hits -system.cpu.dcache.overall_miss_latency 606500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 2310000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.092127 # miss rate for overall accesses system.cpu.dcache.overall_misses 165 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 441500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 2145000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.092127 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 105.359700 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 103.640117 # Cycle average of tags in use system.cpu.dcache.total_refs 1626 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 5643 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3729.241877 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2729.241877 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13960.288809 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12960.288809 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 5366 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1033000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 3867000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.049087 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 277 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 756000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 3590000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.049087 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 277 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 5643 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3729.241877 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2729.241877 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13960.288809 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12960.288809 # average overall mshr miss latency system.cpu.icache.demand_hits 5366 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1033000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 3867000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.049087 # miss rate for demand accesses system.cpu.icache.demand_misses 277 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 756000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 3590000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.049087 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 277 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 5643 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3729.241877 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2729.241877 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13960.288809 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12960.288809 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 5366 # number of overall hits -system.cpu.icache.overall_miss_latency 1033000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 3867000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.049087 # miss rate for overall accesses system.cpu.icache.overall_misses 277 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 756000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 3590000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.049087 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 277 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 277 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 131.245403 # Cycle average of tags in use +system.cpu.icache.tagsinuse 129.241810 # Cycle average of tags in use system.cpu.icache.total_refs 5366 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 441 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2712.018141 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1711.018141 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1196000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 5733000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 441 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 754559 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 4851000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 441 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2712.018141 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1711.018141 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1196000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 5733000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 441 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 754559 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 4851000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 441 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2712.018141 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1711.018141 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1196000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 5733000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 441 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 754559 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 4851000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 441 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 441 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 236.577060 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 232.802947 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5135000 # number of cpu cycles simulated +system.cpu.numCycles 13168000 # number of cpu cycles simulated system.cpu.num_insts 5642 # Number of instructions executed system.cpu.num_refs 1792 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout index a79e87c66..3fc11f801 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:09 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:40 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 5135000 because target called exit() +Exiting @ tick 13168000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index 1e3b2746e..40a8f1a84 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -91,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -267,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -306,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -339,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -363,6 +361,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out index 5df02e4ff..46dc2c36a 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -249,7 +250,7 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -280,14 +281,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -318,14 +318,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -356,7 +355,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -364,4 +362,5 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt index d3074bcf9..c1b1b7625 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 162 # Number of BTB hits -global.BPredUnit.BTBLookups 671 # Number of BTB lookups -global.BPredUnit.RASInCorrect 36 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 220 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 427 # Number of conditional branches predicted -global.BPredUnit.lookups 860 # Number of BP lookups -global.BPredUnit.usedRAS 174 # Number of times the RAS was used to get a target. -host_inst_rate 31252 # Simulator instruction rate (inst/s) +global.BPredUnit.BTBHits 132 # Number of BTB hits +global.BPredUnit.BTBLookups 584 # Number of BTB lookups +global.BPredUnit.RASInCorrect 28 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 208 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 376 # Number of conditional branches predicted +global.BPredUnit.lookups 738 # Number of BP lookups +global.BPredUnit.usedRAS 140 # Number of times the RAS was used to get a target. +host_inst_rate 54176 # Simulator instruction rate (inst/s) host_mem_usage 153592 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -host_tick_rate 21107113 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 9 # Number of conflicting loads. +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 46286693 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 8 # Number of conflicting loads. memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 692 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 385 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 608 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 357 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 1619000 # Number of ticks simulated +sim_ticks 2053000 # Number of ticks simulated system.cpu.commit.COM:branches 396 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 59 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 41 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 2977 +system.cpu.commit.COM:committed_per_cycle.samples 3906 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 2102 7060.80% - 1 212 712.13% - 2 297 997.65% - 3 114 382.94% - 4 83 278.80% - 5 58 194.83% - 6 30 100.77% - 7 22 73.90% - 8 59 198.19% + 0 2949 7549.92% + 1 266 681.00% + 2 333 852.53% + 3 131 335.38% + 4 74 189.45% + 5 64 163.85% + 6 29 74.24% + 7 19 48.64% + 8 41 104.97% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 415 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 709 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 138 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 128 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1420 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 978 # The number of squashed insts skipped by commit system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 1.356933 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.356933 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 537 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 4625 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3811.475410 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 465 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 333000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.134078 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 72 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 232500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.113594 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses +system.cpu.cpi 1.721408 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.721408 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 514 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5456.521739 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4737.288136 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 445 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 376500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.134241 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 69 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 279500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.114786 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 59 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 5013.888889 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4520.833333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 222 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 361000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.244898 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 72 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 48 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 108500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 5669.014085 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5020 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 223 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 402500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.241497 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 71 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 46 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 125500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.085034 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 25 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.082353 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 7.952381 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 831 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 4819.444444 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 4011.764706 # average overall mshr miss latency -system.cpu.dcache.demand_hits 687 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 694000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.173285 # miss rate for demand accesses -system.cpu.dcache.demand_misses 144 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 59 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 341000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.102286 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 808 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 5564.285714 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4821.428571 # average overall mshr miss latency +system.cpu.dcache.demand_hits 668 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 779000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.173267 # miss rate for demand accesses +system.cpu.dcache.demand_misses 140 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 405000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.103960 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 84 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 831 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 4819.444444 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 4011.764706 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 808 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 5564.285714 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4821.428571 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 687 # number of overall hits -system.cpu.dcache.overall_miss_latency 694000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.173285 # miss rate for overall accesses -system.cpu.dcache.overall_misses 144 # number of overall misses -system.cpu.dcache.overall_mshr_hits 59 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 341000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.102286 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses +system.cpu.dcache.overall_hits 668 # number of overall hits +system.cpu.dcache.overall_miss_latency 779000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.173267 # miss rate for overall accesses +system.cpu.dcache.overall_misses 140 # number of overall misses +system.cpu.dcache.overall_mshr_hits 56 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 405000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.103960 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 84 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -119,90 +119,89 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 84 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 50.824604 # Cycle average of tags in use -system.cpu.dcache.total_refs 687 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 51.851940 # Cycle average of tags in use +system.cpu.dcache.total_refs 668 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 83 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 83 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 138 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 4642 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 2009 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 884 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 261 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 313 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 2 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 860 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 736 # Number of cache lines fetched -system.cpu.fetch.Cycles 1668 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 78 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 5463 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 230 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.265514 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 736 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 336 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.686632 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 95 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 81 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 123 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 4033 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 3045 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 767 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 202 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 298 # Number of squashed instructions handled by decode +system.cpu.fetch.Branches 738 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 654 # Number of cache lines fetched +system.cpu.fetch.Cycles 1440 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 120 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 4685 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 218 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.179606 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 654 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 272 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.140180 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 3239 +system.cpu.fetch.rateDist.samples 4109 system.cpu.fetch.rateDist.min_value 0 - 0 2309 7128.74% - 1 47 145.11% - 2 82 253.16% - 3 70 216.12% - 4 128 395.18% - 5 58 179.07% - 6 37 114.23% - 7 46 142.02% - 8 462 1426.37% + 0 3325 8091.99% + 1 32 77.88% + 2 74 180.09% + 3 53 128.99% + 4 99 240.93% + 5 49 119.25% + 6 38 92.48% + 7 35 85.18% + 8 404 983.21% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 736 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4129.533679 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3209.677419 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 543 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 797000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.262228 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 193 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 7 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 597000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.252717 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_accesses 654 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5296.019900 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4553.763441 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 453 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1064500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.307339 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 201 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 847000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.284404 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 186 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2.919355 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2.435484 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 736 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4129.533679 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3209.677419 # average overall mshr miss latency -system.cpu.icache.demand_hits 543 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 797000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.262228 # miss rate for demand accesses -system.cpu.icache.demand_misses 193 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 7 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 597000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.252717 # mshr miss rate for demand accesses +system.cpu.icache.demand_accesses 654 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5296.019900 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4553.763441 # average overall mshr miss latency +system.cpu.icache.demand_hits 453 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1064500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.307339 # miss rate for demand accesses +system.cpu.icache.demand_misses 201 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 15 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 847000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.284404 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 186 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 736 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4129.533679 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3209.677419 # average overall mshr miss latency +system.cpu.icache.overall_accesses 654 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5296.019900 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4553.763441 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 543 # number of overall hits -system.cpu.icache.overall_miss_latency 797000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.262228 # miss rate for overall accesses -system.cpu.icache.overall_misses 193 # number of overall misses -system.cpu.icache.overall_mshr_hits 7 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 597000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.252717 # mshr miss rate for overall accesses +system.cpu.icache.overall_hits 453 # number of overall hits +system.cpu.icache.overall_miss_latency 1064500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.307339 # miss rate for overall accesses +system.cpu.icache.overall_misses 201 # number of overall misses +system.cpu.icache.overall_mshr_hits 15 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 847000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.284404 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 186 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -218,58 +217,59 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 186 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 104.079729 # Cycle average of tags in use -system.cpu.icache.total_refs 543 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 106.237740 # Cycle average of tags in use +system.cpu.icache.total_refs 453 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 535 # Number of branches executed -system.cpu.iew.EXEC:nop 256 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.978388 # Inst execution rate -system.cpu.iew.EXEC:refs 913 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 339 # Number of stores executed +system.cpu.idleCycles 2992 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 501 # Number of branches executed +system.cpu.iew.EXEC:nop 234 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.727184 # Inst execution rate +system.cpu.iew.EXEC:refs 878 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 333 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1857 # num instructions consuming a value -system.cpu.iew.WB:count 3126 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.787291 # average fanout of values written-back +system.cpu.iew.WB:consumers 1652 # num instructions consuming a value +system.cpu.iew.WB:count 2914 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.799637 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1462 # num instructions producing a value -system.cpu.iew.WB:rate 0.965113 # insts written-back per cycle -system.cpu.iew.WB:sent 3139 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 156 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 1321 # num instructions producing a value +system.cpu.iew.WB:rate 0.709175 # insts written-back per cycle +system.cpu.iew.WB:sent 2931 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 135 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 692 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 99 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 385 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 4013 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 574 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 208 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 3169 # Number of executed instructions +system.cpu.iew.iewDispLoadInsts 608 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 7 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 357 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 3571 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 545 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 87 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 2988 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 261 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 202 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 27 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 22 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 10 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 277 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 91 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 193 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 63 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 103 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.736956 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.736956 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 3377 # Type of FU issued +system.cpu.iew.predictedNotTakenIncorrect 98 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 37 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.580920 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.580920 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 3075 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 0 0.00% # Type of FU issued - IntAlu 2413 71.45% # Type of FU issued + IntAlu 2178 70.83% # Type of FU issued IntMult 1 0.03% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 0 0.00% # Type of FU issued @@ -278,16 +278,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 617 18.27% # Type of FU issued - MemWrite 346 10.25% # Type of FU issued + MemRead 561 18.24% # Type of FU issued + MemWrite 335 10.89% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 37 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.010956 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011382 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 1 2.70% # attempts to use FU when none available + IntAlu 2 5.71% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -296,43 +296,42 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 14 37.84% # attempts to use FU when none available - MemWrite 22 59.46% # attempts to use FU when none available + MemRead 12 34.29% # attempts to use FU when none available + MemWrite 21 60.00% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 3239 +system.cpu.iq.ISSUE:issued_per_cycle.samples 4109 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 2006 6193.27% - 1 362 1117.63% - 2 258 796.54% - 3 236 728.62% - 4 193 595.86% - 5 111 342.70% - 6 53 163.63% - 7 14 43.22% - 8 6 18.52% + 0 2849 6933.56% + 1 475 1156.00% + 2 270 657.09% + 3 217 528.11% + 4 159 386.96% + 5 86 209.30% + 6 34 82.75% + 7 13 31.64% + 8 6 14.60% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.042606 # Inst issue rate -system.cpu.iq.iqInstsAdded 3751 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 3377 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1220 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 4 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 564 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 271 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3298.892989 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1993.811808 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 894000 # number of ReadReq miss cycles +system.cpu.iq.ISSUE:rate 0.748357 # Inst issue rate +system.cpu.iq.iqInstsAdded 3330 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 3075 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 7 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 790 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 409 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 270 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4522.222222 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2388.888889 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 1221000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 271 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 540323 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_misses 270 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 645000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 271 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 270 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -341,32 +340,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 271 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3298.892989 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1993.811808 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 270 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4522.222222 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2388.888889 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 894000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 1221000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 271 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 270 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 540323 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 645000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 271 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 270 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 271 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3298.892989 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1993.811808 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 270 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4522.222222 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2388.888889 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 894000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 1221000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 271 # number of overall misses +system.cpu.l2cache.overall_misses 270 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 540323 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 645000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 271 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 270 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -379,27 +378,28 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 271 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 270 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 155.098898 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 158.236294 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 3239 # number of cpu cycles simulated +system.cpu.numCycles 4109 # number of cpu cycles simulated system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 2100 # Number of cycles rename is idle +system.cpu.rename.RENAME:IdleCycles 3116 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 5014 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 4443 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 3193 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 795 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 261 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 7 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1425 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 76 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 52 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed +system.cpu.rename.RENAME:RenameLookups 4416 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 3886 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2777 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 696 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 202 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 6 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1009 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 89 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 9 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 55 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 7 # count of temporary serializing insts renamed +system.cpu.timesIdled 8 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr index e582c15a8..9f8e7c2e9 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr @@ -1,4 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout index 835f03aa2..587034bb2 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:10 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:41 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1619000 because target called exit() +Exiting @ tick 2053000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini index 3e6a662e6..20dfddd0a 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out index a2be80e9b..acc734991 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt index 16257c237..e82d837af 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 254768 # Simulator instruction rate (inst/s) -host_mem_usage 147764 # Number of bytes of host memory used +host_inst_rate 484860 # Simulator instruction rate (inst/s) +host_mem_usage 147796 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 121316260 # Simulator tick rate (ticks/s) +host_tick_rate 225459318 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2578 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout index ddbbe3d32..3b5348194 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:10 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:42 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 1288500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index 52183bdb1..1c1daa355 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out index 05d289a63..45a8521ac 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt index 8671d784f..756244d02 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 125225 # Simulator instruction rate (inst/s) +host_inst_rate 228404 # Simulator instruction rate (inst/s) host_mem_usage 153176 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 116347710 # Simulator tick rate (ticks/s) +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 552831639 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2578 # Number of instructions simulated -sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 2444000 # Number of ticks simulated +sim_seconds 0.000006 # Number of seconds simulated +sim_ticks 6472000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3890.909091 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2890.909091 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 214000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 770000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 159000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 715000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3722.222222 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2722.222222 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 267 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 100500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 378000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.091837 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 27 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 73500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 351000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.091837 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 27 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3835.365854 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2835.365854 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.demand_hits 627 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 314500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 1148000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.115656 # miss rate for demand accesses system.cpu.dcache.demand_misses 82 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 232500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 1066000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.115656 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 82 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3835.365854 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2835.365854 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 627 # number of overall hits -system.cpu.dcache.overall_miss_latency 314500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 1148000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.115656 # miss rate for overall accesses system.cpu.dcache.overall_misses 82 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 232500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 1066000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.115656 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 82 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 51.430454 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 50.002941 # Cycle average of tags in use system.cpu.dcache.total_refs 627 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 2579 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3733.128834 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2733.128834 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 2416 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 608500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 2282000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.063203 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 445500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 2119000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.063203 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 2579 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3733.128834 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2733.128834 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 14000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.icache.demand_hits 2416 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 608500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 2282000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.063203 # miss rate for demand accesses system.cpu.icache.demand_misses 163 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 445500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 2119000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.063203 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 2579 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3733.128834 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2733.128834 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 14000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 2416 # number of overall hits -system.cpu.icache.overall_miss_latency 608500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 2282000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.063203 # miss rate for overall accesses system.cpu.icache.overall_misses 163 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 445500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 2119000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.063203 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 89.421061 # Cycle average of tags in use +system.cpu.icache.tagsinuse 86.067224 # Cycle average of tags in use system.cpu.icache.total_refs 2416 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 245 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2767.346939 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1766.346939 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 678000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 3185000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 245 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 432755 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 2695000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 245 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2767.346939 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1766.346939 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 678000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 3185000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 432755 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2695000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 245 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2767.346939 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1766.346939 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 678000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 3185000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 245 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 432755 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2695000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 245 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 140.951761 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 136.108021 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 2444000 # number of cpu cycles simulated +system.cpu.numCycles 6472000 # number of cpu cycles simulated system.cpu.num_insts 2578 # Number of instructions executed system.cpu.num_refs 710 # Number of memory references system.cpu.workload.PROG:num_syscalls 4 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout index d2bc8bfb7..f5e3a6008 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:11 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:42 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 2444000 because target called exit() +Exiting @ tick 6472000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini index 80ef56747..ea3ba751b 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out index 9f8b84468..06a3d271d 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt index daf99515d..6a0c251b5 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 7127 # Simulator instruction rate (inst/s) -host_mem_usage 148488 # Number of bytes of host memory used -host_seconds 0.79 # Real time elapsed on the host -host_tick_rate 3561193 # Simulator tick rate (ticks/s) +host_inst_rate 535701 # Simulator instruction rate (inst/s) +host_mem_usage 148368 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 257653061 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5657 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout index b975f8f18..7fb23e5a5 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2007 20:47:32 -M5 started Sun Apr 22 20:47:35 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 15 2007 12:54:05 +M5 started Tue May 15 12:54:07 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 2828000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index 29fcae5de..a5d4e6583 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out index d5d160f1e..3f8a51cf4 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt index 71b0896dd..41bb7c8b7 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 224031 # Simulator instruction rate (inst/s) -host_mem_usage 153864 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 205051803 # Simulator tick rate (ticks/s) +host_inst_rate 273338 # Simulator instruction rate (inst/s) +host_mem_usage 153844 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 633390216 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5657 # Number of instructions simulated -sim_seconds 0.000005 # Number of seconds simulated -sim_ticks 5264500 # Number of ticks simulated +sim_seconds 0.000013 # Number of seconds simulated +sim_ticks 13362000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3762.195122 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2762.195122 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 1048 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 308500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 1148000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.072566 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 226500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1066000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.072566 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3690 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2690 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 184500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 700000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.054113 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 50 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 134500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 650000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.054113 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 50 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2054 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3734.848485 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2734.848485 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.demand_hits 1922 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 493000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 1848000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.064265 # miss rate for demand accesses system.cpu.dcache.demand_misses 132 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 361000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 1716000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.064265 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 132 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 2054 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3734.848485 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2734.848485 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1922 # number of overall hits -system.cpu.dcache.overall_miss_latency 493000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 1848000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.064265 # miss rate for overall accesses system.cpu.dcache.overall_misses 132 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 361000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 1716000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.064265 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 132 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 86.050916 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 85.283494 # Cycle average of tags in use system.cpu.dcache.total_refs 1922 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3740.924092 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2740.924092 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13986.798680 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12986.798680 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 5355 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1133500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 4238000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.053552 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 830500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 3935000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 5658 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3740.924092 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2740.924092 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13986.798680 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12986.798680 # average overall mshr miss latency system.cpu.icache.demand_hits 5355 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1133500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 4238000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.053552 # miss rate for demand accesses system.cpu.icache.demand_misses 303 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 830500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 3935000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.053552 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3740.924092 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2740.924092 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13986.798680 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12986.798680 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 5355 # number of overall hits -system.cpu.icache.overall_miss_latency 1133500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 4238000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses system.cpu.icache.overall_misses 303 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 830500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 3935000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.053552 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 13 # number of replacements system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 137.160443 # Cycle average of tags in use +system.cpu.icache.tagsinuse 136.309471 # Cycle average of tags in use system.cpu.icache.total_refs 5355 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 435 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2743.648961 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1742.648961 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1188000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 5629000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.995402 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 433 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 754567 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 4763000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995402 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 433 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -162,29 +162,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2743.648961 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1742.648961 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1188000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 5629000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.995402 # miss rate for demand accesses system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 754567 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 4763000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.995402 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 433 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2743.648961 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1742.648961 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1188000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 5629000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.995402 # miss rate for overall accesses system.cpu.l2cache.overall_misses 433 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 754567 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 4763000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.995402 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 433 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -201,12 +201,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 433 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 224.535228 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 222.872415 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5264500 # number of cpu cycles simulated +system.cpu.numCycles 13362000 # number of cpu cycles simulated system.cpu.num_insts 5657 # Number of instructions executed system.cpu.num_refs 2055 # Number of memory references system.cpu.workload.PROG:num_syscalls 13 # Number of system calls diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout index 1cc143ec3..6b688641a 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2007 20:47:32 -M5 started Sun Apr 22 20:47:36 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 15 2007 12:54:05 +M5 started Tue May 15 12:54:07 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 5264500 because target called exit() +Exiting @ tick 13362000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini index 5d4dafee7..0e142e6ce 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out index 1a521c678..1666790d0 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt index bbc3d0e4f..8e0baaf8b 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 16183 # Simulator instruction rate (inst/s) -host_mem_usage 149132 # Number of bytes of host memory used -host_seconds 0.30 # Real time elapsed on the host -host_tick_rate 8071210 # Simulator tick rate (ticks/s) +host_inst_rate 439375 # Simulator instruction rate (inst/s) +host_mem_usage 149124 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 211870315 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4863 # Number of instructions simulated sim_seconds 0.000002 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout index 84e837005..9e1770f92 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2007 20:15:56 -M5 started Sun Apr 22 20:26:04 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 17:00:05 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 2431000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini index 4371849c9..fdb2bc3c9 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.out b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.out index b02683337..89910d3c9 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.out +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt index c6b55a6f2..839307810 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 189060 # Simulator instruction rate (inst/s) -host_mem_usage 154496 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 164285984 # Simulator tick rate (ticks/s) +host_inst_rate 239687 # Simulator instruction rate (inst/s) +host_mem_usage 154512 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 542234464 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4863 # Number of instructions simulated -sim_seconds 0.000004 # Number of seconds simulated -sim_ticks 4347500 # Number of ticks simulated +sim_seconds 0.000011 # Number of seconds simulated +sim_ticks 11221000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 608 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3740.740741 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2740.740741 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 13796.296296 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12796.296296 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 554 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 202000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 745000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.088816 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 148000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 691000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.088816 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 661 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3625 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2625 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 577 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 304500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 1176000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.127080 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 84 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 220500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1092000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.127080 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 84 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 1269 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3670.289855 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2670.289855 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 13920.289855 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12920.289855 # average overall mshr miss latency system.cpu.dcache.demand_hits 1131 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 506500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 1921000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.108747 # miss rate for demand accesses system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 368500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 1783000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.108747 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 1269 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3670.289855 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2670.289855 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 13920.289855 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12920.289855 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1131 # number of overall hits -system.cpu.dcache.overall_miss_latency 506500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 1921000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.108747 # miss rate for overall accesses system.cpu.dcache.overall_misses 138 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 368500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 1783000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.108747 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 84.314216 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 83.705022 # Cycle average of tags in use system.cpu.dcache.total_refs 1131 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 4864 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3796.875000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2796.875000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13914.062500 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12914.062500 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 4608 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 972000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 3562000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.052632 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 256 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 716000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 3306000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.052632 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 256 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 4864 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3796.875000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2796.875000 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13914.062500 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12914.062500 # average overall mshr miss latency system.cpu.icache.demand_hits 4608 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 972000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 3562000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.052632 # miss rate for demand accesses system.cpu.icache.demand_misses 256 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 716000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 3306000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.052632 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 256 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 4864 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3796.875000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2796.875000 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13914.062500 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12914.062500 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 4608 # number of overall hits -system.cpu.icache.overall_miss_latency 972000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 3562000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.052632 # miss rate for overall accesses system.cpu.icache.overall_misses 256 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 716000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 3306000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.052632 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 256 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 256 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 114.238100 # Cycle average of tags in use +system.cpu.icache.tagsinuse 114.172725 # Cycle average of tags in use system.cpu.icache.total_refs 4608 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 391 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2760.869565 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1759.869565 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1079500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 5083000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 391 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 688109 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 4301000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 391 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 391 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2760.869565 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1759.869565 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1079500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 5083000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 391 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 688109 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 4301000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 391 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 391 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2760.869565 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1759.869565 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1079500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 5083000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 391 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 688109 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 4301000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 391 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 391 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 197.030867 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 196.304892 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4347500 # number of cpu cycles simulated +system.cpu.numCycles 11221000 # number of cpu cycles simulated system.cpu.num_insts 4863 # Number of instructions executed system.cpu.num_refs 1269 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout index 6a58f8e2a..65bf4abca 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2007 20:15:56 -M5 started Sun Apr 22 20:26:05 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 17:00:05 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 4347500 because target called exit() +Exiting @ tick 11221000 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index 5e1ced152..5380fc831 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -91,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -267,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -306,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -339,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -379,6 +377,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out index f04ad4ffd..c8129d10d 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload0] type=LiveProcess @@ -265,7 +266,7 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -296,14 +297,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -334,14 +334,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -372,7 +371,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -380,4 +378,5 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt index b44194dff..484bdcca9 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 687 # Number of BTB hits -global.BPredUnit.BTBLookups 3480 # Number of BTB lookups -global.BPredUnit.RASInCorrect 113 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1086 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 2328 # Number of conditional branches predicted -global.BPredUnit.lookups 4062 # Number of BP lookups -global.BPredUnit.usedRAS 562 # Number of times the RAS was used to get a target. -host_inst_rate 49679 # Simulator instruction rate (inst/s) -host_mem_usage 154724 # Number of bytes of host memory used -host_seconds 0.23 # Real time elapsed on the host -host_tick_rate 20293608 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 15 # Number of conflicting loads. -memdepunit.memDep.conflictingLoads 21 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 59 # Number of conflicting stores. +global.BPredUnit.BTBHits 674 # Number of BTB hits +global.BPredUnit.BTBLookups 3410 # Number of BTB lookups +global.BPredUnit.RASInCorrect 118 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1115 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 2318 # Number of conditional branches predicted +global.BPredUnit.lookups 3964 # Number of BP lookups +global.BPredUnit.usedRAS 532 # Number of times the RAS was used to get a target. +host_inst_rate 56668 # Simulator instruction rate (inst/s) +host_mem_usage 154692 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host +host_tick_rate 27618195 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 19 # Number of conflicting loads. +memdepunit.memDep.conflictingLoads 18 # Number of conflicting loads. memdepunit.memDep.conflictingStores 54 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 1911 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedLoads 1833 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1079 # Number of stores inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1058 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.conflictingStores 59 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 1925 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 1898 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1088 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1090 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 11247 # Number of instructions simulated sim_seconds 0.000005 # Number of seconds simulated -sim_ticks 4600500 # Number of ticks simulated +sim_ticks 5490000 # Number of ticks simulated system.cpu.commit.COM:branches 1724 # Number of branches committed system.cpu.commit.COM:branches_0 862 # Number of branches committed system.cpu.commit.COM:branches_1 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 179 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 165 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 9158 +system.cpu.commit.COM:committed_per_cycle.samples 10929 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 4902 5352.70% - 1 1725 1883.60% - 2 937 1023.15% - 3 472 515.40% - 4 355 387.64% - 5 234 255.51% - 6 234 255.51% - 7 120 131.03% - 8 179 195.46% + 0 6410 5865.13% + 1 2019 1847.38% + 2 999 914.08% + 3 454 415.41% + 4 300 274.50% + 5 246 225.09% + 6 200 183.00% + 7 136 124.44% + 8 165 150.97% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -61,141 +61,133 @@ system.cpu.commit.COM:refs_1 1791 # Nu system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 843 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 874 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 11281 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 7371 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 7769 # The number of squashed insts skipped by commit system.cpu.committedInsts_0 5623 # Number of Instructions Simulated system.cpu.committedInsts_1 5624 # Number of Instructions Simulated system.cpu.committedInsts_total 11247 # Number of Instructions Simulated -system.cpu.cpi_0 1.636671 # CPI: Cycles Per Instruction -system.cpu.cpi_1 1.636380 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.818263 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 2909 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses_0 2909 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 6520.912548 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency_0 6520.912548 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6121.212121 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 6121.212121 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2646 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits_0 2646 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1715000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency_0 1715000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.090409 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate_0 0.090409 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 263 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses_0 263 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 65 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits_0 65 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1212000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency_0 1212000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.068065 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.068065 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 198 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses_0 198 # number of ReadReq MSHR misses +system.cpu.cpi_0 1.952516 # CPI: Cycles Per Instruction +system.cpu.cpi_1 1.952169 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.976171 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 2969 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses_0 2969 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency_0 7072.992701 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 6972.361809 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 2695 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits_0 2695 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 1938000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency_0 1938000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate_0 0.092287 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 274 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses_0 274 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 75 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits_0 75 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1387500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency_0 1387500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.067026 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 199 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses_0 199 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 1624 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses_0 1624 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 4509.846827 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency_0 4509.846827 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4681.506849 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 4681.506849 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 1167 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits_0 1167 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2061000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency_0 2061000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.281404 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate_0 0.281404 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 457 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses_0 457 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 311 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits_0 311 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 683500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency_0 683500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency_0 5352.409639 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 5859.589041 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 1126 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits_0 1126 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 2665500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency_0 2665500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate_0 0.306650 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 498 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses_0 498 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 352 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits_0 352 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 855500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency_0 855500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.089901 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 146 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses_0 146 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.084302 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11.075362 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 4533 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses_0 4533 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 4593 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses_0 4593 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 5244.444444 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency_0 5244.444444 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency_0 5963.082902 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency_1 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 5510.174419 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency_0 5510.174419 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency_0 6501.449275 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency_1 # average overall mshr miss latency -system.cpu.dcache.demand_hits 3813 # number of demand (read+write) hits -system.cpu.dcache.demand_hits_0 3813 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 3821 # number of demand (read+write) hits +system.cpu.dcache.demand_hits_0 3821 # number of demand (read+write) hits system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 3776000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency_0 3776000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 4603500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency_0 4603500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.158835 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate_0 0.158835 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate_0 0.168082 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate_1 # miss rate for demand accesses -system.cpu.dcache.demand_misses 720 # number of demand (read+write) misses -system.cpu.dcache.demand_misses_0 720 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 772 # number of demand (read+write) misses +system.cpu.dcache.demand_misses_0 772 # number of demand (read+write) misses system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 376 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits_0 376 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits 427 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits_0 427 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1895500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency_0 1895500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 2243000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency_0 2243000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.075888 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate_0 0.075888 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate_0 0.075114 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate_1 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 344 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses_0 344 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 345 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses_0 345 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 4533 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses_0 4533 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 4593 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses_0 4593 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 5244.444444 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency_0 5244.444444 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency_0 5963.082902 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency_1 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 5510.174419 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency_0 5510.174419 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency_0 6501.449275 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency_1 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 3813 # number of overall hits -system.cpu.dcache.overall_hits_0 3813 # number of overall hits +system.cpu.dcache.overall_hits 3821 # number of overall hits +system.cpu.dcache.overall_hits_0 3821 # number of overall hits system.cpu.dcache.overall_hits_1 0 # number of overall hits -system.cpu.dcache.overall_miss_latency 3776000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency_0 3776000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 4603500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency_0 4603500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.158835 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate_0 0.158835 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate_0 0.168082 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate_1 # miss rate for overall accesses -system.cpu.dcache.overall_misses 720 # number of overall misses -system.cpu.dcache.overall_misses_0 720 # number of overall misses +system.cpu.dcache.overall_misses 772 # number of overall misses +system.cpu.dcache.overall_misses_0 772 # number of overall misses system.cpu.dcache.overall_misses_1 0 # number of overall misses -system.cpu.dcache.overall_mshr_hits 376 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits_0 376 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits 427 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits_0 427 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1895500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency_0 1895500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 2243000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency_0 2243000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.075888 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate_0 0.075888 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate_0 0.075114 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate_1 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 344 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses_0 344 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 345 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses_0 345 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -215,153 +207,149 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.replacements_0 0 # number of replacements system.cpu.dcache.replacements_1 0 # number of replacements -system.cpu.dcache.sampled_refs 344 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 345 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 218.590181 # Cycle average of tags in use -system.cpu.dcache.total_refs 3813 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 221.724795 # Cycle average of tags in use +system.cpu.dcache.total_refs 3821 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dcache.writebacks_0 0 # number of writebacks system.cpu.dcache.writebacks_1 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1876 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 260 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 354 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 22033 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 11054 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 3598 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1407 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 337 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 284 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 4062 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 2946 # Number of cache lines fetched -system.cpu.fetch.Cycles 6973 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 278 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 24430 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 1145 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.441378 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 2946 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1249 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.654569 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 1857 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 251 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 346 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 21806 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 14535 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 3658 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1498 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 351 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 145 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 3964 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 2983 # Number of cache lines fetched +system.cpu.fetch.Cycles 6940 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 525 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 24033 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 1178 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.361053 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 2983 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1206 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.188997 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 9203 +system.cpu.fetch.rateDist.samples 10979 system.cpu.fetch.rateDist.min_value 0 - 0 5177 5625.34% - 1 291 316.20% - 2 234 254.26% - 3 263 285.78% - 4 314 341.19% - 5 294 319.46% - 6 311 337.93% - 7 262 284.69% - 8 2057 2235.14% + 0 7023 6396.76% + 1 285 259.59% + 2 224 204.03% + 3 248 225.89% + 4 335 305.13% + 5 281 255.94% + 6 301 274.16% + 7 251 228.62% + 8 2031 1849.90% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 2946 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses_0 2946 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4950.682853 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency_0 4950.682853 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 4079.838710 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 4079.838710 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 2287 # number of ReadReq hits -system.cpu.icache.ReadReq_hits_0 2287 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 3262500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency_0 3262500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.223693 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate_0 0.223693 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 659 # number of ReadReq misses -system.cpu.icache.ReadReq_misses_0 659 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 39 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits_0 39 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 2529500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency_0 2529500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.210455 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate_0 0.210455 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 620 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses_0 620 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 2983 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses_0 2983 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency_0 5910.313901 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 5152.173913 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 2314 # number of ReadReq hits +system.cpu.icache.ReadReq_hits_0 2314 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 3954000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency_0 3954000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate_0 0.224271 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 669 # number of ReadReq misses +system.cpu.icache.ReadReq_misses_0 669 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 48 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits_0 48 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 3199500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency_0 3199500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate_0 0.208180 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 621 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses_0 621 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.688710 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.726248 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 2946 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses_0 2946 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 2983 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses_0 2983 # number of demand (read+write) accesses system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4950.682853 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency_0 4950.682853 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency # average overall miss latency +system.cpu.icache.demand_avg_miss_latency_0 5910.313901 # average overall miss latency system.cpu.icache.demand_avg_miss_latency_1 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 4079.838710 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency_0 4079.838710 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency_0 5152.173913 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency_1 # average overall mshr miss latency -system.cpu.icache.demand_hits 2287 # number of demand (read+write) hits -system.cpu.icache.demand_hits_0 2287 # number of demand (read+write) hits +system.cpu.icache.demand_hits 2314 # number of demand (read+write) hits +system.cpu.icache.demand_hits_0 2314 # number of demand (read+write) hits system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 3262500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency_0 3262500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 3954000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency_0 3954000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.223693 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate_0 0.223693 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate # miss rate for demand accesses +system.cpu.icache.demand_miss_rate_0 0.224271 # miss rate for demand accesses system.cpu.icache.demand_miss_rate_1 # miss rate for demand accesses -system.cpu.icache.demand_misses 659 # number of demand (read+write) misses -system.cpu.icache.demand_misses_0 659 # number of demand (read+write) misses +system.cpu.icache.demand_misses 669 # number of demand (read+write) misses +system.cpu.icache.demand_misses_0 669 # number of demand (read+write) misses system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 39 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits_0 39 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits 48 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits_0 48 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2529500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency_0 2529500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 3199500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency_0 3199500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.210455 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate_0 0.210455 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate_0 0.208180 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate_1 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 620 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses_0 620 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 621 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses_0 621 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 2946 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses_0 2946 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 2983 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses_0 2983 # number of overall (read+write) accesses system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4950.682853 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency_0 4950.682853 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency # average overall miss latency +system.cpu.icache.overall_avg_miss_latency_0 5910.313901 # average overall miss latency system.cpu.icache.overall_avg_miss_latency_1 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 4079.838710 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency_0 4079.838710 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency_0 5152.173913 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency_1 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 2287 # number of overall hits -system.cpu.icache.overall_hits_0 2287 # number of overall hits +system.cpu.icache.overall_hits 2314 # number of overall hits +system.cpu.icache.overall_hits_0 2314 # number of overall hits system.cpu.icache.overall_hits_1 0 # number of overall hits -system.cpu.icache.overall_miss_latency 3262500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency_0 3262500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 3954000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency_0 3954000 # number of overall miss cycles system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.223693 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate_0 0.223693 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate # miss rate for overall accesses +system.cpu.icache.overall_miss_rate_0 0.224271 # miss rate for overall accesses system.cpu.icache.overall_miss_rate_1 # miss rate for overall accesses -system.cpu.icache.overall_misses 659 # number of overall misses -system.cpu.icache.overall_misses_0 659 # number of overall misses +system.cpu.icache.overall_misses 669 # number of overall misses +system.cpu.icache.overall_misses_0 669 # number of overall misses system.cpu.icache.overall_misses_1 0 # number of overall misses -system.cpu.icache.overall_mshr_hits 39 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits_0 39 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits 48 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits_0 48 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2529500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency_0 2529500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 3199500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency_0 3199500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.210455 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate_0 0.210455 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate_0 0.208180 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate_1 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 620 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses_0 620 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 621 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses_0 621 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -381,104 +369,104 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 9 # number of replacements system.cpu.icache.replacements_0 9 # number of replacements system.cpu.icache.replacements_1 0 # number of replacements -system.cpu.icache.sampled_refs 620 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 621 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 315.428279 # Cycle average of tags in use -system.cpu.icache.total_refs 2287 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 322.894952 # Cycle average of tags in use +system.cpu.icache.total_refs 2314 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks_0 0 # number of writebacks system.cpu.icache.writebacks_1 0 # number of writebacks -system.cpu.idleCycles -1 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 2339 # Number of branches executed -system.cpu.iew.EXEC:branches_0 1175 # Number of branches executed -system.cpu.iew.EXEC:branches_1 1164 # Number of branches executed -system.cpu.iew.EXEC:nop 72 # number of nop insts executed -system.cpu.iew.EXEC:nop_0 36 # number of nop insts executed +system.cpu.idleCycles 1998 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 2367 # Number of branches executed +system.cpu.iew.EXEC:branches_0 1185 # Number of branches executed +system.cpu.iew.EXEC:branches_1 1182 # Number of branches executed +system.cpu.iew.EXEC:nop 73 # number of nop insts executed +system.cpu.iew.EXEC:nop_0 37 # number of nop insts executed system.cpu.iew.EXEC:nop_1 36 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.666196 # Inst execution rate -system.cpu.iew.EXEC:refs 4928 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_0 2490 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_1 2438 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1865 # Number of stores executed +system.cpu.iew.EXEC:rate 1.416158 # Inst execution rate +system.cpu.iew.EXEC:refs 4978 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_0 2514 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_1 2464 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1867 # Number of stores executed system.cpu.iew.EXEC:stores_0 938 # Number of stores executed -system.cpu.iew.EXEC:stores_1 927 # Number of stores executed +system.cpu.iew.EXEC:stores_1 929 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed -system.cpu.iew.WB:consumers 10157 # num instructions consuming a value -system.cpu.iew.WB:consumers_0 5143 # num instructions consuming a value -system.cpu.iew.WB:consumers_1 5014 # num instructions consuming a value -system.cpu.iew.WB:count 14949 # cumulative count of insts written-back -system.cpu.iew.WB:count_0 7544 # cumulative count of insts written-back -system.cpu.iew.WB:count_1 7405 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.769912 # average fanout of values written-back -system.cpu.iew.WB:fanout_0 0.768229 # average fanout of values written-back -system.cpu.iew.WB:fanout_1 0.771639 # average fanout of values written-back +system.cpu.iew.WB:consumers 10219 # num instructions consuming a value +system.cpu.iew.WB:consumers_0 5113 # num instructions consuming a value +system.cpu.iew.WB:consumers_1 5106 # num instructions consuming a value +system.cpu.iew.WB:count 14974 # cumulative count of insts written-back +system.cpu.iew.WB:count_0 7532 # cumulative count of insts written-back +system.cpu.iew.WB:count_1 7442 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 1.526960 # average fanout of values written-back +system.cpu.iew.WB:fanout_0 0.762957 # average fanout of values written-back +system.cpu.iew.WB:fanout_1 0.764003 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 7820 # num instructions producing a value -system.cpu.iew.WB:producers_0 3951 # num instructions producing a value -system.cpu.iew.WB:producers_1 3869 # num instructions producing a value -system.cpu.iew.WB:rate 1.624362 # insts written-back per cycle -system.cpu.iew.WB:rate_0 0.819733 # insts written-back per cycle -system.cpu.iew.WB:rate_1 0.804629 # insts written-back per cycle -system.cpu.iew.WB:sent 15070 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_0 7606 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_1 7464 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 927 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 6 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 3744 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 587 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2137 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 18669 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 3063 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_0 1552 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_1 1511 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1008 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 15334 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 7802 # num instructions producing a value +system.cpu.iew.WB:producers_0 3901 # num instructions producing a value +system.cpu.iew.WB:producers_1 3901 # num instructions producing a value +system.cpu.iew.WB:rate 1.363876 # insts written-back per cycle +system.cpu.iew.WB:rate_0 0.686037 # insts written-back per cycle +system.cpu.iew.WB:rate_1 0.677840 # insts written-back per cycle +system.cpu.iew.WB:sent 15105 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_0 7590 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_1 7515 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 941 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 7 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 3823 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 501 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2178 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 19078 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 3111 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_0 1576 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_1 1535 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 864 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 15548 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1407 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 1498 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 42 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 56 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 63 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 932 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 267 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 946 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 276 # Number of stores squashed system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.1.forwLoads 49 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.1.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.1.forwLoads 38 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.1.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.1.memOrderViolation 57 # Number of memory ordering violations +system.cpu.iew.lsq.thread.1.memOrderViolation 54 # Number of memory ordering violations system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.1.squashedLoads 854 # Number of loads squashed -system.cpu.iew.lsq.thread.1.squashedStores 246 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 113 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 753 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 174 # Number of branches that were predicted taken incorrectly -system.cpu.ipc_0 0.610996 # IPC: Instructions Per Cycle -system.cpu.ipc_1 0.611105 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.222101 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8271 # Type of FU issued +system.cpu.iew.lsq.thread.1.squashedLoads 919 # Number of loads squashed +system.cpu.iew.lsq.thread.1.squashedStores 278 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 117 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 761 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 180 # Number of branches that were predicted taken incorrectly +system.cpu.ipc_0 0.512160 # IPC: Instructions Per Cycle +system.cpu.ipc_1 0.512251 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.024410 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 8232 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 2 0.02% # Type of FU issued - IntAlu 5600 67.71% # Type of FU issued + IntAlu 5551 67.43% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -487,15 +475,15 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1701 20.57% # Type of FU issued - MemWrite 965 11.67% # Type of FU issued + MemRead 1704 20.70% # Type of FU issued + MemWrite 972 11.81% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:FU_type_1 8071 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1 8180 # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.start_dist (null) 2 0.02% # Type of FU issued - IntAlu 5485 67.96% # Type of FU issued + IntAlu 5536 67.68% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -504,15 +492,15 @@ system.cpu.iq.ISSUE:FU_type_1.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1640 20.32% # Type of FU issued - MemWrite 941 11.66% # Type of FU issued + MemRead 1681 20.55% # Type of FU issued + MemWrite 958 11.71% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.end_dist -system.cpu.iq.ISSUE:FU_type 16342 # Type of FU issued +system.cpu.iq.ISSUE:FU_type 16412 # Type of FU issued system.cpu.iq.ISSUE:FU_type.start_dist (null) 4 0.02% # Type of FU issued - IntAlu 11085 67.83% # Type of FU issued + IntAlu 11087 67.55% # Type of FU issued IntMult 2 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 4 0.02% # Type of FU issued @@ -521,20 +509,20 @@ system.cpu.iq.ISSUE:FU_type.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 3341 20.44% # Type of FU issued - MemWrite 1906 11.66% # Type of FU issued + MemRead 3385 20.63% # Type of FU issued + MemWrite 1930 11.76% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 184 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_0 95 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_1 89 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011259 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_0 0.005813 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_1 0.005446 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 180 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_0 92 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_1 88 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.010968 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_0 0.005606 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_1 0.005362 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 11 5.98% # attempts to use FU when none available + IntAlu 16 8.89% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -543,108 +531,104 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 108 58.70% # attempts to use FU when none available - MemWrite 65 35.33% # attempts to use FU when none available + MemRead 97 53.89% # attempts to use FU when none available + MemWrite 67 37.22% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 9203 +system.cpu.iq.ISSUE:issued_per_cycle.samples 10979 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 3452 3750.95% - 1 1399 1520.16% - 2 1479 1607.08% - 3 1070 1162.66% - 4 845 918.18% - 5 528 573.73% - 6 290 315.11% - 7 105 114.09% - 8 35 38.03% + 0 4788 4361.05% + 1 1816 1654.07% + 2 1657 1509.24% + 3 1039 946.35% + 4 774 704.98% + 5 501 456.33% + 6 289 263.23% + 7 90 81.97% + 8 25 22.77% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.775725 # Inst issue rate -system.cpu.iq.iqInstsAdded 18557 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 16342 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 40 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 6288 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 37 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 3616 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 960 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses_0 960 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4143.899896 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency_0 4143.899896 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2323.820647 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 2323.820647 # average ReadReq mshr miss latency +system.cpu.iq.ISSUE:rate 1.494854 # Inst issue rate +system.cpu.iq.iqInstsAdded 18963 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 16412 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 42 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 6896 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 34 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 4313 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 963 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses_0 963 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency_0 5220.374220 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 2725.051975 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits_0 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 3974000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency_0 3974000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.998958 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate_0 0.998958 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 959 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses_0 959 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 2228544 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency_0 2228544 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.998958 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.998958 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 959 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses_0 959 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 5022000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency_0 5022000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate_0 0.998962 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 962 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses_0 962 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 2621500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency_0 2621500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.998962 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 962 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses_0 962 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.001043 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.001040 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 960 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses_0 960 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 963 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses_0 963 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4143.899896 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency_0 4143.899896 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency_0 5220.374220 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency_1 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2323.820647 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency_0 2323.820647 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency_0 2725.051975 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency_1 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits_0 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3974000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency_0 3974000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 5022000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency_0 5022000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.998958 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate_0 0.998958 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate_0 0.998962 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate_1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 959 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses_0 959 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 962 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses_0 962 # number of demand (read+write) misses system.cpu.l2cache.demand_misses_1 0 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2228544 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency_0 2228544 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2621500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency_0 2621500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.998958 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate_0 0.998958 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate_0 0.998962 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate_1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 959 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses_0 959 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 962 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses_0 962 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 960 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses_0 960 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 963 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses_0 963 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4143.899896 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency_0 4143.899896 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency_0 5220.374220 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency_1 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2323.820647 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency_0 2323.820647 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency_0 2725.051975 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency_1 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 # average overall mshr uncacheable latency @@ -652,26 +636,26 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 system.cpu.l2cache.overall_hits 1 # number of overall hits system.cpu.l2cache.overall_hits_0 1 # number of overall hits system.cpu.l2cache.overall_hits_1 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3974000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency_0 3974000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 5022000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency_0 5022000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.998958 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate_0 0.998958 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate_0 0.998962 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate_1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 959 # number of overall misses -system.cpu.l2cache.overall_misses_0 959 # number of overall misses +system.cpu.l2cache.overall_misses 962 # number of overall misses +system.cpu.l2cache.overall_misses_0 962 # number of overall misses system.cpu.l2cache.overall_misses_1 0 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2228544 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency_0 2228544 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2621500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency_0 2621500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.998958 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate_0 0.998958 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate_0 0.998962 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate_1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 959 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses_0 959 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 962 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses_0 962 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -691,33 +675,33 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements_0 0 # number of replacements system.cpu.l2cache.replacements_1 0 # number of replacements -system.cpu.l2cache.sampled_refs 959 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 962 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 534.228654 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 545.133409 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks_0 0 # number of writebacks system.cpu.l2cache.writebacks_1 0 # number of writebacks -system.cpu.numCycles 9203 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 514 # Number of cycles rename is blocking +system.cpu.numCycles 10979 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 614 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 8102 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 11467 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 762 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 26335 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 20742 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 15622 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 3447 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1407 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 876 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 7520 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 508 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:IdleCycles 14840 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 684 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 26359 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 20748 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 15612 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 3480 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1498 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 744 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 7510 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 517 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 2622 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 38 # count of temporary serializing insts renamed -system.cpu.timesIdled 1 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:skidInsts 2147 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 37 # count of temporary serializing insts renamed +system.cpu.timesIdled 2 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout index ea08dc448..ef617d5ef 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout @@ -7,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:11 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:42 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 4600500 because target called exit() +Exiting @ tick 5490000 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini index 1f1e7a355..61102139c 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -91,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -267,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -306,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -339,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -363,6 +361,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.out b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.out index ac1dcb9ba..70564f749 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.out +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -249,7 +250,7 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -280,14 +281,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -318,14 +318,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -356,7 +355,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -364,4 +362,5 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt index 8359db0f2..7859d5c2b 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 3154 # Number of BTB hits -global.BPredUnit.BTBLookups 9574 # Number of BTB lookups +global.BPredUnit.BTBHits 2726 # Number of BTB hits +global.BPredUnit.BTBLookups 7230 # Number of BTB lookups global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 2047 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 10459 # Number of conditional branches predicted -global.BPredUnit.lookups 10459 # Number of BP lookups +global.BPredUnit.condIncorrect 2062 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 7954 # Number of conditional branches predicted +global.BPredUnit.lookups 7954 # Number of BP lookups global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 26468 # Simulator instruction rate (inst/s) -host_mem_usage 154944 # Number of bytes of host memory used -host_seconds 0.41 # Real time elapsed on the host -host_tick_rate 32157366 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 14 # Number of conflicting loads. +host_inst_rate 37089 # Simulator instruction rate (inst/s) +host_mem_usage 154932 # Number of bytes of host memory used +host_seconds 0.30 # Real time elapsed on the host +host_tick_rate 53780846 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 10 # Number of conflicting loads. memdepunit.memDep.conflictingStores 0 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 3573 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 3440 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 3198 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 2970 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 10976 # Number of instructions simulated -sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 13345500 # Number of ticks simulated +sim_seconds 0.000016 # Number of seconds simulated +sim_ticks 15931500 # Number of ticks simulated system.cpu.commit.COM:branches 2152 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 164 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 146 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 23147 +system.cpu.commit.COM:committed_per_cycle.samples 28801 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 17950 7754.78% - 1 2912 1258.05% - 2 993 429.00% - 3 424 183.18% - 4 287 123.99% - 5 235 101.53% - 6 103 44.50% - 7 79 34.13% - 8 164 70.85% + 0 23411 8128.54% + 1 2862 993.72% + 2 1174 407.62% + 3 608 211.10% + 4 359 124.65% + 5 123 42.71% + 6 103 35.76% + 7 15 5.21% + 8 146 50.69% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 1462 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 2760 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 2047 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 2062 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 10976 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 327 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 18321 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 14297 # The number of squashed insts skipped by commit system.cpu.committedInsts 10976 # Number of Instructions Simulated system.cpu.committedInsts_total 10976 # Number of Instructions Simulated -system.cpu.cpi 2.431851 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.431851 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 2813 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 4311.764706 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3546.153846 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2728 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 366500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.030217 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 85 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 20 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 230500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.023107 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 65 # number of ReadReq MSHR misses +system.cpu.cpi 2.903061 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.903061 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 2743 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5392.857143 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4696.969697 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 2659 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 453000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.030623 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 84 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 18 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 310000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.024061 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 66 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits system.cpu.dcache.WriteReq_accesses 1292 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 4645.408163 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3470.930233 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 1096 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 910500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.151703 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 196 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 110 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 298500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 5505 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4802.325581 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 1092 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 1101000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.154799 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 200 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 114 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 413000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.066563 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 86 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 25.364238 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 24.717105 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 4105 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 4544.483986 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3503.311258 # average overall mshr miss latency -system.cpu.dcache.demand_hits 3824 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1277000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.068453 # miss rate for demand accesses -system.cpu.dcache.demand_misses 281 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 130 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 529000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.036784 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 151 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 4035 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 5471.830986 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4756.578947 # average overall mshr miss latency +system.cpu.dcache.demand_hits 3751 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 1554000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.070384 # miss rate for demand accesses +system.cpu.dcache.demand_misses 284 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 132 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 723000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.037670 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 152 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 4105 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 4544.483986 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3503.311258 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 4035 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 5471.830986 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4756.578947 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 3824 # number of overall hits -system.cpu.dcache.overall_miss_latency 1277000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.068453 # miss rate for overall accesses -system.cpu.dcache.overall_misses 281 # number of overall misses -system.cpu.dcache.overall_mshr_hits 130 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 529000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.036784 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 151 # number of overall MSHR misses +system.cpu.dcache.overall_hits 3751 # number of overall hits +system.cpu.dcache.overall_miss_latency 1554000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.070384 # miss rate for overall accesses +system.cpu.dcache.overall_misses 284 # number of overall misses +system.cpu.dcache.overall_mshr_hits 132 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 723000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.037670 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -121,88 +121,88 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 151 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 152 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 112.362185 # Cycle average of tags in use -system.cpu.dcache.total_refs 3830 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 113.439038 # Cycle average of tags in use +system.cpu.dcache.total_refs 3757 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 4942 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 48420 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 8618 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 9347 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 3545 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 240 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 10459 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 5440 # Number of cache lines fetched -system.cpu.fetch.Cycles 16262 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 216 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 55152 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 2110 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.391840 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 5440 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 3154 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.066237 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 4602 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 38937 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 16098 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 7883 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 3063 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 218 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 7954 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 4933 # Number of cache lines fetched +system.cpu.fetch.Cycles 14166 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 565 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 44421 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 2121 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.249623 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 4933 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 2726 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.394081 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 26692 +system.cpu.fetch.rateDist.samples 31864 system.cpu.fetch.rateDist.min_value 0 - 0 15871 5945.98% - 1 2250 842.95% - 2 637 238.65% - 3 971 363.78% - 4 550 206.05% - 5 848 317.70% - 6 962 360.41% - 7 321 120.26% - 8 4282 1604.23% + 0 22632 7102.69% + 1 2187 686.35% + 2 562 176.37% + 3 869 272.72% + 4 521 163.51% + 5 770 241.65% + 6 886 278.06% + 7 243 76.26% + 8 3194 1002.39% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 5440 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3939.473684 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2944.591029 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 5060 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1497000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.069853 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 380 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 1116000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.069669 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 379 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 4933 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5310.666667 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4396.174863 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 4558 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1991500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.076019 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 375 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 9 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 1609000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.074194 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 366 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 13.350923 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 12.453552 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 5440 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3939.473684 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2944.591029 # average overall mshr miss latency -system.cpu.icache.demand_hits 5060 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1497000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.069853 # miss rate for demand accesses -system.cpu.icache.demand_misses 380 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 1 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1116000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.069669 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 379 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 4933 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5310.666667 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4396.174863 # average overall mshr miss latency +system.cpu.icache.demand_hits 4558 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1991500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.076019 # miss rate for demand accesses +system.cpu.icache.demand_misses 375 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 9 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 1609000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.074194 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 366 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 5440 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3939.473684 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2944.591029 # average overall mshr miss latency +system.cpu.icache.overall_accesses 4933 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5310.666667 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4396.174863 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 5060 # number of overall hits -system.cpu.icache.overall_miss_latency 1497000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.069853 # miss rate for overall accesses -system.cpu.icache.overall_misses 380 # number of overall misses -system.cpu.icache.overall_mshr_hits 1 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1116000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.069669 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 379 # number of overall MSHR misses +system.cpu.icache.overall_hits 4558 # number of overall hits +system.cpu.icache.overall_miss_latency 1991500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.076019 # miss rate for overall accesses +system.cpu.icache.overall_misses 375 # number of overall misses +system.cpu.icache.overall_mshr_hits 9 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 1609000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.074194 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 366 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,60 +215,61 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.sampled_refs 379 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 366 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 242.916499 # Cycle average of tags in use -system.cpu.icache.total_refs 5060 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 233.760012 # Cycle average of tags in use +system.cpu.icache.total_refs 4558 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 3713 # Number of branches executed +system.cpu.idleCycles 499 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 3548 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.830061 # Inst execution rate -system.cpu.iew.EXEC:refs 5553 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 2589 # Number of stores executed +system.cpu.iew.EXEC:rate 0.670318 # Inst execution rate +system.cpu.iew.EXEC:refs 5385 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 2502 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 10966 # num instructions consuming a value -system.cpu.iew.WB:count 21367 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.799836 # average fanout of values written-back +system.cpu.iew.WB:consumers 10159 # num instructions consuming a value +system.cpu.iew.WB:count 20199 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.790629 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 8771 # num instructions producing a value -system.cpu.iew.WB:rate 0.800502 # insts written-back per cycle -system.cpu.iew.WB:sent 21712 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 2654 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 8032 # num instructions producing a value +system.cpu.iew.WB:rate 0.633913 # insts written-back per cycle +system.cpu.iew.WB:sent 20448 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 2568 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 3573 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 630 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1509 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 3440 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 29298 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 2964 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3437 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 22156 # Number of executed instructions +system.cpu.iew.iewDispLoadInsts 3198 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 610 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 2750 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2970 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 25274 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 2883 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1463 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 21359 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 3545 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 3063 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 52 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 48 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 75 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 2111 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 2142 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 75 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 1030 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1624 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.411209 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.411209 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 25593 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 52 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1736 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1672 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 52 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 958 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1610 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.344464 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.344464 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 22822 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 1919 7.50% # Type of FU issued - IntAlu 17231 67.33% # Type of FU issued + (null) 1826 8.00% # Type of FU issued + IntAlu 15247 66.81% # Type of FU issued IntMult 0 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 0 0.00% # Type of FU issued @@ -277,16 +278,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 3429 13.40% # Type of FU issued - MemWrite 3014 11.78% # Type of FU issued + MemRead 3042 13.33% # Type of FU issued + MemWrite 2707 11.86% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 238 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009299 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 190 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.008325 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 99 41.60% # attempts to use FU when none available + IntAlu 50 26.32% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -295,43 +296,43 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 22 9.24% # attempts to use FU when none available - MemWrite 117 49.16% # attempts to use FU when none available + MemRead 25 13.16% # attempts to use FU when none available + MemWrite 115 60.53% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 26692 +system.cpu.iq.ISSUE:issued_per_cycle.samples 31864 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 17644 6610.22% - 1 3262 1222.09% - 2 1371 513.64% - 3 1071 401.24% - 4 1568 587.44% - 5 925 346.55% - 6 579 216.92% - 7 171 64.06% - 8 101 37.84% + 0 22879 7180.20% + 1 3824 1200.10% + 2 1304 409.24% + 3 1251 392.61% + 4 1252 392.92% + 5 751 235.69% + 6 414 129.93% + 7 122 38.29% + 8 67 21.03% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.958827 # Inst issue rate -system.cpu.iq.iqInstsAdded 28668 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 25593 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 630 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 15737 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 133 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 303 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 7975 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 526 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3018.060837 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1812.857414 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1587500 # number of ReadReq miss cycles +system.cpu.iq.ISSUE:rate 0.716231 # Inst issue rate +system.cpu.iq.iqInstsAdded 24664 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 22822 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 610 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 11119 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 83 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 283 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 5685 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 514 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4458.171206 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2373.540856 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 2291500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 526 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 953563 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_misses 514 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1220000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 526 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 514 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -340,32 +341,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 526 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3018.060837 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1812.857414 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 514 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4458.171206 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2373.540856 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1587500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 2291500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 526 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 514 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 953563 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 1220000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 526 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 514 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 526 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3018.060837 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1812.857414 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 514 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4458.171206 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2373.540856 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1587500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 2291500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 526 # number of overall misses +system.cpu.l2cache.overall_misses 514 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 953563 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 1220000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 526 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 514 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -378,28 +379,28 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 526 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 514 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 353.661697 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 345.564898 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 26692 # number of cpu cycles simulated +system.cpu.numCycles 31864 # number of cpu cycles simulated system.cpu.rename.RENAME:CommittedMaps 9868 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 8631 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 59097 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 39751 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 31999 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 9086 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 3545 # Number of cycles rename is squashing -system.cpu.rename.RENAME:SquashedInsts 8167 # Number of squashed instructions processed by rename -system.cpu.rename.RENAME:UnblockCycles 716 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 22131 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 4224 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 665 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 4954 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 658 # count of temporary serializing insts renamed +system.cpu.rename.RENAME:IdleCycles 16082 # Number of cycles rename is idle +system.cpu.rename.RENAME:RenameLookups 44650 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 29655 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 24195 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 7618 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 3063 # Number of cycles rename is squashing +system.cpu.rename.RENAME:SquashedInsts 8815 # Number of squashed instructions processed by rename +system.cpu.rename.RENAME:UnblockCycles 684 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 14327 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 3915 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 631 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 4702 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 623 # count of temporary serializing insts renamed +system.cpu.timesIdled 1 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 8 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout index 0bb67880e..0b6e54449 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout @@ -16,9 +16,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2007 20:15:56 -M5 started Sun Apr 22 20:26:05 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 17:00:06 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing tests/run.py quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 13345500 because target called exit() +Exiting @ tick 15931500 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini index 7e9c12db2..5493b952f 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out index 29915233b..c1a77ba0d 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt index 22ea72ebd..468b3f0a1 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 430012 # Simulator instruction rate (inst/s) -host_mem_usage 149064 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 207711772 # Simulator tick rate (ticks/s) +host_inst_rate 563720 # Simulator instruction rate (inst/s) +host_mem_usage 149048 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 276035132 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 11001 # Number of instructions simulated sim_seconds 0.000005 # Number of seconds simulated diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout index 66bfb4931..01c59e833 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout @@ -16,9 +16,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2007 20:15:56 -M5 started Sun Apr 22 20:26:06 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 17:00:07 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic tests/run.py quick/02.insttest/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 5500000 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini index 394f564a5..2e2789f26 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out index 9d999c4c3..df1a9c852 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt index aef9433e6..33502bf5c 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 285170 # Simulator instruction rate (inst/s) -host_mem_usage 154424 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 211576923 # Simulator tick rate (ticks/s) +host_inst_rate 346412 # Simulator instruction rate (inst/s) +host_mem_usage 154396 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 598818775 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 11001 # Number of instructions simulated -sim_seconds 0.000008 # Number of seconds simulated -sim_ticks 8251500 # Number of ticks simulated +sim_seconds 0.000019 # Number of seconds simulated +sim_ticks 19264000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1462 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3712.962963 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2712.962963 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 1408 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 200500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 756000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.036936 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 146500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 702000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.036936 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits system.cpu.dcache.WriteReq_accesses 1292 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3676.136364 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2676.136364 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 1204 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 323500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 1232000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.068111 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 88 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 235500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1144000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.068111 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 88 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -39,29 +39,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2754 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3690.140845 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2690.140845 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.demand_hits 2612 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 524000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 1988000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.051561 # miss rate for demand accesses system.cpu.dcache.demand_misses 142 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 382000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 1846000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.051561 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 142 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 2754 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3690.140845 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2690.140845 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 2612 # number of overall hits -system.cpu.dcache.overall_miss_latency 524000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 1988000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.051561 # miss rate for overall accesses system.cpu.dcache.overall_misses 142 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 382000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 1846000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.051561 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -78,18 +78,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 106.692969 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 103.809387 # Cycle average of tags in use system.cpu.dcache.total_refs 2618 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 11002 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3743.816254 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2743.816254 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13922.261484 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12922.261484 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 10719 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1059500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 3940000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.025723 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 283 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 776500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 3657000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.025723 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 283 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -101,29 +101,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 11002 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3743.816254 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2743.816254 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13922.261484 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12922.261484 # average overall mshr miss latency system.cpu.icache.demand_hits 10719 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1059500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 3940000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.025723 # miss rate for demand accesses system.cpu.icache.demand_misses 283 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 776500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 3657000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.025723 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 283 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 11002 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3743.816254 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2743.816254 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13922.261484 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12922.261484 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 10719 # number of overall hits -system.cpu.icache.overall_miss_latency 1059500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 3940000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.025723 # miss rate for overall accesses system.cpu.icache.overall_misses 283 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 776500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 3657000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.025723 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 283 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -140,18 +140,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 283 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 170.449932 # Cycle average of tags in use +system.cpu.icache.tagsinuse 163.879834 # Cycle average of tags in use system.cpu.icache.total_refs 10719 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 423 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2730.496454 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1729.496454 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1155000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 5499000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 423 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 731577 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 4653000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 423 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -163,29 +163,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 423 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2730.496454 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1729.496454 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1155000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 5499000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 423 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 731577 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 4653000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 423 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 423 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2730.496454 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1729.496454 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1155000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 5499000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 423 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 731577 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 4653000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 423 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -202,12 +202,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 423 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 276.385948 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 266.922506 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 8251500 # number of cpu cycles simulated +system.cpu.numCycles 19264000 # number of cpu cycles simulated system.cpu.num_insts 11001 # Number of instructions executed system.cpu.num_refs 2760 # Number of memory references system.cpu.workload.PROG:num_syscalls 8 # Number of system calls diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout index dd4d8d282..c2d31ed8f 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout @@ -16,9 +16,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2007 20:15:56 -M5 started Sun Apr 22 20:26:07 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 17:00:07 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing tests/run.py quick/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 8251500 because target called exit() +Exiting @ tick 19264000 because target called exit() diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index 8145ecdc4..6e38281a1 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -5,8 +5,8 @@ dummy=0 [system] type=LinuxAlphaSystem -children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami -boot_cpu_frequency=1 +children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami +boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 console=/dist/m5/system/binaries/console init_param=0 @@ -21,17 +21,22 @@ system_type=34 [system.bridge] type=Bridge -delay=0 -queue_size_a=16 -queue_size_b=16 +delay=50000 +fix_partial_write_a=false +fix_partial_write_b=true +nack_delay=4000 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 write_ack=false side_a=system.iobus.port[0] side_b=system.membus.port[0] [system.cpu0] type=AtomicSimpleCPU -children=dtb itb -clock=1 +children=dcache dtb icache itb +clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true @@ -51,21 +56,109 @@ progress_interval=0 simulate_stalls=false system=system width=1 -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu0.dcache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu0.dcache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi [system.cpu0.dtb] type=AlphaDTB size=64 +[system.cpu0.icache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=1 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu0.icache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu0.icache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + [system.cpu0.itb] type=AlphaITB size=48 [system.cpu1] type=AtomicSimpleCPU -children=dtb itb -clock=1 +children=dcache dtb icache itb +clock=500 cpu_id=1 defer_registration=false do_checkpoint_insts=true @@ -85,13 +178,101 @@ progress_interval=0 simulate_stalls=false system=system width=1 -dcache_port=system.membus.port[5] -icache_port=system.membus.port[4] +dcache_port=system.cpu1.dcache.cpu_side +icache_port=system.cpu1.icache.cpu_side + +[system.cpu1.dcache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu1.dcache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.dcache_port +mem_side=system.toL2Bus.port[4] + +[system.cpu1.dcache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi [system.cpu1.dtb] type=AlphaDTB size=64 +[system.cpu1.icache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=1 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu1.icache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.icache_port +mem_side=system.toL2Bus.port[3] + +[system.cpu1.icache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + [system.cpu1.itb] type=AlphaITB size=48 @@ -99,7 +280,7 @@ size=48 [system.disk0] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk0.image @@ -118,7 +299,7 @@ read_only=true [system.disk2] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk2.image @@ -140,27 +321,67 @@ sys=system [system.iobus] type=Bus +block_size=64 bus_id=0 -clock=2 +clock=1000 responder_set=true width=64 default=system.tsunami.pciconfig.pio port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma +[system.l2c] +type=BaseCache +adaptive_compression=false +assoc=8 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=10000 +lifo=false +max_miss_count=0 +mshrs=92 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=4194304 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[2] + [system.membus] type=Bus children=responder +block_size=64 bus_id=1 -clock=2 +clock=1000 responder_set=false width=64 default=system.membus.responder.pio -port=system.bridge.side_b system.physmem.port system.cpu0.icache_port system.cpu0.dcache_port system.cpu1.icache_port system.cpu1.dcache_port +port=system.bridge.side_b system.physmem.port system.l2c.mem_side [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 platform=system.tsunami ret_bad_addr=true @@ -200,6 +421,33 @@ type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img read_only=true +[system.toL2Bus] +type=Bus +children=responder +block_size=64 +bus_id=0 +clock=1000 +responder_set=false +width=64 +default=system.toL2Bus.responder.pio +port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +platform=system.tsunami +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.toL2Bus.default + [system.tsunami] type=Tsunami children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart @@ -209,7 +457,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -220,7 +468,7 @@ type=AlphaConsole cpu=system.cpu0 disk=system.simple_disk pio_addr=8804682956800 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -235,7 +483,7 @@ peer=Null type=NSGigE children=configdata clock=0 -config_latency=40 +config_latency=20000 configdata=system.tsunami.ethernet.configdata dma_data_free=false dma_desc_free=false @@ -245,19 +493,21 @@ dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 -intr_delay=20000 +intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami rss=false -rx_delay=2000 +rx_delay=1000000 rx_fifo_size=524288 rx_filter=true rx_thread=false system=system -tx_delay=2000 +tx_delay=1000000 tx_fifo_size=524288 tx_thread=false config=system.iobus.port[28] @@ -302,7 +552,7 @@ VendorID=4107 [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 platform=system.tsunami ret_bad_addr=false @@ -318,7 +568,7 @@ pio=system.iobus.port[9] [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -334,7 +584,7 @@ pio=system.iobus.port[20] [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -350,7 +600,7 @@ pio=system.iobus.port[21] [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -366,7 +616,7 @@ pio=system.iobus.port[10] [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -382,7 +632,7 @@ pio=system.iobus.port[12] [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -398,7 +648,7 @@ pio=system.iobus.port[13] [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -414,7 +664,7 @@ pio=system.iobus.port[14] [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -430,7 +680,7 @@ pio=system.iobus.port[15] [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -446,7 +696,7 @@ pio=system.iobus.port[16] [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -462,7 +712,7 @@ pio=system.iobus.port[17] [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -478,7 +728,7 @@ pio=system.iobus.port[18] [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -494,7 +744,7 @@ pio=system.iobus.port[19] [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -510,7 +760,7 @@ pio=system.iobus.port[11] [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -526,7 +776,7 @@ pio=system.iobus.port[8] [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -542,7 +792,7 @@ pio=system.iobus.port[3] [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -558,7 +808,7 @@ pio=system.iobus.port[4] [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -574,7 +824,7 @@ pio=system.iobus.port[5] [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -590,7 +840,7 @@ pio=system.iobus.port[6] [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -607,7 +857,7 @@ pio=system.iobus.port[7] type=BadDevice devicename=FrameBuffer pio_addr=8804615848912 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system pio=system.iobus.port[22] @@ -615,13 +865,15 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController children=configdata -config_latency=40 +config_latency=20000 configdata=system.tsunami.ide.configdata disks=system.disk0 system.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system config=system.iobus.port[30] @@ -665,9 +917,9 @@ VendorID=32902 [system.tsunami.io] type=TsunamiIO -frequency=1953125 +frequency=976562500 pio_addr=8804615847936 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -678,7 +930,7 @@ pio=system.iobus.port[23] [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -696,7 +948,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out index e0c23706f..324ede6b4 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out @@ -11,7 +11,7 @@ zero=false [system] type=LinuxAlphaSystem -boot_cpu_frequency=1 +boot_cpu_frequency=500 physmem=system.physmem mem_mode=atomic kernel=/dist/m5/system/binaries/vmlinux @@ -27,9 +27,10 @@ system_rev=1024 [system.membus] type=Bus bus_id=1 -clock=2 +clock=1000 width=64 responder_set=false +block_size=64 [system.intrctrl] type=IntrControl @@ -43,7 +44,7 @@ intrctrl=system.intrctrl [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 ret_bad_addr=true update_data=false @@ -55,12 +56,54 @@ ret_data64=18446744073709551615 platform=system.tsunami system=system +[system.l2c] +type=BaseCache +size=4194304 +assoc=8 +block_size=64 +latency=10000 +mshrs=92 +tgts_per_mshr=16 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.bridge] type=Bridge -queue_size_a=16 -queue_size_b=16 -delay=0 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +delay=50000 +nack_delay=4000 write_ack=false +fix_partial_write_a=false +fix_partial_write_b=true [system.disk0.image.child] type=RawDiskImage @@ -78,7 +121,7 @@ read_only=false type=IdeDisk image=system.disk0.image driveID=master -delay=2000 +delay=1000000 [system.disk2.image.child] type=RawDiskImage @@ -96,7 +139,7 @@ read_only=false type=IdeDisk image=system.disk2.image driveID=master -delay=2000 +delay=1000000 [system.cpu0.itb] type=AlphaITB @@ -121,7 +164,7 @@ profile=0 do_quiesce=true do_checkpoint_insts=true do_statistics_insts=true -clock=1 +clock=500 phase=0 defer_registration=false width=1 @@ -129,6 +172,90 @@ function_trace=false function_trace_start=0 simulate_stalls=false +[system.cpu0.icache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu0.icache] +type=BaseCache +size=32768 +assoc=1 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu0.icache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + +[system.cpu0.dcache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu0.dcache] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu0.dcache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.cpu1.itb] type=AlphaITB size=48 @@ -152,7 +279,7 @@ profile=0 do_quiesce=true do_checkpoint_insts=true do_statistics_insts=true -clock=1 +clock=500 phase=0 defer_registration=false width=1 @@ -160,6 +287,90 @@ function_trace=false function_trace_start=0 simulate_stalls=false +[system.cpu1.icache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu1.icache] +type=BaseCache +size=32768 +assoc=1 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu1.icache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + +[system.cpu1.dcache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu1.dcache] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu1.dcache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.simple_disk.disk] type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img @@ -173,7 +384,7 @@ disk=system.simple_disk.disk [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -188,7 +399,7 @@ system=system [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -203,7 +414,7 @@ system=system [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -218,7 +429,7 @@ system=system [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -233,7 +444,7 @@ system=system [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -248,7 +459,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -256,8 +467,8 @@ tsunami=system.tsunami [system.tsunami.io] type=TsunamiIO pio_addr=8804615847936 -pio_latency=2 -frequency=1953125 +pio_latency=1000 +frequency=976562500 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -288,12 +499,12 @@ pio_addr=8804682956800 system=system cpu=system.cpu0 platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -308,7 +519,7 @@ system=system [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -323,7 +534,7 @@ system=system [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -331,7 +542,7 @@ tsunami=system.tsunami [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -346,7 +557,7 @@ system=system [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -361,7 +572,7 @@ system=system [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -376,7 +587,7 @@ system=system [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -391,7 +602,7 @@ system=system [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -406,7 +617,7 @@ system=system [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -421,7 +632,7 @@ system=system [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -436,7 +647,7 @@ system=system [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -451,7 +662,7 @@ system=system [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -469,7 +680,7 @@ devicename=FrameBuffer pio_addr=8804615848912 system=system platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.ethernet.configdata] type=PciConfigData @@ -510,12 +721,14 @@ BAR5Size=0 type=NSGigE system=system platform=system.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ethernet.configdata pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 clock=0 dma_desc_free=false dma_data_free=false @@ -524,9 +737,9 @@ dma_write_delay=0 dma_read_factor=0 dma_write_factor=0 dma_no_allocate=true -intr_delay=20000 -rx_delay=2000 -tx_delay=2000 +intr_delay=10000000 +rx_delay=1000000 +tx_delay=1000000 rx_fifo_size=524288 tx_fifo_size=524288 rx_filter=true @@ -543,7 +756,7 @@ device=system.tsunami.ethernet [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 ret_bad_addr=false update_data=false @@ -558,7 +771,7 @@ system=system [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -566,7 +779,7 @@ system=system [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -581,7 +794,7 @@ system=system [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -632,18 +845,44 @@ BAR5Size=0 type=IdeController system=system platform=system.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ide.configdata pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 disks=system.disk0 system.disk2 [system.iobus] type=Bus bus_id=0 -clock=2 +clock=1000 width=64 responder_set=true +block_size=64 + +[system.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false +block_size=64 + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +ret_bad_addr=true +update_data=false +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +platform=system.tsunami +system=system diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt index 2a3b3163d..7765c2852 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt @@ -1,89 +1,256 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 674184 # Simulator instruction rate (inst/s) -host_mem_usage 251408 # Number of bytes of host memory used -host_seconds 93.63 # Real time elapsed on the host -host_tick_rate 39952215 # Simulator tick rate (ticks/s) -sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 63122441 # Number of instructions simulated -sim_seconds 1.870326 # Number of seconds simulated -sim_ticks 3740651174 # Number of ticks simulated +host_inst_rate 607412 # Simulator instruction rate (inst/s) +host_mem_usage 245896 # Number of bytes of host memory used +host_seconds 103.93 # Real time elapsed on the host +host_tick_rate 17996726251 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 63125943 # Number of instructions simulated +sim_seconds 1.870335 # Number of seconds simulated +sim_ticks 1870335097000 # Number of ticks simulated +system.cpu0.dcache.ReadReq_accesses 9163941 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_hits 7464208 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_rate 0.185481 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 1699733 # number of ReadReq misses +system.cpu0.dcache.WriteReq_accesses 5933396 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_hits 5646723 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_rate 0.048315 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 286673 # number of WriteReq misses +system.cpu0.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu0.dcache.avg_refs 6.625609 # Average number of references to valid blocks. +system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.demand_accesses 15097337 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu0.dcache.demand_hits 13110931 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.131573 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 1986406 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.overall_accesses 15097337 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu0.dcache.overall_hits 13110931 # number of overall hits +system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.131573 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 1986406 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu0.dcache.protocol.read_invalid 1699733 # read misses to invalid blocks +system.cpu0.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu0.dcache.protocol.snoop_inv_modified 2 # Invalidate snoops on modified blocks +system.cpu0.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu0.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu0.dcache.protocol.snoop_read_exclusive 689 # read snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_read_modified 4128 # read snoops on modified blocks +system.cpu0.dcache.protocol.snoop_read_owned 122 # read snoops on owned blocks +system.cpu0.dcache.protocol.snoop_read_shared 2691 # read snoops on shared blocks +system.cpu0.dcache.protocol.snoop_readex_exclusive 241 # readEx snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_readex_modified 227 # readEx snoops on modified blocks +system.cpu0.dcache.protocol.snoop_readex_owned 21 # readEx snoops on owned blocks +system.cpu0.dcache.protocol.snoop_readex_shared 14 # readEx snoops on shared blocks +system.cpu0.dcache.protocol.snoop_upgrade_owned 1359 # upgrade snoops on owned blocks +system.cpu0.dcache.protocol.snoop_upgrade_shared 725 # upgradee snoops on shared blocks +system.cpu0.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu0.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu0.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu0.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu0.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu0.dcache.protocol.write_invalid 282337 # write misses to invalid blocks +system.cpu0.dcache.protocol.write_owned 2517 # write misses to owned blocks +system.cpu0.dcache.protocol.write_shared 1819 # write misses to shared blocks +system.cpu0.dcache.replacements 1978969 # number of replacements +system.cpu0.dcache.sampled_refs 1979481 # Sample count of references to valid blocks. +system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.tagsinuse 504.827576 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13115267 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 0 # number of writebacks system.cpu0.dtb.accesses 698037 # DTB accesses system.cpu0.dtb.acv 251 # DTB access violations -system.cpu0.dtb.hits 15071957 # DTB hits +system.cpu0.dtb.hits 15082969 # DTB hits system.cpu0.dtb.misses 7805 # DTB misses system.cpu0.dtb.read_accesses 508987 # DTB read accesses system.cpu0.dtb.read_acv 152 # DTB read access violations -system.cpu0.dtb.read_hits 9142249 # DTB read hits +system.cpu0.dtb.read_hits 9148390 # DTB read hits system.cpu0.dtb.read_misses 7079 # DTB read misses system.cpu0.dtb.write_accesses 189050 # DTB write accesses system.cpu0.dtb.write_acv 99 # DTB write access violations -system.cpu0.dtb.write_hits 5929708 # DTB write hits +system.cpu0.dtb.write_hits 5934579 # DTB write hits system.cpu0.dtb.write_misses 726 # DTB write misses -system.cpu0.idle_fraction 0.984720 # Percentage of idle cycles -system.cpu0.itb.accesses 3857497 # ITB accesses +system.cpu0.icache.ReadReq_accesses 57190172 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_hits 56305300 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_rate 0.015472 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 884872 # number of ReadReq misses +system.cpu0.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu0.icache.avg_refs 63.637052 # Average number of references to valid blocks. +system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.demand_accesses 57190172 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu0.icache.demand_hits 56305300 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.015472 # miss rate for demand accesses +system.cpu0.icache.demand_misses 884872 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.overall_accesses 57190172 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu0.icache.overall_hits 56305300 # number of overall hits +system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.015472 # miss rate for overall accesses +system.cpu0.icache.overall_misses 884872 # number of overall misses +system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu0.icache.protocol.read_invalid 884872 # read misses to invalid blocks +system.cpu0.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu0.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu0.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu0.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu0.icache.protocol.snoop_read_exclusive 25821 # read snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks +system.cpu0.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks +system.cpu0.icache.protocol.snoop_read_shared 13268 # read snoops on shared blocks +system.cpu0.icache.protocol.snoop_readex_exclusive 78 # readEx snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu0.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu0.icache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks +system.cpu0.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu0.icache.protocol.snoop_upgrade_shared 6 # upgradee snoops on shared blocks +system.cpu0.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu0.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu0.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu0.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu0.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu0.icache.protocol.write_invalid 0 # write misses to invalid blocks +system.cpu0.icache.protocol.write_owned 0 # write misses to owned blocks +system.cpu0.icache.protocol.write_shared 0 # write misses to shared blocks +system.cpu0.icache.replacements 884276 # number of replacements +system.cpu0.icache.sampled_refs 884788 # Sample count of references to valid blocks. +system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.tagsinuse 511.244752 # Cycle average of tags in use +system.cpu0.icache.total_refs 56305300 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.writebacks 0 # number of writebacks +system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles +system.cpu0.itb.accesses 3858835 # ITB accesses system.cpu0.itb.acv 127 # ITB acv -system.cpu0.itb.hits 3854012 # ITB hits +system.cpu0.itb.hits 3855350 # ITB hits system.cpu0.itb.misses 3485 # ITB misses -system.cpu0.kern.callpal 183119 # number of callpals executed +system.cpu0.kern.callpal 183272 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal_wripir 111 0.06% 0.06% # number of callpals executed +system.cpu0.kern.callpal_wripir 110 0.06% 0.06% # number of callpals executed system.cpu0.kern.callpal_wrmces 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal_wrfen 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal_swpctx 3759 2.05% 2.12% # number of callpals executed +system.cpu0.kern.callpal_swpctx 3761 2.05% 2.11% # number of callpals executed system.cpu0.kern.callpal_tbi 38 0.02% 2.14% # number of callpals executed system.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal_swpipl 167881 91.68% 93.82% # number of callpals executed -system.cpu0.kern.callpal_rdps 6134 3.35% 97.17% # number of callpals executed +system.cpu0.kern.callpal_swpipl 168017 91.68% 93.82% # number of callpals executed +system.cpu0.kern.callpal_rdps 6150 3.36% 97.17% # number of callpals executed system.cpu0.kern.callpal_wrkgp 1 0.00% 97.17% # number of callpals executed system.cpu0.kern.callpal_wrusp 3 0.00% 97.17% # number of callpals executed -system.cpu0.kern.callpal_rdusp 7 0.00% 97.17% # number of callpals executed +system.cpu0.kern.callpal_rdusp 7 0.00% 97.18% # number of callpals executed system.cpu0.kern.callpal_whami 2 0.00% 97.18% # number of callpals executed system.cpu0.kern.callpal_rti 4673 2.55% 99.73% # number of callpals executed system.cpu0.kern.callpal_callsys 357 0.19% 99.92% # number of callpals executed system.cpu0.kern.callpal_imb 142 0.08% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 196948 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6163 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 174714 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 70932 40.60% 40.60% # number of times we switched to this ipl +system.cpu0.kern.inst.hwrei 197101 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6167 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 174850 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 70996 40.60% 40.60% # number of times we switched to this ipl system.cpu0.kern.ipl_count_21 243 0.14% 40.74% # number of times we switched to this ipl system.cpu0.kern.ipl_count_22 1908 1.09% 41.83% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_30 8 0.00% 41.83% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 101623 58.17% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 141281 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 69565 49.24% 49.24% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count_30 8 0.00% 41.84% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 101695 58.16% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 141409 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 69629 49.24% 49.24% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 69557 49.23% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 3740650759 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 3706243742 99.08% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 40220 0.00% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 164088 0.00% 99.09% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 1899 0.00% 99.09% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 34200810 0.91% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used 0.808642 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_0 0.980728 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good_31 69621 49.23% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 1870334889500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 1853125118000 99.08% 99.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 20110000 0.00% 99.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 82044000 0.00% 99.09% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 949500 0.00% 99.09% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 17106668000 0.91% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used_0 0.980745 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.684461 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_31 0.684606 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.mode_good_kernel 1155 system.cpu0.kern.mode_good_user 1156 system.cpu0.kern.mode_good_idle 0 -system.cpu0.kern.mode_switch_kernel 7088 # number of protection mode switches +system.cpu0.kern.mode_switch_kernel 7090 # number of protection mode switches system.cpu0.kern.mode_switch_user 1156 # number of protection mode switches system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good 0.280325 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.162951 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.162906 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 3738736759 99.95% 99.95% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 1913998 0.05% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_kernel 1869377889500 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 956999000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3760 # number of times the context was actually changed +system.cpu0.kern.swap_context 3762 # number of times the context was actually changed system.cpu0.kern.syscall 226 # number of syscalls executed system.cpu0.kern.syscall_2 6 2.65% 2.65% # number of syscalls executed system.cpu0.kern.syscall_3 19 8.41% 11.06% # number of syscalls executed @@ -115,82 +282,249 @@ system.cpu0.kern.syscall_98 2 0.88% 97.35% # nu system.cpu0.kern.syscall_132 2 0.88% 98.23% # number of syscalls executed system.cpu0.kern.syscall_144 2 0.88% 99.12% # number of syscalls executed system.cpu0.kern.syscall_147 2 0.88% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.015280 # Percentage of non-idle cycles -system.cpu0.numCycles 57155598 # number of cpu cycles simulated -system.cpu0.num_insts 57151986 # Number of instructions executed -system.cpu0.num_refs 15311384 # Number of memory references +system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles +system.cpu0.numCycles 57193784 # number of cpu cycles simulated +system.cpu0.num_insts 57190172 # Number of instructions executed +system.cpu0.num_refs 15322419 # Number of memory references +system.cpu1.dcache.ReadReq_accesses 1167383 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_hits 1124444 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_rate 0.036782 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 42939 # number of ReadReq misses +system.cpu1.dcache.WriteReq_accesses 749650 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_hits 723062 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_rate 0.035467 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 26588 # number of WriteReq misses +system.cpu1.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu1.dcache.avg_refs 29.277705 # Average number of references to valid blocks. +system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.demand_accesses 1917033 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu1.dcache.demand_hits 1847506 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.036268 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 69527 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.overall_accesses 1917033 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu1.dcache.overall_hits 1847506 # number of overall hits +system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.036268 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 69527 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu1.dcache.protocol.read_invalid 42939 # read misses to invalid blocks +system.cpu1.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu1.dcache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu1.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu1.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu1.dcache.protocol.snoop_read_exclusive 939 # read snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_read_modified 2438 # read snoops on modified blocks +system.cpu1.dcache.protocol.snoop_read_owned 337 # read snoops on owned blocks +system.cpu1.dcache.protocol.snoop_read_shared 61769 # read snoops on shared blocks +system.cpu1.dcache.protocol.snoop_readex_exclusive 103 # readEx snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_readex_modified 275 # readEx snoops on modified blocks +system.cpu1.dcache.protocol.snoop_readex_owned 44 # readEx snoops on owned blocks +system.cpu1.dcache.protocol.snoop_readex_shared 39 # readEx snoops on shared blocks +system.cpu1.dcache.protocol.snoop_upgrade_owned 1538 # upgrade snoops on owned blocks +system.cpu1.dcache.protocol.snoop_upgrade_shared 2755 # upgradee snoops on shared blocks +system.cpu1.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu1.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu1.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu1.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu1.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu1.dcache.protocol.write_invalid 24475 # write misses to invalid blocks +system.cpu1.dcache.protocol.write_owned 641 # write misses to owned blocks +system.cpu1.dcache.protocol.write_shared 1472 # write misses to shared blocks +system.cpu1.dcache.replacements 62341 # number of replacements +system.cpu1.dcache.sampled_refs 62660 # Sample count of references to valid blocks. +system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.tagsinuse 391.945837 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1834541 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1851266669500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 0 # number of writebacks system.cpu1.dtb.accesses 323622 # DTB accesses system.cpu1.dtb.acv 116 # DTB access violations -system.cpu1.dtb.hits 1925043 # DTB hits +system.cpu1.dtb.hits 1914885 # DTB hits system.cpu1.dtb.misses 3692 # DTB misses system.cpu1.dtb.read_accesses 220342 # DTB read accesses system.cpu1.dtb.read_acv 58 # DTB read access violations -system.cpu1.dtb.read_hits 1169160 # DTB read hits +system.cpu1.dtb.read_hits 1163439 # DTB read hits system.cpu1.dtb.read_misses 3277 # DTB read misses system.cpu1.dtb.write_accesses 103280 # DTB write accesses system.cpu1.dtb.write_acv 58 # DTB write access violations -system.cpu1.dtb.write_hits 755883 # DTB write hits +system.cpu1.dtb.write_hits 751446 # DTB write hits system.cpu1.dtb.write_misses 415 # DTB write misses -system.cpu1.idle_fraction 0.998403 # Percentage of idle cycles -system.cpu1.itb.accesses 1471216 # ITB accesses +system.cpu1.icache.ReadReq_accesses 5935771 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_hits 5832135 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_rate 0.017460 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 103636 # number of ReadReq misses +system.cpu1.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu1.icache.avg_refs 56.289849 # Average number of references to valid blocks. +system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.demand_accesses 5935771 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu1.icache.demand_hits 5832135 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.017460 # miss rate for demand accesses +system.cpu1.icache.demand_misses 103636 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.overall_accesses 5935771 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu1.icache.overall_hits 5832135 # number of overall hits +system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.017460 # miss rate for overall accesses +system.cpu1.icache.overall_misses 103636 # number of overall misses +system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu1.icache.protocol.read_invalid 103636 # read misses to invalid blocks +system.cpu1.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu1.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu1.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu1.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu1.icache.protocol.snoop_read_exclusive 17328 # read snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks +system.cpu1.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks +system.cpu1.icache.protocol.snoop_read_shared 199395 # read snoops on shared blocks +system.cpu1.icache.protocol.snoop_readex_exclusive 25 # readEx snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu1.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu1.icache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks +system.cpu1.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu1.icache.protocol.snoop_upgrade_shared 2 # upgradee snoops on shared blocks +system.cpu1.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu1.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu1.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu1.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu1.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu1.icache.protocol.write_invalid 0 # write misses to invalid blocks +system.cpu1.icache.protocol.write_owned 0 # write misses to owned blocks +system.cpu1.icache.protocol.write_shared 0 # write misses to shared blocks +system.cpu1.icache.replacements 103097 # number of replacements +system.cpu1.icache.sampled_refs 103609 # Sample count of references to valid blocks. +system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.tagsinuse 427.126314 # Cycle average of tags in use +system.cpu1.icache.total_refs 5832135 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1868932665500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.writebacks 0 # number of writebacks +system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles +system.cpu1.itb.accesses 1469938 # ITB accesses system.cpu1.itb.acv 57 # ITB acv -system.cpu1.itb.hits 1469677 # ITB hits +system.cpu1.itb.hits 1468399 # ITB hits system.cpu1.itb.misses 1539 # ITB misses -system.cpu1.kern.callpal 32267 # number of callpals executed +system.cpu1.kern.callpal 32131 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu1.kern.callpal_wripir 8 0.02% 0.03% # number of callpals executed system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal_swpctx 472 1.46% 1.50% # number of callpals executed +system.cpu1.kern.callpal_swpctx 470 1.46% 1.50% # number of callpals executed system.cpu1.kern.callpal_tbi 15 0.05% 1.54% # number of callpals executed system.cpu1.kern.callpal_wrent 7 0.02% 1.57% # number of callpals executed -system.cpu1.kern.callpal_swpipl 26358 81.69% 83.25% # number of callpals executed -system.cpu1.kern.callpal_rdps 2589 8.02% 91.28% # number of callpals executed -system.cpu1.kern.callpal_wrkgp 1 0.00% 91.28% # number of callpals executed -system.cpu1.kern.callpal_wrusp 4 0.01% 91.29% # number of callpals executed -system.cpu1.kern.callpal_rdusp 2 0.01% 91.30% # number of callpals executed -system.cpu1.kern.callpal_whami 3 0.01% 91.31% # number of callpals executed -system.cpu1.kern.callpal_rti 2608 8.08% 99.39% # number of callpals executed +system.cpu1.kern.callpal_swpipl 26238 81.66% 83.22% # number of callpals executed +system.cpu1.kern.callpal_rdps 2576 8.02% 91.24% # number of callpals executed +system.cpu1.kern.callpal_wrkgp 1 0.00% 91.25% # number of callpals executed +system.cpu1.kern.callpal_wrusp 4 0.01% 91.26% # number of callpals executed +system.cpu1.kern.callpal_rdusp 2 0.01% 91.26% # number of callpals executed +system.cpu1.kern.callpal_whami 3 0.01% 91.27% # number of callpals executed +system.cpu1.kern.callpal_rti 2607 8.11% 99.39% # number of callpals executed system.cpu1.kern.callpal_callsys 158 0.49% 99.88% # number of callpals executed system.cpu1.kern.callpal_imb 38 0.12% 100.00% # number of callpals executed system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 39691 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 2208 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 30985 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 10388 33.53% 33.53% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_22 1907 6.15% 39.68% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_30 111 0.36% 40.04% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 18579 59.96% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 22663 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 10378 45.79% 45.79% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_22 1907 8.41% 54.21% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_30 111 0.49% 54.70% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 10267 45.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 3740237191 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 3718224753 99.41% 99.41% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 164002 0.00% 99.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 28353 0.00% 99.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 21820083 0.58% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used 0.731418 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_0 0.999037 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 2205 # number of quiesce instructions executed +system.cpu1.kern.ipl_count 30863 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 10328 33.46% 33.46% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_22 1907 6.18% 39.64% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_30 110 0.36% 40.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_31 18518 60.00% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 22543 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 1870124001500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 1859122583000 99.41% 99.41% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 82001000 0.00% 99.42% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_30 14064500 0.00% 99.42% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used_0 0.999032 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.552613 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good_kernel 613 +system.cpu1.kern.ipl_used_31 0.551247 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good_kernel 612 system.cpu1.kern.mode_good_user 580 -system.cpu1.kern.mode_good_idle 33 -system.cpu1.kern.mode_switch_kernel 1034 # number of protection mode switches +system.cpu1.kern.mode_good_idle 32 +system.cpu1.kern.mode_switch_kernel 1033 # number of protection mode switches system.cpu1.kern.mode_switch_user 580 # number of protection mode switches -system.cpu1.kern.mode_switch_idle 2048 # number of protection mode switches -system.cpu1.kern.mode_switch_good 0.334790 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.592843 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_idle 2046 # number of protection mode switches +system.cpu1.kern.mode_switch_good 1.608089 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.592449 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_idle 0.016113 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 2786521 0.07% 0.07% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 1016578 0.03% 0.10% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 3735960321 99.90% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 473 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good_idle 0.015640 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks_kernel 1373909500 0.07% 0.07% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 508289000 0.03% 0.10% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 1868002152500 99.90% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 471 # number of times the context was actually changed system.cpu1.kern.syscall 100 # number of syscalls executed system.cpu1.kern.syscall_2 2 2.00% 2.00% # number of syscalls executed system.cpu1.kern.syscall_3 11 11.00% 13.00% # number of syscalls executed @@ -209,10 +543,10 @@ system.cpu1.kern.syscall_71 24 24.00% 89.00% # nu system.cpu1.kern.syscall_74 8 8.00% 97.00% # number of syscalls executed system.cpu1.kern.syscall_90 1 1.00% 98.00% # number of syscalls executed system.cpu1.kern.syscall_132 2 2.00% 100.00% # number of syscalls executed -system.cpu1.not_idle_fraction 0.001597 # Percentage of non-idle cycles -system.cpu1.numCycles 5972051 # number of cpu cycles simulated -system.cpu1.num_insts 5970455 # Number of instructions executed -system.cpu1.num_refs 1936828 # Number of memory references +system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles +system.cpu1.numCycles 5937367 # number of cpu cycles simulated +system.cpu1.num_insts 5935771 # Number of instructions executed +system.cpu1.num_refs 1926645 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -225,6 +559,68 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.l2c.ReadExReq_accesses 306245 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_hits 181107 # number of ReadExReq hits +system.l2c.ReadExReq_miss_rate 0.408621 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 125138 # number of ReadExReq misses +system.l2c.ReadReq_accesses 2724155 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits 1782852 # number of ReadReq hits +system.l2c.ReadReq_miss_rate 0.345539 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 941303 # number of ReadReq misses +system.l2c.Writeback_accesses 427632 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 427632 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.l2c.avg_refs 2.242866 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 2724155 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 0 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.l2c.demand_hits 1782852 # number of demand (read+write) hits +system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.345539 # miss rate for demand accesses +system.l2c.demand_misses 941303 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 3151787 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 0 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.l2c.overall_hits 2210484 # number of overall hits +system.l2c.overall_miss_latency 0 # number of overall miss cycles +system.l2c.overall_miss_rate 0.298657 # miss rate for overall accesses +system.l2c.overall_misses 941303 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 0 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 1000779 # number of replacements +system.l2c.sampled_refs 1066159 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 65517.575355 # Cycle average of tags in use +system.l2c.total_refs 2391252 # Total number of references to valid blocks. +system.l2c.warmup_cycle 618103500 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 0 # number of writebacks system.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr index 111ccf4f1..563ca3160 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr @@ -1,7 +1,5 @@ -Warning: rounding error > tolerance - 0.002000 rounded to 0 -Listening for system connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 -0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001 +Listening for system connection on port 3457 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 +0: system.remote_gdb.listener: listening for remote gdb on port 7002 warn: Entering event queue @ 0. Starting simulation... -warn: 195723: Trying to launch CPU number 1! +warn: 97861500: Trying to launch CPU number 1! diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout index 9ec0f1c3f..6afe2cfa0 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 30 2007 13:38:38 -M5 started Mon Apr 30 13:53:05 2007 -M5 executing on zeep -command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -Global frequency set at 2000000000 ticks per second - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Exiting @ tick 3740651174 because m5_exit instruction encountered +M5 compiled May 15 2007 19:06:05 +M5 started Tue May 15 19:06:07 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 1870335097000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index 26242f3b3..791200f9a 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -5,8 +5,8 @@ dummy=0 [system] type=LinuxAlphaSystem -children=bridge cpu disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami -boot_cpu_frequency=1 +children=bridge cpu disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami +boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 console=/dist/m5/system/binaries/console init_param=0 @@ -21,17 +21,22 @@ system_type=34 [system.bridge] type=Bridge -delay=0 -queue_size_a=16 -queue_size_b=16 +delay=50000 +fix_partial_write_a=false +fix_partial_write_b=true +nack_delay=4000 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 write_ack=false side_a=system.iobus.port[0] side_b=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb -clock=1 +children=dcache dtb icache itb +clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true @@ -51,13 +56,101 @@ progress_interval=0 simulate_stalls=false system=system width=1 -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu.dcache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu.dcache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi [system.cpu.dtb] type=AlphaDTB size=64 +[system.cpu.icache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=1 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu.icache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu.icache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + [system.cpu.itb] type=AlphaITB size=48 @@ -65,7 +158,7 @@ size=48 [system.disk0] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk0.image @@ -84,7 +177,7 @@ read_only=true [system.disk2] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk2.image @@ -106,27 +199,67 @@ sys=system [system.iobus] type=Bus +block_size=64 bus_id=0 -clock=2 +clock=1000 responder_set=true width=64 default=system.tsunami.pciconfig.pio port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma +[system.l2c] +type=BaseCache +adaptive_compression=false +assoc=8 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=10000 +lifo=false +max_miss_count=0 +mshrs=92 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=4194304 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[2] + [system.membus] type=Bus children=responder +block_size=64 bus_id=1 -clock=2 +clock=1000 responder_set=false width=64 default=system.membus.responder.pio -port=system.bridge.side_b system.physmem.port system.cpu.icache_port system.cpu.dcache_port +port=system.bridge.side_b system.physmem.port system.l2c.mem_side [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 platform=system.tsunami ret_bad_addr=true @@ -166,6 +299,33 @@ type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img read_only=true +[system.toL2Bus] +type=Bus +children=responder +block_size=64 +bus_id=0 +clock=1000 +responder_set=false +width=64 +default=system.toL2Bus.responder.pio +port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +platform=system.tsunami +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.toL2Bus.default + [system.tsunami] type=Tsunami children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart @@ -175,7 +335,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -186,7 +346,7 @@ type=AlphaConsole cpu=system.cpu disk=system.simple_disk pio_addr=8804682956800 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -201,7 +361,7 @@ peer=Null type=NSGigE children=configdata clock=0 -config_latency=40 +config_latency=20000 configdata=system.tsunami.ethernet.configdata dma_data_free=false dma_desc_free=false @@ -211,19 +371,21 @@ dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 -intr_delay=20000 +intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami rss=false -rx_delay=2000 +rx_delay=1000000 rx_fifo_size=524288 rx_filter=true rx_thread=false system=system -tx_delay=2000 +tx_delay=1000000 tx_fifo_size=524288 tx_thread=false config=system.iobus.port[28] @@ -268,7 +430,7 @@ VendorID=4107 [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 platform=system.tsunami ret_bad_addr=false @@ -284,7 +446,7 @@ pio=system.iobus.port[9] [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -300,7 +462,7 @@ pio=system.iobus.port[20] [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -316,7 +478,7 @@ pio=system.iobus.port[21] [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -332,7 +494,7 @@ pio=system.iobus.port[10] [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -348,7 +510,7 @@ pio=system.iobus.port[12] [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -364,7 +526,7 @@ pio=system.iobus.port[13] [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -380,7 +542,7 @@ pio=system.iobus.port[14] [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -396,7 +558,7 @@ pio=system.iobus.port[15] [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -412,7 +574,7 @@ pio=system.iobus.port[16] [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -428,7 +590,7 @@ pio=system.iobus.port[17] [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -444,7 +606,7 @@ pio=system.iobus.port[18] [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -460,7 +622,7 @@ pio=system.iobus.port[19] [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -476,7 +638,7 @@ pio=system.iobus.port[11] [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -492,7 +654,7 @@ pio=system.iobus.port[8] [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -508,7 +670,7 @@ pio=system.iobus.port[3] [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -524,7 +686,7 @@ pio=system.iobus.port[4] [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -540,7 +702,7 @@ pio=system.iobus.port[5] [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -556,7 +718,7 @@ pio=system.iobus.port[6] [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -573,7 +735,7 @@ pio=system.iobus.port[7] type=BadDevice devicename=FrameBuffer pio_addr=8804615848912 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system pio=system.iobus.port[22] @@ -581,13 +743,15 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController children=configdata -config_latency=40 +config_latency=20000 configdata=system.tsunami.ide.configdata disks=system.disk0 system.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system config=system.iobus.port[30] @@ -631,9 +795,9 @@ VendorID=32902 [system.tsunami.io] type=TsunamiIO -frequency=1953125 +frequency=976562500 pio_addr=8804615847936 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -644,7 +808,7 @@ pio=system.iobus.port[23] [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -662,7 +826,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out index 7a0f99013..94cc53f32 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out @@ -11,7 +11,7 @@ zero=false [system] type=LinuxAlphaSystem -boot_cpu_frequency=1 +boot_cpu_frequency=500 physmem=system.physmem mem_mode=atomic kernel=/dist/m5/system/binaries/vmlinux @@ -27,9 +27,10 @@ system_rev=1024 [system.membus] type=Bus bus_id=1 -clock=2 +clock=1000 width=64 responder_set=false +block_size=64 [system.intrctrl] type=IntrControl @@ -43,7 +44,7 @@ intrctrl=system.intrctrl [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 ret_bad_addr=true update_data=false @@ -55,12 +56,54 @@ ret_data64=18446744073709551615 platform=system.tsunami system=system +[system.l2c] +type=BaseCache +size=4194304 +assoc=8 +block_size=64 +latency=10000 +mshrs=92 +tgts_per_mshr=16 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.bridge] type=Bridge -queue_size_a=16 -queue_size_b=16 -delay=0 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +delay=50000 +nack_delay=4000 write_ack=false +fix_partial_write_a=false +fix_partial_write_b=true [system.disk0.image.child] type=RawDiskImage @@ -78,7 +121,7 @@ read_only=false type=IdeDisk image=system.disk0.image driveID=master -delay=2000 +delay=1000000 [system.disk2.image.child] type=RawDiskImage @@ -96,7 +139,7 @@ read_only=false type=IdeDisk image=system.disk2.image driveID=master -delay=2000 +delay=1000000 [system.simple_disk.disk] type=RawDiskImage @@ -111,7 +154,7 @@ disk=system.simple_disk.disk [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -126,7 +169,7 @@ system=system [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -141,7 +184,7 @@ system=system [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -156,7 +199,7 @@ system=system [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -171,7 +214,7 @@ system=system [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -186,7 +229,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -194,8 +237,8 @@ tsunami=system.tsunami [system.tsunami.io] type=TsunamiIO pio_addr=8804615847936 -pio_latency=2 -frequency=1953125 +pio_latency=1000 +frequency=976562500 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -241,7 +284,7 @@ profile=0 do_quiesce=true do_checkpoint_insts=true do_statistics_insts=true -clock=1 +clock=500 phase=0 defer_registration=false width=1 @@ -257,12 +300,12 @@ pio_addr=8804682956800 system=system cpu=system.cpu platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -277,7 +320,7 @@ system=system [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -292,7 +335,7 @@ system=system [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -300,7 +343,7 @@ tsunami=system.tsunami [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -315,7 +358,7 @@ system=system [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -330,7 +373,7 @@ system=system [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -345,7 +388,7 @@ system=system [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -360,7 +403,7 @@ system=system [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -375,7 +418,7 @@ system=system [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -390,7 +433,7 @@ system=system [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -405,7 +448,7 @@ system=system [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -420,7 +463,7 @@ system=system [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -438,7 +481,7 @@ devicename=FrameBuffer pio_addr=8804615848912 system=system platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.ethernet.configdata] type=PciConfigData @@ -479,12 +522,14 @@ BAR5Size=0 type=NSGigE system=system platform=system.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ethernet.configdata pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 clock=0 dma_desc_free=false dma_data_free=false @@ -493,9 +538,9 @@ dma_write_delay=0 dma_read_factor=0 dma_write_factor=0 dma_no_allocate=true -intr_delay=20000 -rx_delay=2000 -tx_delay=2000 +intr_delay=10000000 +rx_delay=1000000 +tx_delay=1000000 rx_fifo_size=524288 tx_fifo_size=524288 rx_filter=true @@ -512,7 +557,7 @@ device=system.tsunami.ethernet [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 ret_bad_addr=false update_data=false @@ -527,7 +572,7 @@ system=system [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -535,7 +580,7 @@ system=system [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -550,7 +595,7 @@ system=system [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -601,18 +646,128 @@ BAR5Size=0 type=IdeController system=system platform=system.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ide.configdata pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 disks=system.disk0 system.disk2 +[system.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false +block_size=64 + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +ret_bad_addr=true +update_data=false +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +platform=system.tsunami +system=system + [system.iobus] type=Bus bus_id=0 -clock=2 +clock=1000 width=64 responder_set=true +block_size=64 + +[system.cpu.icache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu.icache] +type=BaseCache +size=32768 +assoc=1 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu.icache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + +[system.cpu.dcache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu.dcache] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu.dcache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt index de848de68..aaa6c0c86 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt @@ -1,31 +1,199 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1069072 # Simulator instruction rate (inst/s) -host_mem_usage 251484 # Number of bytes of host memory used -host_seconds 56.13 # Real time elapsed on the host -host_tick_rate 65146530 # Simulator tick rate (ticks/s) -sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 60007301 # Number of instructions simulated -sim_seconds 1.828354 # Number of seconds simulated -sim_ticks 3656708271 # Number of ticks simulated +host_inst_rate 577751 # Simulator instruction rate (inst/s) +host_mem_usage 244724 # Number of bytes of host memory used +host_seconds 103.86 # Real time elapsed on the host +host_tick_rate 17603359253 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 60007317 # Number of instructions simulated +sim_seconds 1.828355 # Number of seconds simulated +sim_ticks 1828355481500 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 9723333 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits 7984499 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_rate 0.178831 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1738834 # number of ReadReq misses +system.cpu.dcache.WriteReq_accesses 6349447 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_hits 6045093 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_rate 0.047934 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 304354 # number of WriteReq misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 6.866570 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 16072780 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu.dcache.demand_hits 14029592 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.127121 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2043188 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 16072780 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 14029592 # number of overall hits +system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.127121 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2043188 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu.dcache.protocol.read_invalid 1738834 # read misses to invalid blocks +system.cpu.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu.dcache.protocol.snoop_inv_modified 1 # Invalidate snoops on modified blocks +system.cpu.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu.dcache.protocol.snoop_read_exclusive 10 # read snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_read_modified 15 # read snoops on modified blocks +system.cpu.dcache.protocol.snoop_read_owned 2 # read snoops on owned blocks +system.cpu.dcache.protocol.snoop_read_shared 124 # read snoops on shared blocks +system.cpu.dcache.protocol.snoop_readex_exclusive 0 # readEx snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu.dcache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu.dcache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks +system.cpu.dcache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu.dcache.protocol.snoop_upgrade_shared 0 # upgradee snoops on shared blocks +system.cpu.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu.dcache.protocol.write_invalid 304342 # write misses to invalid blocks +system.cpu.dcache.protocol.write_owned 8 # write misses to owned blocks +system.cpu.dcache.protocol.write_shared 4 # write misses to shared blocks +system.cpu.dcache.replacements 2042663 # number of replacements +system.cpu.dcache.sampled_refs 2043175 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 511.997801 # Cycle average of tags in use +system.cpu.dcache.total_refs 14029604 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dtb.accesses 1020787 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 16053817 # DTB hits +system.cpu.dtb.hits 16053818 # DTB hits system.cpu.dtb.misses 11471 # DTB misses system.cpu.dtb.read_accesses 728856 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 9703849 # DTB read hits +system.cpu.dtb.read_hits 9703850 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.write_accesses 291931 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_hits 6349968 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses +system.cpu.icache.ReadReq_accesses 60007317 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_hits 59087263 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_rate 0.015332 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 920054 # number of ReadReq misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 64.229545 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 60007317 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu.icache.demand_hits 59087263 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.015332 # miss rate for demand accesses +system.cpu.icache.demand_misses 920054 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 60007317 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 59087263 # number of overall hits +system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.015332 # miss rate for overall accesses +system.cpu.icache.overall_misses 920054 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu.icache.protocol.read_invalid 920054 # read misses to invalid blocks +system.cpu.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu.icache.protocol.snoop_read_exclusive 643 # read snoops on exclusive blocks +system.cpu.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks +system.cpu.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks +system.cpu.icache.protocol.snoop_read_shared 1039 # read snoops on shared blocks +system.cpu.icache.protocol.snoop_readex_exclusive 105 # readEx snoops on exclusive blocks +system.cpu.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu.icache.protocol.snoop_readex_shared 1 # readEx snoops on shared blocks +system.cpu.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu.icache.protocol.snoop_upgrade_shared 9 # upgradee snoops on shared blocks +system.cpu.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu.icache.protocol.write_invalid 0 # write misses to invalid blocks +system.cpu.icache.protocol.write_owned 0 # write misses to owned blocks +system.cpu.icache.protocol.write_shared 0 # write misses to shared blocks +system.cpu.icache.replacements 919427 # number of replacements +system.cpu.icache.sampled_refs 919939 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 511.214820 # Cycle average of tags in use +system.cpu.icache.total_refs 59087263 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0.983588 # Percentage of idle cycles -system.cpu.itb.accesses 4979206 # ITB accesses +system.cpu.itb.accesses 4979217 # ITB accesses system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 4974200 # ITB hits +system.cpu.itb.hits 4974211 # ITB hits system.cpu.itb.misses 5006 # ITB misses -system.cpu.kern.callpal 192138 # number of callpals executed +system.cpu.kern.callpal 192139 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed @@ -33,7 +201,7 @@ system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal_swpctx 4177 2.17% 2.18% # number of callpals executed system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal_wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal_swpipl 175209 91.19% 93.40% # number of callpals executed +system.cpu.kern.callpal_swpipl 175210 91.19% 93.40% # number of callpals executed system.cpu.kern.callpal_rdps 6770 3.52% 96.92% # number of callpals executed system.cpu.kern.callpal_wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal_wrusp 7 0.00% 96.92% # number of callpals executed @@ -43,41 +211,40 @@ system.cpu.kern.callpal_rti 5202 2.71% 99.64% # nu system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 211276 # number of hwrei instructions executed +system.cpu.kern.inst.hwrei 211277 # number of hwrei instructions executed system.cpu.kern.inst.quiesce 6240 # number of quiesce instructions executed -system.cpu.kern.ipl_count 182520 # number of times we switched to this ipl +system.cpu.kern.ipl_count 182521 # number of times we switched to this ipl system.cpu.kern.ipl_count_0 74815 40.99% 40.99% # number of times we switched to this ipl system.cpu.kern.ipl_count_21 243 0.13% 41.12% # number of times we switched to this ipl system.cpu.kern.ipl_count_22 1865 1.02% 42.14% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 105597 57.86% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 105598 57.86% 100.00% # number of times we switched to this ipl system.cpu.kern.ipl_good 149004 # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_0 73448 49.29% 49.29% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_22 1865 1.25% 50.71% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_31 73448 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 3656707856 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 3622172407 99.06% 99.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 40220 0.00% 99.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 160390 0.00% 99.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 34334839 0.94% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used 0.816371 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_ticks 1828355274000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1811087543000 99.06% 99.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 20110000 0.00% 99.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 80195000 0.00% 99.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 17167426000 0.94% 100.00% # number of cycles we spent at this ipl system.cpu.kern.ipl_used_0 0.981728 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.695550 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1907 -system.cpu.kern.mode_good_user 1736 +system.cpu.kern.ipl_used_31 0.695543 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1908 +system.cpu.kern.mode_good_user 1737 system.cpu.kern.mode_good_idle 171 system.cpu.kern.mode_switch_kernel 5948 # number of protection mode switches -system.cpu.kern.mode_switch_user 1736 # number of protection mode switches +system.cpu.kern.mode_switch_user 1737 # number of protection mode switches system.cpu.kern.mode_switch_idle 2097 # number of protection mode switches -system.cpu.kern.mode_switch_good 0.389940 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.320612 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good 1.402325 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.320780 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 53668047 1.47% 1.47% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 2930128 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 3600109679 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_kernel 26834026500 1.47% 1.47% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 1465069000 0.08% 1.55% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1800056177500 98.45% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.cpu.kern.syscall 326 # number of syscalls executed system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed @@ -111,9 +278,9 @@ system.cpu.kern.syscall_132 4 1.23% 98.77% # nu system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed system.cpu.not_idle_fraction 0.016412 # Percentage of non-idle cycles -system.cpu.numCycles 60012491 # number of cpu cycles simulated -system.cpu.num_insts 60007301 # Number of instructions executed -system.cpu.num_refs 16302128 # Number of memory references +system.cpu.numCycles 60012507 # number of cpu cycles simulated +system.cpu.num_insts 60007317 # Number of instructions executed +system.cpu.num_refs 16302129 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -126,6 +293,68 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.l2c.ReadExReq_accesses 304342 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_hits 187346 # number of ReadExReq hits +system.l2c.ReadExReq_miss_rate 0.384423 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 116996 # number of ReadExReq misses +system.l2c.ReadReq_accesses 2658871 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits 1717827 # number of ReadReq hits +system.l2c.ReadReq_miss_rate 0.353926 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 941044 # number of ReadReq misses +system.l2c.Writeback_accesses 428885 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 428885 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.l2c.avg_refs 2.205900 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 2658871 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 0 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency # average overall mshr miss latency +system.l2c.demand_hits 1717827 # number of demand (read+write) hits +system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.353926 # miss rate for demand accesses +system.l2c.demand_misses 941044 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 3087756 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 0 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.l2c.overall_hits 2146712 # number of overall hits +system.l2c.overall_miss_latency 0 # number of overall miss cycles +system.l2c.overall_miss_rate 0.304766 # miss rate for overall accesses +system.l2c.overall_misses 941044 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 0 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 992432 # number of replacements +system.l2c.sampled_refs 1057820 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 65517.661064 # Cycle average of tags in use +system.l2c.total_refs 2333445 # Total number of references to valid blocks. +system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 0 # number of writebacks system.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr index 969291745..072cb6c8c 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr @@ -1,5 +1,3 @@ -Warning: rounding error > tolerance - 0.002000 rounded to 0 Listening for system connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout index c3a1cb464..e47b6f226 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 30 2007 13:38:38 -M5 started Mon Apr 30 13:52:08 2007 -M5 executing on zeep -command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -Global frequency set at 2000000000 ticks per second - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Exiting @ tick 3656708271 because m5_exit instruction encountered +M5 compiled May 15 2007 19:06:05 +M5 started Tue May 15 19:06:07 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 1828355481500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 8e1ba179d..7bcdbdb71 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -5,14 +5,14 @@ dummy=0 [system] type=LinuxAlphaSystem -children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami -boot_cpu_frequency=1 +children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami +boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/Users/ali/work/system/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/Users/ali/work/system/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux mem_mode=timing -pal=/Users/ali/work/system/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -21,10 +21,10 @@ system_type=34 [system.bridge] type=Bridge -delay=0 +delay=50000 fix_partial_write_a=false fix_partial_write_b=true -nack_delay=0 +nack_delay=4000 req_size_a=16 req_size_b=16 resp_size_a=16 @@ -35,8 +35,8 @@ side_b=system.membus.port[0] [system.cpu0] type=TimingSimpleCPU -children=dtb itb -clock=1 +children=dcache dtb icache itb +clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true @@ -54,21 +54,109 @@ phase=0 profile=0 progress_interval=0 system=system -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu0.dcache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu0.dcache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi [system.cpu0.dtb] type=AlphaDTB size=64 +[system.cpu0.icache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=1 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu0.icache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu0.icache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + [system.cpu0.itb] type=AlphaITB size=48 [system.cpu1] type=TimingSimpleCPU -children=dtb itb -clock=1 +children=dcache dtb icache itb +clock=500 cpu_id=1 defer_registration=false do_checkpoint_insts=true @@ -86,13 +174,101 @@ phase=0 profile=0 progress_interval=0 system=system -dcache_port=system.membus.port[5] -icache_port=system.membus.port[4] +dcache_port=system.cpu1.dcache.cpu_side +icache_port=system.cpu1.icache.cpu_side + +[system.cpu1.dcache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu1.dcache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.dcache_port +mem_side=system.toL2Bus.port[4] + +[system.cpu1.dcache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi [system.cpu1.dtb] type=AlphaDTB size=64 +[system.cpu1.icache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=1 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu1.icache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.icache_port +mem_side=system.toL2Bus.port[3] + +[system.cpu1.icache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + [system.cpu1.itb] type=AlphaITB size=48 @@ -100,7 +276,7 @@ size=48 [system.disk0] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk0.image @@ -113,13 +289,13 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk2.image @@ -132,7 +308,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -143,27 +319,65 @@ sys=system type=Bus block_size=64 bus_id=0 -clock=2 +clock=1000 responder_set=true width=64 default=system.tsunami.pciconfig.pio port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma +[system.l2c] +type=BaseCache +adaptive_compression=false +assoc=8 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=10000 +lifo=false +max_miss_count=0 +mshrs=92 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=4194304 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[2] + [system.membus] type=Bus children=responder block_size=64 bus_id=1 -clock=2 +clock=1000 responder_set=false width=64 default=system.membus.responder.pio -port=system.bridge.side_b system.physmem.port system.cpu0.icache_port system.cpu0.dcache_port system.cpu1.icache_port system.cpu1.dcache_port +port=system.bridge.side_b system.physmem.port system.l2c.mem_side [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 platform=system.tsunami ret_bad_addr=true @@ -200,9 +414,36 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true +[system.toL2Bus] +type=Bus +children=responder +block_size=64 +bus_id=0 +clock=1000 +responder_set=false +width=64 +default=system.toL2Bus.responder.pio +port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +platform=system.tsunami +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.toL2Bus.default + [system.tsunami] type=Tsunami children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart @@ -212,7 +453,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -223,7 +464,7 @@ type=AlphaConsole cpu=system.cpu0 disk=system.simple_disk pio_addr=8804682956800 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -238,7 +479,7 @@ peer=Null type=NSGigE children=configdata clock=0 -config_latency=40 +config_latency=20000 configdata=system.tsunami.ethernet.configdata dma_data_free=false dma_desc_free=false @@ -248,21 +489,21 @@ dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 -intr_delay=20000 -max_backoff_delay=20000 -min_backoff_delay=8 +intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami rss=false -rx_delay=2000 +rx_delay=1000000 rx_fifo_size=524288 rx_filter=true rx_thread=false system=system -tx_delay=2000 +tx_delay=1000000 tx_fifo_size=524288 tx_thread=false config=system.iobus.port[28] @@ -307,7 +548,7 @@ VendorID=4107 [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 platform=system.tsunami ret_bad_addr=false @@ -323,7 +564,7 @@ pio=system.iobus.port[9] [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -339,7 +580,7 @@ pio=system.iobus.port[20] [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -355,7 +596,7 @@ pio=system.iobus.port[21] [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -371,7 +612,7 @@ pio=system.iobus.port[10] [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -387,7 +628,7 @@ pio=system.iobus.port[12] [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -403,7 +644,7 @@ pio=system.iobus.port[13] [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -419,7 +660,7 @@ pio=system.iobus.port[14] [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -435,7 +676,7 @@ pio=system.iobus.port[15] [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -451,7 +692,7 @@ pio=system.iobus.port[16] [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -467,7 +708,7 @@ pio=system.iobus.port[17] [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -483,7 +724,7 @@ pio=system.iobus.port[18] [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -499,7 +740,7 @@ pio=system.iobus.port[19] [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -515,7 +756,7 @@ pio=system.iobus.port[11] [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -531,7 +772,7 @@ pio=system.iobus.port[8] [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -547,7 +788,7 @@ pio=system.iobus.port[3] [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -563,7 +804,7 @@ pio=system.iobus.port[4] [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -579,7 +820,7 @@ pio=system.iobus.port[5] [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -595,7 +836,7 @@ pio=system.iobus.port[6] [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -612,7 +853,7 @@ pio=system.iobus.port[7] type=BadDevice devicename=FrameBuffer pio_addr=8804615848912 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system pio=system.iobus.port[22] @@ -620,15 +861,15 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController children=configdata -config_latency=40 +config_latency=20000 configdata=system.tsunami.ide.configdata disks=system.disk0 system.disk2 -max_backoff_delay=20000 -min_backoff_delay=8 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system config=system.iobus.port[30] @@ -672,9 +913,9 @@ VendorID=32902 [system.tsunami.io] type=TsunamiIO -frequency=1953125 +frequency=976562500 pio_addr=8804615847936 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -685,7 +926,7 @@ pio=system.iobus.port[23] [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -703,7 +944,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out index 890030c19..68698cf83 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out @@ -11,12 +11,12 @@ zero=false [system] type=LinuxAlphaSystem -boot_cpu_frequency=1 +boot_cpu_frequency=500 physmem=system.physmem mem_mode=timing -kernel=/Users/ali/work/system/binaries/vmlinux -console=/Users/ali/work/system/binaries/console -pal=/Users/ali/work/system/binaries/ts_osfpal +kernel=/dist/m5/system/binaries/vmlinux +console=/dist/m5/system/binaries/console +pal=/dist/m5/system/binaries/ts_osfpal boot_osflags=root=/dev/hda1 console=ttyS0 readfile=tests/halt.sh symbolfile= @@ -27,7 +27,7 @@ system_rev=1024 [system.membus] type=Bus bus_id=1 -clock=2 +clock=1000 width=64 responder_set=false block_size=64 @@ -44,7 +44,7 @@ intrctrl=system.intrctrl [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 ret_bad_addr=true update_data=false @@ -56,21 +56,58 @@ ret_data64=18446744073709551615 platform=system.tsunami system=system +[system.l2c] +type=BaseCache +size=4194304 +assoc=8 +block_size=64 +latency=10000 +mshrs=92 +tgts_per_mshr=16 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.bridge] type=Bridge req_size_a=16 req_size_b=16 resp_size_a=16 resp_size_b=16 -delay=0 -nack_delay=0 +delay=50000 +nack_delay=4000 write_ack=false fix_partial_write_a=false fix_partial_write_b=true [system.disk0.image.child] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk0.image] @@ -84,11 +121,11 @@ read_only=false type=IdeDisk image=system.disk0.image driveID=master -delay=2000 +delay=1000000 [system.disk2.image.child] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.disk2.image] @@ -102,7 +139,7 @@ read_only=false type=IdeDisk image=system.disk2.image driveID=master -delay=2000 +delay=1000000 [system.cpu0.itb] type=AlphaITB @@ -127,7 +164,7 @@ profile=0 do_quiesce=true do_checkpoint_insts=true do_statistics_insts=true -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -135,6 +172,90 @@ function_trace=false function_trace_start=0 // simulate_stalls not specified +[system.cpu0.icache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu0.icache] +type=BaseCache +size=32768 +assoc=1 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu0.icache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + +[system.cpu0.dcache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu0.dcache] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu0.dcache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.cpu1.itb] type=AlphaITB size=48 @@ -158,7 +279,7 @@ profile=0 do_quiesce=true do_checkpoint_insts=true do_statistics_insts=true -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -166,9 +287,93 @@ function_trace=false function_trace_start=0 // simulate_stalls not specified +[system.cpu1.icache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu1.icache] +type=BaseCache +size=32768 +assoc=1 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu1.icache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + +[system.cpu1.dcache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu1.dcache] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu1.dcache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.simple_disk.disk] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.simple_disk] @@ -179,7 +384,7 @@ disk=system.simple_disk.disk [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -194,7 +399,7 @@ system=system [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -209,7 +414,7 @@ system=system [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -224,7 +429,7 @@ system=system [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -239,7 +444,7 @@ system=system [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -254,7 +459,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -262,8 +467,8 @@ tsunami=system.tsunami [system.tsunami.io] type=TsunamiIO pio_addr=8804615847936 -pio_latency=2 -frequency=1953125 +pio_latency=1000 +frequency=976562500 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -294,12 +499,12 @@ pio_addr=8804682956800 system=system cpu=system.cpu0 platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -314,7 +519,7 @@ system=system [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -329,7 +534,7 @@ system=system [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -337,7 +542,7 @@ tsunami=system.tsunami [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -352,7 +557,7 @@ system=system [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -367,7 +572,7 @@ system=system [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -382,7 +587,7 @@ system=system [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -397,7 +602,7 @@ system=system [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -412,7 +617,7 @@ system=system [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -427,7 +632,7 @@ system=system [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -442,7 +647,7 @@ system=system [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -457,7 +662,7 @@ system=system [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -475,7 +680,7 @@ devicename=FrameBuffer pio_addr=8804615848912 system=system platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.ethernet.configdata] type=PciConfigData @@ -516,14 +721,14 @@ BAR5Size=0 type=NSGigE system=system platform=system.tsunami -min_backoff_delay=8 -max_backoff_delay=20000 +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ethernet.configdata pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 clock=0 dma_desc_free=false dma_data_free=false @@ -532,9 +737,9 @@ dma_write_delay=0 dma_read_factor=0 dma_write_factor=0 dma_no_allocate=true -intr_delay=20000 -rx_delay=2000 -tx_delay=2000 +intr_delay=10000000 +rx_delay=1000000 +tx_delay=1000000 rx_fifo_size=524288 tx_fifo_size=524288 rx_filter=true @@ -551,7 +756,7 @@ device=system.tsunami.ethernet [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 ret_bad_addr=false update_data=false @@ -566,7 +771,7 @@ system=system [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -574,7 +779,7 @@ system=system [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -589,7 +794,7 @@ system=system [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -640,21 +845,44 @@ BAR5Size=0 type=IdeController system=system platform=system.tsunami -min_backoff_delay=8 -max_backoff_delay=20000 +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ide.configdata pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 disks=system.disk0 system.disk2 [system.iobus] type=Bus bus_id=0 -clock=2 +clock=1000 width=64 responder_set=true block_size=64 +[system.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false +block_size=64 + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +ret_bad_addr=true +update_data=false +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +platform=system.tsunami +system=system + diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt index e808b031d..83bb77f93 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt @@ -1,221 +1,604 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 159511 # Simulator instruction rate (inst/s) -host_seconds 408.44 # Real time elapsed on the host -host_tick_rate 9737848 # Simulator tick rate (ticks/s) -sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 65151264 # Number of instructions simulated -sim_seconds 1.988681 # Number of seconds simulated -sim_ticks 3977362808 # Number of ticks simulated -system.cpu0.dtb.accesses 676531 # DTB accesses -system.cpu0.dtb.acv 306 # DTB access violations -system.cpu0.dtb.hits 12726999 # DTB hits -system.cpu0.dtb.misses 8261 # DTB misses -system.cpu0.dtb.read_accesses 494241 # DTB read accesses -system.cpu0.dtb.read_acv 184 # DTB read access violations -system.cpu0.dtb.read_hits 7906690 # DTB read hits -system.cpu0.dtb.read_misses 7534 # DTB read misses -system.cpu0.dtb.write_accesses 182290 # DTB write accesses -system.cpu0.dtb.write_acv 122 # DTB write access violations -system.cpu0.dtb.write_hits 4820309 # DTB write hits -system.cpu0.dtb.write_misses 727 # DTB write misses -system.cpu0.idle_fraction 0.930953 # Percentage of idle cycles -system.cpu0.itb.accesses 3412195 # ITB accesses -system.cpu0.itb.acv 161 # ITB acv -system.cpu0.itb.hits 3408362 # ITB hits -system.cpu0.itb.misses 3833 # ITB misses -system.cpu0.kern.callpal 142550 # number of callpals executed +host_inst_rate 213082 # Simulator instruction rate (inst/s) +host_mem_usage 203724 # Number of bytes of host memory used +host_seconds 296.83 # Real time elapsed on the host +host_tick_rate 6573231278 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 63248814 # Number of instructions simulated +sim_seconds 1.951129 # Number of seconds simulated +sim_ticks 1951129131000 # Number of ticks simulated +system.cpu0.dcache.ReadReq_accesses 9299202 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency 13073.177688 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12073.152824 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_hits 7589849 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 22346675500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate 0.183817 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 1709353 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_miss_latency 20637280000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.183817 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_misses 1709353 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable 6873 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.cpu0.dcache.ReadResp_mshr_uncacheable_latency 841915000 # number of ReadResp MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_accesses 6016348 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency 12644.438594 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 11630.972878 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_hits 5727689 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 3649931000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate 0.047979 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 288659 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_miss_latency 3357385000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.047979 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_misses 288659 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_uncacheable 9698 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.cpu0.dcache.WriteResp_mshr_uncacheable_latency 1186164500 # number of WriteResp MSHR uncacheable cycles +system.cpu0.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu0.dcache.avg_refs 6.687909 # Average number of references to valid blocks. +system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.demand_accesses 15315550 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 13011.236419 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 12009.269714 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 13317538 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 25996606500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.130456 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 1998012 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 23994665000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0.130456 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 1998012 # number of demand (read+write) MSHR misses +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.overall_accesses 15315550 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 13011.236419 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 12009.269714 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_hits 13317538 # number of overall hits +system.cpu0.dcache.overall_miss_latency 25996606500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.130456 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 1998012 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 23994665000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0.130456 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 1998012 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_misses 16571 # number of overall MSHR uncacheable misses +system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu0.dcache.protocol.read_invalid 1709421 # read misses to invalid blocks +system.cpu0.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu0.dcache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu0.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu0.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu0.dcache.protocol.snoop_read_exclusive 908 # read snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_read_modified 3762 # read snoops on modified blocks +system.cpu0.dcache.protocol.snoop_read_owned 72 # read snoops on owned blocks +system.cpu0.dcache.protocol.snoop_read_shared 2297 # read snoops on shared blocks +system.cpu0.dcache.protocol.snoop_readex_exclusive 235 # readEx snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_readex_modified 207 # readEx snoops on modified blocks +system.cpu0.dcache.protocol.snoop_readex_owned 15 # readEx snoops on owned blocks +system.cpu0.dcache.protocol.snoop_readex_shared 7 # readEx snoops on shared blocks +system.cpu0.dcache.protocol.snoop_upgrade_owned 1074 # upgrade snoops on owned blocks +system.cpu0.dcache.protocol.snoop_upgrade_shared 726 # upgradee snoops on shared blocks +system.cpu0.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu0.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu0.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu0.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu0.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu0.dcache.protocol.write_invalid 284810 # write misses to invalid blocks +system.cpu0.dcache.protocol.write_owned 2533 # write misses to owned blocks +system.cpu0.dcache.protocol.write_shared 1354 # write misses to shared blocks +system.cpu0.dcache.replacements 1991354 # number of replacements +system.cpu0.dcache.sampled_refs 1991866 # Sample count of references to valid blocks. +system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.tagsinuse 503.775443 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13321418 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 57953000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 401606 # number of writebacks +system.cpu0.dtb.accesses 719860 # DTB accesses +system.cpu0.dtb.acv 289 # DTB access violations +system.cpu0.dtb.hits 15299767 # DTB hits +system.cpu0.dtb.misses 8485 # DTB misses +system.cpu0.dtb.read_accesses 524201 # DTB read accesses +system.cpu0.dtb.read_acv 174 # DTB read access violations +system.cpu0.dtb.read_hits 9282693 # DTB read hits +system.cpu0.dtb.read_misses 7687 # DTB read misses +system.cpu0.dtb.write_accesses 195659 # DTB write accesses +system.cpu0.dtb.write_acv 115 # DTB write access violations +system.cpu0.dtb.write_hits 6017074 # DTB write hits +system.cpu0.dtb.write_misses 798 # DTB write misses +system.cpu0.icache.ReadReq_accesses 57872551 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency 12029.752588 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11029.000057 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits 56957639 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 11006165000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate 0.015809 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 914912 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_miss_latency 10090564500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate 0.015809 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_misses 914912 # number of ReadReq MSHR misses +system.cpu0.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu0.icache.avg_refs 62.632934 # Average number of references to valid blocks. +system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.demand_accesses 57872551 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 12029.752588 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 11029.000057 # average overall mshr miss latency +system.cpu0.icache.demand_hits 56957639 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 11006165000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.015809 # miss rate for demand accesses +system.cpu0.icache.demand_misses 914912 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 10090564500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0.015809 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 914912 # number of demand (read+write) MSHR misses +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.overall_accesses 57872551 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 12029.752588 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 11029.000057 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu0.icache.overall_hits 56957639 # number of overall hits +system.cpu0.icache.overall_miss_latency 11006165000 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.015809 # miss rate for overall accesses +system.cpu0.icache.overall_misses 914912 # number of overall misses +system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 10090564500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0.015809 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 914912 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu0.icache.protocol.read_invalid 915158 # read misses to invalid blocks +system.cpu0.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu0.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu0.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu0.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu0.icache.protocol.snoop_read_exclusive 4652 # read snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks +system.cpu0.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks +system.cpu0.icache.protocol.snoop_read_shared 8768 # read snoops on shared blocks +system.cpu0.icache.protocol.snoop_readex_exclusive 121 # readEx snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu0.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu0.icache.protocol.snoop_readex_shared 1 # readEx snoops on shared blocks +system.cpu0.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu0.icache.protocol.snoop_upgrade_shared 12 # upgradee snoops on shared blocks +system.cpu0.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu0.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu0.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu0.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu0.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu0.icache.protocol.write_invalid 0 # write misses to invalid blocks +system.cpu0.icache.protocol.write_owned 0 # write misses to owned blocks +system.cpu0.icache.protocol.write_shared 0 # write misses to shared blocks +system.cpu0.icache.replacements 908876 # number of replacements +system.cpu0.icache.sampled_refs 909388 # Sample count of references to valid blocks. +system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.tagsinuse 508.806183 # Cycle average of tags in use +system.cpu0.icache.total_refs 56957639 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 34906249000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.writebacks 0 # number of writebacks +system.cpu0.idle_fraction 0.943968 # Percentage of idle cycles +system.cpu0.itb.accesses 3944641 # ITB accesses +system.cpu0.itb.acv 143 # ITB acv +system.cpu0.itb.hits 3940800 # ITB hits +system.cpu0.itb.misses 3841 # ITB misses +system.cpu0.kern.callpal 187118 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal_wripir 572 0.40% 0.40% # number of callpals executed -system.cpu0.kern.callpal_wrmces 1 0.00% 0.40% # number of callpals executed -system.cpu0.kern.callpal_wrfen 1 0.00% 0.40% # number of callpals executed -system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.40% # number of callpals executed -system.cpu0.kern.callpal_swpctx 2878 2.02% 2.42% # number of callpals executed -system.cpu0.kern.callpal_tbi 47 0.03% 2.46% # number of callpals executed -system.cpu0.kern.callpal_wrent 7 0.00% 2.46% # number of callpals executed -system.cpu0.kern.callpal_swpipl 127700 89.58% 92.04% # number of callpals executed -system.cpu0.kern.callpal_rdps 6611 4.64% 96.68% # number of callpals executed -system.cpu0.kern.callpal_wrkgp 1 0.00% 96.68% # number of callpals executed -system.cpu0.kern.callpal_wrusp 3 0.00% 96.68% # number of callpals executed -system.cpu0.kern.callpal_rdusp 8 0.01% 96.69% # number of callpals executed -system.cpu0.kern.callpal_whami 2 0.00% 96.69% # number of callpals executed -system.cpu0.kern.callpal_rti 4215 2.96% 99.65% # number of callpals executed -system.cpu0.kern.callpal_callsys 355 0.25% 99.90% # number of callpals executed -system.cpu0.kern.callpal_imb 147 0.10% 100.00% # number of callpals executed +system.cpu0.kern.callpal_wripir 96 0.05% 0.05% # number of callpals executed +system.cpu0.kern.callpal_wrmces 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal_wrfen 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal_swpctx 3865 2.07% 2.12% # number of callpals executed +system.cpu0.kern.callpal_tbi 44 0.02% 2.14% # number of callpals executed +system.cpu0.kern.callpal_wrent 7 0.00% 2.15% # number of callpals executed +system.cpu0.kern.callpal_swpipl 171254 91.52% 93.67% # number of callpals executed +system.cpu0.kern.callpal_rdps 6635 3.55% 97.21% # number of callpals executed +system.cpu0.kern.callpal_wrkgp 1 0.00% 97.21% # number of callpals executed +system.cpu0.kern.callpal_wrusp 4 0.00% 97.22% # number of callpals executed +system.cpu0.kern.callpal_rdusp 7 0.00% 97.22% # number of callpals executed +system.cpu0.kern.callpal_whami 2 0.00% 97.22% # number of callpals executed +system.cpu0.kern.callpal_rti 4694 2.51% 99.73% # number of callpals executed +system.cpu0.kern.callpal_callsys 356 0.19% 99.92% # number of callpals executed +system.cpu0.kern.callpal_imb 149 0.08% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 157735 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6620 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 134538 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 53716 39.93% 39.93% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_21 131 0.10% 40.02% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_22 2009 1.49% 41.52% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_30 482 0.36% 41.88% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 78200 58.12% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 108740 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 53300 49.02% 49.02% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_21 131 0.12% 49.14% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_22 2009 1.85% 50.98% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_30 482 0.44% 51.43% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 52818 48.57% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 3976579702 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 3843619308 96.66% 96.66% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 123584 0.00% 96.66% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 1873872 0.05% 96.71% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 1201752 0.03% 96.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 129761186 3.26% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used 0.808247 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_0 0.992256 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.hwrei 201983 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6162 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 178054 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 72322 40.62% 40.62% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_21 131 0.07% 40.69% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_22 1968 1.11% 41.80% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_30 6 0.00% 41.80% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 103627 58.20% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 144005 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 70953 49.27% 49.27% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_22 1968 1.37% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_31 70947 49.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 1951128432000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 1894864204500 97.12% 97.12% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 72482500 0.00% 97.12% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 564462000 0.03% 97.15% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 4114000 0.00% 97.15% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 55623169000 2.85% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used_0 0.981071 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.675422 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1193 -system.cpu0.kern.mode_good_user 1193 +system.cpu0.kern.ipl_used_31 0.684638 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1230 +system.cpu0.kern.mode_good_user 1231 system.cpu0.kern.mode_good_idle 0 -system.cpu0.kern.mode_switch_kernel 6700 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1193 # number of protection mode switches +system.cpu0.kern.mode_switch_kernel 7215 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1231 # number of protection mode switches system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good 0.302293 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.178060 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.170478 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 3965295376 99.76% 99.76% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 9600934 0.24% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_kernel 1947973402000 99.84% 99.84% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 3155028000 0.16% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2879 # number of times the context was actually changed -system.cpu0.kern.syscall 216 # number of syscalls executed -system.cpu0.kern.syscall_2 7 3.24% 3.24% # number of syscalls executed -system.cpu0.kern.syscall_3 18 8.33% 11.57% # number of syscalls executed -system.cpu0.kern.syscall_4 3 1.39% 12.96% # number of syscalls executed -system.cpu0.kern.syscall_6 30 13.89% 26.85% # number of syscalls executed -system.cpu0.kern.syscall_12 1 0.46% 27.31% # number of syscalls executed -system.cpu0.kern.syscall_15 1 0.46% 27.78% # number of syscalls executed -system.cpu0.kern.syscall_17 9 4.17% 31.94% # number of syscalls executed -system.cpu0.kern.syscall_19 6 2.78% 34.72% # number of syscalls executed -system.cpu0.kern.syscall_20 4 1.85% 36.57% # number of syscalls executed -system.cpu0.kern.syscall_23 2 0.93% 37.50% # number of syscalls executed -system.cpu0.kern.syscall_24 4 1.85% 39.35% # number of syscalls executed -system.cpu0.kern.syscall_33 7 3.24% 42.59% # number of syscalls executed -system.cpu0.kern.syscall_41 2 0.93% 43.52% # number of syscalls executed -system.cpu0.kern.syscall_45 36 16.67% 60.19% # number of syscalls executed -system.cpu0.kern.syscall_47 4 1.85% 62.04% # number of syscalls executed -system.cpu0.kern.syscall_48 8 3.70% 65.74% # number of syscalls executed -system.cpu0.kern.syscall_54 9 4.17% 69.91% # number of syscalls executed -system.cpu0.kern.syscall_58 1 0.46% 70.37% # number of syscalls executed -system.cpu0.kern.syscall_59 6 2.78% 73.15% # number of syscalls executed -system.cpu0.kern.syscall_71 28 12.96% 86.11% # number of syscalls executed -system.cpu0.kern.syscall_73 3 1.39% 87.50% # number of syscalls executed -system.cpu0.kern.syscall_74 8 3.70% 91.20% # number of syscalls executed -system.cpu0.kern.syscall_87 1 0.46% 91.67% # number of syscalls executed -system.cpu0.kern.syscall_90 2 0.93% 92.59% # number of syscalls executed -system.cpu0.kern.syscall_92 7 3.24% 95.83% # number of syscalls executed -system.cpu0.kern.syscall_97 2 0.93% 96.76% # number of syscalls executed -system.cpu0.kern.syscall_98 2 0.93% 97.69% # number of syscalls executed -system.cpu0.kern.syscall_132 2 0.93% 98.61% # number of syscalls executed -system.cpu0.kern.syscall_144 1 0.46% 99.07% # number of syscalls executed -system.cpu0.kern.syscall_147 2 0.93% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.069047 # Percentage of non-idle cycles -system.cpu0.numCycles 3976579942 # number of cpu cycles simulated -system.cpu0.num_insts 50252314 # Number of instructions executed -system.cpu0.num_refs 12958725 # Number of memory references -system.cpu1.dtb.accesses 346252 # DTB accesses -system.cpu1.dtb.acv 67 # DTB access violations -system.cpu1.dtb.hits 4740996 # DTB hits -system.cpu1.dtb.misses 3345 # DTB misses -system.cpu1.dtb.read_accesses 235843 # DTB read accesses -system.cpu1.dtb.read_acv 26 # DTB read access violations -system.cpu1.dtb.read_hits 2707487 # DTB read hits -system.cpu1.dtb.read_misses 2918 # DTB read misses -system.cpu1.dtb.write_accesses 110409 # DTB write accesses -system.cpu1.dtb.write_acv 41 # DTB write access violations -system.cpu1.dtb.write_hits 2033509 # DTB write hits -system.cpu1.dtb.write_misses 427 # DTB write misses -system.cpu1.idle_fraction 0.974578 # Percentage of idle cycles -system.cpu1.itb.accesses 2097175 # ITB accesses -system.cpu1.itb.acv 23 # ITB acv -system.cpu1.itb.hits 2095903 # ITB hits -system.cpu1.itb.misses 1272 # ITB misses -system.cpu1.kern.callpal 80960 # number of callpals executed +system.cpu0.kern.swap_context 3866 # number of times the context was actually changed +system.cpu0.kern.syscall 224 # number of syscalls executed +system.cpu0.kern.syscall_2 6 2.68% 2.68% # number of syscalls executed +system.cpu0.kern.syscall_3 19 8.48% 11.16% # number of syscalls executed +system.cpu0.kern.syscall_4 3 1.34% 12.50% # number of syscalls executed +system.cpu0.kern.syscall_6 30 13.39% 25.89% # number of syscalls executed +system.cpu0.kern.syscall_12 1 0.45% 26.34% # number of syscalls executed +system.cpu0.kern.syscall_15 1 0.45% 26.79% # number of syscalls executed +system.cpu0.kern.syscall_17 10 4.46% 31.25% # number of syscalls executed +system.cpu0.kern.syscall_19 6 2.68% 33.93% # number of syscalls executed +system.cpu0.kern.syscall_20 4 1.79% 35.71% # number of syscalls executed +system.cpu0.kern.syscall_23 2 0.89% 36.61% # number of syscalls executed +system.cpu0.kern.syscall_24 4 1.79% 38.39% # number of syscalls executed +system.cpu0.kern.syscall_33 8 3.57% 41.96% # number of syscalls executed +system.cpu0.kern.syscall_41 2 0.89% 42.86% # number of syscalls executed +system.cpu0.kern.syscall_45 39 17.41% 60.27% # number of syscalls executed +system.cpu0.kern.syscall_47 4 1.79% 62.05% # number of syscalls executed +system.cpu0.kern.syscall_48 7 3.12% 65.18% # number of syscalls executed +system.cpu0.kern.syscall_54 9 4.02% 69.20% # number of syscalls executed +system.cpu0.kern.syscall_58 1 0.45% 69.64% # number of syscalls executed +system.cpu0.kern.syscall_59 5 2.23% 71.88% # number of syscalls executed +system.cpu0.kern.syscall_71 32 14.29% 86.16% # number of syscalls executed +system.cpu0.kern.syscall_73 3 1.34% 87.50% # number of syscalls executed +system.cpu0.kern.syscall_74 9 4.02% 91.52% # number of syscalls executed +system.cpu0.kern.syscall_87 1 0.45% 91.96% # number of syscalls executed +system.cpu0.kern.syscall_90 2 0.89% 92.86% # number of syscalls executed +system.cpu0.kern.syscall_92 7 3.12% 95.98% # number of syscalls executed +system.cpu0.kern.syscall_97 2 0.89% 96.87% # number of syscalls executed +system.cpu0.kern.syscall_98 2 0.89% 97.77% # number of syscalls executed +system.cpu0.kern.syscall_132 2 0.89% 98.66% # number of syscalls executed +system.cpu0.kern.syscall_144 1 0.45% 99.11% # number of syscalls executed +system.cpu0.kern.syscall_147 2 0.89% 100.00% # number of syscalls executed +system.cpu0.not_idle_fraction 0.056032 # Percentage of non-idle cycles +system.cpu0.numCycles 1951129131000 # number of cpu cycles simulated +system.cpu0.num_insts 57872550 # Number of instructions executed +system.cpu0.num_refs 15541096 # Number of memory references +system.cpu1.dcache.ReadReq_accesses 1052558 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency 11119.734481 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 10119.576119 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_hits 1014670 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 421304500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate 0.035996 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 37888 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_miss_latency 383410500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.035996 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_misses 37888 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable 120 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.cpu1.dcache.ReadResp_mshr_uncacheable_latency 14641500 # number of ReadResp MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_accesses 677186 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency 11920.138166 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 10843.231096 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_hits 653157 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 286429000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate 0.035484 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 24029 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_miss_latency 260552000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.035484 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_misses 24029 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_uncacheable 2496 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.cpu1.dcache.WriteResp_mshr_uncacheable_latency 304596500 # number of WriteResp MSHR uncacheable cycles +system.cpu1.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu1.dcache.avg_refs 29.876823 # Average number of references to valid blocks. +system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.demand_accesses 1729744 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 11430.358383 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 10400.415072 # average overall mshr miss latency +system.cpu1.dcache.demand_hits 1667827 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 707733500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.035795 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 61917 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 643962500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0.035795 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 61917 # number of demand (read+write) MSHR misses +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.overall_accesses 1729744 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 11430.358383 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 10400.415072 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_hits 1667827 # number of overall hits +system.cpu1.dcache.overall_miss_latency 707733500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.035795 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 61917 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 643962500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0.035795 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 61917 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_misses 2616 # number of overall MSHR uncacheable misses +system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu1.dcache.protocol.read_invalid 37951 # read misses to invalid blocks +system.cpu1.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu1.dcache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu1.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu1.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu1.dcache.protocol.snoop_read_exclusive 906 # read snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_read_modified 1965 # read snoops on modified blocks +system.cpu1.dcache.protocol.snoop_read_owned 254 # read snoops on owned blocks +system.cpu1.dcache.protocol.snoop_read_shared 65869 # read snoops on shared blocks +system.cpu1.dcache.protocol.snoop_readex_exclusive 191 # readEx snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_readex_modified 198 # readEx snoops on modified blocks +system.cpu1.dcache.protocol.snoop_readex_owned 48 # readEx snoops on owned blocks +system.cpu1.dcache.protocol.snoop_readex_shared 42 # readEx snoops on shared blocks +system.cpu1.dcache.protocol.snoop_upgrade_owned 1132 # upgrade snoops on owned blocks +system.cpu1.dcache.protocol.snoop_upgrade_shared 2716 # upgradee snoops on shared blocks +system.cpu1.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu1.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu1.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu1.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu1.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu1.dcache.protocol.write_invalid 22206 # write misses to invalid blocks +system.cpu1.dcache.protocol.write_owned 601 # write misses to owned blocks +system.cpu1.dcache.protocol.write_shared 1247 # write misses to shared blocks +system.cpu1.dcache.replacements 55360 # number of replacements +system.cpu1.dcache.sampled_refs 55749 # Sample count of references to valid blocks. +system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.tagsinuse 388.749341 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1665603 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1935095598000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 27663 # number of writebacks +system.cpu1.dtb.accesses 302878 # DTB accesses +system.cpu1.dtb.acv 84 # DTB access violations +system.cpu1.dtb.hits 1728432 # DTB hits +system.cpu1.dtb.misses 3106 # DTB misses +system.cpu1.dtb.read_accesses 205838 # DTB read accesses +system.cpu1.dtb.read_acv 36 # DTB read access violations +system.cpu1.dtb.read_hits 1049360 # DTB read hits +system.cpu1.dtb.read_misses 2750 # DTB read misses +system.cpu1.dtb.write_accesses 97040 # DTB write accesses +system.cpu1.dtb.write_acv 48 # DTB write access violations +system.cpu1.dtb.write_hits 679072 # DTB write hits +system.cpu1.dtb.write_misses 356 # DTB write misses +system.cpu1.icache.ReadReq_accesses 5376264 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency 12045.939531 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11045.466957 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits 5281041 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 1147050500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate 0.017712 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 95223 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_miss_latency 1051782500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate 0.017712 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_misses 95223 # number of ReadReq MSHR misses +system.cpu1.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu1.icache.avg_refs 57.662729 # Average number of references to valid blocks. +system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.demand_accesses 5376264 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 12045.939531 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11045.466957 # average overall mshr miss latency +system.cpu1.icache.demand_hits 5281041 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 1147050500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.017712 # miss rate for demand accesses +system.cpu1.icache.demand_misses 95223 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 1051782500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0.017712 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 95223 # number of demand (read+write) MSHR misses +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.overall_accesses 5376264 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 12045.939531 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11045.466957 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu1.icache.overall_hits 5281041 # number of overall hits +system.cpu1.icache.overall_miss_latency 1147050500 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.017712 # miss rate for overall accesses +system.cpu1.icache.overall_misses 95223 # number of overall misses +system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 1051782500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0.017712 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 95223 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu1.icache.protocol.read_invalid 97341 # read misses to invalid blocks +system.cpu1.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu1.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu1.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu1.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu1.icache.protocol.snoop_read_exclusive 39627 # read snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks +system.cpu1.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks +system.cpu1.icache.protocol.snoop_read_shared 214588 # read snoops on shared blocks +system.cpu1.icache.protocol.snoop_readex_exclusive 26 # readEx snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu1.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu1.icache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks +system.cpu1.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu1.icache.protocol.snoop_upgrade_shared 2 # upgradee snoops on shared blocks +system.cpu1.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu1.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu1.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu1.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu1.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu1.icache.protocol.write_invalid 0 # write misses to invalid blocks +system.cpu1.icache.protocol.write_owned 0 # write misses to owned blocks +system.cpu1.icache.protocol.write_shared 0 # write misses to shared blocks +system.cpu1.icache.replacements 91073 # number of replacements +system.cpu1.icache.sampled_refs 91585 # Sample count of references to valid blocks. +system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.tagsinuse 420.500398 # Cycle average of tags in use +system.cpu1.icache.total_refs 5281041 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1947911714000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.writebacks 0 # number of writebacks +system.cpu1.idle_fraction 0.995322 # Percentage of idle cycles +system.cpu1.itb.accesses 1399877 # ITB accesses +system.cpu1.itb.acv 41 # ITB acv +system.cpu1.itb.hits 1398631 # ITB hits +system.cpu1.itb.misses 1246 # ITB misses +system.cpu1.kern.callpal 29847 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal_wripir 482 0.60% 0.60% # number of callpals executed -system.cpu1.kern.callpal_wrmces 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal_wrfen 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal_swpctx 2289 2.83% 3.43% # number of callpals executed -system.cpu1.kern.callpal_tbi 7 0.01% 3.44% # number of callpals executed -system.cpu1.kern.callpal_wrent 7 0.01% 3.44% # number of callpals executed -system.cpu1.kern.callpal_swpipl 71572 88.40% 91.85% # number of callpals executed -system.cpu1.kern.callpal_rdps 2303 2.84% 94.69% # number of callpals executed -system.cpu1.kern.callpal_wrkgp 1 0.00% 94.69% # number of callpals executed -system.cpu1.kern.callpal_wrusp 4 0.00% 94.70% # number of callpals executed -system.cpu1.kern.callpal_rdusp 1 0.00% 94.70% # number of callpals executed -system.cpu1.kern.callpal_whami 3 0.00% 94.70% # number of callpals executed -system.cpu1.kern.callpal_rti 4092 5.05% 99.76% # number of callpals executed -system.cpu1.kern.callpal_callsys 162 0.20% 99.96% # number of callpals executed -system.cpu1.kern.callpal_imb 33 0.04% 100.00% # number of callpals executed +system.cpu1.kern.callpal_wripir 6 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal_swpctx 375 1.26% 1.29% # number of callpals executed +system.cpu1.kern.callpal_tbi 10 0.03% 1.32% # number of callpals executed +system.cpu1.kern.callpal_wrent 7 0.02% 1.34% # number of callpals executed +system.cpu1.kern.callpal_swpipl 24461 81.95% 83.30% # number of callpals executed +system.cpu1.kern.callpal_rdps 2201 7.37% 90.67% # number of callpals executed +system.cpu1.kern.callpal_wrkgp 1 0.00% 90.68% # number of callpals executed +system.cpu1.kern.callpal_wrusp 3 0.01% 90.69% # number of callpals executed +system.cpu1.kern.callpal_rdusp 2 0.01% 90.69% # number of callpals executed +system.cpu1.kern.callpal_whami 3 0.01% 90.70% # number of callpals executed +system.cpu1.kern.callpal_rti 2582 8.65% 99.35% # number of callpals executed +system.cpu1.kern.callpal_callsys 161 0.54% 99.89% # number of callpals executed +system.cpu1.kern.callpal_imb 31 0.10% 100.00% # number of callpals executed system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 88242 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 2815 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 78238 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 30461 38.93% 38.93% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_22 2001 2.56% 41.49% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_30 572 0.73% 42.22% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 45204 57.78% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 61001 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 29500 48.36% 48.36% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_22 2001 3.28% 51.64% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_30 572 0.94% 52.58% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 28928 47.42% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 3977361024 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 3855399740 96.93% 96.93% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 1871566 0.05% 96.98% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 1461344 0.04% 97.02% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 118628374 2.98% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used 0.779685 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_0 0.968451 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.hwrei 36385 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 2332 # number of quiesce instructions executed +system.cpu1.kern.ipl_count 29103 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 9344 32.11% 32.11% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_22 1963 6.75% 38.85% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_30 96 0.33% 39.18% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_31 17700 60.82% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 20635 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 9336 45.24% 45.24% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_22 1963 9.51% 54.76% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_30 96 0.47% 55.22% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_31 9240 44.78% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 1950372731000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 1911409272000 98.00% 98.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 494740000 0.03% 98.03% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_30 52316000 0.00% 98.03% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 38416403000 1.97% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used_0 0.999144 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.639943 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good_kernel 1058 -system.cpu1.kern.mode_good_user 562 -system.cpu1.kern.mode_good_idle 496 -system.cpu1.kern.mode_switch_kernel 2397 # number of protection mode switches -system.cpu1.kern.mode_switch_user 562 # number of protection mode switches -system.cpu1.kern.mode_switch_idle 3035 # number of protection mode switches -system.cpu1.kern.mode_switch_good 0.353020 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.441385 # fraction of useful protection mode switches +system.cpu1.kern.ipl_used_31 0.522034 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good_kernel 538 +system.cpu1.kern.mode_good_user 517 +system.cpu1.kern.mode_good_idle 21 +system.cpu1.kern.mode_switch_kernel 884 # number of protection mode switches +system.cpu1.kern.mode_switch_user 517 # number of protection mode switches +system.cpu1.kern.mode_switch_idle 2075 # number of protection mode switches +system.cpu1.kern.mode_switch_good 1.618718 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.608597 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_idle 0.163427 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 64032120 1.61% 1.61% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 5754658 0.14% 1.75% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 3907574238 98.25% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2290 # number of times the context was actually changed -system.cpu1.kern.syscall 110 # number of syscalls executed -system.cpu1.kern.syscall_2 1 0.91% 0.91% # number of syscalls executed -system.cpu1.kern.syscall_3 12 10.91% 11.82% # number of syscalls executed -system.cpu1.kern.syscall_4 1 0.91% 12.73% # number of syscalls executed -system.cpu1.kern.syscall_6 12 10.91% 23.64% # number of syscalls executed -system.cpu1.kern.syscall_17 6 5.45% 29.09% # number of syscalls executed -system.cpu1.kern.syscall_19 4 3.64% 32.73% # number of syscalls executed -system.cpu1.kern.syscall_20 2 1.82% 34.55% # number of syscalls executed -system.cpu1.kern.syscall_23 2 1.82% 36.36% # number of syscalls executed -system.cpu1.kern.syscall_24 2 1.82% 38.18% # number of syscalls executed -system.cpu1.kern.syscall_33 4 3.64% 41.82% # number of syscalls executed -system.cpu1.kern.syscall_45 18 16.36% 58.18% # number of syscalls executed -system.cpu1.kern.syscall_47 2 1.82% 60.00% # number of syscalls executed -system.cpu1.kern.syscall_48 2 1.82% 61.82% # number of syscalls executed -system.cpu1.kern.syscall_54 1 0.91% 62.73% # number of syscalls executed -system.cpu1.kern.syscall_59 1 0.91% 63.64% # number of syscalls executed -system.cpu1.kern.syscall_71 26 23.64% 87.27% # number of syscalls executed -system.cpu1.kern.syscall_74 8 7.27% 94.55% # number of syscalls executed -system.cpu1.kern.syscall_90 1 0.91% 95.45% # number of syscalls executed -system.cpu1.kern.syscall_92 2 1.82% 97.27% # number of syscalls executed -system.cpu1.kern.syscall_132 2 1.82% 99.09% # number of syscalls executed -system.cpu1.kern.syscall_144 1 0.91% 100.00% # number of syscalls executed -system.cpu1.not_idle_fraction 0.025422 # Percentage of non-idle cycles -system.cpu1.numCycles 3977362808 # number of cpu cycles simulated -system.cpu1.num_insts 14898950 # Number of instructions executed -system.cpu1.num_refs 4770935 # Number of memory references +system.cpu1.kern.mode_switch_good_idle 0.010120 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks_kernel 3563216000 0.18% 0.18% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 1513259000 0.08% 0.26% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 1945257297000 99.74% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 376 # number of times the context was actually changed +system.cpu1.kern.syscall 102 # number of syscalls executed +system.cpu1.kern.syscall_2 2 1.96% 1.96% # number of syscalls executed +system.cpu1.kern.syscall_3 11 10.78% 12.75% # number of syscalls executed +system.cpu1.kern.syscall_4 1 0.98% 13.73% # number of syscalls executed +system.cpu1.kern.syscall_6 12 11.76% 25.49% # number of syscalls executed +system.cpu1.kern.syscall_17 5 4.90% 30.39% # number of syscalls executed +system.cpu1.kern.syscall_19 4 3.92% 34.31% # number of syscalls executed +system.cpu1.kern.syscall_20 2 1.96% 36.27% # number of syscalls executed +system.cpu1.kern.syscall_23 2 1.96% 38.24% # number of syscalls executed +system.cpu1.kern.syscall_24 2 1.96% 40.20% # number of syscalls executed +system.cpu1.kern.syscall_33 3 2.94% 43.14% # number of syscalls executed +system.cpu1.kern.syscall_45 15 14.71% 57.84% # number of syscalls executed +system.cpu1.kern.syscall_47 2 1.96% 59.80% # number of syscalls executed +system.cpu1.kern.syscall_48 3 2.94% 62.75% # number of syscalls executed +system.cpu1.kern.syscall_54 1 0.98% 63.73% # number of syscalls executed +system.cpu1.kern.syscall_59 2 1.96% 65.69% # number of syscalls executed +system.cpu1.kern.syscall_71 22 21.57% 87.25% # number of syscalls executed +system.cpu1.kern.syscall_74 7 6.86% 94.12% # number of syscalls executed +system.cpu1.kern.syscall_90 1 0.98% 95.10% # number of syscalls executed +system.cpu1.kern.syscall_92 2 1.96% 97.06% # number of syscalls executed +system.cpu1.kern.syscall_132 2 1.96% 99.02% # number of syscalls executed +system.cpu1.kern.syscall_144 1 0.98% 100.00% # number of syscalls executed +system.cpu1.not_idle_fraction 0.004678 # Percentage of non-idle cycles +system.cpu1.numCycles 1950372761000 # number of cpu cycles simulated +system.cpu1.num_insts 5376264 # Number of instructions executed +system.cpu1.num_refs 1738417 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -228,6 +611,91 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.l2c.ReadExReq_accesses 306499 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 12998.029396 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 10997.988681 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits 183694 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 1596223000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate 0.400670 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 122805 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 1350608000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate 0.400670 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 122805 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2751323 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 12999.901707 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 10999.990968 # average ReadReq mshr miss latency +system.l2c.ReadReq_hits 1810263 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 12233687500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.342039 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 941060 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 10351530500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.342035 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 941049 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable 6993 # number of ReadReq MSHR uncacheable +system.l2c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.l2c.ReadResp_mshr_uncacheable_latency 779629500 # number of ReadResp MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable 12194 # number of WriteReq MSHR uncacheable +system.l2c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.l2c.WriteResp_mshr_uncacheable_latency 1356619000 # number of WriteResp MSHR uncacheable cycles +system.l2c.Writeback_accesses 429269 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 429256 # number of Writeback hits +system.l2c.Writeback_miss_rate 0.000030 # miss rate for Writeback accesses +system.l2c.Writeback_misses 13 # number of Writeback misses +system.l2c.Writeback_mshr_miss_rate 0.000030 # mshr miss rate for Writeback accesses +system.l2c.Writeback_mshr_misses 13 # number of Writeback MSHR misses +system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.l2c.avg_refs 2.277768 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 2751323 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 12999.901707 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 10999.990968 # average overall mshr miss latency +system.l2c.demand_hits 1810263 # number of demand (read+write) hits +system.l2c.demand_miss_latency 12233687500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.342039 # miss rate for demand accesses +system.l2c.demand_misses 941060 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 10351530500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.342035 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 941049 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 3180592 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 12999.722126 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 10999.990968 # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.l2c.overall_hits 2239519 # number of overall hits +system.l2c.overall_miss_latency 12233687500 # number of overall miss cycles +system.l2c.overall_miss_rate 0.295880 # miss rate for overall accesses +system.l2c.overall_misses 941073 # number of overall misses +system.l2c.overall_mshr_hits 11 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 10351530500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.295872 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 941049 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 19187 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 998318 # number of replacements +system.l2c.sampled_refs 1063854 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 65469.787238 # Cycle average of tags in use +system.l2c.total_refs 2423213 # Total number of references to valid blocks. +system.l2c.warmup_cycle 3064127000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 79556 # number of writebacks system.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr index 9d86a655e..dc84ff88b 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr @@ -1,7 +1,5 @@ -Warning: rounding error > tolerance - 0.002000 rounded to 0 -Listening for system connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 -0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001 +Listening for system connection on port 3457 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 +0: system.remote_gdb.listener: listening for remote gdb on port 7002 warn: Entering event queue @ 0. Starting simulation... -warn: 1082476: Trying to launch CPU number 1! +warn: 423901000: Trying to launch CPU number 1! diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout index ebf8b13c8..a3bd937f6 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 30 2007 13:38:38 -M5 started Mon Apr 30 13:57:20 2007 -M5 executing on zeep -command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -Global frequency set at 2000000000 ticks per second - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Exiting @ tick 3977364868 because m5_exit instruction encountered +M5 compiled May 15 2007 19:06:05 +M5 started Tue May 15 19:07:53 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 1951129131000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index 65aa9c7e6..ded525737 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -5,14 +5,14 @@ dummy=0 [system] type=LinuxAlphaSystem -children=bridge cpu disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami -boot_cpu_frequency=1 +children=bridge cpu disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami +boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/Users/ali/work/system/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/Users/ali/work/system/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux mem_mode=timing -pal=/Users/ali/work/system/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -21,10 +21,10 @@ system_type=34 [system.bridge] type=Bridge -delay=0 +delay=50000 fix_partial_write_a=false fix_partial_write_b=true -nack_delay=0 +nack_delay=4000 req_size_a=16 req_size_b=16 resp_size_a=16 @@ -35,8 +35,8 @@ side_b=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dtb itb -clock=1 +children=dcache dtb icache itb +clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true @@ -54,13 +54,101 @@ phase=0 profile=0 progress_interval=0 system=system -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu.dcache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu.dcache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi [system.cpu.dtb] type=AlphaDTB size=64 +[system.cpu.icache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=1 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu.icache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu.icache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + [system.cpu.itb] type=AlphaITB size=48 @@ -68,7 +156,7 @@ size=48 [system.disk0] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk0.image @@ -81,13 +169,13 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk2.image @@ -100,7 +188,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -111,27 +199,65 @@ sys=system type=Bus block_size=64 bus_id=0 -clock=2 +clock=1000 responder_set=true width=64 default=system.tsunami.pciconfig.pio port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma +[system.l2c] +type=BaseCache +adaptive_compression=false +assoc=8 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=10000 +lifo=false +max_miss_count=0 +mshrs=92 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=4194304 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[2] + [system.membus] type=Bus children=responder block_size=64 bus_id=1 -clock=2 +clock=1000 responder_set=false width=64 default=system.membus.responder.pio -port=system.bridge.side_b system.physmem.port system.cpu.icache_port system.cpu.dcache_port +port=system.bridge.side_b system.physmem.port system.l2c.mem_side [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 platform=system.tsunami ret_bad_addr=true @@ -168,9 +294,36 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true +[system.toL2Bus] +type=Bus +children=responder +block_size=64 +bus_id=0 +clock=1000 +responder_set=false +width=64 +default=system.toL2Bus.responder.pio +port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +platform=system.tsunami +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.toL2Bus.default + [system.tsunami] type=Tsunami children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart @@ -180,7 +333,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -191,7 +344,7 @@ type=AlphaConsole cpu=system.cpu disk=system.simple_disk pio_addr=8804682956800 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -206,7 +359,7 @@ peer=Null type=NSGigE children=configdata clock=0 -config_latency=40 +config_latency=20000 configdata=system.tsunami.ethernet.configdata dma_data_free=false dma_desc_free=false @@ -216,21 +369,21 @@ dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 -intr_delay=20000 -max_backoff_delay=20000 -min_backoff_delay=8 +intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami rss=false -rx_delay=2000 +rx_delay=1000000 rx_fifo_size=524288 rx_filter=true rx_thread=false system=system -tx_delay=2000 +tx_delay=1000000 tx_fifo_size=524288 tx_thread=false config=system.iobus.port[28] @@ -275,7 +428,7 @@ VendorID=4107 [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 platform=system.tsunami ret_bad_addr=false @@ -291,7 +444,7 @@ pio=system.iobus.port[9] [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -307,7 +460,7 @@ pio=system.iobus.port[20] [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -323,7 +476,7 @@ pio=system.iobus.port[21] [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -339,7 +492,7 @@ pio=system.iobus.port[10] [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -355,7 +508,7 @@ pio=system.iobus.port[12] [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -371,7 +524,7 @@ pio=system.iobus.port[13] [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -387,7 +540,7 @@ pio=system.iobus.port[14] [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -403,7 +556,7 @@ pio=system.iobus.port[15] [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -419,7 +572,7 @@ pio=system.iobus.port[16] [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -435,7 +588,7 @@ pio=system.iobus.port[17] [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -451,7 +604,7 @@ pio=system.iobus.port[18] [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -467,7 +620,7 @@ pio=system.iobus.port[19] [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -483,7 +636,7 @@ pio=system.iobus.port[11] [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -499,7 +652,7 @@ pio=system.iobus.port[8] [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -515,7 +668,7 @@ pio=system.iobus.port[3] [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -531,7 +684,7 @@ pio=system.iobus.port[4] [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -547,7 +700,7 @@ pio=system.iobus.port[5] [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -563,7 +716,7 @@ pio=system.iobus.port[6] [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -580,7 +733,7 @@ pio=system.iobus.port[7] type=BadDevice devicename=FrameBuffer pio_addr=8804615848912 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system pio=system.iobus.port[22] @@ -588,15 +741,15 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController children=configdata -config_latency=40 +config_latency=20000 configdata=system.tsunami.ide.configdata disks=system.disk0 system.disk2 -max_backoff_delay=20000 -min_backoff_delay=8 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system config=system.iobus.port[30] @@ -640,9 +793,9 @@ VendorID=32902 [system.tsunami.io] type=TsunamiIO -frequency=1953125 +frequency=976562500 pio_addr=8804615847936 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -653,7 +806,7 @@ pio=system.iobus.port[23] [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -671,7 +824,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out index 1034abd0e..b51eb234e 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out @@ -11,12 +11,12 @@ zero=false [system] type=LinuxAlphaSystem -boot_cpu_frequency=1 +boot_cpu_frequency=500 physmem=system.physmem mem_mode=timing -kernel=/Users/ali/work/system/binaries/vmlinux -console=/Users/ali/work/system/binaries/console -pal=/Users/ali/work/system/binaries/ts_osfpal +kernel=/dist/m5/system/binaries/vmlinux +console=/dist/m5/system/binaries/console +pal=/dist/m5/system/binaries/ts_osfpal boot_osflags=root=/dev/hda1 console=ttyS0 readfile=tests/halt.sh symbolfile= @@ -27,7 +27,7 @@ system_rev=1024 [system.membus] type=Bus bus_id=1 -clock=2 +clock=1000 width=64 responder_set=false block_size=64 @@ -44,7 +44,7 @@ intrctrl=system.intrctrl [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 ret_bad_addr=true update_data=false @@ -56,21 +56,58 @@ ret_data64=18446744073709551615 platform=system.tsunami system=system +[system.l2c] +type=BaseCache +size=4194304 +assoc=8 +block_size=64 +latency=10000 +mshrs=92 +tgts_per_mshr=16 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.bridge] type=Bridge req_size_a=16 req_size_b=16 resp_size_a=16 resp_size_b=16 -delay=0 -nack_delay=0 +delay=50000 +nack_delay=4000 write_ack=false fix_partial_write_a=false fix_partial_write_b=true [system.disk0.image.child] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk0.image] @@ -84,11 +121,11 @@ read_only=false type=IdeDisk image=system.disk0.image driveID=master -delay=2000 +delay=1000000 [system.disk2.image.child] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.disk2.image] @@ -102,11 +139,11 @@ read_only=false type=IdeDisk image=system.disk2.image driveID=master -delay=2000 +delay=1000000 [system.simple_disk.disk] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.simple_disk] @@ -117,7 +154,7 @@ disk=system.simple_disk.disk [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -132,7 +169,7 @@ system=system [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -147,7 +184,7 @@ system=system [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -162,7 +199,7 @@ system=system [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -177,7 +214,7 @@ system=system [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -192,7 +229,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -200,8 +237,8 @@ tsunami=system.tsunami [system.tsunami.io] type=TsunamiIO pio_addr=8804615847936 -pio_latency=2 -frequency=1953125 +pio_latency=1000 +frequency=976562500 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -247,7 +284,7 @@ profile=0 do_quiesce=true do_checkpoint_insts=true do_statistics_insts=true -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -263,12 +300,12 @@ pio_addr=8804682956800 system=system cpu=system.cpu platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -283,7 +320,7 @@ system=system [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -298,7 +335,7 @@ system=system [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -306,7 +343,7 @@ tsunami=system.tsunami [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -321,7 +358,7 @@ system=system [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -336,7 +373,7 @@ system=system [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -351,7 +388,7 @@ system=system [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -366,7 +403,7 @@ system=system [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -381,7 +418,7 @@ system=system [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -396,7 +433,7 @@ system=system [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -411,7 +448,7 @@ system=system [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -426,7 +463,7 @@ system=system [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -444,7 +481,7 @@ devicename=FrameBuffer pio_addr=8804615848912 system=system platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.ethernet.configdata] type=PciConfigData @@ -485,14 +522,14 @@ BAR5Size=0 type=NSGigE system=system platform=system.tsunami -min_backoff_delay=8 -max_backoff_delay=20000 +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ethernet.configdata pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 clock=0 dma_desc_free=false dma_data_free=false @@ -501,9 +538,9 @@ dma_write_delay=0 dma_read_factor=0 dma_write_factor=0 dma_no_allocate=true -intr_delay=20000 -rx_delay=2000 -tx_delay=2000 +intr_delay=10000000 +rx_delay=1000000 +tx_delay=1000000 rx_fifo_size=524288 tx_fifo_size=524288 rx_filter=true @@ -520,7 +557,7 @@ device=system.tsunami.ethernet [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 ret_bad_addr=false update_data=false @@ -535,7 +572,7 @@ system=system [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -543,7 +580,7 @@ system=system [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -558,7 +595,7 @@ system=system [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -609,21 +646,128 @@ BAR5Size=0 type=IdeController system=system platform=system.tsunami -min_backoff_delay=8 -max_backoff_delay=20000 +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ide.configdata pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 disks=system.disk0 system.disk2 +[system.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false +block_size=64 + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +ret_bad_addr=true +update_data=false +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +platform=system.tsunami +system=system + [system.iobus] type=Bus bus_id=0 -clock=2 +clock=1000 width=64 responder_set=true block_size=64 +[system.cpu.icache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu.icache] +type=BaseCache +size=32768 +assoc=1 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu.icache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + +[system.cpu.dcache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu.dcache] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu.dcache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt index 466fb2d27..d9f42b16b 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt @@ -1,83 +1,275 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 233672 # Simulator instruction rate (inst/s) -host_seconds 257.14 # Real time elapsed on the host -host_tick_rate 15108417 # Simulator tick rate (ticks/s) -sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 60085488 # Number of instructions simulated -sim_seconds 1.942464 # Number of seconds simulated -sim_ticks 3884928812 # Number of ticks simulated -system.cpu.dtb.accesses 1020784 # DTB accesses +host_inst_rate 212380 # Simulator instruction rate (inst/s) +host_mem_usage 201984 # Number of bytes of host memory used +host_seconds 282.69 # Real time elapsed on the host +host_tick_rate 6746442466 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 60037406 # Number of instructions simulated +sim_seconds 1.907146 # Number of seconds simulated +sim_ticks 1907146437000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 9726331 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 13065.219101 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12065.192690 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 7984648 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 22755470000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.179069 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1741683 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 21013741000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.179069 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1741683 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable 6727 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.cpu.dcache.ReadResp_mshr_uncacheable_latency 824099000 # number of ReadResp MSHR uncacheable cycles +system.cpu.dcache.WriteReq_accesses 6350552 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 12768.106941 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11768.067509 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6046235 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 3885552000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.047920 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 304317 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 3581223000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.047920 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 304317 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable 9438 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.cpu.dcache.WriteResp_mshr_uncacheable_latency 1154484000 # number of WriteResp MSHR uncacheable cycles +system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 6.857760 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 16076883 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 13021.027370 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12020.999022 # average overall mshr miss latency +system.cpu.dcache.demand_hits 14030883 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 26641022000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.127263 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2046000 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 24594964000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.127263 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2046000 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 16076883 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 13021.027370 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12020.999022 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 14030883 # number of overall hits +system.cpu.dcache.overall_miss_latency 26641022000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.127263 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2046000 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 24594964000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.127263 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2046000 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 16165 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu.dcache.protocol.read_invalid 1741683 # read misses to invalid blocks +system.cpu.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu.dcache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu.dcache.protocol.snoop_read_exclusive 9 # read snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_read_modified 15 # read snoops on modified blocks +system.cpu.dcache.protocol.snoop_read_owned 4 # read snoops on owned blocks +system.cpu.dcache.protocol.snoop_read_shared 92 # read snoops on shared blocks +system.cpu.dcache.protocol.snoop_readex_exclusive 0 # readEx snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu.dcache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu.dcache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks +system.cpu.dcache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu.dcache.protocol.snoop_upgrade_shared 0 # upgradee snoops on shared blocks +system.cpu.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu.dcache.protocol.write_invalid 304305 # write misses to invalid blocks +system.cpu.dcache.protocol.write_owned 8 # write misses to owned blocks +system.cpu.dcache.protocol.write_shared 4 # write misses to shared blocks +system.cpu.dcache.replacements 2045476 # number of replacements +system.cpu.dcache.sampled_refs 2045988 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 511.987904 # Cycle average of tags in use +system.cpu.dcache.total_refs 14030895 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 57945000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 429989 # number of writebacks +system.cpu.dtb.accesses 1020787 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 16070353 # DTB hits -system.cpu.dtb.misses 11466 # DTB misses -system.cpu.dtb.read_accesses 728853 # DTB read accesses +system.cpu.dtb.hits 16057425 # DTB hits +system.cpu.dtb.misses 11471 # DTB misses +system.cpu.dtb.read_accesses 728856 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 9714571 # DTB read hits -system.cpu.dtb.read_misses 10324 # DTB read misses +system.cpu.dtb.read_hits 9706740 # DTB read hits +system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.write_accesses 291931 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_hits 6355782 # DTB write hits +system.cpu.dtb.write_hits 6350685 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses -system.cpu.idle_fraction 0.921526 # Percentage of idle cycles -system.cpu.itb.accesses 4985698 # ITB accesses +system.cpu.icache.ReadReq_accesses 60037407 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 12029.456206 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11028.713640 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 59110217 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 11153591500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.015444 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 927190 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 10225713000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.015444 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 927190 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.cpu.icache.avg_refs 63.763003 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 60037407 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 12029.456206 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11028.713640 # average overall mshr miss latency +system.cpu.icache.demand_hits 59110217 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 11153591500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.015444 # miss rate for demand accesses +system.cpu.icache.demand_misses 927190 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 10225713000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.015444 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 927190 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 60037407 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 12029.456206 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11028.713640 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 59110217 # number of overall hits +system.cpu.icache.overall_miss_latency 11153591500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.015444 # miss rate for overall accesses +system.cpu.icache.overall_misses 927190 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 10225713000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.015444 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 927190 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu.icache.protocol.read_invalid 927190 # read misses to invalid blocks +system.cpu.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu.icache.protocol.snoop_read_exclusive 644 # read snoops on exclusive blocks +system.cpu.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks +system.cpu.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks +system.cpu.icache.protocol.snoop_read_shared 1040 # read snoops on shared blocks +system.cpu.icache.protocol.snoop_readex_exclusive 146 # readEx snoops on exclusive blocks +system.cpu.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu.icache.protocol.snoop_readex_shared 2 # readEx snoops on shared blocks +system.cpu.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu.icache.protocol.snoop_upgrade_shared 12 # upgradee snoops on shared blocks +system.cpu.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu.icache.protocol.write_invalid 0 # write misses to invalid blocks +system.cpu.icache.protocol.write_owned 0 # write misses to owned blocks +system.cpu.icache.protocol.write_shared 0 # write misses to shared blocks +system.cpu.icache.replacements 926519 # number of replacements +system.cpu.icache.sampled_refs 927030 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 508.761542 # Cycle average of tags in use +system.cpu.icache.total_refs 59110217 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 34634685000 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0.940784 # Percentage of idle cycles +system.cpu.itb.accesses 4977586 # ITB accesses system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 4980688 # ITB hits -system.cpu.itb.misses 5010 # ITB misses -system.cpu.kern.callpal 193483 # number of callpals executed +system.cpu.itb.hits 4972580 # ITB hits +system.cpu.itb.misses 5006 # ITB misses +system.cpu.kern.callpal 192752 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_swpctx 4144 2.14% 2.14% # number of callpals executed -system.cpu.kern.callpal_tbi 54 0.03% 2.17% # number of callpals executed -system.cpu.kern.callpal_wrent 7 0.00% 2.18% # number of callpals executed -system.cpu.kern.callpal_swpipl 176511 91.23% 93.40% # number of callpals executed -system.cpu.kern.callpal_rdps 6861 3.55% 96.95% # number of callpals executed -system.cpu.kern.callpal_wrkgp 1 0.00% 96.95% # number of callpals executed -system.cpu.kern.callpal_wrusp 7 0.00% 96.95% # number of callpals executed -system.cpu.kern.callpal_rdusp 9 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal_whami 2 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal_rti 5187 2.68% 99.64% # number of callpals executed +system.cpu.kern.callpal_swpctx 4176 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed +system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed +system.cpu.kern.callpal_swpipl 175824 91.22% 93.42% # number of callpals executed +system.cpu.kern.callpal_rdps 6824 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal_wrkgp 1 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal_wrusp 7 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal_rdusp 9 0.00% 96.97% # number of callpals executed +system.cpu.kern.callpal_whami 2 0.00% 96.97% # number of callpals executed +system.cpu.kern.callpal_rti 5148 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 212605 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6153 # number of quiesce instructions executed -system.cpu.kern.ipl_count 183792 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 75069 40.84% 40.84% # number of times we switched to this ipl -system.cpu.kern.ipl_count_21 131 0.07% 40.92% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 1962 1.07% 41.98% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 106630 58.02% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 149497 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 73702 49.30% 49.30% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_21 131 0.09% 49.39% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 1962 1.31% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 73702 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 3884927028 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 3757863794 96.73% 96.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 112456 0.00% 96.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 918216 0.02% 96.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 126032562 3.24% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used 0.813403 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_0 0.981790 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.hwrei 211836 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6181 # number of quiesce instructions executed +system.cpu.kern.ipl_count 183027 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 74862 40.90% 40.90% # number of times we switched to this ipl +system.cpu.kern.ipl_count_21 131 0.07% 40.97% # number of times we switched to this ipl +system.cpu.kern.ipl_count_22 1923 1.05% 42.02% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 106111 57.98% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 149044 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 73495 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_22 1923 1.29% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_31 73495 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 1907145727000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1851261210000 97.07% 97.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 73754500 0.00% 97.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 531976500 0.03% 97.10% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 55278786000 2.90% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used_0 0.981740 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.691194 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1895 -system.cpu.kern.mode_good_user 1742 -system.cpu.kern.mode_good_idle 153 -system.cpu.kern.mode_switch_kernel 5935 # number of protection mode switches -system.cpu.kern.mode_switch_user 1742 # number of protection mode switches -system.cpu.kern.mode_switch_idle 2062 # number of protection mode switches -system.cpu.kern.mode_switch_good 0.389157 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.319292 # fraction of useful protection mode switches +system.cpu.kern.ipl_used_31 0.692624 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1910 +system.cpu.kern.mode_good_user 1740 +system.cpu.kern.mode_good_idle 170 +system.cpu.kern.mode_switch_kernel 5894 # number of protection mode switches +system.cpu.kern.mode_switch_user 1740 # number of protection mode switches +system.cpu.kern.mode_switch_idle 2096 # number of protection mode switches +system.cpu.kern.mode_switch_good 1.405165 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.324058 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_idle 0.074200 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 112890486 2.91% 2.91% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 15209884 0.39% 3.30% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 3756826650 96.70% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4145 # number of times the context was actually changed +system.cpu.kern.mode_switch_good_idle 0.081107 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks_kernel 42657550000 2.24% 2.24% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 4648649000 0.24% 2.48% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1859839526000 97.52% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4177 # number of times the context was actually changed system.cpu.kern.syscall 326 # number of syscalls executed system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed @@ -109,10 +301,10 @@ system.cpu.kern.syscall_98 2 0.61% 97.55% # nu system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed -system.cpu.not_idle_fraction 0.078474 # Percentage of non-idle cycles -system.cpu.numCycles 3884928812 # number of cpu cycles simulated -system.cpu.num_insts 60085488 # Number of instructions executed -system.cpu.num_refs 16318244 # Number of memory references +system.cpu.not_idle_fraction 0.059216 # Percentage of non-idle cycles +system.cpu.numCycles 1907146437000 # number of cpu cycles simulated +system.cpu.num_insts 60037406 # Number of instructions executed +system.cpu.num_refs 16305563 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -125,6 +317,86 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.l2c.ReadExReq_accesses 304305 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 13000.153945 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 11000.153945 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits 187380 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 1520043000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate 0.384236 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 116925 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 1286193000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate 0.384236 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 116925 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2668854 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 13000.065889 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 11000.065889 # average ReadReq mshr miss latency +system.l2c.ReadReq_hits 1727874 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 12232802000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.352578 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 940980 # number of ReadReq misses +system.l2c.ReadReq_mshr_miss_latency 10350842000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.352578 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 940980 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable 6727 # number of ReadReq MSHR uncacheable +system.l2c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.l2c.ReadResp_mshr_uncacheable_latency 750102000 # number of ReadResp MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable 9438 # number of WriteReq MSHR uncacheable +system.l2c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.l2c.WriteResp_mshr_uncacheable_latency 1050666000 # number of WriteResp MSHR uncacheable cycles +system.l2c.Writeback_accesses 429989 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 429989 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked +system.l2c.avg_refs 2.216875 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 2668854 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 13000.065889 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 11000.065889 # average overall mshr miss latency +system.l2c.demand_hits 1727874 # number of demand (read+write) hits +system.l2c.demand_miss_latency 12232802000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.352578 # miss rate for demand accesses +system.l2c.demand_misses 940980 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 10350842000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.352578 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 940980 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 3098843 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 13000.065889 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 11000.065889 # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.l2c.overall_hits 2157863 # number of overall hits +system.l2c.overall_miss_latency 12232802000 # number of overall miss cycles +system.l2c.overall_miss_rate 0.303655 # miss rate for overall accesses +system.l2c.overall_misses 940980 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 10350842000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.303655 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 940980 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 16165 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 992369 # number of replacements +system.l2c.sampled_refs 1057905 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 65468.856552 # Cycle average of tags in use +system.l2c.total_refs 2345243 # Total number of references to valid blocks. +system.l2c.warmup_cycle 3045832000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 74072 # number of writebacks system.tsunami.ethernet.coalescedRxDesc # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr index 969291745..072cb6c8c 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr @@ -1,5 +1,3 @@ -Warning: rounding error > tolerance - 0.002000 rounded to 0 Listening for system connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout index 427d90ea3..b8196fe27 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 30 2007 13:38:38 -M5 started Mon Apr 30 13:54:39 2007 -M5 executing on zeep -command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing -Global frequency set at 2000000000 ticks per second - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Exiting @ tick 3883112324 because m5_exit instruction encountered +M5 compiled May 15 2007 19:06:05 +M5 started Tue May 15 19:07:53 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 1907146437000 because m5_exit instruction encountered diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini index 0c1dbb0ba..0431dd3db 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini @@ -39,6 +39,7 @@ system=system [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out index 5e988f3f9..73c363bc4 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=EioProcess diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt index bc0a96087..7380e419f 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 689098 # Simulator instruction rate (inst/s) -host_mem_usage 147724 # Number of bytes of host memory used -host_seconds 0.73 # Real time elapsed on the host -host_tick_rate 344128671 # Simulator tick rate (ticks/s) +host_inst_rate 819297 # Simulator instruction rate (inst/s) +host_mem_usage 147636 # Number of bytes of host memory used +host_seconds 0.61 # Real time elapsed on the host +host_tick_rate 409362131 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated sim_seconds 0.000250 # Number of seconds simulated diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout index 47ee09274..c8bcb5723 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout @@ -7,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:12 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:43 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 249999500 because a thread reached the max instruction count diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini index eef4c0a1a..c05a66f9d 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -162,6 +160,7 @@ system=system [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out index e897b733f..570ef7de8 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=EioProcess @@ -52,13 +53,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -89,14 +91,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -127,14 +128,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -165,5 +165,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt index a6caa5891..be87d3617 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 518674 # Simulator instruction rate (inst/s) -host_mem_usage 153108 # Number of bytes of host memory used -host_seconds 0.96 # Real time elapsed on the host -host_tick_rate 355827019 # Simulator tick rate (ticks/s) +host_inst_rate 392036 # Simulator instruction rate (inst/s) +host_mem_usage 153128 # Number of bytes of host memory used +host_seconds 1.28 # Real time elapsed on the host +host_tick_rate 542334315 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated -sim_seconds 0.000343 # Number of seconds simulated -sim_ticks 343161000 # Number of ticks simulated +sim_seconds 0.000692 # Number of seconds simulated +sim_ticks 691915000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3793.650794 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2793.650794 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 124120 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1195000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 4410000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002531 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 315 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 880000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 4095000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002531 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 315 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3600.719424 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2600.719424 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 56201 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 500500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 1946000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 139 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 361500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1807000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 180775 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3734.581498 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2734.581498 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.demand_hits 180321 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1695500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 6356000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002511 # miss rate for demand accesses system.cpu.dcache.demand_misses 454 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1241500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5902000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002511 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 454 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3734.581498 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2734.581498 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 180321 # number of overall hits -system.cpu.dcache.overall_miss_latency 1695500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 6356000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002511 # miss rate for overall accesses system.cpu.dcache.overall_misses 454 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1241500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5902000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002511 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 454 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 291.533202 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 290.922203 # Cycle average of tags in use system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 500000 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3739.454094 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2739.454094 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 499597 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1507000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 5642000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000806 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 403 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 1104000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 5239000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000806 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 403 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 500000 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3739.454094 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2739.454094 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 14000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.icache.demand_hits 499597 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1507000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 5642000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000806 # miss rate for demand accesses system.cpu.icache.demand_misses 403 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1104000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 5239000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000806 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 403 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 500000 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3739.454094 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2739.454094 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 14000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.icache.overall_hits 499597 # number of overall hits -system.cpu.icache.overall_miss_latency 1507000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 5642000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses system.cpu.icache.overall_misses 403 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1104000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 5239000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000806 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 403 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 268.106513 # Cycle average of tags in use +system.cpu.icache.tagsinuse 267.665433 # Cycle average of tags in use system.cpu.icache.total_refs 499597 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 857 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2736.872812 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1735.872812 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 2345500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 11141000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 857 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1487643 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 9427000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 857 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked @@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 857 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2736.872812 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1735.872812 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2345500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 11141000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 857 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1487643 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 9427000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 857 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2736.872812 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1735.872812 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2345500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 11141000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 857 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1487643 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 9427000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 857 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 857 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 559.642213 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 558.588875 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 343161000 # number of cpu cycles simulated +system.cpu.numCycles 691915000 # number of cpu cycles simulated system.cpu.num_insts 500000 # Number of instructions executed system.cpu.num_refs 182203 # Number of memory references system.cpu.workload.PROG:num_syscalls 18 # Number of system calls diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout index 8126fb0fb..83f216de6 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout @@ -7,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:14 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:44 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 343161000 because a thread reached the max instruction count +Exiting @ tick 691915000 because a thread reached the max instruction count diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini index 363cb64d4..bf66a6947 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini @@ -34,8 +34,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=12 @@ -95,8 +94,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=12 @@ -156,8 +154,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=12 @@ -217,8 +214,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=12 @@ -278,8 +274,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=12 @@ -339,8 +334,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=12 @@ -400,8 +394,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=12 @@ -461,8 +454,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=12 @@ -514,8 +506,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=10 +latency=10000 lifo=false max_miss_count=0 mshrs=92 @@ -547,6 +538,7 @@ mem_side=system.membus.port[0] [system.membus] type=Bus +block_size=64 bus_id=0 clock=2 responder_set=false @@ -563,6 +555,7 @@ port=system.membus.port[1] [system.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=2 responder_set=false diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out index b3f4ec871..53f718c0d 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out @@ -20,13 +20,14 @@ bus_id=0 clock=2 width=16 responder_set=false +block_size=64 [system.l2c] type=BaseCache size=65536 assoc=8 block_size=64 -latency=10 +latency=10000 mshrs=92 tgts_per_mshr=16 write_buffers=8 @@ -57,7 +58,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu6] type=MemTest @@ -82,7 +82,7 @@ type=BaseCache size=32768 assoc=4 block_size=64 -latency=1 +latency=1000 mshrs=12 tgts_per_mshr=8 write_buffers=8 @@ -113,7 +113,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu4] type=MemTest @@ -138,7 +137,7 @@ type=BaseCache size=32768 assoc=4 block_size=64 -latency=1 +latency=1000 mshrs=12 tgts_per_mshr=8 write_buffers=8 @@ -169,7 +168,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu5] type=MemTest @@ -194,7 +192,7 @@ type=BaseCache size=32768 assoc=4 block_size=64 -latency=1 +latency=1000 mshrs=12 tgts_per_mshr=8 write_buffers=8 @@ -225,7 +223,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu2] type=MemTest @@ -250,7 +247,7 @@ type=BaseCache size=32768 assoc=4 block_size=64 -latency=1 +latency=1000 mshrs=12 tgts_per_mshr=8 write_buffers=8 @@ -281,7 +278,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu3] type=MemTest @@ -306,7 +302,7 @@ type=BaseCache size=32768 assoc=4 block_size=64 -latency=1 +latency=1000 mshrs=12 tgts_per_mshr=8 write_buffers=8 @@ -337,7 +333,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu0] type=MemTest @@ -362,7 +357,7 @@ type=BaseCache size=32768 assoc=4 block_size=64 -latency=1 +latency=1000 mshrs=12 tgts_per_mshr=8 write_buffers=8 @@ -393,7 +388,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu1] type=MemTest @@ -418,7 +412,7 @@ type=BaseCache size=32768 assoc=4 block_size=64 -latency=1 +latency=1000 mshrs=12 tgts_per_mshr=8 write_buffers=8 @@ -449,7 +443,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.funcmem] type=PhysicalMemory @@ -481,7 +474,7 @@ type=BaseCache size=32768 assoc=4 block_size=64 -latency=1 +latency=1000 mshrs=12 tgts_per_mshr=8 write_buffers=8 @@ -512,7 +505,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.toL2Bus] type=Bus @@ -520,4 +512,5 @@ bus_id=0 clock=2 width=16 responder_set=false +block_size=64 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt index 285ab3702..2617dd49e 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt @@ -1,73 +1,73 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 303680 # Number of bytes of host memory used -host_seconds 32.50 # Real time elapsed on the host -host_tick_rate 177110 # Simulator tick rate (ticks/s) +host_mem_usage 1265676 # Number of bytes of host memory used +host_seconds 390.60 # Real time elapsed on the host +host_tick_rate 215953 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_seconds 0.000006 # Number of seconds simulated -sim_ticks 5755736 # Number of ticks simulated -system.cpu0.l1c.ReadReq_accesses 45048 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_avg_miss_latency 959.688548 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 884.132516 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_hits 7543 # number of ReadReq hits -system.cpu0.l1c.ReadReq_miss_latency 35993119 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_rate 0.832556 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_misses 37505 # number of ReadReq misses -system.cpu0.l1c.ReadReq_mshr_miss_latency 33159390 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate 0.832556 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_misses 37505 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable 9815 # number of ReadReq MSHR uncacheable +sim_seconds 0.000084 # Number of seconds simulated +sim_ticks 84350509 # Number of ticks simulated +system.cpu0.l1c.ReadReq_accesses 44421 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_avg_miss_latency 14010.391786 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 12986.475734 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_hits 7291 # number of ReadReq hits +system.cpu0.l1c.ReadReq_miss_latency 520205847 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_rate 0.835866 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_misses 37130 # number of ReadReq misses +system.cpu0.l1c.ReadReq_mshr_miss_latency 482187844 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate 0.835866 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_misses 37130 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable 9916 # number of ReadReq MSHR uncacheable system.cpu0.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu0.l1c.ReadResp_mshr_uncacheable_latency 17521633 # number of ReadResp MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_accesses 24308 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_avg_miss_latency 862.246942 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 778.821396 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_hits 1173 # number of WriteReq hits -system.cpu0.l1c.WriteReq_miss_latency 19948083 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_rate 0.951744 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_misses 23135 # number of WriteReq misses -system.cpu0.l1c.WriteReq_mshr_miss_latency 18018033 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_rate 0.951744 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_misses 23135 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_uncacheable 5428 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.ReadResp_mshr_uncacheable_latency 255520881 # number of ReadResp MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_accesses 23898 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_avg_miss_latency 12904.605270 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 11399.917485 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_hits 1090 # number of WriteReq hits +system.cpu0.l1c.WriteReq_miss_latency 294328237 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_rate 0.954389 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_misses 22808 # number of WriteReq misses +system.cpu0.l1c.WriteReq_mshr_miss_latency 260009318 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_rate 0.954389 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_misses 22808 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_uncacheable 5184 # number of WriteReq MSHR uncacheable system.cpu0.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu0.l1c.WriteResp_mshr_uncacheable_latency 10755873 # number of WriteResp MSHR uncacheable cycles -system.cpu0.l1c.avg_blocked_cycles_no_mshrs 81.366905 # average number of cycles each access was blocked +system.cpu0.l1c.WriteResp_mshr_uncacheable_latency 154702333 # number of WriteResp MSHR uncacheable cycles +system.cpu0.l1c.avg_blocked_cycles_no_mshrs 1194.948852 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu0.l1c.avg_refs 0.417208 # Average number of references to valid blocks. -system.cpu0.l1c.blocked_no_mshrs 69811 # number of cycles access was blocked +system.cpu0.l1c.avg_refs 0.407238 # Average number of references to valid blocks. +system.cpu0.l1c.blocked_no_mshrs 69093 # number of cycles access was blocked system.cpu0.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked_cycles_no_mshrs 5680305 # number of cycles access was blocked +system.cpu0.l1c.blocked_cycles_no_mshrs 82562601 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.demand_accesses 69356 # number of demand (read+write) accesses -system.cpu0.l1c.demand_avg_miss_latency 922.513226 # average overall miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency 843.954865 # average overall mshr miss latency -system.cpu0.l1c.demand_hits 8716 # number of demand (read+write) hits -system.cpu0.l1c.demand_miss_latency 55941202 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_rate 0.874330 # miss rate for demand accesses -system.cpu0.l1c.demand_misses 60640 # number of demand (read+write) misses +system.cpu0.l1c.demand_accesses 68319 # number of demand (read+write) accesses +system.cpu0.l1c.demand_avg_miss_latency 13589.610664 # average overall miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency 12382.748206 # average overall mshr miss latency +system.cpu0.l1c.demand_hits 8381 # number of demand (read+write) hits +system.cpu0.l1c.demand_miss_latency 814534084 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_rate 0.877325 # miss rate for demand accesses +system.cpu0.l1c.demand_misses 59938 # number of demand (read+write) misses system.cpu0.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.l1c.demand_mshr_miss_latency 51177423 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_rate 0.874330 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_misses 60640 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_miss_latency 742197162 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_rate 0.877325 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_misses 59938 # number of demand (read+write) MSHR misses system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l1c.overall_accesses 69356 # number of overall (read+write) accesses -system.cpu0.l1c.overall_avg_miss_latency 922.513226 # average overall miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency 843.954865 # average overall mshr miss latency +system.cpu0.l1c.overall_accesses 68319 # number of overall (read+write) accesses +system.cpu0.l1c.overall_avg_miss_latency 13589.610664 # average overall miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency 12382.748206 # average overall mshr miss latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu0.l1c.overall_hits 8716 # number of overall hits -system.cpu0.l1c.overall_miss_latency 55941202 # number of overall miss cycles -system.cpu0.l1c.overall_miss_rate 0.874330 # miss rate for overall accesses -system.cpu0.l1c.overall_misses 60640 # number of overall misses +system.cpu0.l1c.overall_hits 8381 # number of overall hits +system.cpu0.l1c.overall_miss_latency 814534084 # number of overall miss cycles +system.cpu0.l1c.overall_miss_rate 0.877325 # miss rate for overall accesses +system.cpu0.l1c.overall_misses 59938 # number of overall misses system.cpu0.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.l1c.overall_mshr_miss_latency 51177423 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_rate 0.874330 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_misses 60640 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_miss_latency 742197162 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_rate 0.877325 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_misses 59938 # number of overall MSHR misses system.cpu0.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_misses 15243 # number of overall MSHR uncacheable misses +system.cpu0.l1c.overall_mshr_uncacheable_misses 15100 # number of overall MSHR uncacheable misses system.cpu0.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu0.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu0.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -78,103 +78,103 @@ system.cpu0.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu0.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu0.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu0.l1c.protocol.read_invalid 109554 # read misses to invalid blocks +system.cpu0.l1c.protocol.read_invalid 1761660 # read misses to invalid blocks system.cpu0.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu0.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu0.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu0.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu0.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu0.l1c.protocol.snoop_read_exclusive 2807 # read snoops on exclusive blocks -system.cpu0.l1c.protocol.snoop_read_modified 12380 # read snoops on modified blocks -system.cpu0.l1c.protocol.snoop_read_owned 7157 # read snoops on owned blocks -system.cpu0.l1c.protocol.snoop_read_shared 22767 # read snoops on shared blocks -system.cpu0.l1c.protocol.snoop_readex_exclusive 1535 # readEx snoops on exclusive blocks -system.cpu0.l1c.protocol.snoop_readex_modified 6851 # readEx snoops on modified blocks -system.cpu0.l1c.protocol.snoop_readex_owned 3877 # readEx snoops on owned blocks -system.cpu0.l1c.protocol.snoop_readex_shared 12465 # readEx snoops on shared blocks -system.cpu0.l1c.protocol.snoop_upgrade_owned 887 # upgrade snoops on owned blocks -system.cpu0.l1c.protocol.snoop_upgrade_shared 2994 # upgradee snoops on shared blocks +system.cpu0.l1c.protocol.snoop_read_exclusive 2836 # read snoops on exclusive blocks +system.cpu0.l1c.protocol.snoop_read_modified 12378 # read snoops on modified blocks +system.cpu0.l1c.protocol.snoop_read_owned 7300 # read snoops on owned blocks +system.cpu0.l1c.protocol.snoop_read_shared 1749577 # read snoops on shared blocks +system.cpu0.l1c.protocol.snoop_readex_exclusive 1616 # readEx snoops on exclusive blocks +system.cpu0.l1c.protocol.snoop_readex_modified 6692 # readEx snoops on modified blocks +system.cpu0.l1c.protocol.snoop_readex_owned 4009 # readEx snoops on owned blocks +system.cpu0.l1c.protocol.snoop_readex_shared 12550 # readEx snoops on shared blocks +system.cpu0.l1c.protocol.snoop_upgrade_owned 790 # upgrade snoops on owned blocks +system.cpu0.l1c.protocol.snoop_upgrade_shared 3004 # upgradee snoops on shared blocks system.cpu0.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks system.cpu0.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks system.cpu0.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks system.cpu0.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks system.cpu0.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks system.cpu0.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu0.l1c.protocol.write_invalid 60706 # write misses to invalid blocks -system.cpu0.l1c.protocol.write_owned 1361 # write misses to owned blocks -system.cpu0.l1c.protocol.write_shared 4416 # write misses to shared blocks -system.cpu0.l1c.replacements 27529 # number of replacements -system.cpu0.l1c.sampled_refs 27883 # Sample count of references to valid blocks. +system.cpu0.l1c.protocol.write_invalid 940728 # write misses to invalid blocks +system.cpu0.l1c.protocol.write_owned 1344 # write misses to owned blocks +system.cpu0.l1c.protocol.write_shared 4484 # write misses to shared blocks +system.cpu0.l1c.replacements 27160 # number of replacements +system.cpu0.l1c.sampled_refs 27495 # Sample count of references to valid blocks. system.cpu0.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.l1c.tagsinuse 342.460043 # Cycle average of tags in use -system.cpu0.l1c.total_refs 11633 # Total number of references to valid blocks. +system.cpu0.l1c.tagsinuse 342.709273 # Cycle average of tags in use +system.cpu0.l1c.total_refs 11197 # Total number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.writebacks 10915 # number of writebacks +system.cpu0.l1c.writebacks 10716 # number of writebacks system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99586 # number of read accesses completed -system.cpu0.num_writes 53803 # number of write accesses completed -system.cpu1.l1c.ReadReq_accesses 44416 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_avg_miss_latency 969.343786 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 893.327484 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_hits 7486 # number of ReadReq hits -system.cpu1.l1c.ReadReq_miss_latency 35797866 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_rate 0.831457 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_misses 36930 # number of ReadReq misses -system.cpu1.l1c.ReadReq_mshr_miss_latency 32990584 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate 0.831457 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_misses 36930 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable 9894 # number of ReadReq MSHR uncacheable +system.cpu0.num_reads 98012 # number of read accesses completed +system.cpu0.num_writes 53207 # number of write accesses completed +system.cpu1.l1c.ReadReq_accesses 44893 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_avg_miss_latency 13909.754864 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 12900.185775 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_hits 7579 # number of ReadReq hits +system.cpu1.l1c.ReadReq_miss_latency 519028593 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_rate 0.831176 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_misses 37314 # number of ReadReq misses +system.cpu1.l1c.ReadReq_mshr_miss_latency 481357532 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate 0.831176 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_misses 37314 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable 9811 # number of ReadReq MSHR uncacheable system.cpu1.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu1.l1c.ReadResp_mshr_uncacheable_latency 17663360 # number of ReadResp MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_accesses 24084 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_avg_miss_latency 871.179293 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 786.258930 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_hits 1155 # number of WriteReq hits -system.cpu1.l1c.WriteReq_miss_latency 19975270 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_rate 0.952043 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_misses 22929 # number of WriteReq misses -system.cpu1.l1c.WriteReq_mshr_miss_latency 18028131 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_rate 0.952043 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_misses 22929 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_uncacheable 5271 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.ReadResp_mshr_uncacheable_latency 251708747 # number of ReadResp MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_accesses 24614 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_avg_miss_latency 12788.679753 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 11344.205121 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_hits 1257 # number of WriteReq hits +system.cpu1.l1c.WriteReq_miss_latency 298705193 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_rate 0.948932 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_misses 23357 # number of WriteReq misses +system.cpu1.l1c.WriteReq_mshr_miss_latency 264966599 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_rate 0.948932 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_misses 23357 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_uncacheable 5453 # number of WriteReq MSHR uncacheable system.cpu1.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu1.l1c.WriteResp_mshr_uncacheable_latency 10523322 # number of WriteResp MSHR uncacheable cycles -system.cpu1.l1c.avg_blocked_cycles_no_mshrs 82.260179 # average number of cycles each access was blocked +system.cpu1.l1c.WriteResp_mshr_uncacheable_latency 163813954 # number of WriteResp MSHR uncacheable cycles +system.cpu1.l1c.avg_blocked_cycles_no_mshrs 1183.149435 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu1.l1c.avg_refs 0.414867 # Average number of references to valid blocks. -system.cpu1.l1c.blocked_no_mshrs 68941 # number of cycles access was blocked +system.cpu1.l1c.avg_refs 0.414323 # Average number of references to valid blocks. +system.cpu1.l1c.blocked_no_mshrs 69763 # number of cycles access was blocked system.cpu1.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked_cycles_no_mshrs 5671099 # number of cycles access was blocked +system.cpu1.l1c.blocked_cycles_no_mshrs 82540054 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.demand_accesses 68500 # number of demand (read+write) accesses -system.cpu1.l1c.demand_avg_miss_latency 931.741860 # average overall miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency 852.314857 # average overall mshr miss latency -system.cpu1.l1c.demand_hits 8641 # number of demand (read+write) hits -system.cpu1.l1c.demand_miss_latency 55773136 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_rate 0.873854 # miss rate for demand accesses -system.cpu1.l1c.demand_misses 59859 # number of demand (read+write) misses +system.cpu1.l1c.demand_accesses 69507 # number of demand (read+write) accesses +system.cpu1.l1c.demand_avg_miss_latency 13478.165615 # average overall miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency 12301.167461 # average overall mshr miss latency +system.cpu1.l1c.demand_hits 8836 # number of demand (read+write) hits +system.cpu1.l1c.demand_miss_latency 817733786 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_rate 0.872876 # miss rate for demand accesses +system.cpu1.l1c.demand_misses 60671 # number of demand (read+write) misses system.cpu1.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.l1c.demand_mshr_miss_latency 51018715 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_rate 0.873854 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_misses 59859 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_miss_latency 746324131 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_rate 0.872876 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_misses 60671 # number of demand (read+write) MSHR misses system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l1c.overall_accesses 68500 # number of overall (read+write) accesses -system.cpu1.l1c.overall_avg_miss_latency 931.741860 # average overall miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency 852.314857 # average overall mshr miss latency +system.cpu1.l1c.overall_accesses 69507 # number of overall (read+write) accesses +system.cpu1.l1c.overall_avg_miss_latency 13478.165615 # average overall miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency 12301.167461 # average overall mshr miss latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu1.l1c.overall_hits 8641 # number of overall hits -system.cpu1.l1c.overall_miss_latency 55773136 # number of overall miss cycles -system.cpu1.l1c.overall_miss_rate 0.873854 # miss rate for overall accesses -system.cpu1.l1c.overall_misses 59859 # number of overall misses +system.cpu1.l1c.overall_hits 8836 # number of overall hits +system.cpu1.l1c.overall_miss_latency 817733786 # number of overall miss cycles +system.cpu1.l1c.overall_miss_rate 0.872876 # miss rate for overall accesses +system.cpu1.l1c.overall_misses 60671 # number of overall misses system.cpu1.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.l1c.overall_mshr_miss_latency 51018715 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_rate 0.873854 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_misses 59859 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_miss_latency 746324131 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_rate 0.872876 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_misses 60671 # number of overall MSHR misses system.cpu1.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_misses 15165 # number of overall MSHR uncacheable misses +system.cpu1.l1c.overall_mshr_uncacheable_misses 15264 # number of overall MSHR uncacheable misses system.cpu1.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu1.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu1.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -185,103 +185,103 @@ system.cpu1.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu1.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu1.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu1.l1c.protocol.read_invalid 114228 # read misses to invalid blocks +system.cpu1.l1c.protocol.read_invalid 1717891 # read misses to invalid blocks system.cpu1.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu1.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu1.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu1.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu1.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu1.l1c.protocol.snoop_read_exclusive 2718 # read snoops on exclusive blocks -system.cpu1.l1c.protocol.snoop_read_modified 12396 # read snoops on modified blocks -system.cpu1.l1c.protocol.snoop_read_owned 7348 # read snoops on owned blocks -system.cpu1.l1c.protocol.snoop_read_shared 23222 # read snoops on shared blocks -system.cpu1.l1c.protocol.snoop_readex_exclusive 1497 # readEx snoops on exclusive blocks -system.cpu1.l1c.protocol.snoop_readex_modified 6706 # readEx snoops on modified blocks -system.cpu1.l1c.protocol.snoop_readex_owned 3865 # readEx snoops on owned blocks -system.cpu1.l1c.protocol.snoop_readex_shared 12512 # readEx snoops on shared blocks -system.cpu1.l1c.protocol.snoop_upgrade_owned 852 # upgrade snoops on owned blocks -system.cpu1.l1c.protocol.snoop_upgrade_shared 2973 # upgradee snoops on shared blocks +system.cpu1.l1c.protocol.snoop_read_exclusive 2925 # read snoops on exclusive blocks +system.cpu1.l1c.protocol.snoop_read_modified 12701 # read snoops on modified blocks +system.cpu1.l1c.protocol.snoop_read_owned 7436 # read snoops on owned blocks +system.cpu1.l1c.protocol.snoop_read_shared 1669937 # read snoops on shared blocks +system.cpu1.l1c.protocol.snoop_readex_exclusive 1611 # readEx snoops on exclusive blocks +system.cpu1.l1c.protocol.snoop_readex_modified 6726 # readEx snoops on modified blocks +system.cpu1.l1c.protocol.snoop_readex_owned 3965 # readEx snoops on owned blocks +system.cpu1.l1c.protocol.snoop_readex_shared 12596 # readEx snoops on shared blocks +system.cpu1.l1c.protocol.snoop_upgrade_owned 860 # upgrade snoops on owned blocks +system.cpu1.l1c.protocol.snoop_upgrade_shared 2979 # upgradee snoops on shared blocks system.cpu1.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks system.cpu1.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks system.cpu1.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks system.cpu1.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks system.cpu1.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks system.cpu1.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu1.l1c.protocol.write_invalid 61595 # write misses to invalid blocks -system.cpu1.l1c.protocol.write_owned 1320 # write misses to owned blocks -system.cpu1.l1c.protocol.write_shared 4183 # write misses to shared blocks -system.cpu1.l1c.replacements 27139 # number of replacements -system.cpu1.l1c.sampled_refs 27498 # Sample count of references to valid blocks. +system.cpu1.l1c.protocol.write_invalid 914774 # write misses to invalid blocks +system.cpu1.l1c.protocol.write_owned 1422 # write misses to owned blocks +system.cpu1.l1c.protocol.write_shared 4382 # write misses to shared blocks +system.cpu1.l1c.replacements 27806 # number of replacements +system.cpu1.l1c.sampled_refs 28164 # Sample count of references to valid blocks. system.cpu1.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.l1c.tagsinuse 341.113569 # Cycle average of tags in use -system.cpu1.l1c.total_refs 11408 # Total number of references to valid blocks. +system.cpu1.l1c.tagsinuse 345.545872 # Cycle average of tags in use +system.cpu1.l1c.total_refs 11669 # Total number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.writebacks 10884 # number of writebacks +system.cpu1.l1c.writebacks 11204 # number of writebacks system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 98821 # number of read accesses completed -system.cpu1.num_writes 53366 # number of write accesses completed -system.cpu2.l1c.ReadReq_accesses 45016 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_avg_miss_latency 956.031371 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 880.781951 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_hits 7529 # number of ReadReq hits -system.cpu2.l1c.ReadReq_miss_latency 35838748 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_rate 0.832748 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_misses 37487 # number of ReadReq misses -system.cpu2.l1c.ReadReq_mshr_miss_latency 33017873 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate 0.832748 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_misses 37487 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable 9887 # number of ReadReq MSHR uncacheable +system.cpu1.num_reads 100000 # number of read accesses completed +system.cpu1.num_writes 54335 # number of write accesses completed +system.cpu2.l1c.ReadReq_accesses 44489 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_avg_miss_latency 14018.031231 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 12993.788573 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_hits 7507 # number of ReadReq hits +system.cpu2.l1c.ReadReq_miss_latency 518414831 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_rate 0.831262 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_misses 36982 # number of ReadReq misses +system.cpu2.l1c.ReadReq_mshr_miss_latency 480536289 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate 0.831262 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_misses 36982 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable 9861 # number of ReadReq MSHR uncacheable system.cpu2.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu2.l1c.ReadResp_mshr_uncacheable_latency 17582637 # number of ReadResp MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_accesses 24456 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_avg_miss_latency 859.707355 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 777.777296 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_hits 1165 # number of WriteReq hits -system.cpu2.l1c.WriteReq_miss_latency 20023444 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_rate 0.952363 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_misses 23291 # number of WriteReq misses -system.cpu2.l1c.WriteReq_mshr_miss_latency 18115211 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_rate 0.952363 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_misses 23291 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_uncacheable 5362 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.ReadResp_mshr_uncacheable_latency 253484666 # number of ReadResp MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_accesses 24340 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_avg_miss_latency 12765.385606 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 11318.971789 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_hits 1122 # number of WriteReq hits +system.cpu2.l1c.WriteReq_miss_latency 296386723 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_rate 0.953903 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_misses 23218 # number of WriteReq misses +system.cpu2.l1c.WriteReq_mshr_miss_latency 262803887 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_rate 0.953903 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_misses 23218 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_uncacheable 5480 # number of WriteReq MSHR uncacheable system.cpu2.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu2.l1c.WriteResp_mshr_uncacheable_latency 10583136 # number of WriteResp MSHR uncacheable cycles -system.cpu2.l1c.avg_blocked_cycles_no_mshrs 81.152375 # average number of cycles each access was blocked +system.cpu2.l1c.WriteResp_mshr_uncacheable_latency 165110755 # number of WriteResp MSHR uncacheable cycles +system.cpu2.l1c.avg_blocked_cycles_no_mshrs 1190.317505 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu2.l1c.avg_refs 0.404365 # Average number of references to valid blocks. -system.cpu2.l1c.blocked_no_mshrs 69867 # number of cycles access was blocked +system.cpu2.l1c.avg_refs 0.414721 # Average number of references to valid blocks. +system.cpu2.l1c.blocked_no_mshrs 69202 # number of cycles access was blocked system.cpu2.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked_cycles_no_mshrs 5669873 # number of cycles access was blocked +system.cpu2.l1c.blocked_cycles_no_mshrs 82372352 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.demand_accesses 69472 # number of demand (read+write) accesses -system.cpu2.l1c.demand_avg_miss_latency 919.118628 # average overall miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency 841.309092 # average overall mshr miss latency -system.cpu2.l1c.demand_hits 8694 # number of demand (read+write) hits -system.cpu2.l1c.demand_miss_latency 55862192 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_rate 0.874856 # miss rate for demand accesses -system.cpu2.l1c.demand_misses 60778 # number of demand (read+write) misses +system.cpu2.l1c.demand_accesses 68829 # number of demand (read+write) accesses +system.cpu2.l1c.demand_avg_miss_latency 13534.909535 # average overall miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency 12347.843455 # average overall mshr miss latency +system.cpu2.l1c.demand_hits 8629 # number of demand (read+write) hits +system.cpu2.l1c.demand_miss_latency 814801554 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_rate 0.874631 # miss rate for demand accesses +system.cpu2.l1c.demand_misses 60200 # number of demand (read+write) misses system.cpu2.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.l1c.demand_mshr_miss_latency 51133084 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_rate 0.874856 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_misses 60778 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_miss_latency 743340176 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_rate 0.874631 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_misses 60200 # number of demand (read+write) MSHR misses system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.l1c.overall_accesses 69472 # number of overall (read+write) accesses -system.cpu2.l1c.overall_avg_miss_latency 919.118628 # average overall miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency 841.309092 # average overall mshr miss latency +system.cpu2.l1c.overall_accesses 68829 # number of overall (read+write) accesses +system.cpu2.l1c.overall_avg_miss_latency 13534.909535 # average overall miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency 12347.843455 # average overall mshr miss latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu2.l1c.overall_hits 8694 # number of overall hits -system.cpu2.l1c.overall_miss_latency 55862192 # number of overall miss cycles -system.cpu2.l1c.overall_miss_rate 0.874856 # miss rate for overall accesses -system.cpu2.l1c.overall_misses 60778 # number of overall misses +system.cpu2.l1c.overall_hits 8629 # number of overall hits +system.cpu2.l1c.overall_miss_latency 814801554 # number of overall miss cycles +system.cpu2.l1c.overall_miss_rate 0.874631 # miss rate for overall accesses +system.cpu2.l1c.overall_misses 60200 # number of overall misses system.cpu2.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.l1c.overall_mshr_miss_latency 51133084 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_rate 0.874856 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_misses 60778 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_miss_latency 743340176 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_rate 0.874631 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_misses 60200 # number of overall MSHR misses system.cpu2.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_misses 15249 # number of overall MSHR uncacheable misses +system.cpu2.l1c.overall_mshr_uncacheable_misses 15341 # number of overall MSHR uncacheable misses system.cpu2.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu2.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu2.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -292,103 +292,103 @@ system.cpu2.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu2.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu2.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu2.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu2.l1c.protocol.read_invalid 111528 # read misses to invalid blocks +system.cpu2.l1c.protocol.read_invalid 1818161 # read misses to invalid blocks system.cpu2.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu2.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu2.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu2.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu2.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu2.l1c.protocol.snoop_read_exclusive 2757 # read snoops on exclusive blocks -system.cpu2.l1c.protocol.snoop_read_modified 12587 # read snoops on modified blocks -system.cpu2.l1c.protocol.snoop_read_owned 7252 # read snoops on owned blocks -system.cpu2.l1c.protocol.snoop_read_shared 22967 # read snoops on shared blocks -system.cpu2.l1c.protocol.snoop_readex_exclusive 1579 # readEx snoops on exclusive blocks -system.cpu2.l1c.protocol.snoop_readex_modified 6680 # readEx snoops on modified blocks -system.cpu2.l1c.protocol.snoop_readex_owned 3891 # readEx snoops on owned blocks -system.cpu2.l1c.protocol.snoop_readex_shared 12468 # readEx snoops on shared blocks -system.cpu2.l1c.protocol.snoop_upgrade_owned 850 # upgrade snoops on owned blocks -system.cpu2.l1c.protocol.snoop_upgrade_shared 2951 # upgradee snoops on shared blocks +system.cpu2.l1c.protocol.snoop_read_exclusive 2846 # read snoops on exclusive blocks +system.cpu2.l1c.protocol.snoop_read_modified 12505 # read snoops on modified blocks +system.cpu2.l1c.protocol.snoop_read_owned 7354 # read snoops on owned blocks +system.cpu2.l1c.protocol.snoop_read_shared 1719896 # read snoops on shared blocks +system.cpu2.l1c.protocol.snoop_readex_exclusive 1512 # readEx snoops on exclusive blocks +system.cpu2.l1c.protocol.snoop_readex_modified 6836 # readEx snoops on modified blocks +system.cpu2.l1c.protocol.snoop_readex_owned 4066 # readEx snoops on owned blocks +system.cpu2.l1c.protocol.snoop_readex_shared 12494 # readEx snoops on shared blocks +system.cpu2.l1c.protocol.snoop_upgrade_owned 828 # upgrade snoops on owned blocks +system.cpu2.l1c.protocol.snoop_upgrade_shared 2975 # upgradee snoops on shared blocks system.cpu2.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks system.cpu2.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks system.cpu2.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks system.cpu2.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks system.cpu2.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks system.cpu2.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu2.l1c.protocol.write_invalid 57618 # write misses to invalid blocks -system.cpu2.l1c.protocol.write_owned 1263 # write misses to owned blocks -system.cpu2.l1c.protocol.write_shared 4251 # write misses to shared blocks -system.cpu2.l1c.replacements 28062 # number of replacements -system.cpu2.l1c.sampled_refs 28405 # Sample count of references to valid blocks. +system.cpu2.l1c.protocol.write_invalid 1061132 # write misses to invalid blocks +system.cpu2.l1c.protocol.write_owned 1410 # write misses to owned blocks +system.cpu2.l1c.protocol.write_shared 4436 # write misses to shared blocks +system.cpu2.l1c.replacements 27337 # number of replacements +system.cpu2.l1c.sampled_refs 27674 # Sample count of references to valid blocks. system.cpu2.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.l1c.tagsinuse 344.040679 # Cycle average of tags in use -system.cpu2.l1c.total_refs 11486 # Total number of references to valid blocks. +system.cpu2.l1c.tagsinuse 343.290844 # Cycle average of tags in use +system.cpu2.l1c.total_refs 11477 # Total number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.writebacks 11295 # number of writebacks +system.cpu2.l1c.writebacks 10872 # number of writebacks system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 100000 # number of read accesses completed -system.cpu2.num_writes 54133 # number of write accesses completed -system.cpu3.l1c.ReadReq_accesses 44504 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_avg_miss_latency 968.772953 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 892.914985 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_hits 7428 # number of ReadReq hits -system.cpu3.l1c.ReadReq_miss_latency 35918226 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_rate 0.833094 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_misses 37076 # number of ReadReq misses -system.cpu3.l1c.ReadReq_mshr_miss_latency 33105716 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate 0.833094 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_misses 37076 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable 9876 # number of ReadReq MSHR uncacheable +system.cpu2.num_reads 98887 # number of read accesses completed +system.cpu2.num_writes 53640 # number of write accesses completed +system.cpu3.l1c.ReadReq_accesses 44566 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_avg_miss_latency 14066.553951 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 13052.525235 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_hits 7375 # number of ReadReq hits +system.cpu3.l1c.ReadReq_miss_latency 523149208 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_rate 0.834515 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_misses 37191 # number of ReadReq misses +system.cpu3.l1c.ReadReq_mshr_miss_latency 485436466 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate 0.834515 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_misses 37191 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable 9820 # number of ReadReq MSHR uncacheable system.cpu3.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu3.l1c.ReadResp_mshr_uncacheable_latency 17594905 # number of ReadResp MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_accesses 24087 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_avg_miss_latency 868.499565 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 784.537397 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_hits 1117 # number of WriteReq hits -system.cpu3.l1c.WriteReq_miss_latency 19949435 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_rate 0.953626 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_misses 22970 # number of WriteReq misses -system.cpu3.l1c.WriteReq_mshr_miss_latency 18020824 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_rate 0.953626 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_misses 22970 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_uncacheable 5355 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.ReadResp_mshr_uncacheable_latency 252799971 # number of ReadResp MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_accesses 24030 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_avg_miss_latency 12807.474484 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 11345.837164 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_hits 1142 # number of WriteReq hits +system.cpu3.l1c.WriteReq_miss_latency 293137476 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_rate 0.952476 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_misses 22888 # number of WriteReq misses +system.cpu3.l1c.WriteReq_mshr_miss_latency 259683521 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_rate 0.952476 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_misses 22888 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_uncacheable 5294 # number of WriteReq MSHR uncacheable system.cpu3.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu3.l1c.WriteResp_mshr_uncacheable_latency 10637792 # number of WriteResp MSHR uncacheable cycles -system.cpu3.l1c.avg_blocked_cycles_no_mshrs 82.097897 # average number of cycles each access was blocked +system.cpu3.l1c.WriteResp_mshr_uncacheable_latency 159218905 # number of WriteResp MSHR uncacheable cycles +system.cpu3.l1c.avg_blocked_cycles_no_mshrs 1193.729049 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu3.l1c.avg_refs 0.411489 # Average number of references to valid blocks. -system.cpu3.l1c.blocked_no_mshrs 69124 # number of cycles access was blocked +system.cpu3.l1c.avg_refs 0.411345 # Average number of references to valid blocks. +system.cpu3.l1c.blocked_no_mshrs 69160 # number of cycles access was blocked system.cpu3.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked_cycles_no_mshrs 5674935 # number of cycles access was blocked +system.cpu3.l1c.blocked_cycles_no_mshrs 82558301 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.demand_accesses 68591 # number of demand (read+write) accesses -system.cpu3.l1c.demand_avg_miss_latency 930.414366 # average overall miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency 851.456217 # average overall mshr miss latency -system.cpu3.l1c.demand_hits 8545 # number of demand (read+write) hits -system.cpu3.l1c.demand_miss_latency 55867661 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_rate 0.875421 # miss rate for demand accesses -system.cpu3.l1c.demand_misses 60046 # number of demand (read+write) misses +system.cpu3.l1c.demand_accesses 68596 # number of demand (read+write) accesses +system.cpu3.l1c.demand_avg_miss_latency 13586.888663 # average overall miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency 12402.336707 # average overall mshr miss latency +system.cpu3.l1c.demand_hits 8517 # number of demand (read+write) hits +system.cpu3.l1c.demand_miss_latency 816286684 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_rate 0.875838 # miss rate for demand accesses +system.cpu3.l1c.demand_misses 60079 # number of demand (read+write) misses system.cpu3.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.l1c.demand_mshr_miss_latency 51126540 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_rate 0.875421 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_misses 60046 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_miss_latency 745119987 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_rate 0.875838 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_misses 60079 # number of demand (read+write) MSHR misses system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.l1c.overall_accesses 68591 # number of overall (read+write) accesses -system.cpu3.l1c.overall_avg_miss_latency 930.414366 # average overall miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency 851.456217 # average overall mshr miss latency +system.cpu3.l1c.overall_accesses 68596 # number of overall (read+write) accesses +system.cpu3.l1c.overall_avg_miss_latency 13586.888663 # average overall miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency 12402.336707 # average overall mshr miss latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu3.l1c.overall_hits 8545 # number of overall hits -system.cpu3.l1c.overall_miss_latency 55867661 # number of overall miss cycles -system.cpu3.l1c.overall_miss_rate 0.875421 # miss rate for overall accesses -system.cpu3.l1c.overall_misses 60046 # number of overall misses +system.cpu3.l1c.overall_hits 8517 # number of overall hits +system.cpu3.l1c.overall_miss_latency 816286684 # number of overall miss cycles +system.cpu3.l1c.overall_miss_rate 0.875838 # miss rate for overall accesses +system.cpu3.l1c.overall_misses 60079 # number of overall misses system.cpu3.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.l1c.overall_mshr_miss_latency 51126540 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_rate 0.875421 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_misses 60046 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_miss_latency 745119987 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_rate 0.875838 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_misses 60079 # number of overall MSHR misses system.cpu3.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_misses 15231 # number of overall MSHR uncacheable misses +system.cpu3.l1c.overall_mshr_uncacheable_misses 15114 # number of overall MSHR uncacheable misses system.cpu3.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu3.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu3.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -399,103 +399,103 @@ system.cpu3.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu3.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu3.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu3.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu3.l1c.protocol.read_invalid 110901 # read misses to invalid blocks +system.cpu3.l1c.protocol.read_invalid 1894373 # read misses to invalid blocks system.cpu3.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu3.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu3.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu3.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu3.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu3.l1c.protocol.snoop_read_exclusive 2843 # read snoops on exclusive blocks -system.cpu3.l1c.protocol.snoop_read_modified 12490 # read snoops on modified blocks -system.cpu3.l1c.protocol.snoop_read_owned 7235 # read snoops on owned blocks -system.cpu3.l1c.protocol.snoop_read_shared 23011 # read snoops on shared blocks -system.cpu3.l1c.protocol.snoop_readex_exclusive 1535 # readEx snoops on exclusive blocks -system.cpu3.l1c.protocol.snoop_readex_modified 6732 # readEx snoops on modified blocks -system.cpu3.l1c.protocol.snoop_readex_owned 3954 # readEx snoops on owned blocks -system.cpu3.l1c.protocol.snoop_readex_shared 12354 # readEx snoops on shared blocks -system.cpu3.l1c.protocol.snoop_upgrade_owned 858 # upgrade snoops on owned blocks -system.cpu3.l1c.protocol.snoop_upgrade_shared 3087 # upgradee snoops on shared blocks +system.cpu3.l1c.protocol.snoop_read_exclusive 2902 # read snoops on exclusive blocks +system.cpu3.l1c.protocol.snoop_read_modified 12291 # read snoops on modified blocks +system.cpu3.l1c.protocol.snoop_read_owned 7221 # read snoops on owned blocks +system.cpu3.l1c.protocol.snoop_read_shared 1743434 # read snoops on shared blocks +system.cpu3.l1c.protocol.snoop_readex_exclusive 1553 # readEx snoops on exclusive blocks +system.cpu3.l1c.protocol.snoop_readex_modified 6822 # readEx snoops on modified blocks +system.cpu3.l1c.protocol.snoop_readex_owned 3914 # readEx snoops on owned blocks +system.cpu3.l1c.protocol.snoop_readex_shared 12477 # readEx snoops on shared blocks +system.cpu3.l1c.protocol.snoop_upgrade_owned 867 # upgrade snoops on owned blocks +system.cpu3.l1c.protocol.snoop_upgrade_shared 3008 # upgradee snoops on shared blocks system.cpu3.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks system.cpu3.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks system.cpu3.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks system.cpu3.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks system.cpu3.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks system.cpu3.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu3.l1c.protocol.write_invalid 59061 # write misses to invalid blocks -system.cpu3.l1c.protocol.write_owned 1261 # write misses to owned blocks -system.cpu3.l1c.protocol.write_shared 4235 # write misses to shared blocks -system.cpu3.l1c.replacements 27216 # number of replacements -system.cpu3.l1c.sampled_refs 27556 # Sample count of references to valid blocks. +system.cpu3.l1c.protocol.write_invalid 1046634 # write misses to invalid blocks +system.cpu3.l1c.protocol.write_owned 1364 # write misses to owned blocks +system.cpu3.l1c.protocol.write_shared 4484 # write misses to shared blocks +system.cpu3.l1c.replacements 27286 # number of replacements +system.cpu3.l1c.sampled_refs 27624 # Sample count of references to valid blocks. system.cpu3.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.l1c.tagsinuse 341.602377 # Cycle average of tags in use -system.cpu3.l1c.total_refs 11339 # Total number of references to valid blocks. +system.cpu3.l1c.tagsinuse 342.290575 # Cycle average of tags in use +system.cpu3.l1c.total_refs 11363 # Total number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.writebacks 10831 # number of writebacks +system.cpu3.l1c.writebacks 10681 # number of writebacks system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 98893 # number of read accesses completed -system.cpu3.num_writes 53654 # number of write accesses completed -system.cpu4.l1c.ReadReq_accesses 44272 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_avg_miss_latency 976.655364 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 901.292278 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_hits 7468 # number of ReadReq hits -system.cpu4.l1c.ReadReq_miss_latency 35944824 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_rate 0.831316 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_misses 36804 # number of ReadReq misses -system.cpu4.l1c.ReadReq_mshr_miss_latency 33171161 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate 0.831316 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_misses 36804 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable 9822 # number of ReadReq MSHR uncacheable +system.cpu3.num_reads 99322 # number of read accesses completed +system.cpu3.num_writes 53280 # number of write accesses completed +system.cpu4.l1c.ReadReq_accesses 44971 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_avg_miss_latency 13943.186039 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 12937.718615 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_hits 7581 # number of ReadReq hits +system.cpu4.l1c.ReadReq_miss_latency 521335726 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_rate 0.831425 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_misses 37390 # number of ReadReq misses +system.cpu4.l1c.ReadReq_mshr_miss_latency 483741299 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate 0.831425 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_misses 37390 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable 9931 # number of ReadReq MSHR uncacheable system.cpu4.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu4.l1c.ReadResp_mshr_uncacheable_latency 17532387 # number of ReadResp MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_accesses 23994 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_avg_miss_latency 874.063859 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 788.017488 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_hits 1178 # number of WriteReq hits -system.cpu4.l1c.WriteReq_miss_latency 19942641 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_rate 0.950904 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_misses 22816 # number of WriteReq misses -system.cpu4.l1c.WriteReq_mshr_miss_latency 17979407 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_rate 0.950904 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_misses 22816 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_uncacheable 5315 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.ReadResp_mshr_uncacheable_latency 254015216 # number of ReadResp MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_accesses 24134 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_avg_miss_latency 12764.573629 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 11273.971841 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_hits 1086 # number of WriteReq hits +system.cpu4.l1c.WriteReq_miss_latency 294197893 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_rate 0.955001 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_misses 23048 # number of WriteReq misses +system.cpu4.l1c.WriteReq_mshr_miss_latency 259842503 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_rate 0.955001 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_misses 23048 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_uncacheable 5390 # number of WriteReq MSHR uncacheable system.cpu4.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu4.l1c.WriteResp_mshr_uncacheable_latency 10563676 # number of WriteResp MSHR uncacheable cycles -system.cpu4.l1c.avg_blocked_cycles_no_mshrs 82.703233 # average number of cycles each access was blocked +system.cpu4.l1c.WriteResp_mshr_uncacheable_latency 161643344 # number of WriteResp MSHR uncacheable cycles +system.cpu4.l1c.avg_blocked_cycles_no_mshrs 1186.636056 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu4.l1c.avg_refs 0.416368 # Average number of references to valid blocks. -system.cpu4.l1c.blocked_no_mshrs 68707 # number of cycles access was blocked +system.cpu4.l1c.avg_refs 0.410931 # Average number of references to valid blocks. +system.cpu4.l1c.blocked_no_mshrs 69637 # number of cycles access was blocked system.cpu4.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked_cycles_no_mshrs 5682291 # number of cycles access was blocked +system.cpu4.l1c.blocked_cycles_no_mshrs 82633775 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.demand_accesses 68266 # number of demand (read+write) accesses -system.cpu4.l1c.demand_avg_miss_latency 937.394582 # average overall miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency 857.943106 # average overall mshr miss latency -system.cpu4.l1c.demand_hits 8646 # number of demand (read+write) hits -system.cpu4.l1c.demand_miss_latency 55887465 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_rate 0.873348 # miss rate for demand accesses -system.cpu4.l1c.demand_misses 59620 # number of demand (read+write) misses +system.cpu4.l1c.demand_accesses 69105 # number of demand (read+write) accesses +system.cpu4.l1c.demand_avg_miss_latency 13493.722807 # average overall miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency 12303.249644 # average overall mshr miss latency +system.cpu4.l1c.demand_hits 8667 # number of demand (read+write) hits +system.cpu4.l1c.demand_miss_latency 815533619 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_rate 0.874582 # miss rate for demand accesses +system.cpu4.l1c.demand_misses 60438 # number of demand (read+write) misses system.cpu4.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu4.l1c.demand_mshr_miss_latency 51150568 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_rate 0.873348 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_misses 59620 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_miss_latency 743583802 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_rate 0.874582 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_misses 60438 # number of demand (read+write) MSHR misses system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.l1c.overall_accesses 68266 # number of overall (read+write) accesses -system.cpu4.l1c.overall_avg_miss_latency 937.394582 # average overall miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency 857.943106 # average overall mshr miss latency +system.cpu4.l1c.overall_accesses 69105 # number of overall (read+write) accesses +system.cpu4.l1c.overall_avg_miss_latency 13493.722807 # average overall miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency 12303.249644 # average overall mshr miss latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu4.l1c.overall_hits 8646 # number of overall hits -system.cpu4.l1c.overall_miss_latency 55887465 # number of overall miss cycles -system.cpu4.l1c.overall_miss_rate 0.873348 # miss rate for overall accesses -system.cpu4.l1c.overall_misses 59620 # number of overall misses +system.cpu4.l1c.overall_hits 8667 # number of overall hits +system.cpu4.l1c.overall_miss_latency 815533619 # number of overall miss cycles +system.cpu4.l1c.overall_miss_rate 0.874582 # miss rate for overall accesses +system.cpu4.l1c.overall_misses 60438 # number of overall misses system.cpu4.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu4.l1c.overall_mshr_miss_latency 51150568 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_rate 0.873348 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_misses 59620 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_miss_latency 743583802 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_rate 0.874582 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_misses 60438 # number of overall MSHR misses system.cpu4.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_misses 15137 # number of overall MSHR uncacheable misses +system.cpu4.l1c.overall_mshr_uncacheable_misses 15321 # number of overall MSHR uncacheable misses system.cpu4.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu4.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu4.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -506,103 +506,103 @@ system.cpu4.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu4.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu4.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu4.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu4.l1c.protocol.read_invalid 113154 # read misses to invalid blocks +system.cpu4.l1c.protocol.read_invalid 1830675 # read misses to invalid blocks system.cpu4.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu4.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu4.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu4.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu4.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu4.l1c.protocol.snoop_read_exclusive 2804 # read snoops on exclusive blocks -system.cpu4.l1c.protocol.snoop_read_modified 12453 # read snoops on modified blocks -system.cpu4.l1c.protocol.snoop_read_owned 7418 # read snoops on owned blocks -system.cpu4.l1c.protocol.snoop_read_shared 23136 # read snoops on shared blocks -system.cpu4.l1c.protocol.snoop_readex_exclusive 1528 # readEx snoops on exclusive blocks -system.cpu4.l1c.protocol.snoop_readex_modified 6607 # readEx snoops on modified blocks -system.cpu4.l1c.protocol.snoop_readex_owned 3922 # readEx snoops on owned blocks -system.cpu4.l1c.protocol.snoop_readex_shared 12524 # readEx snoops on shared blocks -system.cpu4.l1c.protocol.snoop_upgrade_owned 843 # upgrade snoops on owned blocks -system.cpu4.l1c.protocol.snoop_upgrade_shared 2904 # upgradee snoops on shared blocks +system.cpu4.l1c.protocol.snoop_read_exclusive 2847 # read snoops on exclusive blocks +system.cpu4.l1c.protocol.snoop_read_modified 12499 # read snoops on modified blocks +system.cpu4.l1c.protocol.snoop_read_owned 7458 # read snoops on owned blocks +system.cpu4.l1c.protocol.snoop_read_shared 1765770 # read snoops on shared blocks +system.cpu4.l1c.protocol.snoop_readex_exclusive 1560 # readEx snoops on exclusive blocks +system.cpu4.l1c.protocol.snoop_readex_modified 6711 # readEx snoops on modified blocks +system.cpu4.l1c.protocol.snoop_readex_owned 3919 # readEx snoops on owned blocks +system.cpu4.l1c.protocol.snoop_readex_shared 12526 # readEx snoops on shared blocks +system.cpu4.l1c.protocol.snoop_upgrade_owned 902 # upgrade snoops on owned blocks +system.cpu4.l1c.protocol.snoop_upgrade_shared 3023 # upgradee snoops on shared blocks system.cpu4.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks system.cpu4.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks system.cpu4.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks system.cpu4.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks system.cpu4.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks system.cpu4.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu4.l1c.protocol.write_invalid 59622 # write misses to invalid blocks -system.cpu4.l1c.protocol.write_owned 1265 # write misses to owned blocks -system.cpu4.l1c.protocol.write_shared 4187 # write misses to shared blocks -system.cpu4.l1c.replacements 27000 # number of replacements -system.cpu4.l1c.sampled_refs 27346 # Sample count of references to valid blocks. +system.cpu4.l1c.protocol.write_invalid 854606 # write misses to invalid blocks +system.cpu4.l1c.protocol.write_owned 1318 # write misses to owned blocks +system.cpu4.l1c.protocol.write_shared 4519 # write misses to shared blocks +system.cpu4.l1c.replacements 27664 # number of replacements +system.cpu4.l1c.sampled_refs 28012 # Sample count of references to valid blocks. system.cpu4.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu4.l1c.tagsinuse 342.121323 # Cycle average of tags in use -system.cpu4.l1c.total_refs 11386 # Total number of references to valid blocks. +system.cpu4.l1c.tagsinuse 344.185288 # Cycle average of tags in use +system.cpu4.l1c.total_refs 11511 # Total number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.writebacks 10847 # number of writebacks +system.cpu4.l1c.writebacks 10935 # number of writebacks system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 98882 # number of read accesses completed -system.cpu4.num_writes 53288 # number of write accesses completed -system.cpu5.l1c.ReadReq_accesses 44218 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_avg_miss_latency 975.652027 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 898.818359 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_hits 7310 # number of ReadReq hits -system.cpu5.l1c.ReadReq_miss_latency 36009365 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_rate 0.834683 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_misses 36908 # number of ReadReq misses -system.cpu5.l1c.ReadReq_mshr_miss_latency 33173588 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate 0.834683 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_misses 36908 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable 9866 # number of ReadReq MSHR uncacheable +system.cpu4.num_reads 99841 # number of read accesses completed +system.cpu4.num_writes 54005 # number of write accesses completed +system.cpu5.l1c.ReadReq_accesses 45075 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_avg_miss_latency 13980.675167 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 12974.186518 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_hits 7588 # number of ReadReq hits +system.cpu5.l1c.ReadReq_miss_latency 524093570 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_rate 0.831658 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_misses 37487 # number of ReadReq misses +system.cpu5.l1c.ReadReq_mshr_miss_latency 486363330 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate 0.831658 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_misses 37487 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable 9769 # number of ReadReq MSHR uncacheable system.cpu5.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu5.l1c.ReadResp_mshr_uncacheable_latency 17625443 # number of ReadResp MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_accesses 23923 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_avg_miss_latency 873.308611 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 788.173188 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_hits 1150 # number of WriteReq hits -system.cpu5.l1c.WriteReq_miss_latency 19887857 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_rate 0.951929 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_misses 22773 # number of WriteReq misses -system.cpu5.l1c.WriteReq_mshr_miss_latency 17949068 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_rate 0.951929 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_misses 22773 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_uncacheable 5207 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.ReadResp_mshr_uncacheable_latency 252483534 # number of ReadResp MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_accesses 24120 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_avg_miss_latency 12733.111936 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 11249.826210 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_hits 1098 # number of WriteReq hits +system.cpu5.l1c.WriteReq_miss_latency 293141703 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_rate 0.954478 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_misses 23022 # number of WriteReq misses +system.cpu5.l1c.WriteReq_mshr_miss_latency 258993499 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_rate 0.954478 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_misses 23022 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_uncacheable 5232 # number of WriteReq MSHR uncacheable system.cpu5.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu5.l1c.WriteResp_mshr_uncacheable_latency 10374807 # number of WriteResp MSHR uncacheable cycles -system.cpu5.l1c.avg_blocked_cycles_no_mshrs 82.590363 # average number of cycles each access was blocked +system.cpu5.l1c.WriteResp_mshr_uncacheable_latency 155064988 # number of WriteResp MSHR uncacheable cycles +system.cpu5.l1c.avg_blocked_cycles_no_mshrs 1188.349008 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu5.l1c.avg_refs 0.413664 # Average number of references to valid blocks. -system.cpu5.l1c.blocked_no_mshrs 68944 # number of cycles access was blocked +system.cpu5.l1c.avg_refs 0.414917 # Average number of references to valid blocks. +system.cpu5.l1c.blocked_no_mshrs 69537 # number of cycles access was blocked system.cpu5.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked_cycles_no_mshrs 5694110 # number of cycles access was blocked +system.cpu5.l1c.blocked_cycles_no_mshrs 82634225 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.demand_accesses 68141 # number of demand (read+write) accesses -system.cpu5.l1c.demand_avg_miss_latency 936.599956 # average overall miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency 856.598515 # average overall mshr miss latency -system.cpu5.l1c.demand_hits 8460 # number of demand (read+write) hits -system.cpu5.l1c.demand_miss_latency 55897222 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_rate 0.875846 # miss rate for demand accesses -system.cpu5.l1c.demand_misses 59681 # number of demand (read+write) misses +system.cpu5.l1c.demand_accesses 69195 # number of demand (read+write) accesses +system.cpu5.l1c.demand_avg_miss_latency 13506.011883 # average overall miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency 12318.115140 # average overall mshr miss latency +system.cpu5.l1c.demand_hits 8686 # number of demand (read+write) hits +system.cpu5.l1c.demand_miss_latency 817235273 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_rate 0.874471 # miss rate for demand accesses +system.cpu5.l1c.demand_misses 60509 # number of demand (read+write) misses system.cpu5.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu5.l1c.demand_mshr_miss_latency 51122656 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_rate 0.875846 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_misses 59681 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_miss_latency 745356829 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_rate 0.874471 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_misses 60509 # number of demand (read+write) MSHR misses system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.l1c.overall_accesses 68141 # number of overall (read+write) accesses -system.cpu5.l1c.overall_avg_miss_latency 936.599956 # average overall miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency 856.598515 # average overall mshr miss latency +system.cpu5.l1c.overall_accesses 69195 # number of overall (read+write) accesses +system.cpu5.l1c.overall_avg_miss_latency 13506.011883 # average overall miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency 12318.115140 # average overall mshr miss latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu5.l1c.overall_hits 8460 # number of overall hits -system.cpu5.l1c.overall_miss_latency 55897222 # number of overall miss cycles -system.cpu5.l1c.overall_miss_rate 0.875846 # miss rate for overall accesses -system.cpu5.l1c.overall_misses 59681 # number of overall misses +system.cpu5.l1c.overall_hits 8686 # number of overall hits +system.cpu5.l1c.overall_miss_latency 817235273 # number of overall miss cycles +system.cpu5.l1c.overall_miss_rate 0.874471 # miss rate for overall accesses +system.cpu5.l1c.overall_misses 60509 # number of overall misses system.cpu5.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu5.l1c.overall_mshr_miss_latency 51122656 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_rate 0.875846 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_misses 59681 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_miss_latency 745356829 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_rate 0.874471 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_misses 60509 # number of overall MSHR misses system.cpu5.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_misses 15073 # number of overall MSHR uncacheable misses +system.cpu5.l1c.overall_mshr_uncacheable_misses 15001 # number of overall MSHR uncacheable misses system.cpu5.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu5.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu5.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -613,103 +613,103 @@ system.cpu5.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu5.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu5.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu5.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu5.l1c.protocol.read_invalid 114279 # read misses to invalid blocks +system.cpu5.l1c.protocol.read_invalid 1718821 # read misses to invalid blocks system.cpu5.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu5.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu5.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu5.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu5.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu5.l1c.protocol.snoop_read_exclusive 2860 # read snoops on exclusive blocks -system.cpu5.l1c.protocol.snoop_read_modified 12253 # read snoops on modified blocks -system.cpu5.l1c.protocol.snoop_read_owned 7231 # read snoops on owned blocks -system.cpu5.l1c.protocol.snoop_read_shared 23182 # read snoops on shared blocks -system.cpu5.l1c.protocol.snoop_readex_exclusive 1499 # readEx snoops on exclusive blocks -system.cpu5.l1c.protocol.snoop_readex_modified 6757 # readEx snoops on modified blocks -system.cpu5.l1c.protocol.snoop_readex_owned 3896 # readEx snoops on owned blocks -system.cpu5.l1c.protocol.snoop_readex_shared 12461 # readEx snoops on shared blocks -system.cpu5.l1c.protocol.snoop_upgrade_owned 887 # upgrade snoops on owned blocks -system.cpu5.l1c.protocol.snoop_upgrade_shared 3020 # upgradee snoops on shared blocks +system.cpu5.l1c.protocol.snoop_read_exclusive 2926 # read snoops on exclusive blocks +system.cpu5.l1c.protocol.snoop_read_modified 12465 # read snoops on modified blocks +system.cpu5.l1c.protocol.snoop_read_owned 7201 # read snoops on owned blocks +system.cpu5.l1c.protocol.snoop_read_shared 1810557 # read snoops on shared blocks +system.cpu5.l1c.protocol.snoop_readex_exclusive 1622 # readEx snoops on exclusive blocks +system.cpu5.l1c.protocol.snoop_readex_modified 6690 # readEx snoops on modified blocks +system.cpu5.l1c.protocol.snoop_readex_owned 3947 # readEx snoops on owned blocks +system.cpu5.l1c.protocol.snoop_readex_shared 12574 # readEx snoops on shared blocks +system.cpu5.l1c.protocol.snoop_upgrade_owned 818 # upgrade snoops on owned blocks +system.cpu5.l1c.protocol.snoop_upgrade_shared 3092 # upgradee snoops on shared blocks system.cpu5.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks system.cpu5.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks system.cpu5.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks system.cpu5.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks system.cpu5.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks system.cpu5.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu5.l1c.protocol.write_invalid 60969 # write misses to invalid blocks -system.cpu5.l1c.protocol.write_owned 1349 # write misses to owned blocks -system.cpu5.l1c.protocol.write_shared 4191 # write misses to shared blocks -system.cpu5.l1c.replacements 26828 # number of replacements -system.cpu5.l1c.sampled_refs 27196 # Sample count of references to valid blocks. +system.cpu5.l1c.protocol.write_invalid 914561 # write misses to invalid blocks +system.cpu5.l1c.protocol.write_owned 1422 # write misses to owned blocks +system.cpu5.l1c.protocol.write_shared 4534 # write misses to shared blocks +system.cpu5.l1c.replacements 27551 # number of replacements +system.cpu5.l1c.sampled_refs 27914 # Sample count of references to valid blocks. system.cpu5.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu5.l1c.tagsinuse 340.865502 # Cycle average of tags in use -system.cpu5.l1c.total_refs 11250 # Total number of references to valid blocks. +system.cpu5.l1c.tagsinuse 344.440637 # Cycle average of tags in use +system.cpu5.l1c.total_refs 11582 # Total number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.writebacks 10567 # number of writebacks +system.cpu5.l1c.writebacks 10931 # number of writebacks system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 97882 # number of read accesses completed -system.cpu5.num_writes 52965 # number of write accesses completed -system.cpu6.l1c.ReadReq_accesses 44971 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_avg_miss_latency 967.006541 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 890.563660 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_hits 7514 # number of ReadReq hits -system.cpu6.l1c.ReadReq_miss_latency 36221164 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_rate 0.832915 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_misses 37457 # number of ReadReq misses -system.cpu6.l1c.ReadReq_mshr_miss_latency 33357843 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate 0.832915 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_misses 37457 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable 9684 # number of ReadReq MSHR uncacheable +system.cpu5.num_reads 99674 # number of read accesses completed +system.cpu5.num_writes 53393 # number of write accesses completed +system.cpu6.l1c.ReadReq_accesses 44595 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_avg_miss_latency 14001.082353 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 12995.526917 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_hits 7462 # number of ReadReq hits +system.cpu6.l1c.ReadReq_miss_latency 519902191 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_rate 0.832672 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_misses 37133 # number of ReadReq misses +system.cpu6.l1c.ReadReq_mshr_miss_latency 482562901 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate 0.832672 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_misses 37133 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable 9820 # number of ReadReq MSHR uncacheable system.cpu6.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu6.l1c.ReadResp_mshr_uncacheable_latency 17275344 # number of ReadResp MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_accesses 23996 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_avg_miss_latency 873.777515 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 790.631514 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_hits 1181 # number of WriteReq hits -system.cpu6.l1c.WriteReq_miss_latency 19935234 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_rate 0.950783 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_misses 22815 # number of WriteReq misses -system.cpu6.l1c.WriteReq_mshr_miss_latency 18038258 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_rate 0.950783 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_misses 22815 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_uncacheable 5345 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.ReadResp_mshr_uncacheable_latency 251671127 # number of ReadResp MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_accesses 24364 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_avg_miss_latency 12854.640783 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 11385.598176 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_hits 1222 # number of WriteReq hits +system.cpu6.l1c.WriteReq_miss_latency 297482097 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_rate 0.949844 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_misses 23142 # number of WriteReq misses +system.cpu6.l1c.WriteReq_mshr_miss_latency 263485513 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_rate 0.949844 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_misses 23142 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_uncacheable 5447 # number of WriteReq MSHR uncacheable system.cpu6.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu6.l1c.WriteResp_mshr_uncacheable_latency 10602140 # number of WriteResp MSHR uncacheable cycles -system.cpu6.l1c.avg_blocked_cycles_no_mshrs 82.071085 # average number of cycles each access was blocked +system.cpu6.l1c.WriteResp_mshr_uncacheable_latency 163399316 # number of WriteResp MSHR uncacheable cycles +system.cpu6.l1c.avg_blocked_cycles_no_mshrs 1189.328084 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu6.l1c.avg_refs 0.412251 # Average number of references to valid blocks. -system.cpu6.l1c.blocked_no_mshrs 69157 # number of cycles access was blocked +system.cpu6.l1c.avg_refs 0.411043 # Average number of references to valid blocks. +system.cpu6.l1c.blocked_no_mshrs 69345 # number of cycles access was blocked system.cpu6.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked_cycles_no_mshrs 5675790 # number of cycles access was blocked +system.cpu6.l1c.blocked_cycles_no_mshrs 82473956 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.demand_accesses 68967 # number of demand (read+write) accesses -system.cpu6.l1c.demand_avg_miss_latency 931.716187 # average overall miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency 852.735947 # average overall mshr miss latency -system.cpu6.l1c.demand_hits 8695 # number of demand (read+write) hits -system.cpu6.l1c.demand_miss_latency 56156398 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_rate 0.873925 # miss rate for demand accesses -system.cpu6.l1c.demand_misses 60272 # number of demand (read+write) misses +system.cpu6.l1c.demand_accesses 68959 # number of demand (read+write) accesses +system.cpu6.l1c.demand_avg_miss_latency 13560.917263 # average overall miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency 12377.410436 # average overall mshr miss latency +system.cpu6.l1c.demand_hits 8684 # number of demand (read+write) hits +system.cpu6.l1c.demand_miss_latency 817384288 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_rate 0.874070 # miss rate for demand accesses +system.cpu6.l1c.demand_misses 60275 # number of demand (read+write) misses system.cpu6.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu6.l1c.demand_mshr_miss_latency 51396101 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_rate 0.873925 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_misses 60272 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_miss_latency 746048414 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_rate 0.874070 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_misses 60275 # number of demand (read+write) MSHR misses system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.l1c.overall_accesses 68967 # number of overall (read+write) accesses -system.cpu6.l1c.overall_avg_miss_latency 931.716187 # average overall miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency 852.735947 # average overall mshr miss latency +system.cpu6.l1c.overall_accesses 68959 # number of overall (read+write) accesses +system.cpu6.l1c.overall_avg_miss_latency 13560.917263 # average overall miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency 12377.410436 # average overall mshr miss latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu6.l1c.overall_hits 8695 # number of overall hits -system.cpu6.l1c.overall_miss_latency 56156398 # number of overall miss cycles -system.cpu6.l1c.overall_miss_rate 0.873925 # miss rate for overall accesses -system.cpu6.l1c.overall_misses 60272 # number of overall misses +system.cpu6.l1c.overall_hits 8684 # number of overall hits +system.cpu6.l1c.overall_miss_latency 817384288 # number of overall miss cycles +system.cpu6.l1c.overall_miss_rate 0.874070 # miss rate for overall accesses +system.cpu6.l1c.overall_misses 60275 # number of overall misses system.cpu6.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu6.l1c.overall_mshr_miss_latency 51396101 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_rate 0.873925 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_misses 60272 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_miss_latency 746048414 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_rate 0.874070 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_misses 60275 # number of overall MSHR misses system.cpu6.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_misses 15029 # number of overall MSHR uncacheable misses +system.cpu6.l1c.overall_mshr_uncacheable_misses 15267 # number of overall MSHR uncacheable misses system.cpu6.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu6.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu6.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -720,103 +720,103 @@ system.cpu6.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu6.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu6.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu6.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu6.l1c.protocol.read_invalid 114488 # read misses to invalid blocks +system.cpu6.l1c.protocol.read_invalid 1894590 # read misses to invalid blocks system.cpu6.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu6.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu6.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu6.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu6.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu6.l1c.protocol.snoop_read_exclusive 2876 # read snoops on exclusive blocks -system.cpu6.l1c.protocol.snoop_read_modified 12371 # read snoops on modified blocks -system.cpu6.l1c.protocol.snoop_read_owned 7223 # read snoops on owned blocks -system.cpu6.l1c.protocol.snoop_read_shared 23305 # read snoops on shared blocks -system.cpu6.l1c.protocol.snoop_readex_exclusive 1616 # readEx snoops on exclusive blocks -system.cpu6.l1c.protocol.snoop_readex_modified 6693 # readEx snoops on modified blocks -system.cpu6.l1c.protocol.snoop_readex_owned 3909 # readEx snoops on owned blocks -system.cpu6.l1c.protocol.snoop_readex_shared 12446 # readEx snoops on shared blocks -system.cpu6.l1c.protocol.snoop_upgrade_owned 833 # upgrade snoops on owned blocks -system.cpu6.l1c.protocol.snoop_upgrade_shared 2948 # upgradee snoops on shared blocks +system.cpu6.l1c.protocol.snoop_read_exclusive 2887 # read snoops on exclusive blocks +system.cpu6.l1c.protocol.snoop_read_modified 12551 # read snoops on modified blocks +system.cpu6.l1c.protocol.snoop_read_owned 7188 # read snoops on owned blocks +system.cpu6.l1c.protocol.snoop_read_shared 1703425 # read snoops on shared blocks +system.cpu6.l1c.protocol.snoop_readex_exclusive 1550 # readEx snoops on exclusive blocks +system.cpu6.l1c.protocol.snoop_readex_modified 6733 # readEx snoops on modified blocks +system.cpu6.l1c.protocol.snoop_readex_owned 3926 # readEx snoops on owned blocks +system.cpu6.l1c.protocol.snoop_readex_shared 12456 # readEx snoops on shared blocks +system.cpu6.l1c.protocol.snoop_upgrade_owned 800 # upgrade snoops on owned blocks +system.cpu6.l1c.protocol.snoop_upgrade_shared 3156 # upgradee snoops on shared blocks system.cpu6.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks system.cpu6.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks system.cpu6.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks system.cpu6.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks system.cpu6.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks system.cpu6.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu6.l1c.protocol.write_invalid 58413 # write misses to invalid blocks -system.cpu6.l1c.protocol.write_owned 1374 # write misses to owned blocks -system.cpu6.l1c.protocol.write_shared 4109 # write misses to shared blocks -system.cpu6.l1c.replacements 27477 # number of replacements -system.cpu6.l1c.sampled_refs 27835 # Sample count of references to valid blocks. +system.cpu6.l1c.protocol.write_invalid 987928 # write misses to invalid blocks +system.cpu6.l1c.protocol.write_owned 1405 # write misses to owned blocks +system.cpu6.l1c.protocol.write_shared 4406 # write misses to shared blocks +system.cpu6.l1c.replacements 27613 # number of replacements +system.cpu6.l1c.sampled_refs 27946 # Sample count of references to valid blocks. system.cpu6.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu6.l1c.tagsinuse 342.134742 # Cycle average of tags in use -system.cpu6.l1c.total_refs 11475 # Total number of references to valid blocks. +system.cpu6.l1c.tagsinuse 344.860122 # Cycle average of tags in use +system.cpu6.l1c.total_refs 11487 # Total number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.writebacks 10759 # number of writebacks +system.cpu6.l1c.writebacks 11073 # number of writebacks system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99303 # number of read accesses completed -system.cpu6.num_writes 53385 # number of write accesses completed -system.cpu7.l1c.ReadReq_accesses 44438 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_avg_miss_latency 975.306986 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 899.340271 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_hits 7394 # number of ReadReq hits -system.cpu7.l1c.ReadReq_miss_latency 36129272 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_rate 0.833611 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_misses 37044 # number of ReadReq misses -system.cpu7.l1c.ReadReq_mshr_miss_latency 33315161 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate 0.833611 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_misses 37044 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable 9861 # number of ReadReq MSHR uncacheable +system.cpu6.num_reads 98723 # number of read accesses completed +system.cpu6.num_writes 53876 # number of write accesses completed +system.cpu7.l1c.ReadReq_accesses 44990 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_avg_miss_latency 13952.283047 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 12937.789329 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_hits 7505 # number of ReadReq hits +system.cpu7.l1c.ReadReq_miss_latency 523001330 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_rate 0.833185 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_misses 37485 # number of ReadReq misses +system.cpu7.l1c.ReadReq_mshr_miss_latency 484973033 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate 0.833185 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_misses 37485 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable 10001 # number of ReadReq MSHR uncacheable system.cpu7.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu7.l1c.ReadResp_mshr_uncacheable_latency 17576395 # number of ReadResp MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_accesses 23999 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_avg_miss_latency 861.568979 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 776.580264 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_hits 1137 # number of WriteReq hits -system.cpu7.l1c.WriteReq_miss_latency 19697190 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_rate 0.952623 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_misses 22862 # number of WriteReq misses -system.cpu7.l1c.WriteReq_mshr_miss_latency 17754178 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_rate 0.952623 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_misses 22862 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_uncacheable 5386 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.ReadResp_mshr_uncacheable_latency 257188342 # number of ReadResp MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_accesses 24083 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_avg_miss_latency 12615.682417 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 11155.458639 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_hits 1163 # number of WriteReq hits +system.cpu7.l1c.WriteReq_miss_latency 289151441 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_rate 0.951709 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_misses 22920 # number of WriteReq misses +system.cpu7.l1c.WriteReq_mshr_miss_latency 255683112 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_rate 0.951709 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_misses 22920 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_uncacheable 5323 # number of WriteReq MSHR uncacheable system.cpu7.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu7.l1c.WriteResp_mshr_uncacheable_latency 10720857 # number of WriteResp MSHR uncacheable cycles -system.cpu7.l1c.avg_blocked_cycles_no_mshrs 82.167211 # average number of cycles each access was blocked +system.cpu7.l1c.WriteResp_mshr_uncacheable_latency 159397105 # number of WriteResp MSHR uncacheable cycles +system.cpu7.l1c.avg_blocked_cycles_no_mshrs 1185.864523 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu7.l1c.avg_refs 0.419292 # Average number of references to valid blocks. -system.cpu7.l1c.blocked_no_mshrs 68907 # number of cycles access was blocked +system.cpu7.l1c.avg_refs 0.413879 # Average number of references to valid blocks. +system.cpu7.l1c.blocked_no_mshrs 69665 # number of cycles access was blocked system.cpu7.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked_cycles_no_mshrs 5661896 # number of cycles access was blocked +system.cpu7.l1c.blocked_cycles_no_mshrs 82613252 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.demand_accesses 68437 # number of demand (read+write) accesses -system.cpu7.l1c.demand_avg_miss_latency 931.901012 # average overall miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency 852.491220 # average overall mshr miss latency -system.cpu7.l1c.demand_hits 8531 # number of demand (read+write) hits -system.cpu7.l1c.demand_miss_latency 55826462 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_rate 0.875345 # miss rate for demand accesses -system.cpu7.l1c.demand_misses 59906 # number of demand (read+write) misses +system.cpu7.l1c.demand_accesses 69073 # number of demand (read+write) accesses +system.cpu7.l1c.demand_avg_miss_latency 13445.124923 # average overall miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency 12261.503932 # average overall mshr miss latency +system.cpu7.l1c.demand_hits 8668 # number of demand (read+write) hits +system.cpu7.l1c.demand_miss_latency 812152771 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_rate 0.874510 # miss rate for demand accesses +system.cpu7.l1c.demand_misses 60405 # number of demand (read+write) misses system.cpu7.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu7.l1c.demand_mshr_miss_latency 51069339 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_rate 0.875345 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_misses 59906 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_miss_latency 740656145 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_rate 0.874510 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_misses 60405 # number of demand (read+write) MSHR misses system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.l1c.overall_accesses 68437 # number of overall (read+write) accesses -system.cpu7.l1c.overall_avg_miss_latency 931.901012 # average overall miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency 852.491220 # average overall mshr miss latency +system.cpu7.l1c.overall_accesses 69073 # number of overall (read+write) accesses +system.cpu7.l1c.overall_avg_miss_latency 13445.124923 # average overall miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency 12261.503932 # average overall mshr miss latency system.cpu7.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu7.l1c.overall_hits 8531 # number of overall hits -system.cpu7.l1c.overall_miss_latency 55826462 # number of overall miss cycles -system.cpu7.l1c.overall_miss_rate 0.875345 # miss rate for overall accesses -system.cpu7.l1c.overall_misses 59906 # number of overall misses +system.cpu7.l1c.overall_hits 8668 # number of overall hits +system.cpu7.l1c.overall_miss_latency 812152771 # number of overall miss cycles +system.cpu7.l1c.overall_miss_rate 0.874510 # miss rate for overall accesses +system.cpu7.l1c.overall_misses 60405 # number of overall misses system.cpu7.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu7.l1c.overall_mshr_miss_latency 51069339 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_rate 0.875345 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_misses 59906 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_miss_latency 740656145 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_rate 0.874510 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_misses 60405 # number of overall MSHR misses system.cpu7.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_misses 15247 # number of overall MSHR uncacheable misses +system.cpu7.l1c.overall_mshr_uncacheable_misses 15324 # number of overall MSHR uncacheable misses system.cpu7.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu7.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu7.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -827,111 +827,111 @@ system.cpu7.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu7.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu7.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu7.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu7.l1c.protocol.read_invalid 115064 # read misses to invalid blocks +system.cpu7.l1c.protocol.read_invalid 1929884 # read misses to invalid blocks system.cpu7.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu7.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu7.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu7.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu7.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu7.l1c.protocol.snoop_read_exclusive 2793 # read snoops on exclusive blocks -system.cpu7.l1c.protocol.snoop_read_modified 12588 # read snoops on modified blocks -system.cpu7.l1c.protocol.snoop_read_owned 7412 # read snoops on owned blocks -system.cpu7.l1c.protocol.snoop_read_shared 23048 # read snoops on shared blocks -system.cpu7.l1c.protocol.snoop_readex_exclusive 1548 # readEx snoops on exclusive blocks -system.cpu7.l1c.protocol.snoop_readex_modified 6593 # readEx snoops on modified blocks -system.cpu7.l1c.protocol.snoop_readex_owned 3944 # readEx snoops on owned blocks -system.cpu7.l1c.protocol.snoop_readex_shared 12404 # readEx snoops on shared blocks -system.cpu7.l1c.protocol.snoop_upgrade_owned 919 # upgrade snoops on owned blocks -system.cpu7.l1c.protocol.snoop_upgrade_shared 2959 # upgradee snoops on shared blocks +system.cpu7.l1c.protocol.snoop_read_exclusive 2904 # read snoops on exclusive blocks +system.cpu7.l1c.protocol.snoop_read_modified 12387 # read snoops on modified blocks +system.cpu7.l1c.protocol.snoop_read_owned 7174 # read snoops on owned blocks +system.cpu7.l1c.protocol.snoop_read_shared 1782059 # read snoops on shared blocks +system.cpu7.l1c.protocol.snoop_readex_exclusive 1587 # readEx snoops on exclusive blocks +system.cpu7.l1c.protocol.snoop_readex_modified 6687 # readEx snoops on modified blocks +system.cpu7.l1c.protocol.snoop_readex_owned 3842 # readEx snoops on owned blocks +system.cpu7.l1c.protocol.snoop_readex_shared 12759 # readEx snoops on shared blocks +system.cpu7.l1c.protocol.snoop_upgrade_owned 792 # upgrade snoops on owned blocks +system.cpu7.l1c.protocol.snoop_upgrade_shared 3085 # upgradee snoops on shared blocks system.cpu7.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks system.cpu7.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks system.cpu7.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks system.cpu7.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks system.cpu7.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks system.cpu7.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu7.l1c.protocol.write_invalid 58173 # write misses to invalid blocks -system.cpu7.l1c.protocol.write_owned 1351 # write misses to owned blocks -system.cpu7.l1c.protocol.write_shared 4494 # write misses to shared blocks -system.cpu7.l1c.replacements 27080 # number of replacements -system.cpu7.l1c.sampled_refs 27420 # Sample count of references to valid blocks. +system.cpu7.l1c.protocol.write_invalid 930930 # write misses to invalid blocks +system.cpu7.l1c.protocol.write_owned 1422 # write misses to owned blocks +system.cpu7.l1c.protocol.write_shared 4465 # write misses to shared blocks +system.cpu7.l1c.replacements 27486 # number of replacements +system.cpu7.l1c.sampled_refs 27827 # Sample count of references to valid blocks. system.cpu7.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu7.l1c.tagsinuse 342.061742 # Cycle average of tags in use -system.cpu7.l1c.total_refs 11497 # Total number of references to valid blocks. +system.cpu7.l1c.tagsinuse 344.310963 # Cycle average of tags in use +system.cpu7.l1c.total_refs 11517 # Total number of references to valid blocks. system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.writebacks 10789 # number of writebacks +system.cpu7.l1c.writebacks 10979 # number of writebacks system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 98350 # number of read accesses completed -system.cpu7.num_writes 53282 # number of write accesses completed -system.l2c.ReadExReq_accesses 75399 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 89.483714 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 6.467886 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits 39632 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 3200564 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate 0.474370 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 35767 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_hits 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_miss_latency 231311 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate 0.474317 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 35763 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 138997 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 89.683271 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 6.196645 # average ReadReq mshr miss latency -system.l2c.ReadReq_hits 72568 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 5957570 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.477917 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 66429 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 411544 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.477809 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 66414 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable 78703 # number of ReadReq MSHR uncacheable +system.cpu7.num_reads 99734 # number of read accesses completed +system.cpu7.num_writes 53652 # number of write accesses completed +system.l2c.ReadExReq_accesses 75160 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 10115.633652 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 6085.503709 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits 39620 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 359509620 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate 0.472858 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 35540 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_hits 220 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_miss_latency 214939991 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate 0.469931 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 35320 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 138762 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 10150.344064 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 6129.500996 # average ReadReq mshr miss latency +system.l2c.ReadReq_hits 72597 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 671597515 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.476824 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 66165 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 406 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 403069856 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.473898 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 65759 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable 78927 # number of ReadReq MSHR uncacheable system.l2c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.l2c.ReadResp_mshr_uncacheable_latency 420484 # number of ReadResp MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable 42661 # number of WriteReq MSHR uncacheable +system.l2c.ReadResp_mshr_uncacheable_latency 484683934 # number of ReadResp MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable 42802 # number of WriteReq MSHR uncacheable system.l2c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.l2c.WriteResp_mshr_uncacheable_latency 298282 # number of WriteResp MSHR uncacheable cycles -system.l2c.Writeback_accesses 86614 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 18299 # number of Writeback hits -system.l2c.Writeback_miss_rate 0.788729 # miss rate for Writeback accesses -system.l2c.Writeback_misses 68315 # number of Writeback misses -system.l2c.Writeback_mshr_miss_rate 0.788729 # mshr miss rate for Writeback accesses -system.l2c.Writeback_mshr_misses 68315 # number of Writeback MSHR misses -system.l2c.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked +system.l2c.WriteResp_mshr_uncacheable_latency 248118294 # number of WriteResp MSHR uncacheable cycles +system.l2c.Writeback_accesses 86706 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 18948 # number of Writeback hits +system.l2c.Writeback_miss_rate 0.781468 # miss rate for Writeback accesses +system.l2c.Writeback_misses 67758 # number of Writeback misses +system.l2c.Writeback_mshr_miss_rate 0.781468 # mshr miss rate for Writeback accesses +system.l2c.Writeback_mshr_misses 67758 # number of Writeback MSHR misses +system.l2c.avg_blocked_cycles_no_mshrs 3278 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.l2c.avg_refs 1.277186 # Average number of references to valid blocks. -system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.avg_refs 1.297661 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 3 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 9834 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 138997 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 89.683271 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 6.196645 # average overall mshr miss latency -system.l2c.demand_hits 72568 # number of demand (read+write) hits -system.l2c.demand_miss_latency 5957570 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.477917 # miss rate for demand accesses -system.l2c.demand_misses 66429 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 15 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 411544 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.477809 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 66414 # number of demand (read+write) MSHR misses +system.l2c.demand_accesses 138762 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 10150.344064 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 6129.500996 # average overall mshr miss latency +system.l2c.demand_hits 72597 # number of demand (read+write) hits +system.l2c.demand_miss_latency 671597515 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.476824 # miss rate for demand accesses +system.l2c.demand_misses 66165 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 406 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 403069856 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.473898 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 65759 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 225611 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 44.213991 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 6.196645 # average overall mshr miss latency +system.l2c.overall_accesses 225468 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 5014.803394 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 6129.500996 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.l2c.overall_hits 90867 # number of overall hits -system.l2c.overall_miss_latency 5957570 # number of overall miss cycles -system.l2c.overall_miss_rate 0.597240 # miss rate for overall accesses -system.l2c.overall_misses 134744 # number of overall misses -system.l2c.overall_mshr_hits 15 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 411544 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.294374 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 66414 # number of overall MSHR misses +system.l2c.overall_hits 91545 # number of overall hits +system.l2c.overall_miss_latency 671597515 # number of overall miss cycles +system.l2c.overall_miss_rate 0.593978 # miss rate for overall accesses +system.l2c.overall_misses 133923 # number of overall misses +system.l2c.overall_mshr_hits 406 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 403069856 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.291656 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 65759 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_misses 121364 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses 121729 # number of overall MSHR uncacheable misses system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -941,12 +941,12 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 101153 # number of replacements -system.l2c.sampled_refs 102177 # Sample count of references to valid blocks. +system.l2c.replacements 100054 # number of replacements +system.l2c.sampled_refs 101078 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 1022.647312 # Cycle average of tags in use -system.l2c.total_refs 130499 # Total number of references to valid blocks. -system.l2c.warmup_cycle 31838 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 15786 # number of writebacks +system.l2c.tagsinuse 1023.099242 # Cycle average of tags in use +system.l2c.total_refs 131165 # Total number of references to valid blocks. +system.l2c.warmup_cycle 296156 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 16243 # number of writebacks ---------- End Simulation Statistics ---------- diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr b/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr index 16580296b..d45294bbb 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr @@ -1,74 +1,74 @@ warn: Entering event queue @ 0. Starting simulation... -system.cpu2: completed 10000 read accesses @573559 -system.cpu1: completed 10000 read accesses @574452 -system.cpu4: completed 10000 read accesses @578704 -system.cpu6: completed 10000 read accesses @579414 -system.cpu0: completed 10000 read accesses @588706 -system.cpu5: completed 10000 read accesses @590846 -system.cpu7: completed 10000 read accesses @592958 -system.cpu3: completed 10000 read accesses @604807 -system.cpu2: completed 20000 read accesses @1142209 -system.cpu1: completed 20000 read accesses @1143294 -system.cpu6: completed 20000 read accesses @1150506 -system.cpu4: completed 20000 read accesses @1152288 -system.cpu0: completed 20000 read accesses @1160537 -system.cpu3: completed 20000 read accesses @1175338 -system.cpu5: completed 20000 read accesses @1175648 -system.cpu7: completed 20000 read accesses @1180960 -system.cpu6: completed 30000 read accesses @1716218 -system.cpu3: completed 30000 read accesses @1728281 -system.cpu1: completed 30000 read accesses @1735983 -system.cpu0: completed 30000 read accesses @1736422 -system.cpu2: completed 30000 read accesses @1739692 -system.cpu4: completed 30000 read accesses @1746362 -system.cpu5: completed 30000 read accesses @1766199 -system.cpu7: completed 30000 read accesses @1783424 -system.cpu6: completed 40000 read accesses @2281651 -system.cpu0: completed 40000 read accesses @2300760 -system.cpu3: completed 40000 read accesses @2312993 -system.cpu2: completed 40000 read accesses @2314026 -system.cpu4: completed 40000 read accesses @2332178 -system.cpu1: completed 40000 read accesses @2336380 -system.cpu5: completed 40000 read accesses @2349370 -system.cpu7: completed 40000 read accesses @2365352 -system.cpu6: completed 50000 read accesses @2863317 -system.cpu0: completed 50000 read accesses @2878182 -system.cpu2: completed 50000 read accesses @2884989 -system.cpu3: completed 50000 read accesses @2897940 -system.cpu4: completed 50000 read accesses @2918842 -system.cpu1: completed 50000 read accesses @2929102 -system.cpu5: completed 50000 read accesses @2938269 -system.cpu7: completed 50000 read accesses @2944872 -system.cpu6: completed 60000 read accesses @3435715 -system.cpu2: completed 60000 read accesses @3454809 -system.cpu0: completed 60000 read accesses @3462986 -system.cpu3: completed 60000 read accesses @3485243 -system.cpu4: completed 60000 read accesses @3498361 -system.cpu1: completed 60000 read accesses @3501000 -system.cpu5: completed 60000 read accesses @3516984 -system.cpu7: completed 60000 read accesses @3517323 -system.cpu6: completed 70000 read accesses @4032530 -system.cpu0: completed 70000 read accesses @4041457 -system.cpu2: completed 70000 read accesses @4043695 -system.cpu7: completed 70000 read accesses @4070977 -system.cpu1: completed 70000 read accesses @4075964 -system.cpu4: completed 70000 read accesses @4076518 -system.cpu3: completed 70000 read accesses @4082470 -system.cpu5: completed 70000 read accesses @4104778 -system.cpu0: completed 80000 read accesses @4610101 -system.cpu2: completed 80000 read accesses @4622528 -system.cpu6: completed 80000 read accesses @4627690 -system.cpu1: completed 80000 read accesses @4654033 -system.cpu4: completed 80000 read accesses @4661016 -system.cpu3: completed 80000 read accesses @4662752 -system.cpu7: completed 80000 read accesses @4668924 -system.cpu5: completed 80000 read accesses @4689767 -system.cpu2: completed 90000 read accesses @5186824 -system.cpu0: completed 90000 read accesses @5189006 -system.cpu6: completed 90000 read accesses @5214829 -system.cpu1: completed 90000 read accesses @5229787 -system.cpu3: completed 90000 read accesses @5235400 -system.cpu4: completed 90000 read accesses @5240445 -system.cpu7: completed 90000 read accesses @5254426 -system.cpu5: completed 90000 read accesses @5292462 -system.cpu2: completed 100000 read accesses @5755736 +system.cpu7: completed 10000 read accesses @8253930 +system.cpu1: completed 10000 read accesses @8325085 +system.cpu6: completed 10000 read accesses @8427313 +system.cpu4: completed 10000 read accesses @8438233 +system.cpu2: completed 10000 read accesses @8458126 +system.cpu5: completed 10000 read accesses @8549800 +system.cpu3: completed 10000 read accesses @8559995 +system.cpu0: completed 10000 read accesses @8593654 +system.cpu7: completed 20000 read accesses @16744182 +system.cpu1: completed 20000 read accesses @16774744 +system.cpu4: completed 20000 read accesses @16786220 +system.cpu3: completed 20000 read accesses @16787358 +system.cpu5: completed 20000 read accesses @16795808 +system.cpu6: completed 20000 read accesses @16836913 +system.cpu2: completed 20000 read accesses @17031052 +system.cpu0: completed 20000 read accesses @17126654 +system.cpu5: completed 30000 read accesses @24892576 +system.cpu6: completed 30000 read accesses @24903300 +system.cpu3: completed 30000 read accesses @24935860 +system.cpu4: completed 30000 read accesses @25020642 +system.cpu1: completed 30000 read accesses @25031726 +system.cpu7: completed 30000 read accesses @25112091 +system.cpu2: completed 30000 read accesses @25235960 +system.cpu0: completed 30000 read accesses @25505209 +system.cpu5: completed 40000 read accesses @33191203 +system.cpu6: completed 40000 read accesses @33273684 +system.cpu4: completed 40000 read accesses @33345526 +system.cpu3: completed 40000 read accesses @33406412 +system.cpu7: completed 40000 read accesses @33509130 +system.cpu1: completed 40000 read accesses @33509218 +system.cpu2: completed 40000 read accesses @33664822 +system.cpu0: completed 40000 read accesses @33869626 +system.cpu5: completed 50000 read accesses @41488848 +system.cpu4: completed 50000 read accesses @41582702 +system.cpu7: completed 50000 read accesses @41828988 +system.cpu3: completed 50000 read accesses @41829496 +system.cpu1: completed 50000 read accesses @41849534 +system.cpu6: completed 50000 read accesses @41982608 +system.cpu2: completed 50000 read accesses @42197798 +system.cpu0: completed 50000 read accesses @42443468 +system.cpu5: completed 60000 read accesses @49751344 +system.cpu4: completed 60000 read accesses @49783100 +system.cpu1: completed 60000 read accesses @49918062 +system.cpu7: completed 60000 read accesses @49929008 +system.cpu3: completed 60000 read accesses @50173996 +system.cpu6: completed 60000 read accesses @50351766 +system.cpu2: completed 60000 read accesses @50352657 +system.cpu0: completed 60000 read accesses @50789771 +system.cpu4: completed 70000 read accesses @58352386 +system.cpu5: completed 70000 read accesses @58394758 +system.cpu7: completed 70000 read accesses @58570698 +system.cpu1: completed 70000 read accesses @58764169 +system.cpu3: completed 70000 read accesses @58764648 +system.cpu2: completed 70000 read accesses @58921714 +system.cpu6: completed 70000 read accesses @58929984 +system.cpu0: completed 70000 read accesses @59567320 +system.cpu1: completed 80000 read accesses @67092786 +system.cpu5: completed 80000 read accesses @67153667 +system.cpu4: completed 80000 read accesses @67153760 +system.cpu7: completed 80000 read accesses @67207042 +system.cpu3: completed 80000 read accesses @67238507 +system.cpu2: completed 80000 read accesses @67633112 +system.cpu6: completed 80000 read accesses @67664637 +system.cpu0: completed 80000 read accesses @68437288 +system.cpu1: completed 90000 read accesses @75679048 +system.cpu4: completed 90000 read accesses @75680280 +system.cpu7: completed 90000 read accesses @75751053 +system.cpu5: completed 90000 read accesses @75781514 +system.cpu3: completed 90000 read accesses @75844118 +system.cpu2: completed 90000 read accesses @76346671 +system.cpu6: completed 90000 read accesses @76491728 +system.cpu0: completed 90000 read accesses @77376872 +system.cpu1: completed 100000 read accesses @84350509 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout index ea4812a6d..fb8e47d20 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:15 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:46 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest warning: overwriting port funcmem.functional value cpu1.functional with cpu2.functional warning: overwriting port funcmem.functional value cpu2.functional with cpu3.functional @@ -16,4 +16,4 @@ warning: overwriting port funcmem.functional value cpu4.functional with cpu5.fun warning: overwriting port funcmem.functional value cpu5.functional with cpu6.functional warning: overwriting port funcmem.functional value cpu6.functional with cpu7.functional Global frequency set at 1000000000000 ticks per second -Exiting @ tick 5755736 because Maximum number of loads reached! +Exiting @ tick 84350509 because Maximum number of loads reached! diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini index a14d4767e..57b643510 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini @@ -14,16 +14,21 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=drivesys.physmem -readfile=/z/saidi/work/m5.newmem/configs/boot/netperf-server.rcS +readfile=/tmp/newmem/configs/boot/netperf-server.rcS symbolfile= system_rev=1024 system_type=34 [drivesys.bridge] type=Bridge -delay=0 -queue_size_a=16 -queue_size_b=16 +delay=50000 +fix_partial_write_a=false +fix_partial_write_b=true +nack_delay=4000 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 write_ack=false side_a=drivesys.iobus.port[0] side_b=drivesys.membus.port[0] @@ -106,6 +111,7 @@ sys=drivesys [drivesys.iobus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=true @@ -116,6 +122,7 @@ port=drivesys.bridge.side_a drivesys.tsunami.cchip.pio drivesys.tsunami.pchip.pi [drivesys.membus] type=Bus children=responder +block_size=64 bus_id=1 clock=1000 responder_set=false @@ -212,6 +219,8 @@ dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 @@ -584,6 +593,8 @@ children=configdata config_latency=20000 configdata=drivesys.tsunami.ide.configdata disks=drivesys.disk0 drivesys.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 @@ -693,16 +704,21 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=testsys.physmem -readfile=/z/saidi/work/m5.newmem/configs/boot/netperf-stream-client.rcS +readfile=/tmp/newmem/configs/boot/netperf-stream-client.rcS symbolfile= system_rev=1024 system_type=34 [testsys.bridge] type=Bridge -delay=0 -queue_size_a=16 -queue_size_b=16 +delay=50000 +fix_partial_write_a=false +fix_partial_write_b=true +nack_delay=4000 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 write_ack=false side_a=testsys.iobus.port[0] side_b=testsys.membus.port[0] @@ -785,6 +801,7 @@ sys=testsys [testsys.iobus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=true @@ -795,6 +812,7 @@ port=testsys.bridge.side_a testsys.tsunami.cchip.pio testsys.tsunami.pchip.pio t [testsys.membus] type=Bus children=responder +block_size=64 bus_id=1 clock=1000 responder_set=false @@ -891,6 +909,8 @@ dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:02 intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 @@ -1263,6 +1283,8 @@ children=configdata config_latency=20000 configdata=testsys.tsunami.ide.configdata disks=testsys.disk0 testsys.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out index f9fd380da..613664aec 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out @@ -18,7 +18,7 @@ kernel=/dist/m5/system/binaries/vmlinux console=/dist/m5/system/binaries/console pal=/dist/m5/system/binaries/ts_osfpal boot_osflags=root=/dev/hda1 console=ttyS0 -readfile=/z/saidi/work/m5.newmem/configs/boot/netperf-stream-client.rcS +readfile=/tmp/newmem/configs/boot/netperf-stream-client.rcS symbolfile= init_param=0 system_type=34 @@ -30,6 +30,7 @@ bus_id=1 clock=1000 width=64 responder_set=false +block_size=64 [testsys.intrctrl] type=IntrControl @@ -57,10 +58,15 @@ system=testsys [testsys.bridge] type=Bridge -queue_size_a=16 -queue_size_b=16 -delay=0 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +delay=50000 +nack_delay=4000 write_ack=false +fix_partial_write_a=false +fix_partial_write_b=true [testsys.disk0.image.child] type=RawDiskImage @@ -479,6 +485,8 @@ BAR5Size=0 type=NSGigE system=testsys platform=testsys.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=testsys.tsunami.ethernet.configdata pci_bus=0 pci_dev=1 @@ -601,6 +609,8 @@ BAR5Size=0 type=IdeController system=testsys platform=testsys.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=testsys.tsunami.ide.configdata pci_bus=0 pci_dev=0 @@ -615,6 +625,7 @@ bus_id=0 clock=1000 width=64 responder_set=true +block_size=64 [drivesys.physmem] type=PhysicalMemory @@ -632,7 +643,7 @@ kernel=/dist/m5/system/binaries/vmlinux console=/dist/m5/system/binaries/console pal=/dist/m5/system/binaries/ts_osfpal boot_osflags=root=/dev/hda1 console=ttyS0 -readfile=/z/saidi/work/m5.newmem/configs/boot/netperf-server.rcS +readfile=/tmp/newmem/configs/boot/netperf-server.rcS symbolfile= init_param=0 system_type=34 @@ -686,6 +697,8 @@ BAR5Size=0 type=NSGigE system=drivesys platform=drivesys.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=drivesys.tsunami.ethernet.configdata pci_bus=0 pci_dev=1 @@ -736,6 +749,7 @@ bus_id=1 clock=1000 width=64 responder_set=false +block_size=64 [drivesys.membus.responder] type=IsaFake @@ -754,10 +768,15 @@ system=drivesys [drivesys.bridge] type=Bridge -queue_size_a=16 -queue_size_b=16 -delay=0 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +delay=50000 +nack_delay=4000 write_ack=false +fix_partial_write_a=false +fix_partial_write_b=true [drivesys.disk0.image.child] type=RawDiskImage @@ -1229,6 +1248,8 @@ BAR5Size=0 type=IdeController system=drivesys platform=drivesys.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=drivesys.tsunami.ide.configdata pci_bus=0 pci_dev=0 @@ -1243,4 +1264,5 @@ bus_id=0 clock=1000 width=64 responder_set=true +block_size=64 diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt index 8ef183435..1a834ab03 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt @@ -39,12 +39,11 @@ drivesys.cpu.kern.ipl_good_0 1189 45.85% 45.85% # nu drivesys.cpu.kern.ipl_good_21 10 0.39% 46.24% # number of times we switched to this ipl from a different ipl drivesys.cpu.kern.ipl_good_22 205 7.91% 54.15% # number of times we switched to this ipl from a different ipl drivesys.cpu.kern.ipl_good_31 1189 45.85% 100.00% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_ticks 199572064520 # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks_0 199571744808 100.00% 100.00% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks 199572412849 # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks_0 199572093137 100.00% 100.00% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks_21 1620 0.00% 100.00% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks_31 300462 0.00% 100.00% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_used 0.618707 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used_0 1 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl @@ -55,13 +54,13 @@ drivesys.cpu.kern.mode_good_idle 3 drivesys.cpu.kern.mode_switch_kernel 174 # number of protection mode switches drivesys.cpu.kern.mode_switch_user 107 # number of protection mode switches drivesys.cpu.kern.mode_switch_idle 218 # number of protection mode switches -drivesys.cpu.kern.mode_switch_good 0.440882 # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good 1.645945 # fraction of useful protection mode switches drivesys.cpu.kern.mode_switch_good_kernel 0.632184 # fraction of useful protection mode switches drivesys.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches drivesys.cpu.kern.mode_switch_good_idle 0.013761 # fraction of useful protection mode switches drivesys.cpu.kern.mode_ticks_kernel 263256 0.24% 0.24% # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks_user 1278343 1.18% 1.43% # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks_idle 106485080 98.57% 100.00% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks_user 1278343 1.16% 1.40% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks_idle 108485080 98.60% 100.00% # number of ticks spent at the given mode drivesys.cpu.kern.swap_context 70 # number of times the context was actually changed drivesys.cpu.kern.syscall 22 # number of syscalls executed drivesys.cpu.kern.syscall_2 1 4.55% 4.55% # number of syscalls executed @@ -101,9 +100,9 @@ drivesys.tsunami.ethernet.coalescedTotal 1 # av drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post drivesys.tsunami.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post drivesys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post -drivesys.tsunami.ethernet.descDMAReads 5 # Number of descriptors the device read w/ DMA +drivesys.tsunami.ethernet.descDMAReads 4 # Number of descriptors the device read w/ DMA drivesys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA -drivesys.tsunami.ethernet.descDmaReadBytes 120 # number of descriptor bytes read w/ DMA +drivesys.tsunami.ethernet.descDmaReadBytes 96 # number of descriptor bytes read w/ DMA drivesys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped drivesys.tsunami.ethernet.postedInterrupts 10 # number of posts to CPU @@ -131,7 +130,7 @@ drivesys.tsunami.ethernet.totalRxOk 0 # to drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR drivesys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -drivesys.tsunami.ethernet.totalTxIdle 5 # total number of TxIdle written to ISR +drivesys.tsunami.ethernet.totalTxIdle 4 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR drivesys.tsunami.ethernet.txBandwidth 31920 # Transmit Bandwidth (bits/s) drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted @@ -140,35 +139,35 @@ drivesys.tsunami.ethernet.txPPS 25 # Pa drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -host_inst_rate 36787265 # Simulator instruction rate (inst/s) -host_mem_usage 407784 # Number of bytes of host memory used -host_seconds 7.46 # Real time elapsed on the host -host_tick_rate 26810828297 # Simulator tick rate (ticks/s) +host_inst_rate 36401739 # Simulator instruction rate (inst/s) +host_mem_usage 388436 # Number of bytes of host memory used +host_seconds 7.51 # Real time elapsed on the host +host_tick_rate 26633033203 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 274411697 # Number of instructions simulated +sim_insts 273348482 # Number of instructions simulated sim_seconds 0.200001 # Number of seconds simulated sim_ticks 200000789468 # Number of ticks simulated testsys.cpu.dtb.accesses 335402 # DTB accesses testsys.cpu.dtb.acv 161 # DTB access violations -testsys.cpu.dtb.hits 1163325 # DTB hits +testsys.cpu.dtb.hits 1163322 # DTB hits testsys.cpu.dtb.misses 3815 # DTB misses testsys.cpu.dtb.read_accesses 225414 # DTB read accesses testsys.cpu.dtb.read_acv 80 # DTB read access violations -testsys.cpu.dtb.read_hits 658458 # DTB read hits +testsys.cpu.dtb.read_hits 658456 # DTB read hits testsys.cpu.dtb.read_misses 3287 # DTB read misses testsys.cpu.dtb.write_accesses 109988 # DTB write accesses testsys.cpu.dtb.write_acv 81 # DTB write access violations -testsys.cpu.dtb.write_hits 504867 # DTB write hits +testsys.cpu.dtb.write_hits 504866 # DTB write hits testsys.cpu.dtb.write_misses 528 # DTB write misses testsys.cpu.idle_fraction 0.999999 # Percentage of idle cycles -testsys.cpu.itb.accesses 1249840 # ITB accesses +testsys.cpu.itb.accesses 1249851 # ITB accesses testsys.cpu.itb.acv 69 # ITB acv -testsys.cpu.itb.hits 1248343 # ITB hits +testsys.cpu.itb.hits 1248354 # ITB hits testsys.cpu.itb.misses 1497 # ITB misses -testsys.cpu.kern.callpal 13124 # number of callpals executed +testsys.cpu.kern.callpal 13125 # number of callpals executed testsys.cpu.kern.callpal_swpctx 438 3.34% 3.34% # number of callpals executed testsys.cpu.kern.callpal_tbi 20 0.15% 3.49% # number of callpals executed -testsys.cpu.kern.callpal_swpipl 11076 84.40% 87.88% # number of callpals executed +testsys.cpu.kern.callpal_swpipl 11077 84.40% 87.89% # number of callpals executed testsys.cpu.kern.callpal_rdps 359 2.74% 90.62% # number of callpals executed testsys.cpu.kern.callpal_wrusp 3 0.02% 90.64% # number of callpals executed testsys.cpu.kern.callpal_rdusp 3 0.02% 90.67% # number of callpals executed @@ -176,41 +175,40 @@ testsys.cpu.kern.callpal_rti 1041 7.93% 98.60% # nu testsys.cpu.kern.callpal_callsys 140 1.07% 99.66% # number of callpals executed testsys.cpu.kern.callpal_imb 44 0.34% 100.00% # number of callpals executed testsys.cpu.kern.inst.arm 0 # number of arm instructions executed -testsys.cpu.kern.inst.hwrei 19055 # number of hwrei instructions executed -testsys.cpu.kern.inst.quiesce 377 # number of quiesce instructions executed -testsys.cpu.kern.ipl_count 12506 # number of times we switched to this ipl +testsys.cpu.kern.inst.hwrei 19056 # number of hwrei instructions executed +testsys.cpu.kern.inst.quiesce 376 # number of quiesce instructions executed +testsys.cpu.kern.ipl_count 12507 # number of times we switched to this ipl testsys.cpu.kern.ipl_count_0 5061 40.47% 40.47% # number of times we switched to this ipl testsys.cpu.kern.ipl_count_21 184 1.47% 41.94% # number of times we switched to this ipl testsys.cpu.kern.ipl_count_22 205 1.64% 43.58% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count_31 7056 56.42% 100.00% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count_31 7057 56.42% 100.00% # number of times we switched to this ipl testsys.cpu.kern.ipl_good 10499 # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good_0 5055 48.15% 48.15% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good_21 184 1.75% 49.90% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good_22 205 1.95% 51.85% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good_31 5055 48.15% 100.00% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_ticks 199569922466 # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks_0 199569307215 100.00% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks 199570420798 # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks_0 199569805534 100.00% 100.00% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_ticks_21 31026 0.00% 100.00% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks_31 566595 0.00% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_used 0.839517 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_ticks_31 566608 0.00% 100.00% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_used_0 0.998814 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used_31 0.716412 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.mode_good_kernel 654 -testsys.cpu.kern.mode_good_user 649 +testsys.cpu.kern.ipl_used_31 0.716310 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.mode_good_kernel 655 +testsys.cpu.kern.mode_good_user 650 testsys.cpu.kern.mode_good_idle 5 -testsys.cpu.kern.mode_switch_kernel 1099 # number of protection mode switches -testsys.cpu.kern.mode_switch_user 649 # number of protection mode switches -testsys.cpu.kern.mode_switch_idle 381 # number of protection mode switches -testsys.cpu.kern.mode_switch_good 0.614373 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good_kernel 0.595086 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_kernel 1100 # number of protection mode switches +testsys.cpu.kern.mode_switch_user 650 # number of protection mode switches +testsys.cpu.kern.mode_switch_idle 380 # number of protection mode switches +testsys.cpu.kern.mode_switch_good 1.608612 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good_kernel 0.595455 # fraction of useful protection mode switches testsys.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good_idle 0.013123 # fraction of useful protection mode switches -testsys.cpu.kern.mode_ticks_kernel 1821131 2.16% 2.16% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks_user 1065606 1.26% 3.42% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks_idle 81402279 96.58% 100.00% # number of ticks spent at the given mode +testsys.cpu.kern.mode_switch_good_idle 0.013158 # fraction of useful protection mode switches +testsys.cpu.kern.mode_ticks_kernel 1822940 2.12% 2.12% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks_user 1065616 1.24% 3.36% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks_idle 83000460 96.64% 100.00% # number of ticks spent at the given mode testsys.cpu.kern.swap_context 438 # number of times the context was actually changed testsys.cpu.kern.syscall 83 # number of syscalls executed testsys.cpu.kern.syscall_2 3 3.61% 3.61% # number of syscalls executed @@ -235,9 +233,9 @@ testsys.cpu.kern.syscall_104 1 1.20% 93.98% # nu testsys.cpu.kern.syscall_105 3 3.61% 97.59% # number of syscalls executed testsys.cpu.kern.syscall_118 2 2.41% 100.00% # number of syscalls executed testsys.cpu.not_idle_fraction 0.000001 # Percentage of non-idle cycles -testsys.cpu.numCycles 3566068 # number of cpu cycles simulated -testsys.cpu.num_insts 3564502 # Number of instructions executed -testsys.cpu.num_refs 1173608 # Number of memory references +testsys.cpu.numCycles 3566060 # number of cpu cycles simulated +testsys.cpu.num_insts 3564494 # Number of instructions executed +testsys.cpu.num_refs 1173605 # Number of memory references testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -259,9 +257,9 @@ testsys.tsunami.ethernet.coalescedTotal 1 # av testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post -testsys.tsunami.ethernet.descDMAReads 8 # Number of descriptors the device read w/ DMA +testsys.tsunami.ethernet.descDMAReads 6 # Number of descriptors the device read w/ DMA testsys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA -testsys.tsunami.ethernet.descDmaReadBytes 192 # number of descriptor bytes read w/ DMA +testsys.tsunami.ethernet.descDmaReadBytes 144 # number of descriptor bytes read w/ DMA testsys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped testsys.tsunami.ethernet.postedInterrupts 10 # number of posts to CPU @@ -289,7 +287,7 @@ testsys.tsunami.ethernet.totalRxOk 0 # to testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR testsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -testsys.tsunami.ethernet.totalTxIdle 8 # total number of TxIdle written to ISR +testsys.tsunami.ethernet.totalTxIdle 6 # total number of TxIdle written to ISR testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR testsys.tsunami.ethernet.txBandwidth 38400 # Transmit Bandwidth (bits/s) testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted @@ -383,12 +381,12 @@ drivesys.tsunami.ethernet.totalSwi 0 # to drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -host_inst_rate 80923531996 # Simulator instruction rate (inst/s) -host_mem_usage 407784 # Number of bytes of host memory used +host_inst_rate 79025291125 # Simulator instruction rate (inst/s) +host_mem_usage 388436 # Number of bytes of host memory used host_seconds 0.00 # Real time elapsed on the host -host_tick_rate 216582530 # Simulator tick rate (ticks/s) +host_tick_rate 211511841 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 274411697 # Number of instructions simulated +sim_insts 273348482 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated sim_ticks 785978 # Number of ticks simulated testsys.cpu.dtb.accesses 0 # DTB accesses diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr index 8fb9590c3..045c1ddf7 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr @@ -1,6 +1,6 @@ Listening for testsys connection on port 3456 -Listening for drivesys connection on port 3457 -0: testsys.remote_gdb.listener: listening for remote gdb #0 on port 7000 -0: drivesys.remote_gdb.listener: listening for remote gdb #1 on port 7001 +Listening for drivesys connection on port 3458 +0: testsys.remote_gdb.listener: listening for remote gdb on port 7000 +0: drivesys.remote_gdb.listener: listening for remote gdb on port 7003 warn: Entering event queue @ 0. Starting simulation... warn: Obsolete M5 instruction ivlb encountered. diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout index 4fb87de69..4f93fd528 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout @@ -5,11 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 30 2007 13:38:38 -M5 started Mon Apr 30 14:01:42 2007 -M5 executing on zeep -command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic +M5 compiled May 15 2007 19:06:05 +M5 started Tue May 15 19:12:37 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second - 0: testsys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 - 0: drivesys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Exiting @ tick 4300236342388 because checkpoint +Exiting @ tick 4300235844056 because checkpoint From a8278c3bde2ba9abc2820afafa9d0e766e36b2c8 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Wed, 16 May 2007 19:09:18 -0700 Subject: [PATCH 68/68] Update the release notes for the 2.0 beta 3 release --HG-- extra : convert_revision : 708ba7a5878ad60317e527830b54c4fe62f70454 --- RELEASE_NOTES | 43 ++++++++++++++++++++++++------------------- 1 file changed, 24 insertions(+), 19 deletions(-) diff --git a/RELEASE_NOTES b/RELEASE_NOTES index 1c781ac29..e91f5432d 100644 --- a/RELEASE_NOTES +++ b/RELEASE_NOTES @@ -1,32 +1,37 @@ Outstanding issues for 2.0 release: -------------------- -1. Better statistics for the caches. -2. Clean up more SimObject parameter stuff -3. Checkpoint/switchover testing -4. FS mode doesn't work under Cygwin -5. memtest regression crashes under Cygwin -6. Make repository public -7. Testing -8. Validation -9. Testing +1. Fix multi-level coherence/dma issues +2. Fix O3 CPU bug in SE 40.perlbmk fails +3. Fix O3 processing nacks/coherence messages +4. Better statistics for the caches. +5. Clean up more SimObject parameter stuff +6. Checkpoint/switchover testing +7. FS mode doesn't work under Cygwin +8. memtest regression crashes under Cygwin +9. Make repository public +10. Testing +11. Validation +12. Testing -May XX, 2007: m5_2.0_beta3 +May 16, 2007: m5_2.0_beta3 -------------------- New Features 1. Some support for SPARC full-system simulation +2. Reworking of trace facitities (parameter names changed, variadic macros + removed) +3. Scons script cleanups +4. Some support for compiling with Intel CC Bug fixes since beta 2: 1. Many SPARC linux syscall emulation support fixes 2. Multiprocessor linux boot using the detailed O3 CPU module -3. Simulator performance and memory leak fixes -4. Fixed issue where console could stop printing in ALPHA_FS -5. Fix issues with remote debugging -6. Several compile fixes, including gcc 4.1 -7. Reworking of trace facitities (parameter names changed, variadic macros removed) -8. Scons script cleanups -9. Some support for compiling with Intel CC -10. Many other minor fixes and enhancements - +3. Workaround for DMA bug (final solution to be released with 2.0f) +4. Simulator performance and memory leak fixes +5. Fixed issue where console could stop printing in ALPHA_FS +6. Fix issues with remote debugging +7. Several compile fixes, including gcc 4.1 +8. Many other minor fixes and enhancements + Nov. 28, 2006: m5_2.0_beta2 -------------------- Bug fixes since beta 1: