fix interrupting during a quisce on sparc
src/arch/sparc/ua2005.cc: fix interrupting when quisced. Since sticks correspond to instructions when not quisced we need to check if were suspended and interrupt at the guess time src/base/traceflags.py: add trace flag for Iob src/cpu/simple/base.cc: Use Quisce instead of IPI trace flag src/dev/sparc/iob.cc: add some Dprintfs --HG-- extra : convert_revision : 72e18fcc750ad1e4b2bb67b19b354eaffc6af6d5
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@ -195,6 +195,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
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panic("No support for setting spec_en bit\n");
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panic("No support for setting spec_en bit\n");
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setRegNoEffect(miscReg, bits(val,0,0));
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setRegNoEffect(miscReg, bits(val,0,0));
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if (!bits(val,0,0)) {
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if (!bits(val,0,0)) {
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DPRINTF(Quiesce, "Cpu executed quiescing instruction\n");
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// Time to go to sleep
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// Time to go to sleep
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tc->suspend();
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tc->suspend();
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if (tc->getKernelStats())
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if (tc->getKernelStats())
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@ -307,7 +308,7 @@ MiscRegFile::processSTickCompare(ThreadContext *tc)
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tc->getCpuPtr()->instCount();
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tc->getCpuPtr()->instCount();
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assert(ticks >= 0 && "stick compare missed interrupt cycle");
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assert(ticks >= 0 && "stick compare missed interrupt cycle");
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if (ticks == 0) {
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if (ticks == 0 || tc->status() == ThreadContext::Suspended) {
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DPRINTF(Timer, "STick compare cycle reached at %#x\n",
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DPRINTF(Timer, "STick compare cycle reached at %#x\n",
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(stick_cmpr & mask(63)));
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(stick_cmpr & mask(63)));
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if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
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if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
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@ -324,11 +325,15 @@ MiscRegFile::processHSTickCompare(ThreadContext *tc)
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// we're actually at the correct cycle or we need to wait a little while
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// we're actually at the correct cycle or we need to wait a little while
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// more
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// more
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int ticks;
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int ticks;
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if ( tc->status() == ThreadContext::Halted ||
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tc->status() == ThreadContext::Unallocated)
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return;
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ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
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ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
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tc->getCpuPtr()->instCount();
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tc->getCpuPtr()->instCount();
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assert(ticks >= 0 && "hstick compare missed interrupt cycle");
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assert(ticks >= 0 && "hstick compare missed interrupt cycle");
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if (ticks == 0) {
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if (ticks == 0 || tc->status() == ThreadContext::Suspended) {
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DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
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DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
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(stick_cmpr & mask(63)));
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(stick_cmpr & mask(63)));
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if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) {
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if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) {
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@ -116,6 +116,7 @@ baseFlags = [
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'ISP',
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'ISP',
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'IdeCtrl',
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'IdeCtrl',
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'IdeDisk',
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'IdeDisk',
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'Iob',
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'Interrupt',
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'Interrupt',
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'LLSC',
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'LLSC',
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'LSQ',
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'LSQ',
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@ -301,7 +301,7 @@ BaseSimpleCPU::post_interrupt(int int_num, int index)
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BaseCPU::post_interrupt(int_num, index);
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BaseCPU::post_interrupt(int_num, index);
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if (thread->status() == ThreadContext::Suspended) {
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if (thread->status() == ThreadContext::Suspended) {
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DPRINTF(IPI,"Suspended Processor awoke\n");
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DPRINTF(Quiesce,"Suspended Processor awoke\n");
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thread->activate();
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thread->activate();
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}
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}
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}
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}
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@ -192,6 +192,8 @@ Iob::writeIob(PacketPtr pkt)
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data = pkt->get<uint64_t>();
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data = pkt->get<uint64_t>();
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intMan[index].cpu = bits(data,12,8);
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intMan[index].cpu = bits(data,12,8);
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intMan[index].vector = bits(data,5,0);
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intMan[index].vector = bits(data,5,0);
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DPRINTF(Iob, "Wrote IntMan %d cpu %d, vec %d\n", index,
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intMan[index].cpu, intMan[index].vector);
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return;
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return;
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}
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}
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@ -201,11 +203,14 @@ Iob::writeIob(PacketPtr pkt)
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intCtl[index].mask = bits(data,2,2);
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intCtl[index].mask = bits(data,2,2);
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if (bits(data,1,1))
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if (bits(data,1,1))
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intCtl[index].pend = false;
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intCtl[index].pend = false;
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DPRINTF(Iob, "Wrote IntCtl %d pend %d cleared %d\n", index,
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intCtl[index].pend, bits(data,2,2));
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return;
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return;
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}
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}
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if (accessAddr == JIntVecAddr) {
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if (accessAddr == JIntVecAddr) {
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jIntVec = bits(pkt->get<uint64_t>(), 5,0);
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jIntVec = bits(pkt->get<uint64_t>(), 5,0);
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DPRINTF(Iob, "Wrote jIntVec %d\n", jIntVec);
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return;
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return;
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}
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}
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@ -237,11 +242,15 @@ Iob::writeJBus(PacketPtr pkt)
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index = (accessAddr - JIntBusyAddr) >> 3;
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index = (accessAddr - JIntBusyAddr) >> 3;
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data = pkt->get<uint64_t>();
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data = pkt->get<uint64_t>();
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jIntBusy[index].busy = bits(data,5,5);
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jIntBusy[index].busy = bits(data,5,5);
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DPRINTF(Iob, "Wrote jIntBusy index %d busy: %d\n", index,
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jIntBusy[index].busy);
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return;
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return;
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}
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}
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if (accessAddr == JIntABusyAddr) {
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if (accessAddr == JIntABusyAddr) {
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data = pkt->get<uint64_t>();
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data = pkt->get<uint64_t>();
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jIntBusy[cpuid].busy = bits(data,5,5);
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jIntBusy[cpuid].busy = bits(data,5,5);
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DPRINTF(Iob, "Wrote jIntBusy index %d busy: %d\n", cpuid,
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jIntBusy[cpuid].busy);
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return;
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return;
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};
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};
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@ -256,6 +265,8 @@ Iob::receiveDeviceInterrupt(DeviceId devid)
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return;
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return;
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intCtl[devid].mask = true;
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intCtl[devid].mask = true;
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intCtl[devid].pend = true;
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intCtl[devid].pend = true;
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DPRINTF(Iob, "Receiving Device interrupt: %d for cpu %d vec %d\n",
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devid, intMan[devid].cpu, intMan[devid].vector);
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ic->post(intMan[devid].cpu, SparcISA::IT_INT_VEC, intMan[devid].vector);
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ic->post(intMan[devid].cpu, SparcISA::IT_INT_VEC, intMan[devid].vector);
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}
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}
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@ -269,6 +280,8 @@ Iob::generateIpi(Type type, int cpu_id, int vector)
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switch (type) {
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switch (type) {
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case 0: // interrupt
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case 0: // interrupt
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DPRINTF(Iob, "Generating interrupt because of I/O write to cpu: %d vec %d\n",
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cpu_id, vector);
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ic->post(cpu_id, SparcISA::IT_INT_VEC, vector);
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ic->post(cpu_id, SparcISA::IT_INT_VEC, vector);
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break;
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break;
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case 1: // reset
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case 1: // reset
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@ -279,9 +292,11 @@ Iob::generateIpi(Type type, int cpu_id, int vector)
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sys->threadContexts[cpu_id]->activate();
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sys->threadContexts[cpu_id]->activate();
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break;
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break;
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case 2: // idle -- this means stop executing and don't wake on interrupts
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case 2: // idle -- this means stop executing and don't wake on interrupts
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DPRINTF(Iob, "Idling CPU because of I/O write cpu: %d\n", cpu_id);
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sys->threadContexts[cpu_id]->halt();
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sys->threadContexts[cpu_id]->halt();
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break;
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break;
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case 3: // resume
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case 3: // resume
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DPRINTF(Iob, "Resuming CPU because of I/O write cpu: %d\n", cpu_id);
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sys->threadContexts[cpu_id]->activate();
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sys->threadContexts[cpu_id]->activate();
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break;
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break;
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default:
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default:
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@ -297,6 +312,9 @@ Iob::receiveJBusInterrupt(int cpu_id, int source, uint64_t d0, uint64_t d1)
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if (jIntBusy[cpu_id].busy)
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if (jIntBusy[cpu_id].busy)
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return false;
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return false;
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DPRINTF(Iob, "Receiving jBus interrupt: %d for cpu %d vec %d\n",
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source, cpu_id, jIntVec);
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jIntBusy[cpu_id].busy = true;
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jIntBusy[cpu_id].busy = true;
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jIntBusy[cpu_id].source = source;
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jIntBusy[cpu_id].source = source;
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jBusData0[cpu_id] = d0;
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jBusData0[cpu_id] = d0;
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