Stats reset, profiling stuff.
cpu/base.cc: Be sure to deschedule the profile event so it doesn't take profiles while the CPU is switched out. Also include the option to reset stats at a specific instruction. cpu/base.hh: Include the option to reset stats at a specific instruction. cpu/checker/cpu_builder.cc: Handle stats reset inst. cpu/o3/alpha_cpu_builder.cc: Handle stats reset inst, allow for profiling. cpu/ozone/cpu_builder.cc: Handle profiling, stats reset event, slightly different parameters. python/m5/objects/BaseCPU.py: Add in stats reset. --HG-- extra : convert_revision : e27a78f7fb8fd19c53d9f2c1e6edce4a98cbafdb
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cpu/base.cc
29
cpu/base.cc
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@ -45,6 +45,9 @@
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#include "base/trace.hh"
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#include "base/trace.hh"
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// Hack
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#include "sim/stat_control.hh"
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using namespace std;
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using namespace std;
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vector<BaseCPU *> BaseCPU::cpuList;
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vector<BaseCPU *> BaseCPU::cpuList;
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@ -84,6 +87,7 @@ BaseCPU::BaseCPU(Params *p)
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number_of_threads(p->numberOfThreads)
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number_of_threads(p->numberOfThreads)
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#endif
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#endif
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{
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{
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// currentTick = curTick;
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DPRINTF(FullCPU, "BaseCPU: Creating object, mem address %#x.\n", this);
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DPRINTF(FullCPU, "BaseCPU: Creating object, mem address %#x.\n", this);
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// add self to global list of CPUs
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// add self to global list of CPUs
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@ -145,6 +149,12 @@ BaseCPU::BaseCPU(Params *p)
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p->max_loads_all_threads, *counter);
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p->max_loads_all_threads, *counter);
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}
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}
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if (p->stats_reset_inst != 0) {
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Stats::SetupEvent(Stats::Reset, p->stats_reset_inst, 0, comInstEventQueue[0]);
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cprintf("Stats reset event scheduled for %lli insts\n",
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p->stats_reset_inst);
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}
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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memset(interrupts, 0, sizeof(interrupts));
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memset(interrupts, 0, sizeof(interrupts));
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intstatus = 0;
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intstatus = 0;
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@ -261,12 +271,17 @@ BaseCPU::registerExecContexts()
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void
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void
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BaseCPU::switchOut(Sampler *sampler)
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BaseCPU::switchOut(Sampler *sampler)
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{
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{
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panic("This CPU doesn't support sampling!");
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// panic("This CPU doesn't support sampling!");
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#if FULL_SYSTEM
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if (profileEvent && profileEvent->scheduled())
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profileEvent->deschedule();
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#endif
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}
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}
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void
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void
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BaseCPU::takeOverFrom(BaseCPU *oldCPU)
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BaseCPU::takeOverFrom(BaseCPU *oldCPU)
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{
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{
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// currentTick = oldCPU->currentTick;
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assert(execContexts.size() == oldCPU->execContexts.size());
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assert(execContexts.size() == oldCPU->execContexts.size());
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for (int i = 0; i < execContexts.size(); ++i) {
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for (int i = 0; i < execContexts.size(); ++i) {
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@ -281,18 +296,22 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
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assert(newXC->getProcessPtr() == oldXC->getProcessPtr());
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assert(newXC->getProcessPtr() == oldXC->getProcessPtr());
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newXC->getProcessPtr()->replaceExecContext(newXC, newXC->readCpuId());
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newXC->getProcessPtr()->replaceExecContext(newXC, newXC->readCpuId());
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#endif
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#endif
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// TheISA::compareXCs(oldXC, newXC);
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}
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}
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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for (int i = 0; i < TheISA::NumInterruptLevels; ++i)
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for (int i = 0; i < TheISA::NumInterruptLevels; ++i)
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interrupts[i] = oldCPU->interrupts[i];
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interrupts[i] = oldCPU->interrupts[i];
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intstatus = oldCPU->intstatus;
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intstatus = oldCPU->intstatus;
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checkInterrupts = oldCPU->checkInterrupts;
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for (int i = 0; i < execContexts.size(); ++i)
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// for (int i = 0; i < execContexts.size(); ++i)
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execContexts[i]->profileClear();
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// execContexts[i]->profileClear();
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if (profileEvent)
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// The Sampler must take care of this!
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profileEvent->schedule(curTick);
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// if (profileEvent)
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// profileEvent->schedule(curTick);
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#endif
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#endif
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}
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}
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@ -67,9 +67,11 @@ class BaseCPU : public SimObject
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Tick clock;
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Tick clock;
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public:
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public:
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// Tick currentTick;
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inline Tick frequency() const { return Clock::Frequency / clock; }
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inline Tick frequency() const { return Clock::Frequency / clock; }
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inline Tick cycles(int numCycles) const { return clock * numCycles; }
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inline Tick cycles(int numCycles) const { return clock * numCycles; }
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inline Tick curCycle() const { return curTick / clock; }
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inline Tick curCycle() const { return curTick / clock; }
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// inline Tick curCycle() { currentTick+=10000; return currentTick; }
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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protected:
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protected:
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@ -134,6 +136,7 @@ class BaseCPU : public SimObject
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Counter max_insts_all_threads;
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Counter max_insts_all_threads;
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Counter max_loads_any_thread;
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Counter max_loads_any_thread;
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Counter max_loads_all_threads;
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Counter max_loads_all_threads;
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Counter stats_reset_inst;
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Tick clock;
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Tick clock;
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bool functionTrace;
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bool functionTrace;
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Tick functionTraceStart;
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Tick functionTraceStart;
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@ -58,6 +58,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker)
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Param<Counter> max_insts_all_threads;
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Param<Counter> max_insts_all_threads;
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Param<Counter> max_loads_any_thread;
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Param<Counter> max_loads_any_thread;
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Param<Counter> max_loads_all_threads;
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Param<Counter> max_loads_all_threads;
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Param<Counter> stats_reset_inst;
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Param<Tick> progress_interval;
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Param<Tick> progress_interval;
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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@ -92,6 +93,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(OzoneChecker)
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"terminate when any thread reaches this load count"),
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"terminate when any thread reaches this load count"),
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INIT_PARAM(max_loads_all_threads,
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INIT_PARAM(max_loads_all_threads,
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"terminate when all threads have reached this load count"),
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"terminate when all threads have reached this load count"),
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INIT_PARAM(stats_reset_inst,
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"blah"),
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INIT_PARAM_DFLT(progress_interval, "CPU Progress Interval", 0),
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INIT_PARAM_DFLT(progress_interval, "CPU Progress Interval", 0),
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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@ -127,6 +130,7 @@ CREATE_SIM_OBJECT(OzoneChecker)
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params->max_insts_all_threads = 0;
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params->max_insts_all_threads = 0;
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params->max_loads_any_thread = 0;
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params->max_loads_any_thread = 0;
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params->max_loads_all_threads = 0;
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params->max_loads_all_threads = 0;
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params->stats_reset_inst = 0;
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params->exitOnError = exitOnError;
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params->exitOnError = exitOnError;
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params->updateOnError = updateOnError;
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params->updateOnError = updateOnError;
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params->deferRegistration = defer_registration;
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params->deferRegistration = defer_registration;
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temp = max_loads_all_threads;
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temp = max_loads_all_threads;
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Tick temp2 = progress_interval;
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Tick temp2 = progress_interval;
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temp2++;
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temp2++;
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params->progress_interval = 0;
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BaseMem *cache = icache;
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BaseMem *cache = icache;
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cache = dcache;
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cache = dcache;
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@ -55,6 +55,7 @@ SimObjectParam<System *> system;
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Param<int> cpu_id;
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Param<int> cpu_id;
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SimObjectParam<AlphaITB *> itb;
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SimObjectParam<AlphaITB *> itb;
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SimObjectParam<AlphaDTB *> dtb;
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SimObjectParam<AlphaDTB *> dtb;
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Param<Tick> profile;
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#else
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#else
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SimObjectVectorParam<Process *> workload;
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SimObjectVectorParam<Process *> workload;
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//SimObjectParam<PageTable *> page_table;
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//SimObjectParam<PageTable *> page_table;
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@ -68,6 +69,7 @@ Param<Counter> max_insts_any_thread;
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Param<Counter> max_insts_all_threads;
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Param<Counter> max_insts_all_threads;
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Param<Counter> max_loads_any_thread;
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Param<Counter> max_loads_any_thread;
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Param<Counter> max_loads_all_threads;
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Param<Counter> max_loads_all_threads;
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Param<Counter> stats_reset_inst;
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Param<Tick> progress_interval;
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Param<Tick> progress_interval;
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SimObjectParam<BaseCache *> icache;
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SimObjectParam<BaseCache *> icache;
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INIT_PARAM(cpu_id, "processor ID"),
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INIT_PARAM(cpu_id, "processor ID"),
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INIT_PARAM(itb, "Instruction translation buffer"),
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INIT_PARAM(itb, "Instruction translation buffer"),
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INIT_PARAM(dtb, "Data translation buffer"),
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INIT_PARAM(dtb, "Data translation buffer"),
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INIT_PARAM(profile, ""),
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#else
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#else
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INIT_PARAM(workload, "Processes to run"),
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INIT_PARAM(workload, "Processes to run"),
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// INIT_PARAM(page_table, "Page table"),
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// INIT_PARAM(page_table, "Page table"),
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"Terminate when all threads have reached this load"
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"Terminate when all threads have reached this load"
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"count",
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"count",
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0),
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0),
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INIT_PARAM_DFLT(stats_reset_inst,
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"blah",
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0),
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INIT_PARAM_DFLT(progress_interval, "Progress interval", 0),
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INIT_PARAM_DFLT(progress_interval, "Progress interval", 0),
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INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
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INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
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params->cpu_id = cpu_id;
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params->cpu_id = cpu_id;
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params->itb = itb;
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params->itb = itb;
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params->dtb = dtb;
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params->dtb = dtb;
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params->profile = profile;
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#else
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#else
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params->workload = workload;
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params->workload = workload;
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// params->pTable = page_table;
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// params->pTable = page_table;
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params->max_insts_all_threads = max_insts_all_threads;
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params->max_insts_all_threads = max_insts_all_threads;
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params->max_loads_any_thread = max_loads_any_thread;
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params->max_loads_any_thread = max_loads_any_thread;
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params->max_loads_all_threads = max_loads_all_threads;
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params->max_loads_all_threads = max_loads_all_threads;
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params->stats_reset_inst = stats_reset_inst;
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params->progress_interval = progress_interval;
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params->progress_interval = progress_interval;
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//
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//
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Param<int> cpu_id;
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Param<int> cpu_id;
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SimObjectParam<AlphaITB *> itb;
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SimObjectParam<AlphaITB *> itb;
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SimObjectParam<AlphaDTB *> dtb;
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SimObjectParam<AlphaDTB *> dtb;
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Param<Tick> profile;
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#else
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#else
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SimObjectVectorParam<Process *> workload;
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SimObjectVectorParam<Process *> workload;
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//SimObjectParam<PageTable *> page_table;
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//SimObjectParam<PageTable *> page_table;
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@ -84,6 +85,7 @@ Param<Counter> max_insts_any_thread;
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Param<Counter> max_insts_all_threads;
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Param<Counter> max_insts_all_threads;
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Param<Counter> max_loads_any_thread;
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Param<Counter> max_loads_any_thread;
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Param<Counter> max_loads_all_threads;
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Param<Counter> max_loads_all_threads;
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Param<Counter> stats_reset_inst;
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Param<Tick> progress_interval;
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Param<Tick> progress_interval;
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SimObjectParam<BaseCache *> icache;
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SimObjectParam<BaseCache *> icache;
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@ -91,10 +93,11 @@ SimObjectParam<BaseCache *> dcache;
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Param<unsigned> cachePorts;
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Param<unsigned> cachePorts;
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Param<unsigned> width;
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Param<unsigned> width;
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Param<unsigned> frontEndLatency;
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Param<unsigned> frontEndWidth;
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Param<unsigned> frontEndWidth;
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Param<unsigned> backEndLatency;
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Param<unsigned> backEndWidth;
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Param<unsigned> backEndWidth;
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Param<unsigned> backEndSquashLatency;
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Param<unsigned> backEndSquashLatency;
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Param<unsigned> backEndLatency;
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Param<unsigned> maxInstBufferSize;
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Param<unsigned> maxInstBufferSize;
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Param<unsigned> numPhysicalRegs;
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Param<unsigned> numPhysicalRegs;
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Param<unsigned> maxOutstandingMemOps;
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Param<unsigned> maxOutstandingMemOps;
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@ -149,6 +152,7 @@ Param<unsigned> RASSize;
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Param<unsigned> LQEntries;
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Param<unsigned> LQEntries;
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Param<unsigned> SQEntries;
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Param<unsigned> SQEntries;
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Param<bool> lsqLimits;
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Param<unsigned> LFSTSize;
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Param<unsigned> LFSTSize;
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Param<unsigned> SSITSize;
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Param<unsigned> SSITSize;
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INIT_PARAM(cpu_id, "processor ID"),
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INIT_PARAM(cpu_id, "processor ID"),
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INIT_PARAM(itb, "Instruction translation buffer"),
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INIT_PARAM(itb, "Instruction translation buffer"),
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INIT_PARAM(dtb, "Data translation buffer"),
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INIT_PARAM(dtb, "Data translation buffer"),
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INIT_PARAM(profile, ""),
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#else
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#else
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INIT_PARAM(workload, "Processes to run"),
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INIT_PARAM(workload, "Processes to run"),
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// INIT_PARAM(page_table, "Page table"),
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// INIT_PARAM(page_table, "Page table"),
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@ -213,6 +218,9 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
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"Terminate when all threads have reached this load"
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"Terminate when all threads have reached this load"
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"count",
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"count",
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0),
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0),
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INIT_PARAM_DFLT(stats_reset_inst,
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"blah",
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0),
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INIT_PARAM_DFLT(progress_interval, "Progress interval", 0),
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INIT_PARAM_DFLT(progress_interval, "Progress interval", 0),
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INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
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INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
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@ -220,10 +228,11 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
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INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
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INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
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INIT_PARAM_DFLT(width, "Width", 1),
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INIT_PARAM_DFLT(width, "Width", 1),
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INIT_PARAM_DFLT(frontEndLatency, "Front end latency", 1),
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INIT_PARAM_DFLT(frontEndWidth, "Front end width", 1),
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INIT_PARAM_DFLT(frontEndWidth, "Front end width", 1),
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INIT_PARAM_DFLT(backEndLatency, "Back end latency", 1),
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INIT_PARAM_DFLT(backEndWidth, "Back end width", 1),
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INIT_PARAM_DFLT(backEndWidth, "Back end width", 1),
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INIT_PARAM_DFLT(backEndSquashLatency, "Back end squash latency", 1),
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INIT_PARAM_DFLT(backEndSquashLatency, "Back end squash latency", 1),
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INIT_PARAM_DFLT(backEndLatency, "Back end latency", 1),
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INIT_PARAM_DFLT(maxInstBufferSize, "Maximum instruction buffer size", 16),
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INIT_PARAM_DFLT(maxInstBufferSize, "Maximum instruction buffer size", 16),
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INIT_PARAM(numPhysicalRegs, "Number of physical registers"),
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INIT_PARAM(numPhysicalRegs, "Number of physical registers"),
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INIT_PARAM_DFLT(maxOutstandingMemOps, "Maximum outstanding memory operations", 4),
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INIT_PARAM_DFLT(maxOutstandingMemOps, "Maximum outstanding memory operations", 4),
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@ -284,6 +293,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
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INIT_PARAM(LQEntries, "Number of load queue entries"),
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INIT_PARAM(LQEntries, "Number of load queue entries"),
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INIT_PARAM(SQEntries, "Number of store queue entries"),
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INIT_PARAM(SQEntries, "Number of store queue entries"),
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INIT_PARAM_DFLT(lsqLimits, "LSQ size limits dispatch", true),
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INIT_PARAM(LFSTSize, "Last fetched store table size"),
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INIT_PARAM(LFSTSize, "Last fetched store table size"),
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INIT_PARAM(SSITSize, "Store set ID table size"),
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INIT_PARAM(SSITSize, "Store set ID table size"),
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@ -346,6 +356,7 @@ CREATE_SIM_OBJECT(DerivOzoneCPU)
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params->cpu_id = cpu_id;
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params->cpu_id = cpu_id;
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params->itb = itb;
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params->itb = itb;
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params->dtb = dtb;
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params->dtb = dtb;
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params->profile = profile;
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#else
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#else
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params->workload = workload;
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params->workload = workload;
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// params->pTable = page_table;
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// params->pTable = page_table;
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@ -357,6 +368,7 @@ CREATE_SIM_OBJECT(DerivOzoneCPU)
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params->max_insts_all_threads = max_insts_all_threads;
|
params->max_insts_all_threads = max_insts_all_threads;
|
||||||
params->max_loads_any_thread = max_loads_any_thread;
|
params->max_loads_any_thread = max_loads_any_thread;
|
||||||
params->max_loads_all_threads = max_loads_all_threads;
|
params->max_loads_all_threads = max_loads_all_threads;
|
||||||
|
params->stats_reset_inst = stats_reset_inst;
|
||||||
params->progress_interval = progress_interval;
|
params->progress_interval = progress_interval;
|
||||||
|
|
||||||
//
|
//
|
||||||
|
@ -368,6 +380,7 @@ CREATE_SIM_OBJECT(DerivOzoneCPU)
|
||||||
|
|
||||||
params->width = width;
|
params->width = width;
|
||||||
params->frontEndWidth = frontEndWidth;
|
params->frontEndWidth = frontEndWidth;
|
||||||
|
params->frontEndLatency = frontEndLatency;
|
||||||
params->backEndWidth = backEndWidth;
|
params->backEndWidth = backEndWidth;
|
||||||
params->backEndSquashLatency = backEndSquashLatency;
|
params->backEndSquashLatency = backEndSquashLatency;
|
||||||
params->backEndLatency = backEndLatency;
|
params->backEndLatency = backEndLatency;
|
||||||
|
@ -425,6 +438,7 @@ CREATE_SIM_OBJECT(DerivOzoneCPU)
|
||||||
|
|
||||||
params->LQEntries = LQEntries;
|
params->LQEntries = LQEntries;
|
||||||
params->SQEntries = SQEntries;
|
params->SQEntries = SQEntries;
|
||||||
|
params->lsqLimits = lsqLimits;
|
||||||
|
|
||||||
params->SSITSize = SSITSize;
|
params->SSITSize = SSITSize;
|
||||||
params->LFSTSize = LFSTSize;
|
params->LFSTSize = LFSTSize;
|
||||||
|
|
|
@ -22,6 +22,8 @@ class BaseCPU(SimObject):
|
||||||
"terminate when all threads have reached this load count")
|
"terminate when all threads have reached this load count")
|
||||||
max_loads_any_thread = Param.Counter(0,
|
max_loads_any_thread = Param.Counter(0,
|
||||||
"terminate when any thread reaches this load count")
|
"terminate when any thread reaches this load count")
|
||||||
|
stats_reset_inst = Param.Counter(0,
|
||||||
|
"reset stats once this many instructions are committed")
|
||||||
progress_interval = Param.Tick(0, "interval to print out the progress message")
|
progress_interval = Param.Tick(0, "interval to print out the progress message")
|
||||||
|
|
||||||
defer_registration = Param.Bool(False,
|
defer_registration = Param.Bool(False,
|
||||||
|
|
Loading…
Reference in a new issue