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ua2005.cc:

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i SWEAR i committed this already, but apparently i didnt.  ust start using HPSTATE::hpriv, etc. to access bitfields.

src/arch/sparc/ua2005.cc:
    i SWEAR i committed this already, but apparently i didnt.  ust start using HPSTATE::hpriv, etc. to access bitfields.

--HG--
extra : convert_revision : e66fac9c63088c0fc1a62bd0fac92df305beadff
This commit is contained in:
Lisa Hsu 2007-01-11 09:29:03 -05:00
parent d939060ec6
commit 9f75c1c58f
1 changed files with 2 additions and 4 deletions
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6
src/arch/sparc/ua2005.cc
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@ -24,8 +24,6 @@
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Ali Saidi
*/ */
#include "arch/sparc/miscregfile.hh" #include "arch/sparc/miscregfile.hh"
@ -81,7 +79,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
break; break;
case MISCREG_PSTATE: case MISCREG_PSTATE:
if (val & ie && !(pstate & ie)) { if (val & PSTATE::ie && !(pstate & PSTATE::ie)) {
tc->getCpuPtr()->checkInterrupts = true; tc->getCpuPtr()->checkInterrupts = true;
} }
setReg(miscReg, val); setReg(miscReg, val);
@ -128,7 +126,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
case MISCREG_HPSTATE: case MISCREG_HPSTATE:
// T1000 spec says impl. dependent val must always be 1 // T1000 spec says impl. dependent val must always be 1
setReg(miscReg, val | id); setReg(miscReg, val | HPSTATE::id);
break; break;
case MISCREG_HTSTATE: case MISCREG_HTSTATE:
case MISCREG_STRAND_STS_REG: case MISCREG_STRAND_STS_REG: