change name of 2nd switch_cpu so that ckpt recovery with multiple cpus doens't get confused.
--HG-- extra : convert_revision : 16c710c4196c520d03c1993a26f38cf1f04ab637
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1 changed files with 8 additions and 6 deletions
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@ -53,25 +53,27 @@ def run(options, root, testsys):
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if options.standard_switch:
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if options.standard_switch:
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switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
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switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
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for i in xrange(np)]
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for i in xrange(np)]
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switch_cpus1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
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switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
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for i in xrange(np)]
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for i in xrange(np)]
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for i in xrange(np):
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for i in xrange(np):
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switch_cpus[i].system = testsys
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switch_cpus[i].system = testsys
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switch_cpus1[i].system = testsys
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switch_cpus_1[i].system = testsys
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if not m5.build_env['FULL_SYSTEM']:
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if not m5.build_env['FULL_SYSTEM']:
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switch_cpus[i].workload = testsys.cpu[i].workload
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switch_cpus[i].workload = testsys.cpu[i].workload
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switch_cpus1[i].workload = testsys.cpu[i].workload
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switch_cpus_1[i].workload = testsys.cpu[i].workload
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switch_cpus[i].clock = testsys.cpu[0].clock
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switch_cpus[i].clock = testsys.cpu[0].clock
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switch_cpus1[i].clock = testsys.cpu[0].clock
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switch_cpus_1[i].clock = testsys.cpu[0].clock
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if options.caches:
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if options.caches:
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switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
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switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
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L1Cache(size = '64kB'))
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L1Cache(size = '64kB'))
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switch_cpus[i].connectMemPorts(testsys.membus)
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switch_cpus[i].connectMemPorts(testsys.membus)
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root.switch_cpus = switch_cpus
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root.switch_cpus = switch_cpus
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root.switch_cpus1 = switch_cpus1
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root.switch_cpus_1 = switch_cpus_1
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switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
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switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
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switch_cpu_list1 = [(switch_cpus[i], switch_cpus1[i]) for i in xrange(np)]
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switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
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m5.instantiate(root)
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m5.instantiate(root)
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