diff --git a/configs/ruby/MESI_CMP_directory.py b/configs/ruby/MESI_CMP_directory.py index 95b4904a5..6408d1ed0 100644 --- a/configs/ruby/MESI_CMP_directory.py +++ b/configs/ruby/MESI_CMP_directory.py @@ -72,8 +72,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): l2_bits = int(math.log(options.num_l2caches, 2)) block_size_bits = int(math.log(options.cacheline_size, 2)) - cntrl_count = 0 - for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu @@ -90,7 +88,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): prefetcher = RubyPrefetcher.Prefetcher() l1_cntrl = L1Cache_Controller(version = i, - cntrl_id = cntrl_count, L1Icache = l1i_cache, L1Dcache = l1d_cache, l2_select_num_bits = l2_bits, @@ -119,8 +116,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) - cntrl_count += 1 - l2_index_start = block_size_bits + l2_bits for i in xrange(options.num_l2caches): @@ -132,7 +127,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): start_index_bit = l2_index_start) l2_cntrl = L2Cache_Controller(version = i, - cntrl_id = cntrl_count, L2cache = l2_cache, transitions_per_cycle=options.ports, ruby_system = ruby_system) @@ -140,8 +134,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) l2_cntrl_nodes.append(l2_cntrl) - cntrl_count += 1 - phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) assert(phys_mem_size % options.num_dirs == 0) mem_module_size = phys_mem_size / options.num_dirs @@ -167,22 +159,18 @@ def create_system(options, system, piobus, dma_ports, ruby_system): dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, - cntrl_id = cntrl_count, directory = \ RubyDirectoryMemory(version = i, size = dir_size, use_map = options.use_map), memBuffer = mem_cntrl, - l2_select_num_bits = l2_bits, transitions_per_cycle = options.ports, ruby_system = ruby_system) exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) - cntrl_count += 1 - for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller @@ -191,7 +179,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): ruby_system = ruby_system) dma_cntrl = DMA_Controller(version = i, - cntrl_id = cntrl_count, dma_sequencer = dma_seq, transitions_per_cycle = options.ports, ruby_system = ruby_system) @@ -199,7 +186,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) dma_cntrl_nodes.append(dma_cntrl) - cntrl_count += 1 all_cntrls = l1_cntrl_nodes + \ l2_cntrl_nodes + \ diff --git a/configs/ruby/MI_example.py b/configs/ruby/MI_example.py index d7fa2d75d..8f6c6e490 100644 --- a/configs/ruby/MI_example.py +++ b/configs/ruby/MI_example.py @@ -64,8 +64,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): # block_size_bits = int(math.log(options.cacheline_size, 2)) - cntrl_count = 0 - for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu @@ -80,7 +78,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): # Only one unified L1 cache exists. Can cache instructions and data. # l1_cntrl = L1Cache_Controller(version = i, - cntrl_id = cntrl_count, cacheMemory = cache, send_evictions = ( options.cpu_type == "detailed"), @@ -104,8 +101,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) - cntrl_count += 1 - phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) assert(phys_mem_size % options.num_dirs == 0) mem_module_size = phys_mem_size / options.num_dirs @@ -131,7 +126,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, - cntrl_id = cntrl_count, directory = \ RubyDirectoryMemory( \ version = i, @@ -146,8 +140,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) - cntrl_count += 1 - for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller @@ -156,7 +148,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): ruby_system = ruby_system) dma_cntrl = DMA_Controller(version = i, - cntrl_id = cntrl_count, dma_sequencer = dma_seq, transitions_per_cycle = options.ports, ruby_system = ruby_system) @@ -164,7 +155,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) dma_cntrl_nodes.append(dma_cntrl) - cntrl_count += 1 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes diff --git a/configs/ruby/MOESI_CMP_directory.py b/configs/ruby/MOESI_CMP_directory.py index 30fa6479c..9ebee8952 100644 --- a/configs/ruby/MOESI_CMP_directory.py +++ b/configs/ruby/MOESI_CMP_directory.py @@ -72,8 +72,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): l2_bits = int(math.log(options.num_l2caches, 2)) block_size_bits = int(math.log(options.cacheline_size, 2)) - cntrl_count = 0 - for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu @@ -88,7 +86,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): is_icache = False) l1_cntrl = L1Cache_Controller(version = i, - cntrl_id = cntrl_count, L1Icache = l1i_cache, L1Dcache = l1d_cache, l2_select_num_bits = l2_bits, @@ -114,8 +111,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) - cntrl_count += 1 - l2_index_start = block_size_bits + l2_bits for i in xrange(options.num_l2caches): @@ -127,7 +122,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): start_index_bit = l2_index_start) l2_cntrl = L2Cache_Controller(version = i, - cntrl_id = cntrl_count, L2cache = l2_cache, transitions_per_cycle = options.ports, ruby_system = ruby_system) @@ -135,8 +129,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) l2_cntrl_nodes.append(l2_cntrl) - cntrl_count += 1 - phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) assert(phys_mem_size % options.num_dirs == 0) mem_module_size = phys_mem_size / options.num_dirs @@ -162,7 +154,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, - cntrl_id = cntrl_count, directory = \ RubyDirectoryMemory(version = i, size = dir_size, @@ -174,8 +165,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) - cntrl_count += 1 - for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller @@ -184,7 +173,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): ruby_system = ruby_system) dma_cntrl = DMA_Controller(version = i, - cntrl_id = cntrl_count, dma_sequencer = dma_seq, transitions_per_cycle = options.ports, ruby_system = ruby_system) @@ -192,7 +180,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) dma_cntrl_nodes.append(dma_cntrl) - cntrl_count += 1 all_cntrls = l1_cntrl_nodes + \ l2_cntrl_nodes + \ diff --git a/configs/ruby/MOESI_CMP_token.py b/configs/ruby/MOESI_CMP_token.py index c7ec908eb..699f159f8 100644 --- a/configs/ruby/MOESI_CMP_token.py +++ b/configs/ruby/MOESI_CMP_token.py @@ -85,8 +85,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): l2_bits = int(math.log(options.num_l2caches, 2)) block_size_bits = int(math.log(options.cacheline_size, 2)) - cntrl_count = 0 - for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu @@ -99,7 +97,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): start_index_bit = block_size_bits) l1_cntrl = L1Cache_Controller(version = i, - cntrl_id = cntrl_count, L1Icache = l1i_cache, L1Dcache = l1d_cache, l2_select_num_bits = l2_bits, @@ -134,8 +131,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) - cntrl_count += 1 - l2_index_start = block_size_bits + l2_bits for i in xrange(options.num_l2caches): @@ -147,7 +142,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): start_index_bit = l2_index_start) l2_cntrl = L2Cache_Controller(version = i, - cntrl_id = cntrl_count, L2cache = l2_cache, N_tokens = n_tokens, transitions_per_cycle = options.ports, @@ -156,8 +150,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) l2_cntrl_nodes.append(l2_cntrl) - cntrl_count += 1 - phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) assert(phys_mem_size % options.num_dirs == 0) mem_module_size = phys_mem_size / options.num_dirs @@ -183,7 +175,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, - cntrl_id = cntrl_count, directory = \ RubyDirectoryMemory(version = i, use_map = options.use_map, @@ -196,8 +187,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) - cntrl_count += 1 - for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller @@ -206,7 +195,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): ruby_system = ruby_system) dma_cntrl = DMA_Controller(version = i, - cntrl_id = cntrl_count, dma_sequencer = dma_seq, transitions_per_cycle = options.ports, ruby_system = ruby_system) @@ -214,7 +202,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) dma_cntrl_nodes.append(dma_cntrl) - cntrl_count += 1 all_cntrls = l1_cntrl_nodes + \ l2_cntrl_nodes + \ diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py index 819834f56..47e37de30 100644 --- a/configs/ruby/MOESI_hammer.py +++ b/configs/ruby/MOESI_hammer.py @@ -81,8 +81,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): # block_size_bits = int(math.log(options.cacheline_size, 2)) - cntrl_count = 0 - for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu @@ -99,7 +97,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): start_index_bit = block_size_bits) l1_cntrl = L1Cache_Controller(version = i, - cntrl_id = cntrl_count, L1Icache = l1i_cache, L1Dcache = l1d_cache, L2cache = l2_cache, @@ -130,8 +127,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) - cntrl_count += 1 - phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) assert(phys_mem_size % options.num_dirs == 0) mem_module_size = phys_mem_size / options.num_dirs @@ -183,7 +178,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): start_index_bit = pf_start_bit) dir_cntrl = Directory_Controller(version = i, - cntrl_id = cntrl_count, directory = \ RubyDirectoryMemory( \ version = i, @@ -206,8 +200,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) - cntrl_count += 1 - for i, dma_port in enumerate(dma_ports): # # Create the Ruby objects associated with the dma controller @@ -216,7 +208,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): ruby_system = ruby_system) dma_cntrl = DMA_Controller(version = i, - cntrl_id = cntrl_count, dma_sequencer = dma_seq, transitions_per_cycle = options.ports, ruby_system = ruby_system) @@ -228,10 +219,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system): if options.recycle_latency: dma_cntrl.recycle_latency = options.recycle_latency - cntrl_count += 1 - all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes - topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology) diff --git a/configs/ruby/Network_test.py b/configs/ruby/Network_test.py index 6dfcc0b59..f48f5a792 100644 --- a/configs/ruby/Network_test.py +++ b/configs/ruby/Network_test.py @@ -68,8 +68,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): # controller constructors are called before the network constructor # - cntrl_count = 0 - for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu @@ -83,7 +81,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): # Only one unified L1 cache exists. Can cache instructions and data. # l1_cntrl = L1Cache_Controller(version = i, - cntrl_id = cntrl_count, cacheMemory = cache, ruby_system = ruby_system) @@ -101,8 +98,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) - cntrl_count += 1 - phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) assert(phys_mem_size % options.num_dirs == 0) mem_module_size = phys_mem_size / options.num_dirs @@ -128,7 +123,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): dir_size.value = mem_module_size dir_cntrl = Directory_Controller(version = i, - cntrl_id = cntrl_count, directory = \ RubyDirectoryMemory(version = i, size = dir_size), @@ -138,10 +132,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system): exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) - cntrl_count += 1 - all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes - topology = create_topology(all_cntrls, options) - return (cpu_sequencers, dir_cntrl_nodes, topology)