Split Checker up properly into templated and non-templated definitions.
--HG-- extra : convert_revision : 3ead18e42f4a536f2f868da07cb81a8940a7fa2f
This commit is contained in:
Kevin Lim
parent
0fc3055e96
commit
9ca5427c03
3 changed files with 409 additions and 362 deletions
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@ -184,6 +184,7 @@ if 'OzoneCPU' in env['CPU_MODELS']:
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sources += Split('ozone/checker_builder.cc')
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if env['USE_CHECKER']:
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sources += Split('checker/cpu.cc')
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checker_supports = False
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for i in CheckerSupportedCPUList:
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if i in env['CPU_MODELS']:
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408
src/cpu/checker/cpu.cc
Normal file
408
src/cpu/checker/cpu.cc
Normal file
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@ -0,0 +1,408 @@
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/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#include <list>
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#include <string>
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#include "cpu/base.hh"
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#include "cpu/checker/cpu.hh"
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#include "cpu/simple_thread.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/static_inst.hh"
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#include "mem/packet_impl.hh"
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#include "sim/byteswap.hh"
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#if FULL_SYSTEM
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#include "arch/vtophys.hh"
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#include "kern/kernel_stats.hh"
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#endif // FULL_SYSTEM
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using namespace std;
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//The CheckerCPU does alpha only
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using namespace AlphaISA;
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void
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CheckerCPU::init()
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{
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}
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CheckerCPU::CheckerCPU(Params *p)
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: BaseCPU(p), thread(NULL), tc(NULL)
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{
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memReq = NULL;
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numInst = 0;
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startNumInst = 0;
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numLoad = 0;
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startNumLoad = 0;
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youngestSN = 0;
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changedPC = willChangePC = changedNextPC = false;
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exitOnError = p->exitOnError;
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warnOnlyOnLoadError = p->warnOnlyOnLoadError;
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#if FULL_SYSTEM
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itb = p->itb;
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dtb = p->dtb;
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systemPtr = NULL;
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#else
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process = p->process;
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#endif
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result.integer = 0;
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}
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CheckerCPU::~CheckerCPU()
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{
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}
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void
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CheckerCPU::setMemory(MemObject *mem)
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{
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#if !FULL_SYSTEM
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memPtr = mem;
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thread = new SimpleThread(this, /* thread_num */ 0, process,
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/* asid */ 0, mem);
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thread->setStatus(ThreadContext::Suspended);
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tc = thread->getTC();
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threadContexts.push_back(tc);
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#endif
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}
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void
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CheckerCPU::setSystem(System *system)
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{
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#if FULL_SYSTEM
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systemPtr = system;
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thread = new SimpleThread(this, 0, systemPtr, itb, dtb, false);
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thread->setStatus(ThreadContext::Suspended);
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tc = thread->getTC();
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threadContexts.push_back(tc);
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delete thread->kernelStats;
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thread->kernelStats = NULL;
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#endif
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}
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void
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CheckerCPU::setIcachePort(Port *icache_port)
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{
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icachePort = icache_port;
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}
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void
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CheckerCPU::setDcachePort(Port *dcache_port)
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{
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dcachePort = dcache_port;
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}
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void
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CheckerCPU::serialize(ostream &os)
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{
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/*
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BaseCPU::serialize(os);
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SERIALIZE_SCALAR(inst);
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nameOut(os, csprintf("%s.xc", name()));
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thread->serialize(os);
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cacheCompletionEvent.serialize(os);
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*/
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}
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void
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CheckerCPU::unserialize(Checkpoint *cp, const string §ion)
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{
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/*
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BaseCPU::unserialize(cp, section);
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UNSERIALIZE_SCALAR(inst);
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thread->unserialize(cp, csprintf("%s.xc", section));
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*/
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}
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Fault
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CheckerCPU::copySrcTranslate(Addr src)
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{
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panic("Unimplemented!");
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}
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Fault
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CheckerCPU::copy(Addr dest)
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{
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panic("Unimplemented!");
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}
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template <class T>
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Fault
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CheckerCPU::read(Addr addr, T &data, unsigned flags)
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{
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// need to fill in CPU & thread IDs here
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memReq = new Request();
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memReq->setVirt(0, addr, sizeof(T), flags, thread->readPC());
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// translate to physical address
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translateDataReadReq(memReq);
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Packet *pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
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pkt->dataStatic(&data);
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if (!(memReq->getFlags() & UNCACHEABLE)) {
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// Access memory to see if we have the same data
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dcachePort->sendFunctional(pkt);
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} else {
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// Assume the data is correct if it's an uncached access
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memcpy(&data, &unverifiedResult.integer, sizeof(T));
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}
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delete pkt;
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return NoFault;
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}
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#ifndef DOXYGEN_SHOULD_SKIP_THIS
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template
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Fault
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CheckerCPU::read(Addr addr, uint64_t &data, unsigned flags);
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template
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Fault
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CheckerCPU::read(Addr addr, uint32_t &data, unsigned flags);
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template
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Fault
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CheckerCPU::read(Addr addr, uint16_t &data, unsigned flags);
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template
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Fault
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CheckerCPU::read(Addr addr, uint8_t &data, unsigned flags);
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#endif //DOXYGEN_SHOULD_SKIP_THIS
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template<>
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Fault
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CheckerCPU::read(Addr addr, double &data, unsigned flags)
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{
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return read(addr, *(uint64_t*)&data, flags);
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}
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template<>
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Fault
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CheckerCPU::read(Addr addr, float &data, unsigned flags)
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{
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return read(addr, *(uint32_t*)&data, flags);
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}
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template<>
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Fault
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CheckerCPU::read(Addr addr, int32_t &data, unsigned flags)
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{
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return read(addr, (uint32_t&)data, flags);
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}
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template <class T>
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Fault
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CheckerCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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{
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// need to fill in CPU & thread IDs here
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memReq = new Request();
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memReq->setVirt(0, addr, sizeof(T), flags, thread->readPC());
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// translate to physical address
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thread->translateDataWriteReq(memReq);
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// Can compare the write data and result only if it's cacheable,
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// not a store conditional, or is a store conditional that
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// succeeded.
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// @todo: Verify that actual memory matches up with these values.
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// Right now it only verifies that the instruction data is the
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// same as what was in the request that got sent to memory; there
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// is no verification that it is the same as what is in memory.
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// This is because the LSQ would have to be snooped in the CPU to
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// verify this data.
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if (unverifiedReq &&
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!(unverifiedReq->getFlags() & UNCACHEABLE) &&
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(!(unverifiedReq->getFlags() & LOCKED) ||
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((unverifiedReq->getFlags() & LOCKED) &&
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unverifiedReq->getScResult() == 1))) {
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T inst_data;
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/*
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// This code would work if the LSQ allowed for snooping.
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Packet *pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
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pkt.dataStatic(&inst_data);
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dcachePort->sendFunctional(pkt);
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delete pkt;
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*/
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memcpy(&inst_data, unverifiedMemData, sizeof(T));
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if (data != inst_data) {
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warn("%lli: Store value does not match value in memory! "
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"Instruction: %#x, memory: %#x",
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curTick, inst_data, data);
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handleError();
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}
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}
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// Assume the result was the same as the one passed in. This checker
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// doesn't check if the SC should succeed or fail, it just checks the
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// value.
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if (res && unverifiedReq->scResultValid())
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*res = unverifiedReq->getScResult();
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return NoFault;
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}
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#ifndef DOXYGEN_SHOULD_SKIP_THIS
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template
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Fault
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CheckerCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res);
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template
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Fault
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CheckerCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res);
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template
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Fault
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CheckerCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res);
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template
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Fault
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CheckerCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res);
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#endif //DOXYGEN_SHOULD_SKIP_THIS
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template<>
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Fault
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CheckerCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
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{
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return write(*(uint64_t*)&data, addr, flags, res);
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}
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template<>
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Fault
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CheckerCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
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{
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return write(*(uint32_t*)&data, addr, flags, res);
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}
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template<>
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Fault
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CheckerCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
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{
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return write((uint32_t)data, addr, flags, res);
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}
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#if FULL_SYSTEM
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Addr
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CheckerCPU::dbg_vtophys(Addr addr)
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{
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return vtophys(tc, addr);
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}
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#endif // FULL_SYSTEM
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bool
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CheckerCPU::translateInstReq(Request *req)
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{
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#if FULL_SYSTEM
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return (thread->translateInstReq(req) == NoFault);
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#else
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thread->translateInstReq(req);
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return true;
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#endif
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}
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void
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CheckerCPU::translateDataReadReq(Request *req)
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{
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thread->translateDataReadReq(req);
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if (req->getVaddr() != unverifiedReq->getVaddr()) {
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warn("%lli: Request virtual addresses do not match! Inst: %#x, "
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"checker: %#x",
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curTick, unverifiedReq->getVaddr(), req->getVaddr());
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handleError();
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}
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req->setPaddr(unverifiedReq->getPaddr());
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if (checkFlags(req)) {
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warn("%lli: Request flags do not match! Inst: %#x, checker: %#x",
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curTick, unverifiedReq->getFlags(), req->getFlags());
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handleError();
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}
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}
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void
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CheckerCPU::translateDataWriteReq(Request *req)
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{
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thread->translateDataWriteReq(req);
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if (req->getVaddr() != unverifiedReq->getVaddr()) {
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warn("%lli: Request virtual addresses do not match! Inst: %#x, "
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"checker: %#x",
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curTick, unverifiedReq->getVaddr(), req->getVaddr());
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handleError();
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}
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req->setPaddr(unverifiedReq->getPaddr());
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if (checkFlags(req)) {
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warn("%lli: Request flags do not match! Inst: %#x, checker: %#x",
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curTick, unverifiedReq->getFlags(), req->getFlags());
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handleError();
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}
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}
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bool
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CheckerCPU::checkFlags(Request *req)
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{
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// Remove any dynamic flags that don't have to do with the request itself.
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unsigned flags = unverifiedReq->getFlags();
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unsigned mask = LOCKED | PHYSICAL | VPTE | ALTMODE | UNCACHEABLE | NO_FAULT;
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flags = flags & (mask);
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if (flags == req->getFlags()) {
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return false;
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} else {
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return true;
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}
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}
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void
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CheckerCPU::dumpAndExit()
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{
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warn("%lli: Checker PC:%#x, next PC:%#x",
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curTick, thread->readPC(), thread->readNextPC());
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panic("Checker found an error!");
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}
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@ -32,7 +32,6 @@
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#include <string>
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#include "base/refcnt.hh"
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#include "cpu/base.hh"
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#include "cpu/base_dyn_inst.hh"
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#include "cpu/checker/cpu.hh"
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#include "cpu/simple_thread.hh"
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@ -44,374 +43,13 @@
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#include "sim/stats.hh"
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#if FULL_SYSTEM
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#include "sim/system.hh"
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#include "arch/vtophys.hh"
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#include "kern/kernel_stats.hh"
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#endif // FULL_SYSTEM
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using namespace std;
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//The CheckerCPU does alpha only
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using namespace AlphaISA;
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void
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CheckerCPU::init()
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{
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}
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CheckerCPU::CheckerCPU(Params *p)
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: BaseCPU(p), thread(NULL), tc(NULL)
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{
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memReq = NULL;
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numInst = 0;
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startNumInst = 0;
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numLoad = 0;
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startNumLoad = 0;
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youngestSN = 0;
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changedPC = willChangePC = changedNextPC = false;
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exitOnError = p->exitOnError;
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warnOnlyOnLoadError = p->warnOnlyOnLoadError;
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#if FULL_SYSTEM
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itb = p->itb;
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dtb = p->dtb;
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systemPtr = NULL;
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#else
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process = p->process;
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#endif
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result.integer = 0;
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}
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CheckerCPU::~CheckerCPU()
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{
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}
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void
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CheckerCPU::setMemory(MemObject *mem)
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{
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#if !FULL_SYSTEM
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memPtr = mem;
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thread = new SimpleThread(this, /* thread_num */ 0, process,
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/* asid */ 0, mem);
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thread->setStatus(ThreadContext::Suspended);
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tc = thread->getTC();
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threadContexts.push_back(tc);
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#endif
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}
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void
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CheckerCPU::setSystem(System *system)
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{
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#if FULL_SYSTEM
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systemPtr = system;
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thread = new SimpleThread(this, 0, systemPtr, itb, dtb, false);
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thread->setStatus(ThreadContext::Suspended);
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tc = thread->getTC();
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threadContexts.push_back(tc);
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delete thread->kernelStats;
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thread->kernelStats = NULL;
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#endif
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}
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void
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CheckerCPU::setIcachePort(Port *icache_port)
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{
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icachePort = icache_port;
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}
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void
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CheckerCPU::setDcachePort(Port *dcache_port)
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{
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dcachePort = dcache_port;
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}
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void
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CheckerCPU::serialize(ostream &os)
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{
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/*
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BaseCPU::serialize(os);
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SERIALIZE_SCALAR(inst);
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nameOut(os, csprintf("%s.xc", name()));
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thread->serialize(os);
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cacheCompletionEvent.serialize(os);
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*/
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}
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void
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CheckerCPU::unserialize(Checkpoint *cp, const string §ion)
|
||||
{
|
||||
/*
|
||||
BaseCPU::unserialize(cp, section);
|
||||
UNSERIALIZE_SCALAR(inst);
|
||||
thread->unserialize(cp, csprintf("%s.xc", section));
|
||||
*/
|
||||
}
|
||||
|
||||
Fault
|
||||
CheckerCPU::copySrcTranslate(Addr src)
|
||||
{
|
||||
panic("Unimplemented!");
|
||||
}
|
||||
|
||||
Fault
|
||||
CheckerCPU::copy(Addr dest)
|
||||
{
|
||||
panic("Unimplemented!");
|
||||
}
|
||||
|
||||
template <class T>
|
||||
Fault
|
||||
CheckerCPU::read(Addr addr, T &data, unsigned flags)
|
||||
{
|
||||
// need to fill in CPU & thread IDs here
|
||||
memReq = new Request();
|
||||
|
||||
memReq->setVirt(0, addr, sizeof(T), flags, thread->readPC());
|
||||
|
||||
// translate to physical address
|
||||
translateDataReadReq(memReq);
|
||||
|
||||
Packet *pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
|
||||
|
||||
pkt->dataStatic(&data);
|
||||
|
||||
if (!(memReq->getFlags() & UNCACHEABLE)) {
|
||||
// Access memory to see if we have the same data
|
||||
dcachePort->sendFunctional(pkt);
|
||||
} else {
|
||||
// Assume the data is correct if it's an uncached access
|
||||
memcpy(&data, &unverifiedResult.integer, sizeof(T));
|
||||
}
|
||||
|
||||
delete pkt;
|
||||
|
||||
return NoFault;
|
||||
}
|
||||
|
||||
#ifndef DOXYGEN_SHOULD_SKIP_THIS
|
||||
|
||||
template
|
||||
Fault
|
||||
CheckerCPU::read(Addr addr, uint64_t &data, unsigned flags);
|
||||
|
||||
template
|
||||
Fault
|
||||
CheckerCPU::read(Addr addr, uint32_t &data, unsigned flags);
|
||||
|
||||
template
|
||||
Fault
|
||||
CheckerCPU::read(Addr addr, uint16_t &data, unsigned flags);
|
||||
|
||||
template
|
||||
Fault
|
||||
CheckerCPU::read(Addr addr, uint8_t &data, unsigned flags);
|
||||
|
||||
#endif //DOXYGEN_SHOULD_SKIP_THIS
|
||||
|
||||
template<>
|
||||
Fault
|
||||
CheckerCPU::read(Addr addr, double &data, unsigned flags)
|
||||
{
|
||||
return read(addr, *(uint64_t*)&data, flags);
|
||||
}
|
||||
|
||||
template<>
|
||||
Fault
|
||||
CheckerCPU::read(Addr addr, float &data, unsigned flags)
|
||||
{
|
||||
return read(addr, *(uint32_t*)&data, flags);
|
||||
}
|
||||
|
||||
template<>
|
||||
Fault
|
||||
CheckerCPU::read(Addr addr, int32_t &data, unsigned flags)
|
||||
{
|
||||
return read(addr, (uint32_t&)data, flags);
|
||||
}
|
||||
|
||||
template <class T>
|
||||
Fault
|
||||
CheckerCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
|
||||
{
|
||||
// need to fill in CPU & thread IDs here
|
||||
memReq = new Request();
|
||||
|
||||
memReq->setVirt(0, addr, sizeof(T), flags, thread->readPC());
|
||||
|
||||
// translate to physical address
|
||||
thread->translateDataWriteReq(memReq);
|
||||
|
||||
// Can compare the write data and result only if it's cacheable,
|
||||
// not a store conditional, or is a store conditional that
|
||||
// succeeded.
|
||||
// @todo: Verify that actual memory matches up with these values.
|
||||
// Right now it only verifies that the instruction data is the
|
||||
// same as what was in the request that got sent to memory; there
|
||||
// is no verification that it is the same as what is in memory.
|
||||
// This is because the LSQ would have to be snooped in the CPU to
|
||||
// verify this data.
|
||||
if (unverifiedReq &&
|
||||
!(unverifiedReq->getFlags() & UNCACHEABLE) &&
|
||||
(!(unverifiedReq->getFlags() & LOCKED) ||
|
||||
((unverifiedReq->getFlags() & LOCKED) &&
|
||||
unverifiedReq->getScResult() == 1))) {
|
||||
T inst_data;
|
||||
/*
|
||||
// This code would work if the LSQ allowed for snooping.
|
||||
Packet *pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
|
||||
pkt.dataStatic(&inst_data);
|
||||
|
||||
dcachePort->sendFunctional(pkt);
|
||||
|
||||
delete pkt;
|
||||
*/
|
||||
memcpy(&inst_data, unverifiedMemData, sizeof(T));
|
||||
|
||||
if (data != inst_data) {
|
||||
warn("%lli: Store value does not match value in memory! "
|
||||
"Instruction: %#x, memory: %#x",
|
||||
curTick, inst_data, data);
|
||||
handleError();
|
||||
}
|
||||
}
|
||||
|
||||
// Assume the result was the same as the one passed in. This checker
|
||||
// doesn't check if the SC should succeed or fail, it just checks the
|
||||
// value.
|
||||
if (res && unverifiedReq->scResultValid())
|
||||
*res = unverifiedReq->getScResult();
|
||||
|
||||
return NoFault;
|
||||
}
|
||||
|
||||
|
||||
#ifndef DOXYGEN_SHOULD_SKIP_THIS
|
||||
template
|
||||
Fault
|
||||
CheckerCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res);
|
||||
|
||||
template
|
||||
Fault
|
||||
CheckerCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res);
|
||||
|
||||
template
|
||||
Fault
|
||||
CheckerCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res);
|
||||
|
||||
template
|
||||
Fault
|
||||
CheckerCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res);
|
||||
|
||||
#endif //DOXYGEN_SHOULD_SKIP_THIS
|
||||
|
||||
template<>
|
||||
Fault
|
||||
CheckerCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
|
||||
{
|
||||
return write(*(uint64_t*)&data, addr, flags, res);
|
||||
}
|
||||
|
||||
template<>
|
||||
Fault
|
||||
CheckerCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
|
||||
{
|
||||
return write(*(uint32_t*)&data, addr, flags, res);
|
||||
}
|
||||
|
||||
template<>
|
||||
Fault
|
||||
CheckerCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
|
||||
{
|
||||
return write((uint32_t)data, addr, flags, res);
|
||||
}
|
||||
|
||||
|
||||
#if FULL_SYSTEM
|
||||
Addr
|
||||
CheckerCPU::dbg_vtophys(Addr addr)
|
||||
{
|
||||
return vtophys(tc, addr);
|
||||
}
|
||||
#endif // FULL_SYSTEM
|
||||
|
||||
bool
|
||||
CheckerCPU::translateInstReq(Request *req)
|
||||
{
|
||||
#if FULL_SYSTEM
|
||||
return (thread->translateInstReq(req) == NoFault);
|
||||
#else
|
||||
thread->translateInstReq(req);
|
||||
return true;
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
CheckerCPU::translateDataReadReq(Request *req)
|
||||
{
|
||||
thread->translateDataReadReq(req);
|
||||
|
||||
if (req->getVaddr() != unverifiedReq->getVaddr()) {
|
||||
warn("%lli: Request virtual addresses do not match! Inst: %#x, "
|
||||
"checker: %#x",
|
||||
curTick, unverifiedReq->getVaddr(), req->getVaddr());
|
||||
handleError();
|
||||
}
|
||||
req->setPaddr(unverifiedReq->getPaddr());
|
||||
|
||||
if (checkFlags(req)) {
|
||||
warn("%lli: Request flags do not match! Inst: %#x, checker: %#x",
|
||||
curTick, unverifiedReq->getFlags(), req->getFlags());
|
||||
handleError();
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
CheckerCPU::translateDataWriteReq(Request *req)
|
||||
{
|
||||
thread->translateDataWriteReq(req);
|
||||
|
||||
if (req->getVaddr() != unverifiedReq->getVaddr()) {
|
||||
warn("%lli: Request virtual addresses do not match! Inst: %#x, "
|
||||
"checker: %#x",
|
||||
curTick, unverifiedReq->getVaddr(), req->getVaddr());
|
||||
handleError();
|
||||
}
|
||||
req->setPaddr(unverifiedReq->getPaddr());
|
||||
|
||||
if (checkFlags(req)) {
|
||||
warn("%lli: Request flags do not match! Inst: %#x, checker: %#x",
|
||||
curTick, unverifiedReq->getFlags(), req->getFlags());
|
||||
handleError();
|
||||
}
|
||||
}
|
||||
|
||||
bool
|
||||
CheckerCPU::checkFlags(Request *req)
|
||||
{
|
||||
// Remove any dynamic flags that don't have to do with the request itself.
|
||||
unsigned flags = unverifiedReq->getFlags();
|
||||
unsigned mask = LOCKED | PHYSICAL | VPTE | ALTMODE | UNCACHEABLE | NO_FAULT;
|
||||
flags = flags & (mask);
|
||||
if (flags == req->getFlags()) {
|
||||
return false;
|
||||
} else {
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
CheckerCPU::dumpAndExit()
|
||||
{
|
||||
warn("%lli: Checker PC:%#x, next PC:%#x",
|
||||
curTick, thread->readPC(), thread->readNextPC());
|
||||
panic("Checker found an error!");
|
||||
}
|
||||
|
||||
template <class DynInstPtr>
|
||||
void
|
||||
Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
|
||||
|
|
|
|||
Loading…
Reference in a new issue