Fixes for uni-coherence in timing mode for FS.
Still a bug in atomic uni-coherence in FS. src/cpu/o3/fetch_impl.hh: src/cpu/o3/lsq_impl.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: Make CPU models handle coherence requests src/mem/cache/base_cache.cc: Properly signal coherence CSHRs src/mem/cache/coherence/uni_coherence.cc: Only deallocate once --HG-- extra : convert_revision : c4533de421c371c5532ee505e3ecd451511f5c99
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4fff6d4603
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6 changed files with 46 additions and 24 deletions
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@ -80,7 +80,10 @@ template<class Impl>
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bool
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bool
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DefaultFetch<Impl>::IcachePort::recvTiming(Packet *pkt)
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DefaultFetch<Impl>::IcachePort::recvTiming(Packet *pkt)
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{
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{
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if (pkt->isResponse()) {
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fetch->processCacheCompletion(pkt);
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fetch->processCacheCompletion(pkt);
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}
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//else Snooped a coherence request, just return
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return true;
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return true;
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}
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}
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@ -63,7 +63,14 @@ template <class Impl>
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bool
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bool
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LSQ<Impl>::DcachePort::recvTiming(PacketPtr pkt)
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LSQ<Impl>::DcachePort::recvTiming(PacketPtr pkt)
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{
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{
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if (pkt->isResponse()) {
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lsq->thread[pkt->req->getThreadNum()].completeDataAccess(pkt);
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lsq->thread[pkt->req->getThreadNum()].completeDataAccess(pkt);
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}
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else {
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//else it is a coherence request, maybe you need to do something
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warn("Recieved a coherence request (Invalidate??), 03CPU doesn't"
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"update LSQ for these\n");
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}
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return true;
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return true;
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}
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}
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@ -101,7 +101,7 @@ AtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt)
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Tick
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Tick
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AtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
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AtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
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{
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{
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panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
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//Snooping a coherence request, just return
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return curTick;
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return curTick;
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}
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}
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@ -528,6 +528,7 @@ TimingSimpleCPU::IcachePort::ITickEvent::process()
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bool
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bool
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TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
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TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
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{
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{
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if (pkt->isResponse()) {
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// delay processing of returned data until next CPU clock edge
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// delay processing of returned data until next CPU clock edge
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Tick time = pkt->req->getTime();
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Tick time = pkt->req->getTime();
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while (time < curTick)
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while (time < curTick)
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@ -540,6 +541,11 @@ TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
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return true;
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return true;
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}
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}
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else {
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//Snooping a Coherence Request, do nothing
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return true;
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}
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}
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void
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void
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TimingSimpleCPU::IcachePort::recvRetry()
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TimingSimpleCPU::IcachePort::recvRetry()
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@ -600,6 +606,7 @@ TimingSimpleCPU::completeDrain()
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bool
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bool
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TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
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TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
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{
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{
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if (pkt->isResponse()) {
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// delay processing of returned data until next CPU clock edge
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// delay processing of returned data until next CPU clock edge
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Tick time = pkt->req->getTime();
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Tick time = pkt->req->getTime();
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while (time < curTick)
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while (time < curTick)
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@ -612,6 +619,11 @@ TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
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return true;
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return true;
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}
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}
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else {
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//Snooping a coherence req, do nothing
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return true;
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}
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}
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void
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void
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TimingSimpleCPU::DcachePort::DTickEvent::process()
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TimingSimpleCPU::DcachePort::DTickEvent::process()
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2
src/mem/cache/base_cache.cc
vendored
2
src/mem/cache/base_cache.cc
vendored
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@ -331,7 +331,7 @@ BaseCache::CacheEvent::process()
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pkt = cachePort->cache->getCoherencePacket();
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pkt = cachePort->cache->getCoherencePacket();
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MSHR* cshr = (MSHR*) pkt->senderState;
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MSHR* cshr = (MSHR*) pkt->senderState;
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bool success = cachePort->sendTiming(pkt);
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bool success = cachePort->sendTiming(pkt);
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cachePort->cache->sendResult(pkt, cshr, success);
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cachePort->cache->sendCoherenceResult(pkt, cshr, success);
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cachePort->waitingOnRetry = !success;
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cachePort->waitingOnRetry = !success;
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if (cachePort->waitingOnRetry)
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if (cachePort->waitingOnRetry)
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DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name());
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DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name());
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4
src/mem/cache/coherence/uni_coherence.cc
vendored
4
src/mem/cache/coherence/uni_coherence.cc
vendored
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@ -53,11 +53,11 @@ UniCoherence::sendResult(Packet * &pkt, MSHR* cshr, bool success)
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if (success)
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if (success)
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{
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{
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bool unblock = cshrs.isFull();
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bool unblock = cshrs.isFull();
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cshrs.markInService(cshr);
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// cshrs.markInService(cshr);
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cshrs.deallocate(cshr);
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if (!cshrs.havePending()) {
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if (!cshrs.havePending()) {
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cache->clearSlaveRequest(Request_Coherence);
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cache->clearSlaveRequest(Request_Coherence);
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}
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}
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cshrs.deallocate(cshr);
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if (unblock) {
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if (unblock) {
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//since CSHRs are always used as buffers, should always get rid of one
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//since CSHRs are always used as buffers, should always get rid of one
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assert(!cshrs.isFull());
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assert(!cshrs.isFull());
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