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ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.

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By using an underscore, the "." is still available and can unambiguously be
used to refer to members of a structure if an operand is a structure, class,
etc. This change mostly just replaces the appropriate "."s with "_"s, but
there were also a few places where the ISA descriptions where handling the
extensions themselves and had their own regular expressions to update. The
regular expressions in the isa parser were updated as well. It also now
looks for one of the defined type extensions specifically after connecting "_"
where before it would look for any sequence of characters after a "."
following an operand name and try to use it as the extension. This helps to
disambiguate cases where a "_" may legitimately be part of an operand name but
not separate the name from the type suffix.

Because leaving the "_" and suffix on the variable name still leaves a valid
C++ identifier and all extensions need to be consistent in a given context, I
considered leaving them on as a breadcrumb that would show what the intended
type was for that operand. Unfortunately the operands can be referred to in
code templates, the Mem operand in particular, and since the exact type of Mem
can be different for different uses of the same template, that broke things.
This commit is contained in:
Gabe Black 2011-09-26 23:48:54 -07:00
parent 56bddab189
commit 997cbe1c09
29 changed files with 1386 additions and 1386 deletions
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264
src/arch/alpha/isa/decoder.isa
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@ -41,35 +41,35 @@ decode OPCODE default Unknown::unknown() {
} }
format LoadOrNop { format LoadOrNop {
0x0a: ldbu({{ Ra.uq = Mem.ub; }}); 0x0a: ldbu({{ Ra_uq = Mem_ub; }});
0x0c: ldwu({{ Ra.uq = Mem.uw; }}); 0x0c: ldwu({{ Ra_uq = Mem_uw; }});
0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }}); 0x0b: ldq_u({{ Ra = Mem_uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }});
0x23: ldt({{ Fa = Mem.df; }}); 0x23: ldt({{ Fa = Mem_df; }});
0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LLSC); 0x2a: ldl_l({{ Ra_sl = Mem_sl; }}, mem_flags = LLSC);
0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LLSC); 0x2b: ldq_l({{ Ra_uq = Mem_uq; }}, mem_flags = LLSC);
} }
format LoadOrPrefetch { format LoadOrPrefetch {
0x28: ldl({{ Ra.sl = Mem.sl; }}); 0x28: ldl({{ Ra_sl = Mem_sl; }});
0x29: ldq({{ Ra.uq = Mem.uq; }}, pf_flags = EVICT_NEXT); 0x29: ldq({{ Ra_uq = Mem_uq; }}, pf_flags = EVICT_NEXT);
// IsFloating flag on lds gets the prefetch to disassemble // IsFloating flag on lds gets the prefetch to disassemble
// using f31 instead of r31... funcitonally it's unnecessary // using f31 instead of r31... funcitonally it's unnecessary
0x22: lds({{ Fa.uq = s_to_t(Mem.ul); }}, 0x22: lds({{ Fa_uq = s_to_t(Mem_ul); }},
pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating); pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating);
} }
format Store { format Store {
0x0e: stb({{ Mem.ub = Ra<7:0>; }}); 0x0e: stb({{ Mem_ub = Ra<7:0>; }});
0x0d: stw({{ Mem.uw = Ra<15:0>; }}); 0x0d: stw({{ Mem_uw = Ra<15:0>; }});
0x2c: stl({{ Mem.ul = Ra<31:0>; }}); 0x2c: stl({{ Mem_ul = Ra<31:0>; }});
0x2d: stq({{ Mem.uq = Ra.uq; }}); 0x2d: stq({{ Mem_uq = Ra_uq; }});
0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }}); 0x0f: stq_u({{ Mem_uq = Ra_uq; }}, {{ EA = (Rb + disp) & ~7; }});
0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }}); 0x26: sts({{ Mem_ul = t_to_s(Fa_uq); }});
0x27: stt({{ Mem.df = Fa; }}); 0x27: stt({{ Mem_df = Fa; }});
} }
format StoreCond { format StoreCond {
0x2e: stl_c({{ Mem.ul = Ra<31:0>; }}, 0x2e: stl_c({{ Mem_ul = Ra<31:0>; }},
{{ {{
uint64_t tmp = write_result; uint64_t tmp = write_result;
// see stq_c // see stq_c
@ -78,7 +78,7 @@ decode OPCODE default Unknown::unknown() {
xc->setStCondFailures(0); xc->setStCondFailures(0);
} }
}}, mem_flags = LLSC, inst_flags = IsStoreConditional); }}, mem_flags = LLSC, inst_flags = IsStoreConditional);
0x2f: stq_c({{ Mem.uq = Ra; }}, 0x2f: stq_c({{ Mem_uq = Ra; }},
{{ {{
uint64_t tmp = write_result; uint64_t tmp = write_result;
// If the write operation returns 0 or 1, then // If the write operation returns 0 or 1, then
@ -102,17 +102,17 @@ decode OPCODE default Unknown::unknown() {
0x10: decode INTFUNC { // integer arithmetic operations 0x10: decode INTFUNC { // integer arithmetic operations
0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }}); 0x00: addl({{ Rc_sl = Ra_sl + Rb_or_imm_sl; }});
0x40: addlv({{ 0x40: addlv({{
int32_t tmp = Ra.sl + Rb_or_imm.sl; int32_t tmp = Ra_sl + Rb_or_imm_sl;
// signed overflow occurs when operands have same sign // signed overflow occurs when operands have same sign
// and sign of result does not match. // and sign of result does not match.
if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>) if (Ra_sl<31:> == Rb_or_imm_sl<31:> && tmp<31:> != Ra_sl<31:>)
fault = new IntegerOverflowFault; fault = new IntegerOverflowFault;
Rc.sl = tmp; Rc_sl = tmp;
}}); }});
0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }}); 0x02: s4addl({{ Rc_sl = (Ra_sl << 2) + Rb_or_imm_sl; }});
0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }}); 0x12: s8addl({{ Rc_sl = (Ra_sl << 3) + Rb_or_imm_sl; }});
0x20: addq({{ Rc = Ra + Rb_or_imm; }}); 0x20: addq({{ Rc = Ra + Rb_or_imm; }});
0x60: addqv({{ 0x60: addqv({{
@ -126,19 +126,19 @@ decode OPCODE default Unknown::unknown() {
0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }}); 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }}); 0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }});
0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }}); 0x09: subl({{ Rc_sl = Ra_sl - Rb_or_imm_sl; }});
0x49: sublv({{ 0x49: sublv({{
int32_t tmp = Ra.sl - Rb_or_imm.sl; int32_t tmp = Ra_sl - Rb_or_imm_sl;
// signed overflow detection is same as for add, // signed overflow detection is same as for add,
// except we need to look at the *complemented* // except we need to look at the *complemented*
// sign bit of the subtrahend (Rb), i.e., if the initial // sign bit of the subtrahend (Rb), i.e., if the initial
// signs are the *same* then no overflow can occur // signs are the *same* then no overflow can occur
if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>) if (Ra_sl<31:> != Rb_or_imm_sl<31:> && tmp<31:> != Ra_sl<31:>)
fault = new IntegerOverflowFault; fault = new IntegerOverflowFault;
Rc.sl = tmp; Rc_sl = tmp;
}}); }});
0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }}); 0x0b: s4subl({{ Rc_sl = (Ra_sl << 2) - Rb_or_imm_sl; }});
0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }}); 0x1b: s8subl({{ Rc_sl = (Ra_sl << 3) - Rb_or_imm_sl; }});
0x29: subq({{ Rc = Ra - Rb_or_imm; }}); 0x29: subq({{ Rc = Ra - Rb_or_imm; }});
0x69: subqv({{ 0x69: subqv({{
@ -155,17 +155,17 @@ decode OPCODE default Unknown::unknown() {
0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }}); 0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }});
0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }}); 0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }});
0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }}); 0x6d: cmple({{ Rc = (Ra_sq <= Rb_or_imm_sq); }});
0x4d: cmplt({{ Rc = (Ra.sq < Rb_or_imm.sq); }}); 0x4d: cmplt({{ Rc = (Ra_sq < Rb_or_imm_sq); }});
0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }}); 0x3d: cmpule({{ Rc = (Ra_uq <= Rb_or_imm_uq); }});
0x1d: cmpult({{ Rc = (Ra.uq < Rb_or_imm.uq); }}); 0x1d: cmpult({{ Rc = (Ra_uq < Rb_or_imm_uq); }});
0x0f: cmpbge({{ 0x0f: cmpbge({{
int hi = 7; int hi = 7;
int lo = 0; int lo = 0;
uint64_t tmp = 0; uint64_t tmp = 0;
for (int i = 0; i < 8; ++i) { for (int i = 0; i < 8; ++i) {
tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i; tmp |= (Ra_uq<hi:lo> >= Rb_or_imm_uq<hi:lo>) << i;
hi += 8; hi += 8;
lo += 8; lo += 8;
} }
@ -187,10 +187,10 @@ decode OPCODE default Unknown::unknown() {
0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }}); 0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }});
0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }}); 0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }});
0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }}); 0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }});
0x44: cmovlt({{ Rc = (Ra.sq < 0) ? Rb_or_imm : Rc; }}); 0x44: cmovlt({{ Rc = (Ra_sq < 0) ? Rb_or_imm : Rc; }});
0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }}); 0x46: cmovge({{ Rc = (Ra_sq >= 0) ? Rb_or_imm : Rc; }});
0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }}); 0x64: cmovle({{ Rc = (Ra_sq <= 0) ? Rb_or_imm : Rc; }});
0x66: cmovgt({{ Rc = (Ra.sq > 0) ? Rb_or_imm : Rc; }}); 0x66: cmovgt({{ Rc = (Ra_sq > 0) ? Rb_or_imm : Rc; }});
// For AMASK, RA must be R31. // For AMASK, RA must be R31.
0x61: decode RA { 0x61: decode RA {
@ -214,8 +214,8 @@ decode OPCODE default Unknown::unknown() {
0x12: decode INTFUNC { 0x12: decode INTFUNC {
0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }}); 0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }}); 0x34: srl({{ Rc = Ra_uq >> Rb_or_imm<5:0>; }});
0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }}); 0x3c: sra({{ Rc = Ra_sq >> Rb_or_imm<5:0>; }});
0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }}); 0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});
0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }}); 0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }});
@ -235,10 +235,10 @@ decode OPCODE default Unknown::unknown() {
Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra; Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra;
}}); }});
0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }}); 0x06: extbl({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }}); 0x16: extwl({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }}); 0x26: extll({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }}); 0x36: extql({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8)); }});
0x5a: extwh({{ 0x5a: extwh({{
Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }}); Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }});
@ -254,15 +254,15 @@ decode OPCODE default Unknown::unknown() {
0x57: inswh({{ 0x57: inswh({{
int bv = Rb_or_imm<2:0>; int bv = Rb_or_imm<2:0>;
Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0; Rc = bv ? (Ra_uq<15:0> >> (64 - 8 * bv)) : 0;
}}); }});
0x67: inslh({{ 0x67: inslh({{
int bv = Rb_or_imm<2:0>; int bv = Rb_or_imm<2:0>;
Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0; Rc = bv ? (Ra_uq<31:0> >> (64 - 8 * bv)) : 0;
}}); }});
0x77: insqh({{ 0x77: insqh({{
int bv = Rb_or_imm<2:0>; int bv = Rb_or_imm<2:0>;
Rc = bv ? (Ra.uq >> (64 - 8 * bv)) : 0; Rc = bv ? (Ra_uq >> (64 - 8 * bv)) : 0;
}}); }});
0x30: zap({{ 0x30: zap({{
@ -284,7 +284,7 @@ decode OPCODE default Unknown::unknown() {
} }
0x13: decode INTFUNC { // integer multiplies 0x13: decode INTFUNC { // integer multiplies
0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp); 0x00: mull({{ Rc_sl = Ra_sl * Rb_or_imm_sl; }}, IntMultOp);
0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp); 0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp);
0x30: umulh({{ 0x30: umulh({{
uint64_t hi, lo; uint64_t hi, lo;
@ -293,8 +293,8 @@ decode OPCODE default Unknown::unknown() {
}}, IntMultOp); }}, IntMultOp);
0x40: mullv({{ 0x40: mullv({{
// 32-bit multiply with trap on overflow // 32-bit multiply with trap on overflow
int64_t Rax = Ra.sl; // sign extended version of Ra.sl int64_t Rax = Ra_sl; // sign extended version of Ra_sl
int64_t Rbx = Rb_or_imm.sl; int64_t Rbx = Rb_or_imm_sl;
int64_t tmp = Rax * Rbx; int64_t tmp = Rax * Rbx;
// To avoid overflow, all the upper 32 bits must match // To avoid overflow, all the upper 32 bits must match
// the sign bit of the lower 32. We code this as // the sign bit of the lower 32. We code this as
@ -302,7 +302,7 @@ decode OPCODE default Unknown::unknown() {
uint64_t sign_bits = tmp<63:31>; uint64_t sign_bits = tmp<63:31>;
if (sign_bits != 0 && sign_bits != mask(33)) if (sign_bits != 0 && sign_bits != mask(33))
fault = new IntegerOverflowFault; fault = new IntegerOverflowFault;
Rc.sl = tmp<31:0>; Rc_sl = tmp<31:0>;
}}, IntMultOp); }}, IntMultOp);
0x60: mulqv({{ 0x60: mulqv({{
// 64-bit multiply with trap on overflow // 64-bit multiply with trap on overflow
@ -318,8 +318,8 @@ decode OPCODE default Unknown::unknown() {
} }
0x1c: decode INTFUNC { 0x1c: decode INTFUNC {
0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); } 0x00: decode RA { 31: sextb({{ Rc_sb = Rb_or_imm< 7:0>; }}); }
0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); } 0x01: decode RA { 31: sextw({{ Rc_sw = Rb_or_imm<15:0>; }}); }
0x30: ctpop({{ 0x30: ctpop({{
uint64_t count = 0; uint64_t count = 0;
@ -335,8 +335,8 @@ decode OPCODE default Unknown::unknown() {
int hi = 7; int hi = 7;
int lo = 0; int lo = 0;
for (int i = 0; i < 8; ++i) { for (int i = 0; i < 8; ++i) {
uint8_t ra_ub = Ra.uq<hi:lo>; uint8_t ra_ub = Ra_uq<hi:lo>;
uint8_t rb_ub = Rb.uq<hi:lo>; uint8_t rb_ub = Rb_uq<hi:lo>;
temp += (ra_ub >= rb_ub) ? temp += (ra_ub >= rb_ub) ?
(ra_ub - rb_ub) : (rb_ub - ra_ub); (ra_ub - rb_ub) : (rb_ub - ra_ub);
hi += 8; hi += 8;
@ -375,25 +375,25 @@ decode OPCODE default Unknown::unknown() {
0x34: unpkbw({{ 0x34: unpkbw({{
Rc = (Rb.uq<7:0> Rc = (Rb_uq<7:0>
| (Rb.uq<15:8> << 16) | (Rb_uq<15:8> << 16)
| (Rb.uq<23:16> << 32) | (Rb_uq<23:16> << 32)
| (Rb.uq<31:24> << 48)); | (Rb_uq<31:24> << 48));
}}, IntAluOp); }}, IntAluOp);
0x35: unpkbl({{ 0x35: unpkbl({{
Rc = (Rb.uq<7:0> | (Rb.uq<15:8> << 32)); Rc = (Rb_uq<7:0> | (Rb_uq<15:8> << 32));
}}, IntAluOp); }}, IntAluOp);
0x36: pkwb({{ 0x36: pkwb({{
Rc = (Rb.uq<7:0> Rc = (Rb_uq<7:0>
| (Rb.uq<23:16> << 8) | (Rb_uq<23:16> << 8)
| (Rb.uq<39:32> << 16) | (Rb_uq<39:32> << 16)
| (Rb.uq<55:48> << 24)); | (Rb_uq<55:48> << 24));
}}, IntAluOp); }}, IntAluOp);
0x37: pklb({{ 0x37: pklb({{
Rc = (Rb.uq<7:0> | (Rb.uq<39:32> << 8)); Rc = (Rb_uq<7:0> | (Rb_uq<39:32> << 8));
}}, IntAluOp); }}, IntAluOp);
0x38: minsb8({{ 0x38: minsb8({{
@ -401,11 +401,11 @@ decode OPCODE default Unknown::unknown() {
int hi = 63; int hi = 63;
int lo = 56; int lo = 56;
for (int i = 7; i >= 0; --i) { for (int i = 7; i >= 0; --i) {
int8_t ra_sb = Ra.uq<hi:lo>; int8_t ra_sb = Ra_uq<hi:lo>;
int8_t rb_sb = Rb.uq<hi:lo>; int8_t rb_sb = Rb_uq<hi:lo>;
temp = ((temp << 8) temp = ((temp << 8)
| ((ra_sb < rb_sb) ? Ra.uq<hi:lo> | ((ra_sb < rb_sb) ? Ra_uq<hi:lo>
: Rb.uq<hi:lo>)); : Rb_uq<hi:lo>));
hi -= 8; hi -= 8;
lo -= 8; lo -= 8;
} }
@ -417,11 +417,11 @@ decode OPCODE default Unknown::unknown() {
int hi = 63; int hi = 63;
int lo = 48; int lo = 48;
for (int i = 3; i >= 0; --i) { for (int i = 3; i >= 0; --i) {
int16_t ra_sw = Ra.uq<hi:lo>; int16_t ra_sw = Ra_uq<hi:lo>;
int16_t rb_sw = Rb.uq<hi:lo>; int16_t rb_sw = Rb_uq<hi:lo>;
temp = ((temp << 16) temp = ((temp << 16)
| ((ra_sw < rb_sw) ? Ra.uq<hi:lo> | ((ra_sw < rb_sw) ? Ra_uq<hi:lo>
: Rb.uq<hi:lo>)); : Rb_uq<hi:lo>));
hi -= 16; hi -= 16;
lo -= 16; lo -= 16;
} }
@ -433,11 +433,11 @@ decode OPCODE default Unknown::unknown() {
int hi = 63; int hi = 63;
int lo = 56; int lo = 56;
for (int i = 7; i >= 0; --i) { for (int i = 7; i >= 0; --i) {
uint8_t ra_ub = Ra.uq<hi:lo>; uint8_t ra_ub = Ra_uq<hi:lo>;
uint8_t rb_ub = Rb.uq<hi:lo>; uint8_t rb_ub = Rb_uq<hi:lo>;
temp = ((temp << 8) temp = ((temp << 8)
| ((ra_ub < rb_ub) ? Ra.uq<hi:lo> | ((ra_ub < rb_ub) ? Ra_uq<hi:lo>
: Rb.uq<hi:lo>)); : Rb_uq<hi:lo>));
hi -= 8; hi -= 8;
lo -= 8; lo -= 8;
} }
@ -449,11 +449,11 @@ decode OPCODE default Unknown::unknown() {
int hi = 63; int hi = 63;
int lo = 48; int lo = 48;
for (int i = 3; i >= 0; --i) { for (int i = 3; i >= 0; --i) {
uint16_t ra_sw = Ra.uq<hi:lo>; uint16_t ra_sw = Ra_uq<hi:lo>;
uint16_t rb_sw = Rb.uq<hi:lo>; uint16_t rb_sw = Rb_uq<hi:lo>;
temp = ((temp << 16) temp = ((temp << 16)
| ((ra_sw < rb_sw) ? Ra.uq<hi:lo> | ((ra_sw < rb_sw) ? Ra_uq<hi:lo>
: Rb.uq<hi:lo>)); : Rb_uq<hi:lo>));
hi -= 16; hi -= 16;
lo -= 16; lo -= 16;
} }
@ -465,11 +465,11 @@ decode OPCODE default Unknown::unknown() {
int hi = 63; int hi = 63;
int lo = 56; int lo = 56;
for (int i = 7; i >= 0; --i) { for (int i = 7; i >= 0; --i) {
uint8_t ra_ub = Ra.uq<hi:lo>; uint8_t ra_ub = Ra_uq<hi:lo>;
uint8_t rb_ub = Rb.uq<hi:lo>; uint8_t rb_ub = Rb_uq<hi:lo>;
temp = ((temp << 8) temp = ((temp << 8)
| ((ra_ub > rb_ub) ? Ra.uq<hi:lo> | ((ra_ub > rb_ub) ? Ra_uq<hi:lo>
: Rb.uq<hi:lo>)); : Rb_uq<hi:lo>));
hi -= 8; hi -= 8;
lo -= 8; lo -= 8;
} }
@ -481,11 +481,11 @@ decode OPCODE default Unknown::unknown() {
int hi = 63; int hi = 63;
int lo = 48; int lo = 48;
for (int i = 3; i >= 0; --i) { for (int i = 3; i >= 0; --i) {
uint16_t ra_uw = Ra.uq<hi:lo>; uint16_t ra_uw = Ra_uq<hi:lo>;
uint16_t rb_uw = Rb.uq<hi:lo>; uint16_t rb_uw = Rb_uq<hi:lo>;
temp = ((temp << 16) temp = ((temp << 16)
| ((ra_uw > rb_uw) ? Ra.uq<hi:lo> | ((ra_uw > rb_uw) ? Ra_uq<hi:lo>
: Rb.uq<hi:lo>)); : Rb_uq<hi:lo>));
hi -= 16; hi -= 16;
lo -= 16; lo -= 16;
} }
@ -497,11 +497,11 @@ decode OPCODE default Unknown::unknown() {
int hi = 63; int hi = 63;
int lo = 56; int lo = 56;
for (int i = 7; i >= 0; --i) { for (int i = 7; i >= 0; --i) {
int8_t ra_sb = Ra.uq<hi:lo>; int8_t ra_sb = Ra_uq<hi:lo>;
int8_t rb_sb = Rb.uq<hi:lo>; int8_t rb_sb = Rb_uq<hi:lo>;
temp = ((temp << 8) temp = ((temp << 8)
| ((ra_sb > rb_sb) ? Ra.uq<hi:lo> | ((ra_sb > rb_sb) ? Ra_uq<hi:lo>
: Rb.uq<hi:lo>)); : Rb_uq<hi:lo>));
hi -= 8; hi -= 8;
lo -= 8; lo -= 8;
} }
@ -513,11 +513,11 @@ decode OPCODE default Unknown::unknown() {
int hi = 63; int hi = 63;
int lo = 48; int lo = 48;
for (int i = 3; i >= 0; --i) { for (int i = 3; i >= 0; --i) {
int16_t ra_sw = Ra.uq<hi:lo>; int16_t ra_sw = Ra_uq<hi:lo>;
int16_t rb_sw = Rb.uq<hi:lo>; int16_t rb_sw = Rb_uq<hi:lo>;
temp = ((temp << 16) temp = ((temp << 16)
| ((ra_sw > rb_sw) ? Ra.uq<hi:lo> | ((ra_sw > rb_sw) ? Ra_uq<hi:lo>
: Rb.uq<hi:lo>)); : Rb_uq<hi:lo>));
hi -= 16; hi -= 16;
lo -= 16; lo -= 16;
} }
@ -526,10 +526,10 @@ decode OPCODE default Unknown::unknown() {
format BasicOperateWithNopCheck { format BasicOperateWithNopCheck {
0x70: decode RB { 0x70: decode RB {
31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp); 31: ftoit({{ Rc = Fa_uq; }}, FloatCvtOp);
} }
0x78: decode RB { 0x78: decode RB {
31: ftois({{ Rc.sl = t_to_s(Fa.uq); }}, 31: ftois({{ Rc_sl = t_to_s(Fa_uq); }},
FloatCvtOp); FloatCvtOp);
} }
} }
@ -540,10 +540,10 @@ decode OPCODE default Unknown::unknown() {
format CondBranch { format CondBranch {
0x39: beq({{ cond = (Ra == 0); }}); 0x39: beq({{ cond = (Ra == 0); }});
0x3d: bne({{ cond = (Ra != 0); }}); 0x3d: bne({{ cond = (Ra != 0); }});
0x3e: bge({{ cond = (Ra.sq >= 0); }}); 0x3e: bge({{ cond = (Ra_sq >= 0); }});
0x3f: bgt({{ cond = (Ra.sq > 0); }}); 0x3f: bgt({{ cond = (Ra_sq > 0); }});
0x3b: ble({{ cond = (Ra.sq <= 0); }}); 0x3b: ble({{ cond = (Ra_sq <= 0); }});
0x3a: blt({{ cond = (Ra.sq < 0); }}); 0x3a: blt({{ cond = (Ra_sq < 0); }});
0x38: blbc({{ cond = ((Ra & 1) == 0); }}); 0x38: blbc({{ cond = ((Ra & 1) == 0); }});
0x3c: blbs({{ cond = ((Ra & 1) == 1); }}); 0x3c: blbs({{ cond = ((Ra & 1) == 1); }});
@ -577,8 +577,8 @@ decode OPCODE default Unknown::unknown() {
0x4: decode RB { 0x4: decode RB {
31: decode FP_FULLFUNC { 31: decode FP_FULLFUNC {
format BasicOperateWithNopCheck { format BasicOperateWithNopCheck {
0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp); 0x004: itofs({{ Fc_uq = s_to_t(Ra_ul); }}, FloatCvtOp);
0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp); 0x024: itoft({{ Fc_uq = Ra_uq; }}, FloatCvtOp);
0x014: FailUnimpl::itoff(); // VAX-format conversion 0x014: FailUnimpl::itoff(); // VAX-format conversion
} }
} }
@ -596,9 +596,9 @@ decode OPCODE default Unknown::unknown() {
}}, FloatSqrtOp); }}, FloatSqrtOp);
#else #else
0x0b: sqrts({{ 0x0b: sqrts({{
if (Fb.sf < 0.0) if (Fb_sf < 0.0)
fault = new ArithmeticFault; fault = new ArithmeticFault;
Fc.sf = sqrt(Fb.sf); Fc_sf = sqrt(Fb_sf);
}}, FloatSqrtOp); }}, FloatSqrtOp);
#endif #endif
0x2b: sqrtt({{ 0x2b: sqrtt({{
@ -638,10 +638,10 @@ decode OPCODE default Unknown::unknown() {
0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp); 0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp);
0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp); 0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp);
#else #else
0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }}); 0x00: adds({{ Fc_sf = Fa_sf + Fb_sf; }});
0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }}); 0x01: subs({{ Fc_sf = Fa_sf - Fb_sf; }});
0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp); 0x02: muls({{ Fc_sf = Fa_sf * Fb_sf; }}, FloatMultOp);
0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp); 0x03: divs({{ Fc_sf = Fa_sf / Fb_sf; }}, FloatDivOp);
#endif #endif
0x20: addt({{ Fc = Fa + Fb; }}); 0x20: addt({{ Fc = Fa + Fb; }});
@ -681,13 +681,13 @@ decode OPCODE default Unknown::unknown() {
0x2f: decode FP_ROUNDMODE { 0x2f: decode FP_ROUNDMODE {
format FPFixedRounding { format FPFixedRounding {
// "chopped" i.e. round toward zero // "chopped" i.e. round toward zero
0: cvttq({{ Fc.sq = (int64_t)trunc(Fb); }}, 0: cvttq({{ Fc_sq = (int64_t)trunc(Fb); }},
Chopped); Chopped);
// round to minus infinity // round to minus infinity
1: cvttq({{ Fc.sq = (int64_t)floor(Fb); }}, 1: cvttq({{ Fc_sq = (int64_t)floor(Fb); }},
MinusInfinity); MinusInfinity);
} }
default: cvttq({{ Fc.sq = (int64_t)nearbyint(Fb); }}); default: cvttq({{ Fc_sq = (int64_t)nearbyint(Fb); }});
} }
// The cvtts opcode is overloaded to be cvtst if the trap // The cvtts opcode is overloaded to be cvtst if the trap
@ -696,9 +696,9 @@ decode OPCODE default Unknown::unknown() {
format BasicOperateWithNopCheck { format BasicOperateWithNopCheck {
// trap on denorm version "cvtst/s" is // trap on denorm version "cvtst/s" is
// simulated same as cvtst // simulated same as cvtst
0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }}); 0x2ac, 0x6ac: cvtst({{ Fc = Fb_sf; }});
} }
default: cvtts({{ Fc.sf = Fb; }}); default: cvtts({{ Fc_sf = Fb; }});
} }
// The trapping mode for integer-to-FP conversions // The trapping mode for integer-to-FP conversions
@ -706,10 +706,10 @@ decode OPCODE default Unknown::unknown() {
// allowed. The full set of rounding modes are // allowed. The full set of rounding modes are
// supported though. // supported though.
0x3c: decode FP_TRAPMODE { 0x3c: decode FP_TRAPMODE {
0,7: cvtqs({{ Fc.sf = Fb.sq; }}); 0,7: cvtqs({{ Fc_sf = Fb_sq; }});
} }
0x3e: decode FP_TRAPMODE { 0x3e: decode FP_TRAPMODE {
0,7: cvtqt({{ Fc = Fb.sq; }}); 0,7: cvtqt({{ Fc = Fb_sq; }});
} }
} }
} }
@ -720,10 +720,10 @@ decode OPCODE default Unknown::unknown() {
0x17: decode FP_FULLFUNC { 0x17: decode FP_FULLFUNC {
format BasicOperateWithNopCheck { format BasicOperateWithNopCheck {
0x010: cvtlq({{ 0x010: cvtlq({{
Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>; Fc_sl = (Fb_uq<63:62> << 30) | Fb_uq<58:29>;
}}); }});
0x030: cvtql({{ 0x030: cvtql({{
Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29); Fc_uq = (Fb_uq<31:30> << 62) | (Fb_uq<29:0> << 29);
}}); }});
// We treat the precise & imprecise trapping versions of // We treat the precise & imprecise trapping versions of
@ -732,20 +732,20 @@ decode OPCODE default Unknown::unknown() {
// To avoid overflow, all the upper 32 bits must match // To avoid overflow, all the upper 32 bits must match
// the sign bit of the lower 32. We code this as // the sign bit of the lower 32. We code this as
// checking the upper 33 bits for all 0s or all 1s. // checking the upper 33 bits for all 0s or all 1s.
uint64_t sign_bits = Fb.uq<63:31>; uint64_t sign_bits = Fb_uq<63:31>;
if (sign_bits != 0 && sign_bits != mask(33)) if (sign_bits != 0 && sign_bits != mask(33))
fault = new IntegerOverflowFault; fault = new IntegerOverflowFault;
Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29); Fc_uq = (Fb_uq<31:30> << 62) | (Fb_uq<29:0> << 29);
}}); }});
0x020: cpys({{ // copy sign 0x020: cpys({{ // copy sign
Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>; Fc_uq = (Fa_uq<63:> << 63) | Fb_uq<62:0>;
}}); }});
0x021: cpysn({{ // copy sign negated 0x021: cpysn({{ // copy sign negated
Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>; Fc_uq = (~Fa_uq<63:> << 63) | Fb_uq<62:0>;
}}); }});
0x022: cpyse({{ // copy sign and exponent 0x022: cpyse({{ // copy sign and exponent
Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>; Fc_uq = (Fa_uq<63:52> << 52) | Fb_uq<51:0>;
}}); }});
0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }}); 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
@ -755,8 +755,8 @@ decode OPCODE default Unknown::unknown() {
0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }}); 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }}); 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }});
0x024: mt_fpcr({{ FPCR = Fa.uq; }}, IsIprAccess); 0x024: mt_fpcr({{ FPCR = Fa_uq; }}, IsIprAccess);
0x025: mf_fpcr({{ Fa.uq = FPCR; }}, IsIprAccess); 0x025: mf_fpcr({{ Fa_uq = FPCR; }}, IsIprAccess);
} }
} }
@ -862,9 +862,9 @@ decode OPCODE default Unknown::unknown() {
0: OpcdecFault::hw_st_quad(); 0: OpcdecFault::hw_st_quad();
1: decode HW_LDST_QUAD { 1: decode HW_LDST_QUAD {
format HwLoad { format HwLoad {
0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem_ul; }},
L, IsSerializing, IsSerializeBefore); L, IsSerializing, IsSerializeBefore);
1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem_uq; }},
Q, IsSerializing, IsSerializeBefore); Q, IsSerializing, IsSerializeBefore);
} }
} }
@ -876,9 +876,9 @@ decode OPCODE default Unknown::unknown() {
1: decode HW_LDST_COND { 1: decode HW_LDST_COND {
0: decode HW_LDST_QUAD { 0: decode HW_LDST_QUAD {
0: hw_st({{ EA = (Rb + disp) & ~3; }}, 0: hw_st({{ EA = (Rb + disp) & ~3; }},
{{ Mem.ul = Ra<31:0>; }}, L, IsSerializing, IsSerializeBefore); {{ Mem_ul = Ra<31:0>; }}, L, IsSerializing, IsSerializeBefore);
1: hw_st({{ EA = (Rb + disp) & ~7; }}, 1: hw_st({{ EA = (Rb + disp) & ~7; }},
{{ Mem.uq = Ra.uq; }}, Q, IsSerializing, IsSerializeBefore); {{ Mem_uq = Ra_uq; }}, Q, IsSerializing, IsSerializeBefore);
} }
1: FailUnimpl::hw_st_cond(); 1: FailUnimpl::hw_st_cond();

2
src/arch/alpha/isa/int.isa
View file

@ -110,7 +110,7 @@ def format IntegerOperate(code, *opt_flags) {{
# generate immediate version by substituting 'imm' # generate immediate version by substituting 'imm'
# note that imm takes no extenstion, so we extend # note that imm takes no extenstion, so we extend
# the regexp to replace any extension as well # the regexp to replace any extension as well
imm_code = re.sub(r'Rb_or_imm(\.\w+)?', 'imm', orig_code) imm_code = re.sub(r'Rb_or_imm(_\w+)?', 'imm', orig_code)
# generate declaration for register version # generate declaration for register version
iop = InstObjParams(name, Name, 'AlphaStaticInst', code, opt_flags) iop = InstObjParams(name, Name, 'AlphaStaticInst', code, opt_flags)

2
src/arch/alpha/isa/main.isa
View file

@ -176,7 +176,7 @@ def operand_types {{
def operands {{ def operands {{
# Int regs default to unsigned, but code should not count on this. # Int regs default to unsigned, but code should not count on this.
# For clarity, descriptions that depend on unsigned behavior should # For clarity, descriptions that depend on unsigned behavior should
# explicitly specify '.uq'. # explicitly specify '_uq'.
'Ra': ('IntReg', 'uq', 'PALMODE ? reg_redir[RA] : RA', 'Ra': ('IntReg', 'uq', 'PALMODE ? reg_redir[RA] : RA',
'IsInteger', 1), 'IsInteger', 1),
'Rb': ('IntReg', 'uq', 'PALMODE ? reg_redir[RB] : RB', 'Rb': ('IntReg', 'uq', 'PALMODE ? reg_redir[RB] : RB',

4
src/arch/arm/isa/insts/branch.isa
View file

@ -172,7 +172,7 @@ let {{
ArmISA::TLB::MustBeOne; ArmISA::TLB::MustBeOne;
EA = Op1 + Op2 * 2 EA = Op1 + Op2 * 2
''' '''
accCode = 'NPC = PC + 2 * (Mem.uh);\n' accCode = 'NPC = PC + 2 * (Mem_uh);\n'
mnem = "tbh" mnem = "tbh"
else: else:
eaCode = ''' eaCode = '''
@ -181,7 +181,7 @@ let {{
ArmISA::TLB::MustBeOne; ArmISA::TLB::MustBeOne;
EA = Op1 + Op2 EA = Op1 + Op2
''' '''
accCode = 'NPC = PC + 2 * (Mem.ub)' accCode = 'NPC = PC + 2 * (Mem_ub)'
mnem = "tbb" mnem = "tbb"
iop = InstObjParams(mnem, mnem.capitalize(), "BranchRegReg", iop = InstObjParams(mnem, mnem.capitalize(), "BranchRegReg",
{'ea_code': eaCode, {'ea_code': eaCode,

156
src/arch/arm/isa/insts/data.isa
View file

@ -302,7 +302,7 @@ let {{
buildRegDataInst("qadd", ''' buildRegDataInst("qadd", '''
int32_t midRes; int32_t midRes;
resTemp = saturateOp<32>(midRes, Op1.sw, Op2.sw); resTemp = saturateOp<32>(midRes, Op1_sw, Op2_sw);
Dest = midRes; Dest = midRes;
''', flagType="saturate", buildNonCc=False) ''', flagType="saturate", buildNonCc=False)
buildRegDataInst("qadd16", ''' buildRegDataInst("qadd16", '''
@ -310,8 +310,8 @@ let {{
for (unsigned i = 0; i < 2; i++) { for (unsigned i = 0; i < 2; i++) {
int high = (i + 1) * 16 - 1; int high = (i + 1) * 16 - 1;
int low = i * 16; int low = i * 16;
int64_t arg1 = sext<16>(bits(Op1.sw, high, low)); int64_t arg1 = sext<16>(bits(Op1_sw, high, low));
int64_t arg2 = sext<16>(bits(Op2.sw, high, low)); int64_t arg2 = sext<16>(bits(Op2_sw, high, low));
saturateOp<16>(midRes, arg1, arg2); saturateOp<16>(midRes, arg1, arg2);
replaceBits(resTemp, high, low, midRes); replaceBits(resTemp, high, low, midRes);
} }
@ -322,8 +322,8 @@ let {{
for (unsigned i = 0; i < 4; i++) { for (unsigned i = 0; i < 4; i++) {
int high = (i + 1) * 8 - 1; int high = (i + 1) * 8 - 1;
int low = i * 8; int low = i * 8;
int64_t arg1 = sext<8>(bits(Op1.sw, high, low)); int64_t arg1 = sext<8>(bits(Op1_sw, high, low));
int64_t arg2 = sext<8>(bits(Op2.sw, high, low)); int64_t arg2 = sext<8>(bits(Op2_sw, high, low));
saturateOp<8>(midRes, arg1, arg2); saturateOp<8>(midRes, arg1, arg2);
replaceBits(resTemp, high, low, midRes); replaceBits(resTemp, high, low, midRes);
} }
@ -331,13 +331,13 @@ let {{
''', flagType="none", buildCc=False) ''', flagType="none", buildCc=False)
buildRegDataInst("qdadd", ''' buildRegDataInst("qdadd", '''
int32_t midRes; int32_t midRes;
resTemp = saturateOp<32>(midRes, Op2.sw, Op2.sw) | resTemp = saturateOp<32>(midRes, Op2_sw, Op2_sw) |
saturateOp<32>(midRes, Op1.sw, midRes); saturateOp<32>(midRes, Op1_sw, midRes);
Dest = midRes; Dest = midRes;
''', flagType="saturate", buildNonCc=False) ''', flagType="saturate", buildNonCc=False)
buildRegDataInst("qsub", ''' buildRegDataInst("qsub", '''
int32_t midRes; int32_t midRes;
resTemp = saturateOp<32>(midRes, Op1.sw, Op2.sw, true); resTemp = saturateOp<32>(midRes, Op1_sw, Op2_sw, true);
Dest = midRes; Dest = midRes;
''', flagType="saturate") ''', flagType="saturate")
buildRegDataInst("qsub16", ''' buildRegDataInst("qsub16", '''
@ -345,8 +345,8 @@ let {{
for (unsigned i = 0; i < 2; i++) { for (unsigned i = 0; i < 2; i++) {
int high = (i + 1) * 16 - 1; int high = (i + 1) * 16 - 1;
int low = i * 16; int low = i * 16;
int64_t arg1 = sext<16>(bits(Op1.sw, high, low)); int64_t arg1 = sext<16>(bits(Op1_sw, high, low));
int64_t arg2 = sext<16>(bits(Op2.sw, high, low)); int64_t arg2 = sext<16>(bits(Op2_sw, high, low));
saturateOp<16>(midRes, arg1, arg2, true); saturateOp<16>(midRes, arg1, arg2, true);
replaceBits(resTemp, high, low, midRes); replaceBits(resTemp, high, low, midRes);
} }
@ -357,8 +357,8 @@ let {{
for (unsigned i = 0; i < 4; i++) { for (unsigned i = 0; i < 4; i++) {
int high = (i + 1) * 8 - 1; int high = (i + 1) * 8 - 1;
int low = i * 8; int low = i * 8;
int64_t arg1 = sext<8>(bits(Op1.sw, high, low)); int64_t arg1 = sext<8>(bits(Op1_sw, high, low));
int64_t arg2 = sext<8>(bits(Op2.sw, high, low)); int64_t arg2 = sext<8>(bits(Op2_sw, high, low));
saturateOp<8>(midRes, arg1, arg2, true); saturateOp<8>(midRes, arg1, arg2, true);
replaceBits(resTemp, high, low, midRes); replaceBits(resTemp, high, low, midRes);
} }
@ -366,16 +366,16 @@ let {{
''', flagType="none", buildCc=False) ''', flagType="none", buildCc=False)
buildRegDataInst("qdsub", ''' buildRegDataInst("qdsub", '''
int32_t midRes; int32_t midRes;
resTemp = saturateOp<32>(midRes, Op2.sw, Op2.sw) | resTemp = saturateOp<32>(midRes, Op2_sw, Op2_sw) |
saturateOp<32>(midRes, Op1.sw, midRes, true); saturateOp<32>(midRes, Op1_sw, midRes, true);
Dest = midRes; Dest = midRes;
''', flagType="saturate", buildNonCc=False) ''', flagType="saturate", buildNonCc=False)
buildRegDataInst("qasx", ''' buildRegDataInst("qasx", '''
int32_t midRes; int32_t midRes;
int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0)); int64_t arg1Low = sext<16>(bits(Op1_sw, 15, 0));
int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16)); int64_t arg1High = sext<16>(bits(Op1_sw, 31, 16));
int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0)); int64_t arg2Low = sext<16>(bits(Op2_sw, 15, 0));
int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16)); int64_t arg2High = sext<16>(bits(Op2_sw, 31, 16));
saturateOp<16>(midRes, arg1Low, arg2High, true); saturateOp<16>(midRes, arg1Low, arg2High, true);
replaceBits(resTemp, 15, 0, midRes); replaceBits(resTemp, 15, 0, midRes);
saturateOp<16>(midRes, arg1High, arg2Low); saturateOp<16>(midRes, arg1High, arg2Low);
@ -384,10 +384,10 @@ let {{
''', flagType="none", buildCc=False) ''', flagType="none", buildCc=False)
buildRegDataInst("qsax", ''' buildRegDataInst("qsax", '''
int32_t midRes; int32_t midRes;
int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0)); int64_t arg1Low = sext<16>(bits(Op1_sw, 15, 0));
int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16)); int64_t arg1High = sext<16>(bits(Op1_sw, 31, 16));
int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0)); int64_t arg2Low = sext<16>(bits(Op2_sw, 15, 0));
int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16)); int64_t arg2High = sext<16>(bits(Op2_sw, 31, 16));
saturateOp<16>(midRes, arg1Low, arg2High); saturateOp<16>(midRes, arg1Low, arg2High);
replaceBits(resTemp, 15, 0, midRes); replaceBits(resTemp, 15, 0, midRes);
saturateOp<16>(midRes, arg1High, arg2Low, true); saturateOp<16>(midRes, arg1High, arg2Low, true);
@ -401,8 +401,8 @@ let {{
for (unsigned i = 0; i < 4; i++) { for (unsigned i = 0; i < 4; i++) {
int high = (i + 1) * 8 - 1; int high = (i + 1) * 8 - 1;
int low = i * 8; int low = i * 8;
int32_t midRes = sext<8>(bits(Op1.sw, high, low)) + int32_t midRes = sext<8>(bits(Op1_sw, high, low)) +
sext<8>(bits(Op2.sw, high, low)); sext<8>(bits(Op2_sw, high, low));
replaceBits(resTemp, high, low, midRes); replaceBits(resTemp, high, low, midRes);
if (midRes >= 0) { if (midRes >= 0) {
geBits = geBits | (1 << i); geBits = geBits | (1 << i);
@ -417,8 +417,8 @@ let {{
for (unsigned i = 0; i < 2; i++) { for (unsigned i = 0; i < 2; i++) {
int high = (i + 1) * 16 - 1; int high = (i + 1) * 16 - 1;
int low = i * 16; int low = i * 16;
int32_t midRes = sext<16>(bits(Op1.sw, high, low)) + int32_t midRes = sext<16>(bits(Op1_sw, high, low)) +
sext<16>(bits(Op2.sw, high, low)); sext<16>(bits(Op2_sw, high, low));
replaceBits(resTemp, high, low, midRes); replaceBits(resTemp, high, low, midRes);
if (midRes >= 0) { if (midRes >= 0) {
geBits = geBits | (0x3 << (i * 2)); geBits = geBits | (0x3 << (i * 2));
@ -434,8 +434,8 @@ let {{
for (unsigned i = 0; i < 4; i++) { for (unsigned i = 0; i < 4; i++) {
int high = (i + 1) * 8 - 1; int high = (i + 1) * 8 - 1;
int low = i * 8; int low = i * 8;
int32_t midRes = sext<8>(bits(Op1.sw, high, low)) - int32_t midRes = sext<8>(bits(Op1_sw, high, low)) -
sext<8>(bits(Op2.sw, high, low)); sext<8>(bits(Op2_sw, high, low));
replaceBits(resTemp, high, low, midRes); replaceBits(resTemp, high, low, midRes);
if (midRes >= 0) { if (midRes >= 0) {
geBits = geBits | (1 << i); geBits = geBits | (1 << i);
@ -450,8 +450,8 @@ let {{
for (unsigned i = 0; i < 2; i++) { for (unsigned i = 0; i < 2; i++) {
int high = (i + 1) * 16 - 1; int high = (i + 1) * 16 - 1;
int low = i * 16; int low = i * 16;
int32_t midRes = sext<16>(bits(Op1.sw, high, low)) - int32_t midRes = sext<16>(bits(Op1_sw, high, low)) -
sext<16>(bits(Op2.sw, high, low)); sext<16>(bits(Op2_sw, high, low));
replaceBits(resTemp, high, low, midRes); replaceBits(resTemp, high, low, midRes);
if (midRes >= 0) { if (midRes >= 0) {
geBits = geBits | (0x3 << (i * 2)); geBits = geBits | (0x3 << (i * 2));
@ -463,10 +463,10 @@ let {{
buildRegDataInst("sasx", ''' buildRegDataInst("sasx", '''
int32_t midRes, geBits = 0; int32_t midRes, geBits = 0;
resTemp = 0; resTemp = 0;
int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0)); int64_t arg1Low = sext<16>(bits(Op1_sw, 15, 0));
int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16)); int64_t arg1High = sext<16>(bits(Op1_sw, 31, 16));
int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0)); int64_t arg2Low = sext<16>(bits(Op2_sw, 15, 0));
int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16)); int64_t arg2High = sext<16>(bits(Op2_sw, 31, 16));
midRes = arg1Low - arg2High; midRes = arg1Low - arg2High;
if (midRes >= 0) { if (midRes >= 0) {
geBits = geBits | 0x3; geBits = geBits | 0x3;
@ -483,10 +483,10 @@ let {{
buildRegDataInst("ssax", ''' buildRegDataInst("ssax", '''
int32_t midRes, geBits = 0; int32_t midRes, geBits = 0;
resTemp = 0; resTemp = 0;
int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0)); int64_t arg1Low = sext<16>(bits(Op1_sw, 15, 0));
int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16)); int64_t arg1High = sext<16>(bits(Op1_sw, 31, 16));
int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0)); int64_t arg2Low = sext<16>(bits(Op2_sw, 15, 0));
int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16)); int64_t arg2High = sext<16>(bits(Op2_sw, 31, 16));
midRes = arg1Low + arg2High; midRes = arg1Low + arg2High;
if (midRes >= 0) { if (midRes >= 0) {
geBits = geBits | 0x3; geBits = geBits | 0x3;
@ -507,8 +507,8 @@ let {{
int high = (i + 1) * 8 - 1; int high = (i + 1) * 8 - 1;
int low = i * 8; int low = i * 8;
int32_t midRes = int32_t midRes =
(uint64_t)(sext<8>(bits(Op1.sw, high, low)) + (uint64_t)(sext<8>(bits(Op1_sw, high, low)) +
sext<8>(bits(Op2.sw, high, low))) >> 1; sext<8>(bits(Op2_sw, high, low))) >> 1;
replaceBits(resTemp, high, low, midRes); replaceBits(resTemp, high, low, midRes);
} }
Dest = resTemp; Dest = resTemp;
@ -519,8 +519,8 @@ let {{
int high = (i + 1) * 16 - 1; int high = (i + 1) * 16 - 1;
int low = i * 16; int low = i * 16;
int32_t midRes = int32_t midRes =
(uint64_t)(sext<16>(bits(Op1.sw, high, low)) + (uint64_t)(sext<16>(bits(Op1_sw, high, low)) +
sext<16>(bits(Op2.sw, high, low))) >> 1; sext<16>(bits(Op2_sw, high, low))) >> 1;
replaceBits(resTemp, high, low, midRes); replaceBits(resTemp, high, low, midRes);
} }
Dest = resTemp; Dest = resTemp;
@ -531,8 +531,8 @@ let {{
int high = (i + 1) * 8 - 1; int high = (i + 1) * 8 - 1;
int low = i * 8; int low = i * 8;
int32_t midRes = int32_t midRes =
(uint64_t)(sext<8>(bits(Op1.sw, high, low)) - (uint64_t)(sext<8>(bits(Op1_sw, high, low)) -
sext<8>(bits(Op2.sw, high, low))) >> 1; sext<8>(bits(Op2_sw, high, low))) >> 1;
replaceBits(resTemp, high, low, midRes); replaceBits(resTemp, high, low, midRes);
} }
Dest = resTemp; Dest = resTemp;
@ -543,8 +543,8 @@ let {{
int high = (i + 1) * 16 - 1; int high = (i + 1) * 16 - 1;
int low = i * 16; int low = i * 16;
int32_t midRes = int32_t midRes =
(uint64_t)(sext<16>(bits(Op1.sw, high, low)) - (uint64_t)(sext<16>(bits(Op1_sw, high, low)) -
sext<16>(bits(Op2.sw, high, low))) >> 1; sext<16>(bits(Op2_sw, high, low))) >> 1;
replaceBits(resTemp, high, low, midRes); replaceBits(resTemp, high, low, midRes);
} }
Dest = resTemp; Dest = resTemp;
@ -552,10 +552,10 @@ let {{
buildRegDataInst("shasx", ''' buildRegDataInst("shasx", '''
int32_t midRes; int32_t midRes;
resTemp = 0; resTemp = 0;
int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0)); int64_t arg1Low = sext<16>(bits(Op1_sw, 15, 0));
int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16)); int64_t arg1High = sext<16>(bits(Op1_sw, 31, 16));
int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0)); int64_t arg2Low = sext<16>(bits(Op2_sw, 15, 0));
int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16)); int64_t arg2High = sext<16>(bits(Op2_sw, 31, 16));
midRes = (uint64_t)(arg1Low - arg2High) >> 1; midRes = (uint64_t)(arg1Low - arg2High) >> 1;
replaceBits(resTemp, 15, 0, midRes); replaceBits(resTemp, 15, 0, midRes);
midRes = (arg1High + arg2Low) >> 1; midRes = (arg1High + arg2Low) >> 1;
@ -565,10 +565,10 @@ let {{
buildRegDataInst("shsax", ''' buildRegDataInst("shsax", '''
int32_t midRes; int32_t midRes;
resTemp = 0; resTemp = 0;
int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0)); int64_t arg1Low = sext<16>(bits(Op1_sw, 15, 0));
int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16)); int64_t arg1High = sext<16>(bits(Op1_sw, 31, 16));
int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0)); int64_t arg2Low = sext<16>(bits(Op2_sw, 15, 0));
int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16)); int64_t arg2High = sext<16>(bits(Op2_sw, 31, 16));
midRes = (uint64_t)(arg1Low + arg2High) >> 1; midRes = (uint64_t)(arg1Low + arg2High) >> 1;
replaceBits(resTemp, 15, 0, midRes); replaceBits(resTemp, 15, 0, midRes);
midRes = (uint64_t)(arg1High - arg2Low) >> 1; midRes = (uint64_t)(arg1High - arg2Low) >> 1;
@ -626,10 +626,10 @@ let {{
''', flagType="none", buildCc=False) ''', flagType="none", buildCc=False)
buildRegDataInst("uqasx", ''' buildRegDataInst("uqasx", '''
uint32_t midRes; uint32_t midRes;
uint64_t arg1Low = bits(Op1.sw, 15, 0); uint64_t arg1Low = bits(Op1_sw, 15, 0);
uint64_t arg1High = bits(Op1.sw, 31, 16); uint64_t arg1High = bits(Op1_sw, 31, 16);
uint64_t arg2Low = bits(Op2.sw, 15, 0); uint64_t arg2Low = bits(Op2_sw, 15, 0);
uint64_t arg2High = bits(Op2.sw, 31, 16); uint64_t arg2High = bits(Op2_sw, 31, 16);
uSaturateOp<16>(midRes, arg1Low, arg2High, true); uSaturateOp<16>(midRes, arg1Low, arg2High, true);
replaceBits(resTemp, 15, 0, midRes); replaceBits(resTemp, 15, 0, midRes);
uSaturateOp<16>(midRes, arg1High, arg2Low); uSaturateOp<16>(midRes, arg1High, arg2Low);
@ -638,10 +638,10 @@ let {{
''', flagType="none", buildCc=False) ''', flagType="none", buildCc=False)
buildRegDataInst("uqsax", ''' buildRegDataInst("uqsax", '''
uint32_t midRes; uint32_t midRes;
uint64_t arg1Low = bits(Op1.sw, 15, 0); uint64_t arg1Low = bits(Op1_sw, 15, 0);
uint64_t arg1High = bits(Op1.sw, 31, 16); uint64_t arg1High = bits(Op1_sw, 31, 16);
uint64_t arg2Low = bits(Op2.sw, 15, 0); uint64_t arg2Low = bits(Op2_sw, 15, 0);
uint64_t arg2High = bits(Op2.sw, 31, 16); uint64_t arg2High = bits(Op2_sw, 31, 16);
uSaturateOp<16>(midRes, arg1Low, arg2High); uSaturateOp<16>(midRes, arg1Low, arg2High);
replaceBits(resTemp, 15, 0, midRes); replaceBits(resTemp, 15, 0, midRes);
uSaturateOp<16>(midRes, arg1High, arg2Low, true); uSaturateOp<16>(midRes, arg1High, arg2Low, true);
@ -716,10 +716,10 @@ let {{
buildRegDataInst("uasx", ''' buildRegDataInst("uasx", '''
int32_t midRes, geBits = 0; int32_t midRes, geBits = 0;
resTemp = 0; resTemp = 0;
int64_t arg1Low = bits(Op1.sw, 15, 0); int64_t arg1Low = bits(Op1_sw, 15, 0);
int64_t arg1High = bits(Op1.sw, 31, 16); int64_t arg1High = bits(Op1_sw, 31, 16);
int64_t arg2Low = bits(Op2.sw, 15, 0); int64_t arg2Low = bits(Op2_sw, 15, 0);
int64_t arg2High = bits(Op2.sw, 31, 16); int64_t arg2High = bits(Op2_sw, 31, 16);
midRes = arg1Low - arg2High; midRes = arg1Low - arg2High;
if (midRes >= 0) { if (midRes >= 0) {
geBits = geBits | 0x3; geBits = geBits | 0x3;
@ -736,10 +736,10 @@ let {{
buildRegDataInst("usax", ''' buildRegDataInst("usax", '''
int32_t midRes, geBits = 0; int32_t midRes, geBits = 0;
resTemp = 0; resTemp = 0;
int64_t arg1Low = bits(Op1.sw, 15, 0); int64_t arg1Low = bits(Op1_sw, 15, 0);
int64_t arg1High = bits(Op1.sw, 31, 16); int64_t arg1High = bits(Op1_sw, 31, 16);
int64_t arg2Low = bits(Op2.sw, 15, 0); int64_t arg2Low = bits(Op2_sw, 15, 0);
int64_t arg2High = bits(Op2.sw, 31, 16); int64_t arg2High = bits(Op2_sw, 31, 16);
midRes = arg1Low + arg2High; midRes = arg1Low + arg2High;
if (midRes >= 0x10000) { if (midRes >= 0x10000) {
geBits = geBits | 0x3; geBits = geBits | 0x3;
@ -801,10 +801,10 @@ let {{
buildRegDataInst("uhasx", ''' buildRegDataInst("uhasx", '''
int32_t midRes; int32_t midRes;
resTemp = 0; resTemp = 0;
int64_t arg1Low = bits(Op1.sw, 15, 0); int64_t arg1Low = bits(Op1_sw, 15, 0);
int64_t arg1High = bits(Op1.sw, 31, 16); int64_t arg1High = bits(Op1_sw, 31, 16);
int64_t arg2Low = bits(Op2.sw, 15, 0); int64_t arg2Low = bits(Op2_sw, 15, 0);
int64_t arg2High = bits(Op2.sw, 31, 16); int64_t arg2High = bits(Op2_sw, 31, 16);
midRes = (arg1Low - arg2High) >> 1; midRes = (arg1Low - arg2High) >> 1;
replaceBits(resTemp, 15, 0, midRes); replaceBits(resTemp, 15, 0, midRes);
midRes = (arg1High + arg2Low) >> 1; midRes = (arg1High + arg2Low) >> 1;
@ -814,10 +814,10 @@ let {{
buildRegDataInst("uhsax", ''' buildRegDataInst("uhsax", '''
int32_t midRes; int32_t midRes;
resTemp = 0; resTemp = 0;
int64_t arg1Low = bits(Op1.sw, 15, 0); int64_t arg1Low = bits(Op1_sw, 15, 0);
int64_t arg1High = bits(Op1.sw, 31, 16); int64_t arg1High = bits(Op1_sw, 31, 16);
int64_t arg2Low = bits(Op2.sw, 15, 0); int64_t arg2Low = bits(Op2_sw, 15, 0);
int64_t arg2High = bits(Op2.sw, 31, 16); int64_t arg2High = bits(Op2_sw, 31, 16);
midRes = (arg1Low + arg2High) >> 1; midRes = (arg1Low + arg2High) >> 1;
replaceBits(resTemp, 15, 0, midRes); replaceBits(resTemp, 15, 0, midRes);
midRes = (arg1High - arg2Low) >> 1; midRes = (arg1High - arg2Low) >> 1;

16
src/arch/arm/isa/insts/div.isa
View file

@ -39,7 +39,7 @@
let {{ let {{
sdivCode = ''' sdivCode = '''
if (Op2.sw == 0) { if (Op2_sw == 0) {
if (((SCTLR)Sctlr).dz) { if (((SCTLR)Sctlr).dz) {
#if FULL_SYSTEM #if FULL_SYSTEM
return new UndefinedInstruction; return new UndefinedInstruction;
@ -47,11 +47,11 @@ let {{
return new UndefinedInstruction(false, mnemonic); return new UndefinedInstruction(false, mnemonic);
#endif #endif
} }
Dest.sw = 0; Dest_sw = 0;
} else if (Op1.sw == INT_MIN && Op2.sw == -1) { } else if (Op1_sw == INT_MIN && Op2_sw == -1) {
Dest.sw = INT_MIN; Dest_sw = INT_MIN;
} else { } else {
Dest.sw = Op1.sw / Op2.sw; Dest_sw = Op1_sw / Op2_sw;
} }
''' '''
sdivIop = InstObjParams("sdiv", "Sdiv", "RegRegRegOp", sdivIop = InstObjParams("sdiv", "Sdiv", "RegRegRegOp",
@ -63,7 +63,7 @@ let {{
exec_output = PredOpExecute.subst(sdivIop) exec_output = PredOpExecute.subst(sdivIop)
udivCode = ''' udivCode = '''
if (Op2.uw == 0) { if (Op2_uw == 0) {
if (((SCTLR)Sctlr).dz) { if (((SCTLR)Sctlr).dz) {
#if FULL_SYSTEM #if FULL_SYSTEM
return new UndefinedInstruction; return new UndefinedInstruction;
@ -71,9 +71,9 @@ let {{
return new UndefinedInstruction(false, mnemonic); return new UndefinedInstruction(false, mnemonic);
#endif #endif
} }
Dest.uw = 0; Dest_uw = 0;
} else { } else {
Dest.uw = Op1.uw / Op2.uw; Dest_uw = Op1_uw / Op2_uw;
} }
''' '''
udivIop = InstObjParams("udiv", "Udiv", "RegRegRegOp", udivIop = InstObjParams("udiv", "Udiv", "RegRegRegOp",

284
src/arch/arm/isa/insts/fp.isa
View file

@ -250,7 +250,7 @@ let {{
exec_output += PredOpExecute.subst(vmrsApsrFpscrIop); exec_output += PredOpExecute.subst(vmrsApsrFpscrIop);
vmovImmSCode = vfpEnabledCheckCode + ''' vmovImmSCode = vfpEnabledCheckCode + '''
FpDest.uw = bits(imm, 31, 0); FpDest_uw = bits(imm, 31, 0);
''' '''
vmovImmSIop = InstObjParams("vmov", "VmovImmS", "FpRegImmOp", vmovImmSIop = InstObjParams("vmov", "VmovImmS", "FpRegImmOp",
{ "code": vmovImmSCode, { "code": vmovImmSCode,
@ -261,8 +261,8 @@ let {{
exec_output += PredOpExecute.subst(vmovImmSIop); exec_output += PredOpExecute.subst(vmovImmSIop);
vmovImmDCode = vfpEnabledCheckCode + ''' vmovImmDCode = vfpEnabledCheckCode + '''
FpDestP0.uw = bits(imm, 31, 0); FpDestP0_uw = bits(imm, 31, 0);
FpDestP1.uw = bits(imm, 63, 32); FpDestP1_uw = bits(imm, 63, 32);
''' '''
vmovImmDIop = InstObjParams("vmov", "VmovImmD", "FpRegImmOp", vmovImmDIop = InstObjParams("vmov", "VmovImmD", "FpRegImmOp",
{ "code": vmovImmDCode, { "code": vmovImmDCode,
@ -273,10 +273,10 @@ let {{
exec_output += PredOpExecute.subst(vmovImmDIop); exec_output += PredOpExecute.subst(vmovImmDIop);
vmovImmQCode = vfpEnabledCheckCode + ''' vmovImmQCode = vfpEnabledCheckCode + '''
FpDestP0.uw = bits(imm, 31, 0); FpDestP0_uw = bits(imm, 31, 0);
FpDestP1.uw = bits(imm, 63, 32); FpDestP1_uw = bits(imm, 63, 32);
FpDestP2.uw = bits(imm, 31, 0); FpDestP2_uw = bits(imm, 31, 0);
FpDestP3.uw = bits(imm, 63, 32); FpDestP3_uw = bits(imm, 63, 32);
''' '''
vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "FpRegImmOp", vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "FpRegImmOp",
{ "code": vmovImmQCode, { "code": vmovImmQCode,
@ -287,7 +287,7 @@ let {{
exec_output += PredOpExecute.subst(vmovImmQIop); exec_output += PredOpExecute.subst(vmovImmQIop);
vmovRegSCode = vfpEnabledCheckCode + ''' vmovRegSCode = vfpEnabledCheckCode + '''
FpDest.uw = FpOp1.uw; FpDest_uw = FpOp1_uw;
''' '''
vmovRegSIop = InstObjParams("vmov", "VmovRegS", "FpRegRegOp", vmovRegSIop = InstObjParams("vmov", "VmovRegS", "FpRegRegOp",
{ "code": vmovRegSCode, { "code": vmovRegSCode,
@ -298,8 +298,8 @@ let {{
exec_output += PredOpExecute.subst(vmovRegSIop); exec_output += PredOpExecute.subst(vmovRegSIop);
vmovRegDCode = vfpEnabledCheckCode + ''' vmovRegDCode = vfpEnabledCheckCode + '''
FpDestP0.uw = FpOp1P0.uw; FpDestP0_uw = FpOp1P0_uw;
FpDestP1.uw = FpOp1P1.uw; FpDestP1_uw = FpOp1P1_uw;
''' '''
vmovRegDIop = InstObjParams("vmov", "VmovRegD", "FpRegRegOp", vmovRegDIop = InstObjParams("vmov", "VmovRegD", "FpRegRegOp",
{ "code": vmovRegDCode, { "code": vmovRegDCode,
@ -310,10 +310,10 @@ let {{
exec_output += PredOpExecute.subst(vmovRegDIop); exec_output += PredOpExecute.subst(vmovRegDIop);
vmovRegQCode = vfpEnabledCheckCode + ''' vmovRegQCode = vfpEnabledCheckCode + '''
FpDestP0.uw = FpOp1P0.uw; FpDestP0_uw = FpOp1P0_uw;
FpDestP1.uw = FpOp1P1.uw; FpDestP1_uw = FpOp1P1_uw;
FpDestP2.uw = FpOp1P2.uw; FpDestP2_uw = FpOp1P2_uw;
FpDestP3.uw = FpOp1P3.uw; FpDestP3_uw = FpOp1P3_uw;
''' '''
vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "FpRegRegOp", vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "FpRegRegOp",
{ "code": vmovRegQCode, { "code": vmovRegQCode,
@ -324,7 +324,7 @@ let {{
exec_output += PredOpExecute.subst(vmovRegQIop); exec_output += PredOpExecute.subst(vmovRegQIop);
vmovCoreRegBCode = vfpEnabledCheckCode + ''' vmovCoreRegBCode = vfpEnabledCheckCode + '''
FpDest.uw = insertBits(FpDest.uw, imm * 8 + 7, imm * 8, Op1.ub); FpDest_uw = insertBits(FpDest_uw, imm * 8 + 7, imm * 8, Op1_ub);
''' '''
vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "FpRegRegImmOp", vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "FpRegRegImmOp",
{ "code": vmovCoreRegBCode, { "code": vmovCoreRegBCode,
@ -335,7 +335,7 @@ let {{
exec_output += PredOpExecute.subst(vmovCoreRegBIop); exec_output += PredOpExecute.subst(vmovCoreRegBIop);
vmovCoreRegHCode = vfpEnabledCheckCode + ''' vmovCoreRegHCode = vfpEnabledCheckCode + '''
FpDest.uw = insertBits(FpDest.uw, imm * 16 + 15, imm * 16, Op1.uh); FpDest_uw = insertBits(FpDest_uw, imm * 16 + 15, imm * 16, Op1_uh);
''' '''
vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "FpRegRegImmOp", vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "FpRegRegImmOp",
{ "code": vmovCoreRegHCode, { "code": vmovCoreRegHCode,
@ -346,7 +346,7 @@ let {{
exec_output += PredOpExecute.subst(vmovCoreRegHIop); exec_output += PredOpExecute.subst(vmovCoreRegHIop);
vmovCoreRegWCode = vfpEnabledCheckCode + ''' vmovCoreRegWCode = vfpEnabledCheckCode + '''
FpDest.uw = Op1.uw; FpDest_uw = Op1_uw;
''' '''
vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "FpRegRegOp", vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "FpRegRegOp",
{ "code": vmovCoreRegWCode, { "code": vmovCoreRegWCode,
@ -358,7 +358,7 @@ let {{
vmovRegCoreUBCode = vfpEnabledCheckCode + ''' vmovRegCoreUBCode = vfpEnabledCheckCode + '''
assert(imm < 4); assert(imm < 4);
Dest = bits(FpOp1.uw, imm * 8 + 7, imm * 8); Dest = bits(FpOp1_uw, imm * 8 + 7, imm * 8);
''' '''
vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "FpRegRegImmOp", vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "FpRegRegImmOp",
{ "code": vmovRegCoreUBCode, { "code": vmovRegCoreUBCode,
@ -370,7 +370,7 @@ let {{
vmovRegCoreUHCode = vfpEnabledCheckCode + ''' vmovRegCoreUHCode = vfpEnabledCheckCode + '''
assert(imm < 2); assert(imm < 2);
Dest = bits(FpOp1.uw, imm * 16 + 15, imm * 16); Dest = bits(FpOp1_uw, imm * 16 + 15, imm * 16);
''' '''
vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "FpRegRegImmOp", vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "FpRegRegImmOp",
{ "code": vmovRegCoreUHCode, { "code": vmovRegCoreUHCode,
@ -382,7 +382,7 @@ let {{
vmovRegCoreSBCode = vfpEnabledCheckCode + ''' vmovRegCoreSBCode = vfpEnabledCheckCode + '''
assert(imm < 4); assert(imm < 4);
Dest = sext<8>(bits(FpOp1.uw, imm * 8 + 7, imm * 8)); Dest = sext<8>(bits(FpOp1_uw, imm * 8 + 7, imm * 8));
''' '''
vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "FpRegRegImmOp", vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "FpRegRegImmOp",
{ "code": vmovRegCoreSBCode, { "code": vmovRegCoreSBCode,
@ -394,7 +394,7 @@ let {{
vmovRegCoreSHCode = vfpEnabledCheckCode + ''' vmovRegCoreSHCode = vfpEnabledCheckCode + '''
assert(imm < 2); assert(imm < 2);
Dest = sext<16>(bits(FpOp1.uw, imm * 16 + 15, imm * 16)); Dest = sext<16>(bits(FpOp1_uw, imm * 16 + 15, imm * 16));
''' '''
vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "FpRegRegImmOp", vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "FpRegRegImmOp",
{ "code": vmovRegCoreSHCode, { "code": vmovRegCoreSHCode,
@ -405,7 +405,7 @@ let {{
exec_output += PredOpExecute.subst(vmovRegCoreSHIop); exec_output += PredOpExecute.subst(vmovRegCoreSHIop);
vmovRegCoreWCode = vfpEnabledCheckCode + ''' vmovRegCoreWCode = vfpEnabledCheckCode + '''
Dest = FpOp1.uw; Dest = FpOp1_uw;
''' '''
vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "FpRegRegOp", vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "FpRegRegOp",
{ "code": vmovRegCoreWCode, { "code": vmovRegCoreWCode,
@ -416,8 +416,8 @@ let {{
exec_output += PredOpExecute.subst(vmovRegCoreWIop); exec_output += PredOpExecute.subst(vmovRegCoreWIop);
vmov2Reg2CoreCode = vfpEnabledCheckCode + ''' vmov2Reg2CoreCode = vfpEnabledCheckCode + '''
FpDestP0.uw = Op1.uw; FpDestP0_uw = Op1_uw;
FpDestP1.uw = Op2.uw; FpDestP1_uw = Op2_uw;
''' '''
vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "FpRegRegRegOp", vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "FpRegRegRegOp",
{ "code": vmov2Reg2CoreCode, { "code": vmov2Reg2CoreCode,
@ -428,8 +428,8 @@ let {{
exec_output += PredOpExecute.subst(vmov2Reg2CoreIop); exec_output += PredOpExecute.subst(vmov2Reg2CoreIop);
vmov2Core2RegCode = vfpEnabledCheckCode + ''' vmov2Core2RegCode = vfpEnabledCheckCode + '''
Dest.uw = FpOp2P0.uw; Dest_uw = FpOp2P0_uw;
Op1.uw = FpOp2P1.uw; Op1_uw = FpOp2P1_uw;
''' '''
vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "FpRegRegRegOp", vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "FpRegRegRegOp",
{ "code": vmov2Core2RegCode, { "code": vmov2Core2RegCode,
@ -459,17 +459,17 @@ let {{
doubleCode = vfpEnabledCheckCode + ''' doubleCode = vfpEnabledCheckCode + '''
FPSCR fpscr = (FPSCR) FpscrExc; FPSCR fpscr = (FPSCR) FpscrExc;
double dest = %(op)s; double dest = %(op)s;
FpDestP0.uw = dblLow(dest); FpDestP0_uw = dblLow(dest);
FpDestP1.uw = dblHi(dest); FpDestP1_uw = dblHi(dest);
FpscrExc = fpscr; FpscrExc = fpscr;
''' '''
doubleBinOp = ''' doubleBinOp = '''
binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw),
dbl(FpOp2P0.uw, FpOp2P1.uw), dbl(FpOp2P0_uw, FpOp2P1_uw),
%(func)s, fpscr.fz, fpscr.dn, fpscr.rMode); %(func)s, fpscr.fz, fpscr.dn, fpscr.rMode);
''' '''
doubleUnaryOp = ''' doubleUnaryOp = '''
unaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), %(func)s, unaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw), %(func)s,
fpscr.fz, fpscr.rMode) fpscr.fz, fpscr.rMode)
''' '''
@ -559,9 +559,9 @@ let {{
exec_output += PredOpExecute.subst(iop) exec_output += PredOpExecute.subst(iop)
buildSimpleUnaryFpOp("vneg", "Vneg", "FpRegRegOp", "SimdFloatMiscOp", buildSimpleUnaryFpOp("vneg", "Vneg", "FpRegRegOp", "SimdFloatMiscOp",
"-FpOp1", "-dbl(FpOp1P0.uw, FpOp1P1.uw)") "-FpOp1", "-dbl(FpOp1P0_uw, FpOp1P1_uw)")
buildSimpleUnaryFpOp("vabs", "Vabs", "FpRegRegOp", "SimdFloatMiscOp", buildSimpleUnaryFpOp("vabs", "Vabs", "FpRegRegOp", "SimdFloatMiscOp",
"fabsf(FpOp1)", "fabs(dbl(FpOp1P0.uw, FpOp1P1.uw))") "fabsf(FpOp1)", "fabs(dbl(FpOp1P0_uw, FpOp1P1_uw))")
}}; }};
let {{ let {{
@ -588,14 +588,14 @@ let {{
vmlaDCode = vfpEnabledCheckCode + ''' vmlaDCode = vfpEnabledCheckCode + '''
FPSCR fpscr = (FPSCR) FpscrExc; FPSCR fpscr = (FPSCR) FpscrExc;
double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), double mid = binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw),
dbl(FpOp2P0.uw, FpOp2P1.uw), dbl(FpOp2P0_uw, FpOp2P1_uw),
fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode);
double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw), double dest = binaryOp(fpscr, dbl(FpDestP0_uw, FpDestP1_uw),
mid, fpAddD, fpscr.fz, mid, fpAddD, fpscr.fz,
fpscr.dn, fpscr.rMode); fpscr.dn, fpscr.rMode);
FpDestP0.uw = dblLow(dest); FpDestP0_uw = dblLow(dest);
FpDestP1.uw = dblHi(dest); FpDestP1_uw = dblHi(dest);
FpscrExc = fpscr; FpscrExc = fpscr;
''' '''
vmlaDIop = InstObjParams("vmlad", "VmlaD", "FpRegRegRegOp", vmlaDIop = InstObjParams("vmlad", "VmlaD", "FpRegRegRegOp",
@ -624,14 +624,14 @@ let {{
vmlsDCode = vfpEnabledCheckCode + ''' vmlsDCode = vfpEnabledCheckCode + '''
FPSCR fpscr = (FPSCR) FpscrExc; FPSCR fpscr = (FPSCR) FpscrExc;
double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), double mid = binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw),
dbl(FpOp2P0.uw, FpOp2P1.uw), dbl(FpOp2P0_uw, FpOp2P1_uw),
fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode);
double dest = binaryOp(fpscr, dbl(FpDestP0.uw, FpDestP1.uw), double dest = binaryOp(fpscr, dbl(FpDestP0_uw, FpDestP1_uw),
-mid, fpAddD, fpscr.fz, -mid, fpAddD, fpscr.fz,
fpscr.dn, fpscr.rMode); fpscr.dn, fpscr.rMode);
FpDestP0.uw = dblLow(dest); FpDestP0_uw = dblLow(dest);
FpDestP1.uw = dblHi(dest); FpDestP1_uw = dblHi(dest);
FpscrExc = fpscr; FpscrExc = fpscr;
''' '''
vmlsDIop = InstObjParams("vmlsd", "VmlsD", "FpRegRegRegOp", vmlsDIop = InstObjParams("vmlsd", "VmlsD", "FpRegRegRegOp",
@ -660,14 +660,14 @@ let {{
vnmlaDCode = vfpEnabledCheckCode + ''' vnmlaDCode = vfpEnabledCheckCode + '''
FPSCR fpscr = (FPSCR) FpscrExc; FPSCR fpscr = (FPSCR) FpscrExc;
double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), double mid = binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw),
dbl(FpOp2P0.uw, FpOp2P1.uw), dbl(FpOp2P0_uw, FpOp2P1_uw),
fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode);
double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw), double dest = binaryOp(fpscr, -dbl(FpDestP0_uw, FpDestP1_uw),
-mid, fpAddD, fpscr.fz, -mid, fpAddD, fpscr.fz,
fpscr.dn, fpscr.rMode); fpscr.dn, fpscr.rMode);
FpDestP0.uw = dblLow(dest); FpDestP0_uw = dblLow(dest);
FpDestP1.uw = dblHi(dest); FpDestP1_uw = dblHi(dest);
FpscrExc = fpscr; FpscrExc = fpscr;
''' '''
vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "FpRegRegRegOp", vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "FpRegRegRegOp",
@ -696,14 +696,14 @@ let {{
vnmlsDCode = vfpEnabledCheckCode + ''' vnmlsDCode = vfpEnabledCheckCode + '''
FPSCR fpscr = (FPSCR) FpscrExc; FPSCR fpscr = (FPSCR) FpscrExc;
double mid = binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), double mid = binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw),
dbl(FpOp2P0.uw, FpOp2P1.uw), dbl(FpOp2P0_uw, FpOp2P1_uw),
fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode); fpMulD, fpscr.fz, fpscr.dn, fpscr.rMode);
double dest = binaryOp(fpscr, -dbl(FpDestP0.uw, FpDestP1.uw), double dest = binaryOp(fpscr, -dbl(FpDestP0_uw, FpDestP1_uw),
mid, fpAddD, fpscr.fz, mid, fpAddD, fpscr.fz,
fpscr.dn, fpscr.rMode); fpscr.dn, fpscr.rMode);
FpDestP0.uw = dblLow(dest); FpDestP0_uw = dblLow(dest);
FpDestP1.uw = dblHi(dest); FpDestP1_uw = dblHi(dest);
FpscrExc = fpscr; FpscrExc = fpscr;
''' '''
vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "FpRegRegRegOp", vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "FpRegRegRegOp",
@ -730,12 +730,12 @@ let {{
vnmulDCode = vfpEnabledCheckCode + ''' vnmulDCode = vfpEnabledCheckCode + '''
FPSCR fpscr = (FPSCR) FpscrExc; FPSCR fpscr = (FPSCR) FpscrExc;
double dest = -binaryOp(fpscr, dbl(FpOp1P0.uw, FpOp1P1.uw), double dest = -binaryOp(fpscr, dbl(FpOp1P0_uw, FpOp1P1_uw),
dbl(FpOp2P0.uw, FpOp2P1.uw), dbl(FpOp2P0_uw, FpOp2P1_uw),
fpMulD, fpscr.fz, fpscr.dn, fpMulD, fpscr.fz, fpscr.dn,
fpscr.rMode); fpscr.rMode);
FpDestP0.uw = dblLow(dest); FpDestP0_uw = dblLow(dest);
FpDestP1.uw = dblHi(dest); FpDestP1_uw = dblHi(dest);
FpscrExc = fpscr; FpscrExc = fpscr;
''' '''
vnmulDIop = InstObjParams("vnmuld", "VnmulD", "FpRegRegRegOp", vnmulDIop = InstObjParams("vnmuld", "VnmulD", "FpRegRegRegOp",
@ -756,8 +756,8 @@ let {{
vcvtUIntFpSCode = vfpEnabledCheckCode + ''' vcvtUIntFpSCode = vfpEnabledCheckCode + '''
FPSCR fpscr = (FPSCR) FpscrExc; FPSCR fpscr = (FPSCR) FpscrExc;
VfpSavedState state = prepFpState(fpscr.rMode); VfpSavedState state = prepFpState(fpscr.rMode);
__asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); __asm__ __volatile__("" : "=m" (FpOp1_uw) : "m" (FpOp1_uw));
FpDest = FpOp1.uw; FpDest = FpOp1_uw;
__asm__ __volatile__("" :: "m" (FpDest)); __asm__ __volatile__("" :: "m" (FpDest));
finishVfp(fpscr, state, fpscr.fz); finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr; FpscrExc = fpscr;
@ -773,12 +773,12 @@ let {{
vcvtUIntFpDCode = vfpEnabledCheckCode + ''' vcvtUIntFpDCode = vfpEnabledCheckCode + '''
FPSCR fpscr = (FPSCR) FpscrExc; FPSCR fpscr = (FPSCR) FpscrExc;
VfpSavedState state = prepFpState(fpscr.rMode); VfpSavedState state = prepFpState(fpscr.rMode);
__asm__ __volatile__("" : "=m" (FpOp1P0.uw) : "m" (FpOp1P0.uw)); __asm__ __volatile__("" : "=m" (FpOp1P0_uw) : "m" (FpOp1P0_uw));
double cDest = (uint64_t)FpOp1P0.uw; double cDest = (uint64_t)FpOp1P0_uw;
__asm__ __volatile__("" :: "m" (cDest)); __asm__ __volatile__("" :: "m" (cDest));
finishVfp(fpscr, state, fpscr.fz); finishVfp(fpscr, state, fpscr.fz);
FpDestP0.uw = dblLow(cDest); FpDestP0_uw = dblLow(cDest);
FpDestP1.uw = dblHi(cDest); FpDestP1_uw = dblHi(cDest);
FpscrExc = fpscr; FpscrExc = fpscr;
''' '''
vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "FpRegRegOp", vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "FpRegRegOp",
@ -792,8 +792,8 @@ let {{
vcvtSIntFpSCode = vfpEnabledCheckCode + ''' vcvtSIntFpSCode = vfpEnabledCheckCode + '''
FPSCR fpscr = (FPSCR) FpscrExc; FPSCR fpscr = (FPSCR) FpscrExc;
VfpSavedState state = prepFpState(fpscr.rMode); VfpSavedState state = prepFpState(fpscr.rMode);
__asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); __asm__ __volatile__("" : "=m" (FpOp1_sw) : "m" (FpOp1_sw));
FpDest = FpOp1.sw; FpDest = FpOp1_sw;
__asm__ __volatile__("" :: "m" (FpDest)); __asm__ __volatile__("" :: "m" (FpDest));
finishVfp(fpscr, state, fpscr.fz); finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr; FpscrExc = fpscr;
@ -809,12 +809,12 @@ let {{
vcvtSIntFpDCode = vfpEnabledCheckCode + ''' vcvtSIntFpDCode = vfpEnabledCheckCode + '''
FPSCR fpscr = (FPSCR) FpscrExc; FPSCR fpscr = (FPSCR) FpscrExc;
VfpSavedState state = prepFpState(fpscr.rMode); VfpSavedState state = prepFpState(fpscr.rMode);
__asm__ __volatile__("" : "=m" (FpOp1P0.sw) : "m" (FpOp1P0.sw)); __asm__ __volatile__("" : "=m" (FpOp1P0_sw) : "m" (FpOp1P0_sw));
double cDest = FpOp1P0.sw; double cDest = FpOp1P0_sw;
__asm__ __volatile__("" :: "m" (cDest)); __asm__ __volatile__("" :: "m" (cDest));
finishVfp(fpscr, state, fpscr.fz); finishVfp(fpscr, state, fpscr.fz);
FpDestP0.uw = dblLow(cDest); FpDestP0_uw = dblLow(cDest);
FpDestP1.uw = dblHi(cDest); FpDestP1_uw = dblHi(cDest);
FpscrExc = fpscr; FpscrExc = fpscr;
''' '''
vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "FpRegRegOp", vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "FpRegRegOp",
@ -830,8 +830,8 @@ let {{
VfpSavedState state = prepFpState(fpscr.rMode); VfpSavedState state = prepFpState(fpscr.rMode);
vfpFlushToZero(fpscr, FpOp1); vfpFlushToZero(fpscr, FpOp1);
__asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0, false); FpDest_uw = vfpFpSToFixed(FpOp1, false, false, 0, false);
__asm__ __volatile__("" :: "m" (FpDest.uw)); __asm__ __volatile__("" :: "m" (FpDest_uw));
finishVfp(fpscr, state, fpscr.fz); finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr; FpscrExc = fpscr;
''' '''
@ -845,14 +845,14 @@ let {{
vcvtFpUIntDRCode = vfpEnabledCheckCode + ''' vcvtFpUIntDRCode = vfpEnabledCheckCode + '''
FPSCR fpscr = (FPSCR) FpscrExc; FPSCR fpscr = (FPSCR) FpscrExc;
double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw);
vfpFlushToZero(fpscr, cOp1); vfpFlushToZero(fpscr, cOp1);
VfpSavedState state = prepFpState(fpscr.rMode); VfpSavedState state = prepFpState(fpscr.rMode);
__asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
uint64_t result = vfpFpDToFixed(cOp1, false, false, 0, false); uint64_t result = vfpFpDToFixed(cOp1, false, false, 0, false);
__asm__ __volatile__("" :: "m" (result)); __asm__ __volatile__("" :: "m" (result));
finishVfp(fpscr, state, fpscr.fz); finishVfp(fpscr, state, fpscr.fz);
FpDestP0.uw = result; FpDestP0_uw = result;
FpscrExc = fpscr; FpscrExc = fpscr;
''' '''
vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp", vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "FpRegRegOp",
@ -868,8 +868,8 @@ let {{
VfpSavedState state = prepFpState(fpscr.rMode); VfpSavedState state = prepFpState(fpscr.rMode);
vfpFlushToZero(fpscr, FpOp1); vfpFlushToZero(fpscr, FpOp1);
__asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0, false); FpDest_sw = vfpFpSToFixed(FpOp1, true, false, 0, false);
__asm__ __volatile__("" :: "m" (FpDest.sw)); __asm__ __volatile__("" :: "m" (FpDest_sw));
finishVfp(fpscr, state, fpscr.fz); finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr; FpscrExc = fpscr;
''' '''
@ -883,14 +883,14 @@ let {{
vcvtFpSIntDRCode = vfpEnabledCheckCode + ''' vcvtFpSIntDRCode = vfpEnabledCheckCode + '''
FPSCR fpscr = (FPSCR) FpscrExc; FPSCR fpscr = (FPSCR) FpscrExc;
double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw);
vfpFlushToZero(fpscr, cOp1); vfpFlushToZero(fpscr, cOp1);
VfpSavedState state = prepFpState(fpscr.rMode); VfpSavedState state = prepFpState(fpscr.rMode);
__asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
int64_t result = vfpFpDToFixed(cOp1, true, false, 0, false); int64_t result = vfpFpDToFixed(cOp1, true, false, 0, false);
__asm__ __volatile__("" :: "m" (result)); __asm__ __volatile__("" :: "m" (result));
finishVfp(fpscr, state, fpscr.fz); finishVfp(fpscr, state, fpscr.fz);
FpDestP0.uw = result; FpDestP0_uw = result;
FpscrExc = fpscr; FpscrExc = fpscr;
''' '''
vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp", vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "FpRegRegOp",
@ -907,8 +907,8 @@ let {{
VfpSavedState state = prepFpState(fpscr.rMode); VfpSavedState state = prepFpState(fpscr.rMode);
fesetround(FeRoundZero); fesetround(FeRoundZero);
__asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
FpDest.uw = vfpFpSToFixed(FpOp1, false, false, 0); FpDest_uw = vfpFpSToFixed(FpOp1, false, false, 0);
__asm__ __volatile__("" :: "m" (FpDest.uw)); __asm__ __volatile__("" :: "m" (FpDest_uw));
finishVfp(fpscr, state, fpscr.fz); finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr; FpscrExc = fpscr;
''' '''
@ -922,7 +922,7 @@ let {{
vcvtFpUIntDCode = vfpEnabledCheckCode + ''' vcvtFpUIntDCode = vfpEnabledCheckCode + '''
FPSCR fpscr = (FPSCR) FpscrExc; FPSCR fpscr = (FPSCR) FpscrExc;
double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw);
vfpFlushToZero(fpscr, cOp1); vfpFlushToZero(fpscr, cOp1);
VfpSavedState state = prepFpState(fpscr.rMode); VfpSavedState state = prepFpState(fpscr.rMode);
fesetround(FeRoundZero); fesetround(FeRoundZero);
@ -930,7 +930,7 @@ let {{
uint64_t result = vfpFpDToFixed(cOp1, false, false, 0); uint64_t result = vfpFpDToFixed(cOp1, false, false, 0);
__asm__ __volatile__("" :: "m" (result)); __asm__ __volatile__("" :: "m" (result));
finishVfp(fpscr, state, fpscr.fz); finishVfp(fpscr, state, fpscr.fz);
FpDestP0.uw = result; FpDestP0_uw = result;
FpscrExc = fpscr; FpscrExc = fpscr;
''' '''
vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "FpRegRegOp", vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "FpRegRegOp",
@ -947,8 +947,8 @@ let {{
VfpSavedState state = prepFpState(fpscr.rMode); VfpSavedState state = prepFpState(fpscr.rMode);
fesetround(FeRoundZero); fesetround(FeRoundZero);
__asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
FpDest.sw = vfpFpSToFixed(FpOp1, true, false, 0); FpDest_sw = vfpFpSToFixed(FpOp1, true, false, 0);
__asm__ __volatile__("" :: "m" (FpDest.sw)); __asm__ __volatile__("" :: "m" (FpDest_sw));
finishVfp(fpscr, state, fpscr.fz); finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr; FpscrExc = fpscr;
''' '''
@ -962,7 +962,7 @@ let {{
vcvtFpSIntDCode = vfpEnabledCheckCode + ''' vcvtFpSIntDCode = vfpEnabledCheckCode + '''
FPSCR fpscr = (FPSCR) FpscrExc; FPSCR fpscr = (FPSCR) FpscrExc;
double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw);
vfpFlushToZero(fpscr, cOp1); vfpFlushToZero(fpscr, cOp1);
VfpSavedState state = prepFpState(fpscr.rMode); VfpSavedState state = prepFpState(fpscr.rMode);
fesetround(FeRoundZero); fesetround(FeRoundZero);
@ -970,7 +970,7 @@ let {{
int64_t result = vfpFpDToFixed(cOp1, true, false, 0); int64_t result = vfpFpDToFixed(cOp1, true, false, 0);
__asm__ __volatile__("" :: "m" (result)); __asm__ __volatile__("" :: "m" (result));
finishVfp(fpscr, state, fpscr.fz); finishVfp(fpscr, state, fpscr.fz);
FpDestP0.uw = result; FpDestP0_uw = result;
FpscrExc = fpscr; FpscrExc = fpscr;
''' '''
vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "FpRegRegOp", vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "FpRegRegOp",
@ -989,8 +989,8 @@ let {{
double cDest = fixFpSFpDDest(FpscrExc, FpOp1); double cDest = fixFpSFpDDest(FpscrExc, FpOp1);
__asm__ __volatile__("" :: "m" (cDest)); __asm__ __volatile__("" :: "m" (cDest));
finishVfp(fpscr, state, fpscr.fz); finishVfp(fpscr, state, fpscr.fz);
FpDestP0.uw = dblLow(cDest); FpDestP0_uw = dblLow(cDest);
FpDestP1.uw = dblHi(cDest); FpDestP1_uw = dblHi(cDest);
FpscrExc = fpscr; FpscrExc = fpscr;
''' '''
vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "FpRegRegOp", vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "FpRegRegOp",
@ -1003,7 +1003,7 @@ let {{
vcvtFpDFpSCode = vfpEnabledCheckCode + ''' vcvtFpDFpSCode = vfpEnabledCheckCode + '''
FPSCR fpscr = (FPSCR) FpscrExc; FPSCR fpscr = (FPSCR) FpscrExc;
double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw);
vfpFlushToZero(fpscr, cOp1); vfpFlushToZero(fpscr, cOp1);
VfpSavedState state = prepFpState(fpscr.rMode); VfpSavedState state = prepFpState(fpscr.rMode);
__asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
@ -1061,12 +1061,12 @@ let {{
FPSCR fpscr = (FPSCR) FpscrExc; FPSCR fpscr = (FPSCR) FpscrExc;
vfpFlushToZero(fpscr, FpOp1); vfpFlushToZero(fpscr, FpOp1);
VfpSavedState state = prepFpState(fpscr.rMode); VfpSavedState state = prepFpState(fpscr.rMode);
__asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest.uw) __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest_uw)
: "m" (FpOp1), "m" (FpDest.uw)); : "m" (FpOp1), "m" (FpDest_uw));
FpDest.uw = insertBits(FpDest.uw, 31, 16,, FpDest_uw = insertBits(FpDest_uw, 31, 16,,
vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn, vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn,
fpscr.rMode, fpscr.ahp, FpOp1)); fpscr.rMode, fpscr.ahp, FpOp1));
__asm__ __volatile__("" :: "m" (FpDest.uw)); __asm__ __volatile__("" :: "m" (FpDest_uw));
finishVfp(fpscr, state, fpscr.fz); finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr; FpscrExc = fpscr;
''' '''
@ -1082,12 +1082,12 @@ let {{
FPSCR fpscr = (FPSCR) FpscrExc; FPSCR fpscr = (FPSCR) FpscrExc;
vfpFlushToZero(fpscr, FpOp1); vfpFlushToZero(fpscr, FpOp1);
VfpSavedState state = prepFpState(fpscr.rMode); VfpSavedState state = prepFpState(fpscr.rMode);
__asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest.uw) __asm__ __volatile__("" : "=m" (FpOp1), "=m" (FpDest_uw)
: "m" (FpOp1), "m" (FpDest.uw)); : "m" (FpOp1), "m" (FpDest_uw));
FpDest.uw = insertBits(FpDest.uw, 15, 0, FpDest_uw = insertBits(FpDest_uw, 15, 0,
vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn, vcvtFpSFpH(fpscr, fpscr.fz, fpscr.dn,
fpscr.rMode, fpscr.ahp, FpOp1)); fpscr.rMode, fpscr.ahp, FpOp1));
__asm__ __volatile__("" :: "m" (FpDest.uw)); __asm__ __volatile__("" :: "m" (FpDest_uw));
finishVfp(fpscr, state, fpscr.fz); finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr; FpscrExc = fpscr;
''' '''
@ -1130,8 +1130,8 @@ let {{
exec_output += PredOpExecute.subst(vcmpSIop); exec_output += PredOpExecute.subst(vcmpSIop);
vcmpDCode = vfpEnabledCheckCode + ''' vcmpDCode = vfpEnabledCheckCode + '''
double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw);
double cDest = dbl(FpDestP0.uw, FpDestP1.uw); double cDest = dbl(FpDestP0_uw, FpDestP1_uw);
FPSCR fpscr = (FPSCR) FpscrExc; FPSCR fpscr = (FPSCR) FpscrExc;
vfpFlushToZero(fpscr, cDest, cOp1); vfpFlushToZero(fpscr, cDest, cOp1);
if (cDest == cOp1) { if (cDest == cOp1) {
@ -1194,7 +1194,7 @@ let {{
vcmpZeroDCode = vfpEnabledCheckCode + ''' vcmpZeroDCode = vfpEnabledCheckCode + '''
// This only handles imm == 0 for now. // This only handles imm == 0 for now.
assert(imm == 0); assert(imm == 0);
double cDest = dbl(FpDestP0.uw, FpDestP1.uw); double cDest = dbl(FpDestP0_uw, FpDestP1_uw);
FPSCR fpscr = (FPSCR) FpscrExc; FPSCR fpscr = (FPSCR) FpscrExc;
vfpFlushToZero(fpscr, cDest); vfpFlushToZero(fpscr, cDest);
if (cDest == imm) { if (cDest == imm) {
@ -1247,8 +1247,8 @@ let {{
exec_output += PredOpExecute.subst(vcmpeSIop); exec_output += PredOpExecute.subst(vcmpeSIop);
vcmpeDCode = vfpEnabledCheckCode + ''' vcmpeDCode = vfpEnabledCheckCode + '''
double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw);
double cDest = dbl(FpDestP0.uw, FpDestP1.uw); double cDest = dbl(FpDestP0_uw, FpDestP1_uw);
FPSCR fpscr = (FPSCR) FpscrExc; FPSCR fpscr = (FPSCR) FpscrExc;
vfpFlushToZero(fpscr, cDest, cOp1); vfpFlushToZero(fpscr, cDest, cOp1);
if (cDest == cOp1) { if (cDest == cOp1) {
@ -1297,7 +1297,7 @@ let {{
exec_output += PredOpExecute.subst(vcmpeZeroSIop); exec_output += PredOpExecute.subst(vcmpeZeroSIop);
vcmpeZeroDCode = vfpEnabledCheckCode + ''' vcmpeZeroDCode = vfpEnabledCheckCode + '''
double cDest = dbl(FpDestP0.uw, FpDestP1.uw); double cDest = dbl(FpDestP0_uw, FpDestP1_uw);
FPSCR fpscr = (FPSCR) FpscrExc; FPSCR fpscr = (FPSCR) FpscrExc;
vfpFlushToZero(fpscr, cDest); vfpFlushToZero(fpscr, cDest);
if (cDest == imm) { if (cDest == imm) {
@ -1333,8 +1333,8 @@ let {{
vfpFlushToZero(fpscr, FpOp1); vfpFlushToZero(fpscr, FpOp1);
VfpSavedState state = prepFpState(fpscr.rMode); VfpSavedState state = prepFpState(fpscr.rMode);
__asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm); FpDest_sw = vfpFpSToFixed(FpOp1, true, false, imm);
__asm__ __volatile__("" :: "m" (FpDest.sw)); __asm__ __volatile__("" :: "m" (FpDest_sw));
finishVfp(fpscr, state, fpscr.fz); finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr; FpscrExc = fpscr;
''' '''
@ -1348,15 +1348,15 @@ let {{
vcvtFpSFixedDCode = vfpEnabledCheckCode + ''' vcvtFpSFixedDCode = vfpEnabledCheckCode + '''
FPSCR fpscr = (FPSCR) FpscrExc; FPSCR fpscr = (FPSCR) FpscrExc;
double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw);
vfpFlushToZero(fpscr, cOp1); vfpFlushToZero(fpscr, cOp1);
VfpSavedState state = prepFpState(fpscr.rMode); VfpSavedState state = prepFpState(fpscr.rMode);
__asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
uint64_t mid = vfpFpDToFixed(cOp1, true, false, imm); uint64_t mid = vfpFpDToFixed(cOp1, true, false, imm);
__asm__ __volatile__("" :: "m" (mid)); __asm__ __volatile__("" :: "m" (mid));
finishVfp(fpscr, state, fpscr.fz); finishVfp(fpscr, state, fpscr.fz);
FpDestP0.uw = mid; FpDestP0_uw = mid;
FpDestP1.uw = mid >> 32; FpDestP1_uw = mid >> 32;
FpscrExc = fpscr; FpscrExc = fpscr;
''' '''
vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "FpRegRegImmOp", vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "FpRegRegImmOp",
@ -1372,8 +1372,8 @@ let {{
vfpFlushToZero(fpscr, FpOp1); vfpFlushToZero(fpscr, FpOp1);
VfpSavedState state = prepFpState(fpscr.rMode); VfpSavedState state = prepFpState(fpscr.rMode);
__asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm); FpDest_uw = vfpFpSToFixed(FpOp1, false, false, imm);
__asm__ __volatile__("" :: "m" (FpDest.uw)); __asm__ __volatile__("" :: "m" (FpDest_uw));
finishVfp(fpscr, state, fpscr.fz); finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr; FpscrExc = fpscr;
''' '''
@ -1387,15 +1387,15 @@ let {{
vcvtFpUFixedDCode = vfpEnabledCheckCode + ''' vcvtFpUFixedDCode = vfpEnabledCheckCode + '''
FPSCR fpscr = (FPSCR) FpscrExc; FPSCR fpscr = (FPSCR) FpscrExc;
double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw);
vfpFlushToZero(fpscr, cOp1); vfpFlushToZero(fpscr, cOp1);
VfpSavedState state = prepFpState(fpscr.rMode); VfpSavedState state = prepFpState(fpscr.rMode);
__asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
uint64_t mid = vfpFpDToFixed(cOp1, false, false, imm); uint64_t mid = vfpFpDToFixed(cOp1, false, false, imm);
__asm__ __volatile__("" :: "m" (mid)); __asm__ __volatile__("" :: "m" (mid));
finishVfp(fpscr, state, fpscr.fz); finishVfp(fpscr, state, fpscr.fz);
FpDestP0.uw = mid; FpDestP0_uw = mid;
FpDestP1.uw = mid >> 32; FpDestP1_uw = mid >> 32;
FpscrExc = fpscr; FpscrExc = fpscr;
''' '''
vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "FpRegRegImmOp", vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "FpRegRegImmOp",
@ -1409,8 +1409,8 @@ let {{
vcvtSFixedFpSCode = vfpEnabledCheckCode + ''' vcvtSFixedFpSCode = vfpEnabledCheckCode + '''
FPSCR fpscr = (FPSCR) FpscrExc; FPSCR fpscr = (FPSCR) FpscrExc;
VfpSavedState state = prepFpState(fpscr.rMode); VfpSavedState state = prepFpState(fpscr.rMode);
__asm__ __volatile__("" : "=m" (FpOp1.sw) : "m" (FpOp1.sw)); __asm__ __volatile__("" : "=m" (FpOp1_sw) : "m" (FpOp1_sw));
FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.sw, false, imm); FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_sw, false, imm);
__asm__ __volatile__("" :: "m" (FpDest)); __asm__ __volatile__("" :: "m" (FpDest));
finishVfp(fpscr, state, fpscr.fz); finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr; FpscrExc = fpscr;
@ -1425,14 +1425,14 @@ let {{
vcvtSFixedFpDCode = vfpEnabledCheckCode + ''' vcvtSFixedFpDCode = vfpEnabledCheckCode + '''
FPSCR fpscr = (FPSCR) FpscrExc; FPSCR fpscr = (FPSCR) FpscrExc;
uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32));
VfpSavedState state = prepFpState(fpscr.rMode); VfpSavedState state = prepFpState(fpscr.rMode);
__asm__ __volatile__("" : "=m" (mid) : "m" (mid)); __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm); double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm);
__asm__ __volatile__("" :: "m" (cDest)); __asm__ __volatile__("" :: "m" (cDest));
finishVfp(fpscr, state, fpscr.fz); finishVfp(fpscr, state, fpscr.fz);
FpDestP0.uw = dblLow(cDest); FpDestP0_uw = dblLow(cDest);
FpDestP1.uw = dblHi(cDest); FpDestP1_uw = dblHi(cDest);
FpscrExc = fpscr; FpscrExc = fpscr;
''' '''
vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "FpRegRegImmOp", vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "FpRegRegImmOp",
@ -1446,8 +1446,8 @@ let {{
vcvtUFixedFpSCode = vfpEnabledCheckCode + ''' vcvtUFixedFpSCode = vfpEnabledCheckCode + '''
FPSCR fpscr = (FPSCR) FpscrExc; FPSCR fpscr = (FPSCR) FpscrExc;
VfpSavedState state = prepFpState(fpscr.rMode); VfpSavedState state = prepFpState(fpscr.rMode);
__asm__ __volatile__("" : "=m" (FpOp1.uw) : "m" (FpOp1.uw)); __asm__ __volatile__("" : "=m" (FpOp1_uw) : "m" (FpOp1_uw));
FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.uw, false, imm); FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_uw, false, imm);
__asm__ __volatile__("" :: "m" (FpDest)); __asm__ __volatile__("" :: "m" (FpDest));
finishVfp(fpscr, state, fpscr.fz); finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr; FpscrExc = fpscr;
@ -1462,14 +1462,14 @@ let {{
vcvtUFixedFpDCode = vfpEnabledCheckCode + ''' vcvtUFixedFpDCode = vfpEnabledCheckCode + '''
FPSCR fpscr = (FPSCR) FpscrExc; FPSCR fpscr = (FPSCR) FpscrExc;
uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32));
VfpSavedState state = prepFpState(fpscr.rMode); VfpSavedState state = prepFpState(fpscr.rMode);
__asm__ __volatile__("" : "=m" (mid) : "m" (mid)); __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm); double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, false, imm);
__asm__ __volatile__("" :: "m" (cDest)); __asm__ __volatile__("" :: "m" (cDest));
finishVfp(fpscr, state, fpscr.fz); finishVfp(fpscr, state, fpscr.fz);
FpDestP0.uw = dblLow(cDest); FpDestP0_uw = dblLow(cDest);
FpDestP1.uw = dblHi(cDest); FpDestP1_uw = dblHi(cDest);
FpscrExc = fpscr; FpscrExc = fpscr;
''' '''
vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "FpRegRegImmOp", vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "FpRegRegImmOp",
@ -1485,8 +1485,8 @@ let {{
vfpFlushToZero(fpscr, FpOp1); vfpFlushToZero(fpscr, FpOp1);
VfpSavedState state = prepFpState(fpscr.rMode); VfpSavedState state = prepFpState(fpscr.rMode);
__asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm); FpDest_sh = vfpFpSToFixed(FpOp1, true, true, imm);
__asm__ __volatile__("" :: "m" (FpDest.sh)); __asm__ __volatile__("" :: "m" (FpDest_sh));
finishVfp(fpscr, state, fpscr.fz); finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr; FpscrExc = fpscr;
''' '''
@ -1501,15 +1501,15 @@ let {{
vcvtFpSHFixedDCode = vfpEnabledCheckCode + ''' vcvtFpSHFixedDCode = vfpEnabledCheckCode + '''
FPSCR fpscr = (FPSCR) FpscrExc; FPSCR fpscr = (FPSCR) FpscrExc;
double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw);
vfpFlushToZero(fpscr, cOp1); vfpFlushToZero(fpscr, cOp1);
VfpSavedState state = prepFpState(fpscr.rMode); VfpSavedState state = prepFpState(fpscr.rMode);
__asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
uint64_t result = vfpFpDToFixed(cOp1, true, true, imm); uint64_t result = vfpFpDToFixed(cOp1, true, true, imm);
__asm__ __volatile__("" :: "m" (result)); __asm__ __volatile__("" :: "m" (result));
finishVfp(fpscr, state, fpscr.fz); finishVfp(fpscr, state, fpscr.fz);
FpDestP0.uw = result; FpDestP0_uw = result;
FpDestP1.uw = result >> 32; FpDestP1_uw = result >> 32;
FpscrExc = fpscr; FpscrExc = fpscr;
''' '''
vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD", vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD",
@ -1526,8 +1526,8 @@ let {{
vfpFlushToZero(fpscr, FpOp1); vfpFlushToZero(fpscr, FpOp1);
VfpSavedState state = prepFpState(fpscr.rMode); VfpSavedState state = prepFpState(fpscr.rMode);
__asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1)); __asm__ __volatile__("" : "=m" (FpOp1) : "m" (FpOp1));
FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm); FpDest_uh = vfpFpSToFixed(FpOp1, false, true, imm);
__asm__ __volatile__("" :: "m" (FpDest.uh)); __asm__ __volatile__("" :: "m" (FpDest_uh));
finishVfp(fpscr, state, fpscr.fz); finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr; FpscrExc = fpscr;
''' '''
@ -1542,15 +1542,15 @@ let {{
vcvtFpUHFixedDCode = vfpEnabledCheckCode + ''' vcvtFpUHFixedDCode = vfpEnabledCheckCode + '''
FPSCR fpscr = (FPSCR) FpscrExc; FPSCR fpscr = (FPSCR) FpscrExc;
double cOp1 = dbl(FpOp1P0.uw, FpOp1P1.uw); double cOp1 = dbl(FpOp1P0_uw, FpOp1P1_uw);
vfpFlushToZero(fpscr, cOp1); vfpFlushToZero(fpscr, cOp1);
VfpSavedState state = prepFpState(fpscr.rMode); VfpSavedState state = prepFpState(fpscr.rMode);
__asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1)); __asm__ __volatile__("" : "=m" (cOp1) : "m" (cOp1));
uint64_t mid = vfpFpDToFixed(cOp1, false, true, imm); uint64_t mid = vfpFpDToFixed(cOp1, false, true, imm);
__asm__ __volatile__("" :: "m" (mid)); __asm__ __volatile__("" :: "m" (mid));
finishVfp(fpscr, state, fpscr.fz); finishVfp(fpscr, state, fpscr.fz);
FpDestP0.uw = mid; FpDestP0_uw = mid;
FpDestP1.uw = mid >> 32; FpDestP1_uw = mid >> 32;
FpscrExc = fpscr; FpscrExc = fpscr;
''' '''
vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD", vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD",
@ -1565,8 +1565,8 @@ let {{
vcvtSHFixedFpSCode = vfpEnabledCheckCode + ''' vcvtSHFixedFpSCode = vfpEnabledCheckCode + '''
FPSCR fpscr = (FPSCR) FpscrExc; FPSCR fpscr = (FPSCR) FpscrExc;
VfpSavedState state = prepFpState(fpscr.rMode); VfpSavedState state = prepFpState(fpscr.rMode);
__asm__ __volatile__("" : "=m" (FpOp1.sh) : "m" (FpOp1.sh)); __asm__ __volatile__("" : "=m" (FpOp1_sh) : "m" (FpOp1_sh));
FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.sh, true, imm); FpDest = vfpSFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_sh, true, imm);
__asm__ __volatile__("" :: "m" (FpDest)); __asm__ __volatile__("" :: "m" (FpDest));
finishVfp(fpscr, state, fpscr.fz); finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr; FpscrExc = fpscr;
@ -1582,14 +1582,14 @@ let {{
vcvtSHFixedFpDCode = vfpEnabledCheckCode + ''' vcvtSHFixedFpDCode = vfpEnabledCheckCode + '''
FPSCR fpscr = (FPSCR) FpscrExc; FPSCR fpscr = (FPSCR) FpscrExc;
uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32));
VfpSavedState state = prepFpState(fpscr.rMode); VfpSavedState state = prepFpState(fpscr.rMode);
__asm__ __volatile__("" : "=m" (mid) : "m" (mid)); __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm); double cDest = vfpSFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm);
__asm__ __volatile__("" :: "m" (cDest)); __asm__ __volatile__("" :: "m" (cDest));
finishVfp(fpscr, state, fpscr.fz); finishVfp(fpscr, state, fpscr.fz);
FpDestP0.uw = dblLow(cDest); FpDestP0_uw = dblLow(cDest);
FpDestP1.uw = dblHi(cDest); FpDestP1_uw = dblHi(cDest);
FpscrExc = fpscr; FpscrExc = fpscr;
''' '''
vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD", vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD",
@ -1604,8 +1604,8 @@ let {{
vcvtUHFixedFpSCode = vfpEnabledCheckCode + ''' vcvtUHFixedFpSCode = vfpEnabledCheckCode + '''
FPSCR fpscr = (FPSCR) FpscrExc; FPSCR fpscr = (FPSCR) FpscrExc;
VfpSavedState state = prepFpState(fpscr.rMode); VfpSavedState state = prepFpState(fpscr.rMode);
__asm__ __volatile__("" : "=m" (FpOp1.uh) : "m" (FpOp1.uh)); __asm__ __volatile__("" : "=m" (FpOp1_uh) : "m" (FpOp1_uh));
FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1.uh, true, imm); FpDest = vfpUFixedToFpS(fpscr.fz, fpscr.dn, FpOp1_uh, true, imm);
__asm__ __volatile__("" :: "m" (FpDest)); __asm__ __volatile__("" :: "m" (FpDest));
finishVfp(fpscr, state, fpscr.fz); finishVfp(fpscr, state, fpscr.fz);
FpscrExc = fpscr; FpscrExc = fpscr;
@ -1621,14 +1621,14 @@ let {{
vcvtUHFixedFpDCode = vfpEnabledCheckCode + ''' vcvtUHFixedFpDCode = vfpEnabledCheckCode + '''
FPSCR fpscr = (FPSCR) FpscrExc; FPSCR fpscr = (FPSCR) FpscrExc;
uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); uint64_t mid = ((uint64_t)FpOp1P0_uw | ((uint64_t)FpOp1P1_uw << 32));
VfpSavedState state = prepFpState(fpscr.rMode); VfpSavedState state = prepFpState(fpscr.rMode);
__asm__ __volatile__("" : "=m" (mid) : "m" (mid)); __asm__ __volatile__("" : "=m" (mid) : "m" (mid));
double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm); double cDest = vfpUFixedToFpD(fpscr.fz, fpscr.dn, mid, true, imm);
__asm__ __volatile__("" :: "m" (cDest)); __asm__ __volatile__("" :: "m" (cDest));
finishVfp(fpscr, state, fpscr.fz); finishVfp(fpscr, state, fpscr.fz);
FpDestP0.uw = dblLow(cDest); FpDestP0_uw = dblLow(cDest);
FpDestP1.uw = dblHi(cDest); FpDestP1_uw = dblHi(cDest);
FpscrExc = fpscr; FpscrExc = fpscr;
''' '''
vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD", vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD",

16
src/arch/arm/isa/insts/ldr.isa
View file

@ -111,8 +111,8 @@ let {{
cpsr.v = CondCodesV; cpsr.v = CondCodesV;
cpsr.ge = CondCodesGE; cpsr.ge = CondCodesGE;
URc = cpsr; URc = cpsr;
URa = cSwap<uint32_t>(Mem.ud, cpsr.e); URa = cSwap<uint32_t>(Mem_ud, cpsr.e);
URb = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e); URb = cSwap<uint32_t>(Mem_ud >> 32, cpsr.e);
''' '''
self.codeBlobs["memacc_code"] = accCode self.codeBlobs["memacc_code"] = accCode
@ -196,7 +196,7 @@ let {{
if self.flavor == "dprefetch" or self.flavor == "iprefetch": if self.flavor == "dprefetch" or self.flavor == "iprefetch":
accCode = 'uint64_t temp = Mem%s; temp = temp;' accCode = 'uint64_t temp = Mem%s; temp = temp;'
elif self.flavor == "fp": elif self.flavor == "fp":
accCode = "FpDest.uw = cSwap(Mem%s, ((CPSR)Cpsr).e);\n" accCode = "FpDest_uw = cSwap(Mem%s, ((CPSR)Cpsr).e);\n"
else: else:
accCode = "IWDest = cSwap(Mem%s, ((CPSR)Cpsr).e);" accCode = "IWDest = cSwap(Mem%s, ((CPSR)Cpsr).e);"
accCode = accCode % buildMemSuffix(self.sign, self.size) accCode = accCode % buildMemSuffix(self.sign, self.size)
@ -260,14 +260,14 @@ let {{
if self.flavor != "fp": if self.flavor != "fp":
accCode = ''' accCode = '''
CPSR cpsr = Cpsr; CPSR cpsr = Cpsr;
Dest = cSwap<uint32_t>(Mem.ud, cpsr.e); Dest = cSwap<uint32_t>(Mem_ud, cpsr.e);
Dest2 = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e); Dest2 = cSwap<uint32_t>(Mem_ud >> 32, cpsr.e);
''' '''
else: else:
accCode = ''' accCode = '''
uint64_t swappedMem = cSwap(Mem.ud, ((CPSR)Cpsr).e); uint64_t swappedMem = cSwap(Mem_ud, ((CPSR)Cpsr).e);
FpDest.uw = (uint32_t)swappedMem; FpDest_uw = (uint32_t)swappedMem;
FpDest2.uw = (uint32_t)(swappedMem >> 32); FpDest2_uw = (uint32_t)(swappedMem >> 32);
''' '''
self.codeBlobs["memacc_code"] = accCode self.codeBlobs["memacc_code"] = accCode

66
src/arch/arm/isa/insts/macromem.isa
View file

@ -47,7 +47,7 @@
// //
let {{ let {{
microLdrUopCode = "IWRa = cSwap(Mem.uw, ((CPSR)Cpsr).e);" microLdrUopCode = "IWRa = cSwap(Mem_uw, ((CPSR)Cpsr).e);"
microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop', microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop',
'MicroMemOp', 'MicroMemOp',
{'memacc_code': microLdrUopCode, {'memacc_code': microLdrUopCode,
@ -55,7 +55,7 @@ let {{
'predicate_test': predicateTest}, 'predicate_test': predicateTest},
['IsMicroop']) ['IsMicroop'])
microLdrFpUopCode = "Fa.uw = cSwap(Mem.uw, ((CPSR)Cpsr).e);" microLdrFpUopCode = "Fa_uw = cSwap(Mem_uw, ((CPSR)Cpsr).e);"
microLdrFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrFpUop', microLdrFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrFpUop',
'MicroMemOp', 'MicroMemOp',
{'memacc_code': microLdrFpUopCode, {'memacc_code': microLdrFpUopCode,
@ -64,7 +64,7 @@ let {{
'predicate_test': predicateTest}, 'predicate_test': predicateTest},
['IsMicroop']) ['IsMicroop'])
microLdrDBFpUopCode = "Fa.uw = cSwap(Mem.uw, ((CPSR)Cpsr).e);" microLdrDBFpUopCode = "Fa_uw = cSwap(Mem_uw, ((CPSR)Cpsr).e);"
microLdrDBFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrDBFpUop', microLdrDBFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrDBFpUop',
'MicroMemOp', 'MicroMemOp',
{'memacc_code': microLdrFpUopCode, {'memacc_code': microLdrFpUopCode,
@ -75,7 +75,7 @@ let {{
'predicate_test': predicateTest}, 'predicate_test': predicateTest},
['IsMicroop']) ['IsMicroop'])
microLdrDTFpUopCode = "Fa.uw = cSwap(Mem.uw, ((CPSR)Cpsr).e);" microLdrDTFpUopCode = "Fa_uw = cSwap(Mem_uw, ((CPSR)Cpsr).e);"
microLdrDTFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrDTFpUop', microLdrDTFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrDTFpUop',
'MicroMemOp', 'MicroMemOp',
{'memacc_code': microLdrFpUopCode, {'memacc_code': microLdrFpUopCode,
@ -106,14 +106,14 @@ let {{
microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop', microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop',
'MicroMemOp', 'MicroMemOp',
{'memacc_code': {'memacc_code':
microRetUopCode % 'Mem.uw', microRetUopCode % 'Mem_uw',
'ea_code': 'ea_code':
'EA = URb + (up ? imm : -imm);', 'EA = URb + (up ? imm : -imm);',
'predicate_test': condPredicateTest}, 'predicate_test': condPredicateTest},
['IsMicroop','IsNonSpeculative', ['IsMicroop','IsNonSpeculative',
'IsSerializeAfter']) 'IsSerializeAfter'])
microStrUopCode = "Mem = cSwap(URa.uw, ((CPSR)Cpsr).e);" microStrUopCode = "Mem = cSwap(URa_uw, ((CPSR)Cpsr).e);"
microStrUopIop = InstObjParams('str_uop', 'MicroStrUop', microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
'MicroMemOp', 'MicroMemOp',
{'memacc_code': microStrUopCode, {'memacc_code': microStrUopCode,
@ -122,7 +122,7 @@ let {{
'predicate_test': predicateTest}, 'predicate_test': predicateTest},
['IsMicroop']) ['IsMicroop'])
microStrFpUopCode = "Mem = cSwap(Fa.uw, ((CPSR)Cpsr).e);" microStrFpUopCode = "Mem = cSwap(Fa_uw, ((CPSR)Cpsr).e);"
microStrFpUopIop = InstObjParams('strfp_uop', 'MicroStrFpUop', microStrFpUopIop = InstObjParams('strfp_uop', 'MicroStrFpUop',
'MicroMemOp', 'MicroMemOp',
{'memacc_code': microStrFpUopCode, {'memacc_code': microStrFpUopCode,
@ -132,7 +132,7 @@ let {{
'predicate_test': predicateTest}, 'predicate_test': predicateTest},
['IsMicroop']) ['IsMicroop'])
microStrDBFpUopCode = "Mem = cSwap(Fa.uw, ((CPSR)Cpsr).e);" microStrDBFpUopCode = "Mem = cSwap(Fa_uw, ((CPSR)Cpsr).e);"
microStrDBFpUopIop = InstObjParams('strfp_uop', 'MicroStrDBFpUop', microStrDBFpUopIop = InstObjParams('strfp_uop', 'MicroStrDBFpUop',
'MicroMemOp', 'MicroMemOp',
{'memacc_code': microStrFpUopCode, {'memacc_code': microStrFpUopCode,
@ -144,7 +144,7 @@ let {{
'predicate_test': predicateTest}, 'predicate_test': predicateTest},
['IsMicroop']) ['IsMicroop'])
microStrDTFpUopCode = "Mem = cSwap(Fa.uw, ((CPSR)Cpsr).e);" microStrDTFpUopCode = "Mem = cSwap(Fa_uw, ((CPSR)Cpsr).e);"
microStrDTFpUopIop = InstObjParams('strfp_uop', 'MicroStrDTFpUop', microStrDTFpUopIop = InstObjParams('strfp_uop', 'MicroStrDTFpUop',
'MicroMemOp', 'MicroMemOp',
{'memacc_code': microStrFpUopCode, {'memacc_code': microStrFpUopCode,
@ -214,14 +214,14 @@ let {{
if reg == regs - 1: if reg == regs - 1:
mask = ' & mask(%d)' % (32 - 8 * (regs * 4 - size)) mask = ' & mask(%d)' % (32 - 8 * (regs * 4 - size))
regSetCode += ''' regSetCode += '''
FpDestP%(reg)d.uw = gtoh(memUnion.floatRegBits[%(reg)d])%(mask)s; FpDestP%(reg)d_uw = gtoh(memUnion.floatRegBits[%(reg)d])%(mask)s;
''' % { "reg" : reg, "mask" : mask } ''' % { "reg" : reg, "mask" : mask }
# Pull everything in from registers # Pull everything in from registers
regGetCode = '' regGetCode = ''
for reg in range(regs): for reg in range(regs):
regGetCode += ''' regGetCode += '''
memUnion.floatRegBits[%(reg)d] = htog(FpDestP%(reg)d.uw); memUnion.floatRegBits[%(reg)d] = htog(FpDestP%(reg)d_uw);
''' % { "reg" : reg } ''' % { "reg" : reg }
loadMemAccCode = convCode + regSetCode loadMemAccCode = convCode + regSetCode
@ -293,12 +293,12 @@ let {{
unloadConv = '' unloadConv = ''
for dReg in range(dRegs): for dReg in range(dRegs):
loadConv += ''' loadConv += '''
conv1.cRegs[%(sReg0)d] = htog(FpOp1P%(sReg0)d.uw); conv1.cRegs[%(sReg0)d] = htog(FpOp1P%(sReg0)d_uw);
conv1.cRegs[%(sReg1)d] = htog(FpOp1P%(sReg1)d.uw); conv1.cRegs[%(sReg1)d] = htog(FpOp1P%(sReg1)d_uw);
''' % { "sReg0" : (dReg * 2), "sReg1" : (dReg * 2 + 1) } ''' % { "sReg0" : (dReg * 2), "sReg1" : (dReg * 2 + 1) }
unloadConv += ''' unloadConv += '''
FpDestS%(dReg)dP0.uw = gtoh(conv2.cRegs[2 * %(dReg)d + 0]); FpDestS%(dReg)dP0_uw = gtoh(conv2.cRegs[2 * %(dReg)d + 0]);
FpDestS%(dReg)dP1.uw = gtoh(conv2.cRegs[2 * %(dReg)d + 1]); FpDestS%(dReg)dP1_uw = gtoh(conv2.cRegs[2 * %(dReg)d + 1]);
''' % { "dReg" : dReg } ''' % { "dReg" : dReg }
microDeintNeonCode = ''' microDeintNeonCode = '''
const unsigned dRegs = %(dRegs)d; const unsigned dRegs = %(dRegs)d;
@ -339,12 +339,12 @@ let {{
unloadConv = '' unloadConv = ''
for dReg in range(dRegs): for dReg in range(dRegs):
loadConv += ''' loadConv += '''
conv1.cRegs[2 * %(dReg)d + 0] = htog(FpOp1S%(dReg)dP0.uw); conv1.cRegs[2 * %(dReg)d + 0] = htog(FpOp1S%(dReg)dP0_uw);
conv1.cRegs[2 * %(dReg)d + 1] = htog(FpOp1S%(dReg)dP1.uw); conv1.cRegs[2 * %(dReg)d + 1] = htog(FpOp1S%(dReg)dP1_uw);
''' % { "dReg" : dReg } ''' % { "dReg" : dReg }
unloadConv += ''' unloadConv += '''
FpDestP%(sReg0)d.uw = gtoh(conv2.cRegs[%(sReg0)d]); FpDestP%(sReg0)d_uw = gtoh(conv2.cRegs[%(sReg0)d]);
FpDestP%(sReg1)d.uw = gtoh(conv2.cRegs[%(sReg1)d]); FpDestP%(sReg1)d_uw = gtoh(conv2.cRegs[%(sReg1)d]);
''' % { "sReg0" : (dReg * 2), "sReg1" : (dReg * 2 + 1) } ''' % { "sReg0" : (dReg * 2), "sReg1" : (dReg * 2 + 1) }
microInterNeonCode = ''' microInterNeonCode = '''
const unsigned dRegs = %(dRegs)d; const unsigned dRegs = %(dRegs)d;
@ -405,8 +405,8 @@ let {{
baseLoadRegs = '' baseLoadRegs = ''
for reg in range(sRegs): for reg in range(sRegs):
baseLoadRegs += ''' baseLoadRegs += '''
sourceRegs.fRegs[%(reg0)d] = htog(FpOp1P%(reg0)d.uw); sourceRegs.fRegs[%(reg0)d] = htog(FpOp1P%(reg0)d_uw);
sourceRegs.fRegs[%(reg1)d] = htog(FpOp1P%(reg1)d.uw); sourceRegs.fRegs[%(reg1)d] = htog(FpOp1P%(reg1)d_uw);
''' % { "reg0" : (2 * reg + 0), ''' % { "reg0" : (2 * reg + 0),
"reg1" : (2 * reg + 1) } "reg1" : (2 * reg + 1) }
for dRegs in range(sRegs, 5): for dRegs in range(sRegs, 5):
@ -414,12 +414,12 @@ let {{
loadRegs = baseLoadRegs loadRegs = baseLoadRegs
for reg in range(dRegs): for reg in range(dRegs):
loadRegs += ''' loadRegs += '''
destRegs[%(reg)d].fRegs[0] = htog(FpDestS%(reg)dP0.uw); destRegs[%(reg)d].fRegs[0] = htog(FpDestS%(reg)dP0_uw);
destRegs[%(reg)d].fRegs[1] = htog(FpDestS%(reg)dP1.uw); destRegs[%(reg)d].fRegs[1] = htog(FpDestS%(reg)dP1_uw);
''' % { "reg" : reg } ''' % { "reg" : reg }
unloadRegs += ''' unloadRegs += '''
FpDestS%(reg)dP0.uw = gtoh(destRegs[%(reg)d].fRegs[0]); FpDestS%(reg)dP0_uw = gtoh(destRegs[%(reg)d].fRegs[0]);
FpDestS%(reg)dP1.uw = gtoh(destRegs[%(reg)d].fRegs[1]); FpDestS%(reg)dP1_uw = gtoh(destRegs[%(reg)d].fRegs[1]);
''' % { "reg" : reg } ''' % { "reg" : reg }
microUnpackNeonCode = ''' microUnpackNeonCode = '''
const unsigned perDReg = (2 * sizeof(FloatRegBits)) / const unsigned perDReg = (2 * sizeof(FloatRegBits)) /
@ -460,16 +460,16 @@ let {{
loadRegs = '' loadRegs = ''
for reg in range(sRegs): for reg in range(sRegs):
loadRegs += ''' loadRegs += '''
sourceRegs.fRegs[%(reg0)d] = htog(FpOp1P%(reg0)d.uw); sourceRegs.fRegs[%(reg0)d] = htog(FpOp1P%(reg0)d_uw);
sourceRegs.fRegs[%(reg1)d] = htog(FpOp1P%(reg1)d.uw); sourceRegs.fRegs[%(reg1)d] = htog(FpOp1P%(reg1)d_uw);
''' % { "reg0" : (2 * reg + 0), ''' % { "reg0" : (2 * reg + 0),
"reg1" : (2 * reg + 1) } "reg1" : (2 * reg + 1) }
for dRegs in range(sRegs, 5): for dRegs in range(sRegs, 5):
unloadRegs = '' unloadRegs = ''
for reg in range(dRegs): for reg in range(dRegs):
unloadRegs += ''' unloadRegs += '''
FpDestS%(reg)dP0.uw = gtoh(destRegs[%(reg)d].fRegs[0]); FpDestS%(reg)dP0_uw = gtoh(destRegs[%(reg)d].fRegs[0]);
FpDestS%(reg)dP1.uw = gtoh(destRegs[%(reg)d].fRegs[1]); FpDestS%(reg)dP1_uw = gtoh(destRegs[%(reg)d].fRegs[1]);
''' % { "reg" : reg } ''' % { "reg" : reg }
microUnpackAllNeonCode = ''' microUnpackAllNeonCode = '''
const unsigned perDReg = (2 * sizeof(FloatRegBits)) / const unsigned perDReg = (2 * sizeof(FloatRegBits)) /
@ -511,16 +511,16 @@ let {{
unloadRegs = '' unloadRegs = ''
for reg in range(dRegs): for reg in range(dRegs):
unloadRegs += ''' unloadRegs += '''
FpDestP%(reg0)d.uw = gtoh(destRegs.fRegs[%(reg0)d]); FpDestP%(reg0)d_uw = gtoh(destRegs.fRegs[%(reg0)d]);
FpDestP%(reg1)d.uw = gtoh(destRegs.fRegs[%(reg1)d]); FpDestP%(reg1)d_uw = gtoh(destRegs.fRegs[%(reg1)d]);
''' % { "reg0" : (2 * reg + 0), ''' % { "reg0" : (2 * reg + 0),
"reg1" : (2 * reg + 1) } "reg1" : (2 * reg + 1) }
for sRegs in range(dRegs, 5): for sRegs in range(dRegs, 5):
loadRegs = '' loadRegs = ''
for reg in range(sRegs): for reg in range(sRegs):
loadRegs += ''' loadRegs += '''
sourceRegs[%(reg)d].fRegs[0] = htog(FpOp1S%(reg)dP0.uw); sourceRegs[%(reg)d].fRegs[0] = htog(FpOp1S%(reg)dP0_uw);
sourceRegs[%(reg)d].fRegs[1] = htog(FpOp1S%(reg)dP1.uw); sourceRegs[%(reg)d].fRegs[1] = htog(FpOp1S%(reg)dP1_uw);
''' % { "reg" : reg } ''' % { "reg" : reg }
microPackNeonCode = ''' microPackNeonCode = '''
const unsigned perDReg = (2 * sizeof(FloatRegBits)) / const unsigned perDReg = (2 * sizeof(FloatRegBits)) /

8
src/arch/arm/isa/insts/mem.isa
View file

@ -180,14 +180,14 @@ let {{
memSuffix = '' memSuffix = ''
elif size == 2: elif size == 2:
if sign: if sign:
memSuffix = '.sh' memSuffix = '_sh'
else: else:
memSuffix = '.uh' memSuffix = '_uh'
elif size == 1: elif size == 1:
if sign: if sign:
memSuffix = '.sb' memSuffix = '_sb'
else: else:
memSuffix = '.ub' memSuffix = '_ub'
else: else:
raise Exception, "Unrecognized size for access %d" % size raise Exception, "Unrecognized size for access %d" % size

8
src/arch/arm/isa/insts/misc.isa
View file

@ -287,7 +287,7 @@ let {{
sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp", sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp",
{ "code": { "code":
"Dest = sext<8>((uint8_t)(Op1.ud >> imm));", "Dest = sext<8>((uint8_t)(Op1_ud >> imm));",
"predicate_test": predicateTest }, []) "predicate_test": predicateTest }, [])
header_output += RegImmRegOpDeclare.subst(sxtbIop) header_output += RegImmRegOpDeclare.subst(sxtbIop)
decoder_output += RegImmRegOpConstructor.subst(sxtbIop) decoder_output += RegImmRegOpConstructor.subst(sxtbIop)
@ -296,7 +296,7 @@ let {{
sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp", sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp",
{ "code": { "code":
''' '''
Dest = sext<8>((uint8_t)(Op2.ud >> imm)) + Dest = sext<8>((uint8_t)(Op2_ud >> imm)) +
Op1; Op1;
''', ''',
"predicate_test": predicateTest }, []) "predicate_test": predicateTest }, [])
@ -359,7 +359,7 @@ let {{
exec_output += PredOpExecute.subst(sxtahIop) exec_output += PredOpExecute.subst(sxtahIop)
uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp", uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp",
{ "code": "Dest = (uint8_t)(Op1.ud >> imm);", { "code": "Dest = (uint8_t)(Op1_ud >> imm);",
"predicate_test": predicateTest }, []) "predicate_test": predicateTest }, [])
header_output += RegImmRegOpDeclare.subst(uxtbIop) header_output += RegImmRegOpDeclare.subst(uxtbIop)
decoder_output += RegImmRegOpConstructor.subst(uxtbIop) decoder_output += RegImmRegOpConstructor.subst(uxtbIop)
@ -367,7 +367,7 @@ let {{
uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp", uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp",
{ "code": { "code":
"Dest = (uint8_t)(Op2.ud >> imm) + Op1;", "Dest = (uint8_t)(Op2_ud >> imm) + Op1;",
"predicate_test": predicateTest }, []) "predicate_test": predicateTest }, [])
header_output += RegRegRegImmOpDeclare.subst(uxtabIop) header_output += RegRegRegImmOpDeclare.subst(uxtabIop)
decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop) decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop)

160
src/arch/arm/isa/insts/mult.isa
View file

@ -135,29 +135,29 @@ let {{
buildMult3Inst ("mul", "Reg0 = resTemp = Reg1 * Reg2;") buildMult3Inst ("mul", "Reg0 = resTemp = Reg1 * Reg2;")
buildMult4InstCc ("smlabb", '''Reg0 = resTemp = buildMult4InstCc ("smlabb", '''Reg0 = resTemp =
sext<16>(bits(Reg1, 15, 0)) * sext<16>(bits(Reg1, 15, 0)) *
sext<16>(bits(Reg2.sw, 15, 0)) + sext<16>(bits(Reg2_sw, 15, 0)) +
Reg3.sw; Reg3_sw;
resTemp = bits(resTemp, 32) != resTemp = bits(resTemp, 32) !=
bits(resTemp, 31); bits(resTemp, 31);
''', "overflow") ''', "overflow")
buildMult4InstCc ("smlabt", '''Reg0 = resTemp = buildMult4InstCc ("smlabt", '''Reg0 = resTemp =
sext<16>(bits(Reg1, 15, 0)) * sext<16>(bits(Reg1, 15, 0)) *
sext<16>(bits(Reg2.sw, 31, 16)) + sext<16>(bits(Reg2_sw, 31, 16)) +
Reg3.sw; Reg3_sw;
resTemp = bits(resTemp, 32) != resTemp = bits(resTemp, 32) !=
bits(resTemp, 31); bits(resTemp, 31);
''', "overflow") ''', "overflow")
buildMult4InstCc ("smlatb", '''Reg0 = resTemp = buildMult4InstCc ("smlatb", '''Reg0 = resTemp =
sext<16>(bits(Reg1, 31, 16)) * sext<16>(bits(Reg1, 31, 16)) *
sext<16>(bits(Reg2.sw, 15, 0)) + sext<16>(bits(Reg2_sw, 15, 0)) +
Reg3.sw; Reg3_sw;
resTemp = bits(resTemp, 32) != resTemp = bits(resTemp, 32) !=
bits(resTemp, 31); bits(resTemp, 31);
''', "overflow") ''', "overflow")
buildMult4InstCc ("smlatt", '''Reg0 = resTemp = buildMult4InstCc ("smlatt", '''Reg0 = resTemp =
sext<16>(bits(Reg1, 31, 16)) * sext<16>(bits(Reg1, 31, 16)) *
sext<16>(bits(Reg2.sw, 31, 16)) + sext<16>(bits(Reg2_sw, 31, 16)) +
Reg3.sw; Reg3_sw;
resTemp = bits(resTemp, 32) != resTemp = bits(resTemp, 32) !=
bits(resTemp, 31); bits(resTemp, 31);
''', "overflow") ''', "overflow")
@ -166,7 +166,7 @@ let {{
sext<16>(bits(Reg2, 31, 16)) + sext<16>(bits(Reg2, 31, 16)) +
sext<16>(bits(Reg1, 15, 0)) * sext<16>(bits(Reg1, 15, 0)) *
sext<16>(bits(Reg2, 15, 0)) + sext<16>(bits(Reg2, 15, 0)) +
Reg3.sw; Reg3_sw;
resTemp = bits(resTemp, 32) != resTemp = bits(resTemp, 32) !=
bits(resTemp, 31); bits(resTemp, 31);
''', "overflow") ''', "overflow")
@ -175,74 +175,74 @@ let {{
sext<16>(bits(Reg2, 15, 0)) + sext<16>(bits(Reg2, 15, 0)) +
sext<16>(bits(Reg1, 15, 0)) * sext<16>(bits(Reg1, 15, 0)) *
sext<16>(bits(Reg2, 31, 16)) + sext<16>(bits(Reg2, 31, 16)) +
Reg3.sw; Reg3_sw;
resTemp = bits(resTemp, 32) != resTemp = bits(resTemp, 32) !=
bits(resTemp, 31); bits(resTemp, 31);
''', "overflow") ''', "overflow")
buildMult4Inst ("smlal", '''resTemp = sext<32>(Reg2) * sext<32>(Reg3) + buildMult4Inst ("smlal", '''resTemp = sext<32>(Reg2) * sext<32>(Reg3) +
(int64_t)((Reg1.ud << 32) | Reg0.ud); (int64_t)((Reg1_ud << 32) | Reg0_ud);
Reg0.ud = (uint32_t)resTemp; Reg0_ud = (uint32_t)resTemp;
Reg1.ud = (uint32_t)(resTemp >> 32); Reg1_ud = (uint32_t)(resTemp >> 32);
''', "llbit") ''', "llbit")
buildMult4InstUnCc("smlalbb", '''resTemp = sext<16>(bits(Reg2, 15, 0)) * buildMult4InstUnCc("smlalbb", '''resTemp = sext<16>(bits(Reg2, 15, 0)) *
sext<16>(bits(Reg3, 15, 0)) + sext<16>(bits(Reg3, 15, 0)) +
(int64_t)((Reg1.ud << 32) | (int64_t)((Reg1_ud << 32) |
Reg0.ud); Reg0_ud);
Reg0.ud = (uint32_t)resTemp; Reg0_ud = (uint32_t)resTemp;
Reg1.ud = (uint32_t)(resTemp >> 32); Reg1_ud = (uint32_t)(resTemp >> 32);
''') ''')
buildMult4InstUnCc("smlalbt", '''resTemp = sext<16>(bits(Reg2, 15, 0)) * buildMult4InstUnCc("smlalbt", '''resTemp = sext<16>(bits(Reg2, 15, 0)) *
sext<16>(bits(Reg3, 31, 16)) + sext<16>(bits(Reg3, 31, 16)) +
(int64_t)((Reg1.ud << 32) | (int64_t)((Reg1_ud << 32) |
Reg0.ud); Reg0_ud);
Reg0.ud = (uint32_t)resTemp; Reg0_ud = (uint32_t)resTemp;
Reg1.ud = (uint32_t)(resTemp >> 32); Reg1_ud = (uint32_t)(resTemp >> 32);
''') ''')
buildMult4InstUnCc("smlaltb", '''resTemp = sext<16>(bits(Reg2, 31, 16)) * buildMult4InstUnCc("smlaltb", '''resTemp = sext<16>(bits(Reg2, 31, 16)) *
sext<16>(bits(Reg3, 15, 0)) + sext<16>(bits(Reg3, 15, 0)) +
(int64_t)((Reg1.ud << 32) | (int64_t)((Reg1_ud << 32) |
Reg0.ud); Reg0_ud);
Reg0.ud = (uint32_t)resTemp; Reg0_ud = (uint32_t)resTemp;
Reg1.ud = (uint32_t)(resTemp >> 32); Reg1_ud = (uint32_t)(resTemp >> 32);
''') ''')
buildMult4InstUnCc("smlaltt", '''resTemp = sext<16>(bits(Reg2, 31, 16)) * buildMult4InstUnCc("smlaltt", '''resTemp = sext<16>(bits(Reg2, 31, 16)) *
sext<16>(bits(Reg3, 31, 16)) + sext<16>(bits(Reg3, 31, 16)) +
(int64_t)((Reg1.ud << 32) | (int64_t)((Reg1_ud << 32) |
Reg0.ud); Reg0_ud);
Reg0.ud = (uint32_t)resTemp; Reg0_ud = (uint32_t)resTemp;
Reg1.ud = (uint32_t)(resTemp >> 32); Reg1_ud = (uint32_t)(resTemp >> 32);
''') ''')
buildMult4InstUnCc("smlald", '''resTemp = buildMult4InstUnCc("smlald", '''resTemp =
sext<16>(bits(Reg2, 31, 16)) * sext<16>(bits(Reg2, 31, 16)) *
sext<16>(bits(Reg3, 31, 16)) + sext<16>(bits(Reg3, 31, 16)) +
sext<16>(bits(Reg2, 15, 0)) * sext<16>(bits(Reg2, 15, 0)) *
sext<16>(bits(Reg3, 15, 0)) + sext<16>(bits(Reg3, 15, 0)) +
(int64_t)((Reg1.ud << 32) | (int64_t)((Reg1_ud << 32) |
Reg0.ud); Reg0_ud);
Reg0.ud = (uint32_t)resTemp; Reg0_ud = (uint32_t)resTemp;
Reg1.ud = (uint32_t)(resTemp >> 32); Reg1_ud = (uint32_t)(resTemp >> 32);
''') ''')
buildMult4InstUnCc("smlaldx", '''resTemp = buildMult4InstUnCc("smlaldx", '''resTemp =
sext<16>(bits(Reg2, 31, 16)) * sext<16>(bits(Reg2, 31, 16)) *
sext<16>(bits(Reg3, 15, 0)) + sext<16>(bits(Reg3, 15, 0)) +
sext<16>(bits(Reg2, 15, 0)) * sext<16>(bits(Reg2, 15, 0)) *
sext<16>(bits(Reg3, 31, 16)) + sext<16>(bits(Reg3, 31, 16)) +
(int64_t)((Reg1.ud << 32) | (int64_t)((Reg1_ud << 32) |
Reg0.ud); Reg0_ud);
Reg0.ud = (uint32_t)resTemp; Reg0_ud = (uint32_t)resTemp;
Reg1.ud = (uint32_t)(resTemp >> 32); Reg1_ud = (uint32_t)(resTemp >> 32);
''') ''')
buildMult4InstCc ("smlawb", '''Reg0 = resTemp = buildMult4InstCc ("smlawb", '''Reg0 = resTemp =
(Reg1.sw * (Reg1_sw *
sext<16>(bits(Reg2, 15, 0)) + sext<16>(bits(Reg2, 15, 0)) +
((int64_t)Reg3.sw << 16)) >> 16; ((int64_t)Reg3_sw << 16)) >> 16;
resTemp = bits(resTemp, 32) != resTemp = bits(resTemp, 32) !=
bits(resTemp, 31); bits(resTemp, 31);
''', "overflow") ''', "overflow")
buildMult4InstCc ("smlawt", '''Reg0 = resTemp = buildMult4InstCc ("smlawt", '''Reg0 = resTemp =
(Reg1.sw * (Reg1_sw *
sext<16>(bits(Reg2, 31, 16)) + sext<16>(bits(Reg2, 31, 16)) +
((int64_t)Reg3.sw << 16)) >> 16; ((int64_t)Reg3_sw << 16)) >> 16;
resTemp = bits(resTemp, 32) != resTemp = bits(resTemp, 32) !=
bits(resTemp, 31); bits(resTemp, 31);
''', "overflow") ''', "overflow")
@ -251,7 +251,7 @@ let {{
sext<16>(bits(Reg2, 15, 0)) - sext<16>(bits(Reg2, 15, 0)) -
sext<16>(bits(Reg1, 31, 16)) * sext<16>(bits(Reg1, 31, 16)) *
sext<16>(bits(Reg2, 31, 16)) + sext<16>(bits(Reg2, 31, 16)) +
Reg3.sw; Reg3_sw;
resTemp = bits(resTemp, 32) != resTemp = bits(resTemp, 32) !=
bits(resTemp, 31); bits(resTemp, 31);
''', "overflow") ''', "overflow")
@ -260,7 +260,7 @@ let {{
sext<16>(bits(Reg2, 31, 16)) - sext<16>(bits(Reg2, 31, 16)) -
sext<16>(bits(Reg1, 31, 16)) * sext<16>(bits(Reg1, 31, 16)) *
sext<16>(bits(Reg2, 15, 0)) + sext<16>(bits(Reg2, 15, 0)) +
Reg3.sw; Reg3_sw;
resTemp = bits(resTemp, 32) != resTemp = bits(resTemp, 32) !=
bits(resTemp, 31); bits(resTemp, 31);
''', "overflow") ''', "overflow")
@ -269,50 +269,50 @@ let {{
sext<16>(bits(Reg3, 15, 0)) - sext<16>(bits(Reg3, 15, 0)) -
sext<16>(bits(Reg2, 31, 16)) * sext<16>(bits(Reg2, 31, 16)) *
sext<16>(bits(Reg3, 31, 16)) + sext<16>(bits(Reg3, 31, 16)) +
(int64_t)((Reg1.ud << 32) | (int64_t)((Reg1_ud << 32) |
Reg0.ud); Reg0_ud);
Reg0.ud = (uint32_t)resTemp; Reg0_ud = (uint32_t)resTemp;
Reg1.ud = (uint32_t)(resTemp >> 32); Reg1_ud = (uint32_t)(resTemp >> 32);
''') ''')
buildMult4InstUnCc("smlsldx", '''resTemp = buildMult4InstUnCc("smlsldx", '''resTemp =
sext<16>(bits(Reg2, 15, 0)) * sext<16>(bits(Reg2, 15, 0)) *
sext<16>(bits(Reg3, 31, 16)) - sext<16>(bits(Reg3, 31, 16)) -
sext<16>(bits(Reg2, 31, 16)) * sext<16>(bits(Reg2, 31, 16)) *
sext<16>(bits(Reg3, 15, 0)) + sext<16>(bits(Reg3, 15, 0)) +
(int64_t)((Reg1.ud << 32) | (int64_t)((Reg1_ud << 32) |
Reg0.ud); Reg0_ud);
Reg0.ud = (uint32_t)resTemp; Reg0_ud = (uint32_t)resTemp;
Reg1.ud = (uint32_t)(resTemp >> 32); Reg1_ud = (uint32_t)(resTemp >> 32);
''') ''')
buildMult4InstUnCc("smmla", '''Reg0 = resTemp = buildMult4InstUnCc("smmla", '''Reg0 = resTemp =
((int64_t)(Reg3.ud << 32) + ((int64_t)(Reg3_ud << 32) +
(int64_t)Reg1.sw * (int64_t)Reg1_sw *
(int64_t)Reg2.sw) >> 32; (int64_t)Reg2_sw) >> 32;
''') ''')
buildMult4InstUnCc("smmlar", '''Reg0 = resTemp = buildMult4InstUnCc("smmlar", '''Reg0 = resTemp =
((int64_t)(Reg3.ud << 32) + ((int64_t)(Reg3_ud << 32) +
(int64_t)Reg1.sw * (int64_t)Reg1_sw *
(int64_t)Reg2.sw + (int64_t)Reg2_sw +
ULL(0x80000000)) >> 32; ULL(0x80000000)) >> 32;
''') ''')
buildMult4InstUnCc("smmls", '''Reg0 = resTemp = buildMult4InstUnCc("smmls", '''Reg0 = resTemp =
((int64_t)(Reg3.ud << 32) - ((int64_t)(Reg3_ud << 32) -
(int64_t)Reg1.sw * (int64_t)Reg1_sw *
(int64_t)Reg2.sw) >> 32; (int64_t)Reg2_sw) >> 32;
''') ''')
buildMult4InstUnCc("smmlsr", '''Reg0 = resTemp = buildMult4InstUnCc("smmlsr", '''Reg0 = resTemp =
((int64_t)(Reg3.ud << 32) - ((int64_t)(Reg3_ud << 32) -
(int64_t)Reg1.sw * (int64_t)Reg1_sw *
(int64_t)Reg2.sw + (int64_t)Reg2_sw +
ULL(0x80000000)) >> 32; ULL(0x80000000)) >> 32;
''') ''')
buildMult3InstUnCc("smmul", '''Reg0 = resTemp = buildMult3InstUnCc("smmul", '''Reg0 = resTemp =
((int64_t)Reg1.sw * ((int64_t)Reg1_sw *
(int64_t)Reg2.sw) >> 32; (int64_t)Reg2_sw) >> 32;
''') ''')
buildMult3InstUnCc("smmulr", '''Reg0 = resTemp = buildMult3InstUnCc("smmulr", '''Reg0 = resTemp =
((int64_t)Reg1.sw * ((int64_t)Reg1_sw *
(int64_t)Reg2.sw + (int64_t)Reg2_sw +
ULL(0x80000000)) >> 32; ULL(0x80000000)) >> 32;
''') ''')
buildMult3InstCc ("smuad", '''Reg0 = resTemp = buildMult3InstCc ("smuad", '''Reg0 = resTemp =
@ -347,17 +347,17 @@ let {{
sext<16>(bits(Reg1, 31, 16)) * sext<16>(bits(Reg1, 31, 16)) *
sext<16>(bits(Reg2, 31, 16)); sext<16>(bits(Reg2, 31, 16));
''') ''')
buildMult4Inst ("smull", '''resTemp = (int64_t)Reg2.sw * buildMult4Inst ("smull", '''resTemp = (int64_t)Reg2_sw *
(int64_t)Reg3.sw; (int64_t)Reg3_sw;
Reg1 = (int32_t)(resTemp >> 32); Reg1 = (int32_t)(resTemp >> 32);
Reg0 = (int32_t)resTemp; Reg0 = (int32_t)resTemp;
''', "llbit") ''', "llbit")
buildMult3InstUnCc("smulwb", '''Reg0 = resTemp = buildMult3InstUnCc("smulwb", '''Reg0 = resTemp =
(Reg1.sw * (Reg1_sw *
sext<16>(bits(Reg2, 15, 0))) >> 16; sext<16>(bits(Reg2, 15, 0))) >> 16;
''') ''')
buildMult3InstUnCc("smulwt", '''Reg0 = resTemp = buildMult3InstUnCc("smulwt", '''Reg0 = resTemp =
(Reg1.sw * (Reg1_sw *
sext<16>(bits(Reg2, 31, 16))) >> 16; sext<16>(bits(Reg2, 31, 16))) >> 16;
''') ''')
buildMult3InstUnCc("smusd", '''Reg0 = resTemp = buildMult3InstUnCc("smusd", '''Reg0 = resTemp =
@ -372,17 +372,17 @@ let {{
sext<16>(bits(Reg1, 31, 16)) * sext<16>(bits(Reg1, 31, 16)) *
sext<16>(bits(Reg2, 15, 0)); sext<16>(bits(Reg2, 15, 0));
''') ''')
buildMult4InstUnCc("umaal", '''resTemp = Reg2.ud * Reg3.ud + buildMult4InstUnCc("umaal", '''resTemp = Reg2_ud * Reg3_ud +
Reg0.ud + Reg1.ud; Reg0_ud + Reg1_ud;
Reg1.ud = (uint32_t)(resTemp >> 32); Reg1_ud = (uint32_t)(resTemp >> 32);
Reg0.ud = (uint32_t)resTemp; Reg0_ud = (uint32_t)resTemp;
''') ''')
buildMult4Inst ("umlal", '''resTemp = Reg2.ud * Reg3.ud + Reg0.ud + buildMult4Inst ("umlal", '''resTemp = Reg2_ud * Reg3_ud + Reg0_ud +
(Reg1.ud << 32); (Reg1_ud << 32);
Reg1.ud = (uint32_t)(resTemp >> 32); Reg1_ud = (uint32_t)(resTemp >> 32);
Reg0.ud = (uint32_t)resTemp; Reg0_ud = (uint32_t)resTemp;
''', "llbit") ''', "llbit")
buildMult4Inst ("umull", '''resTemp = Reg2.ud * Reg3.ud; buildMult4Inst ("umull", '''resTemp = Reg2_ud * Reg3_ud;
Reg1 = (uint32_t)(resTemp >> 32); Reg1 = (uint32_t)(resTemp >> 32);
Reg0 = (uint32_t)resTemp; Reg0 = (uint32_t)resTemp;
''', "llbit") ''', "llbit")

118
src/arch/arm/isa/insts/neon.isa
View file

@ -639,12 +639,12 @@ let {{
''' '''
for reg in range(rCount): for reg in range(rCount):
eWalkCode += ''' eWalkCode += '''
srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw); srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d.uw); srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw);
''' % { "reg" : reg } ''' % { "reg" : reg }
if readDest: if readDest:
eWalkCode += ''' eWalkCode += '''
destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw); destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
''' % { "reg" : reg } ''' % { "reg" : reg }
readDestCode = '' readDestCode = ''
if readDest: if readDest:
@ -677,7 +677,7 @@ let {{
''' % { "op" : op, "readDest" : readDestCode } ''' % { "op" : op, "readDest" : readDestCode }
for reg in range(rCount): for reg in range(rCount):
eWalkCode += ''' eWalkCode += '''
FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]); FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
''' % { "reg" : reg } ''' % { "reg" : reg }
iop = InstObjParams(name, Name, iop = InstObjParams(name, Name,
"RegRegRegOp", "RegRegRegOp",
@ -758,7 +758,7 @@ let {{
for reg in range(rCount): for reg in range(rCount):
if toInt: if toInt:
eWalkCode += ''' eWalkCode += '''
FpDestP%(reg)d.uw = destRegs.regs[%(reg)d]; FpDestP%(reg)d_uw = destRegs.regs[%(reg)d];
''' % { "reg" : reg } ''' % { "reg" : reg }
else: else:
eWalkCode += ''' eWalkCode += '''
@ -798,16 +798,16 @@ let {{
''' % (src1Prefix, src2Prefix, destPrefix) ''' % (src1Prefix, src2Prefix, destPrefix)
for reg in range(src1Cnt): for reg in range(src1Cnt):
eWalkCode += ''' eWalkCode += '''
srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw); srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
''' % { "reg" : reg } ''' % { "reg" : reg }
for reg in range(src2Cnt): for reg in range(src2Cnt):
eWalkCode += ''' eWalkCode += '''
srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d.uw); srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw);
''' % { "reg" : reg } ''' % { "reg" : reg }
if readDest: if readDest:
for reg in range(destCnt): for reg in range(destCnt):
eWalkCode += ''' eWalkCode += '''
destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw); destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
''' % { "reg" : reg } ''' % { "reg" : reg }
readDestCode = '' readDestCode = ''
if readDest: if readDest:
@ -826,7 +826,7 @@ let {{
"destPrefix" : destPrefix } "destPrefix" : destPrefix }
for reg in range(destCnt): for reg in range(destCnt):
eWalkCode += ''' eWalkCode += '''
FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]); FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
''' % { "reg" : reg } ''' % { "reg" : reg }
iop = InstObjParams(name, Name, iop = InstObjParams(name, Name,
"RegRegRegOp", "RegRegRegOp",
@ -860,12 +860,12 @@ let {{
''' '''
for reg in range(rCount): for reg in range(rCount):
eWalkCode += ''' eWalkCode += '''
srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw); srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d.uw); srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw);
''' % { "reg" : reg } ''' % { "reg" : reg }
if readDest: if readDest:
eWalkCode += ''' eWalkCode += '''
destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw); destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
''' % { "reg" : reg } ''' % { "reg" : reg }
readDestCode = '' readDestCode = ''
if readDest: if readDest:
@ -890,7 +890,7 @@ let {{
''' % { "op" : op, "readDest" : readDestCode } ''' % { "op" : op, "readDest" : readDestCode }
for reg in range(rCount): for reg in range(rCount):
eWalkCode += ''' eWalkCode += '''
FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]); FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
''' % { "reg" : reg } ''' % { "reg" : reg }
iop = InstObjParams(name, Name, iop = InstObjParams(name, Name,
"RegRegRegImmOp", "RegRegRegImmOp",
@ -914,13 +914,13 @@ let {{
''' '''
for reg in range(rCount): for reg in range(rCount):
eWalkCode += ''' eWalkCode += '''
srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw); srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d.uw);; srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw);;
''' % { "reg" : reg } ''' % { "reg" : reg }
if readDest: if readDest:
for reg in range(2 * rCount): for reg in range(2 * rCount):
eWalkCode += ''' eWalkCode += '''
destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw); destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
''' % { "reg" : reg } ''' % { "reg" : reg }
readDestCode = '' readDestCode = ''
if readDest: if readDest:
@ -945,7 +945,7 @@ let {{
''' % { "op" : op, "readDest" : readDestCode } ''' % { "op" : op, "readDest" : readDestCode }
for reg in range(2 * rCount): for reg in range(2 * rCount):
eWalkCode += ''' eWalkCode += '''
FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]); FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
''' % { "reg" : reg } ''' % { "reg" : reg }
iop = InstObjParams(name, Name, iop = InstObjParams(name, Name,
"RegRegRegImmOp", "RegRegRegImmOp",
@ -1021,11 +1021,11 @@ let {{
''' '''
for reg in range(rCount): for reg in range(rCount):
eWalkCode += ''' eWalkCode += '''
srcRegs1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw); srcRegs1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
''' % { "reg" : reg } ''' % { "reg" : reg }
if readDest: if readDest:
eWalkCode += ''' eWalkCode += '''
destRegs.regs[%(reg)d] = htog(FpDestP%(reg)d.uw); destRegs.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
''' % { "reg" : reg } ''' % { "reg" : reg }
readDestCode = '' readDestCode = ''
if readDest: if readDest:
@ -1055,7 +1055,7 @@ let {{
"writeDest" : writeDestCode } "writeDest" : writeDestCode }
for reg in range(rCount): for reg in range(rCount):
eWalkCode += ''' eWalkCode += '''
FpDestP%(reg)d.uw = gtoh(destRegs.regs[%(reg)d]); FpDestP%(reg)d_uw = gtoh(destRegs.regs[%(reg)d]);
''' % { "reg" : reg } ''' % { "reg" : reg }
iop = InstObjParams(name, Name, iop = InstObjParams(name, Name,
"RegRegImmOp", "RegRegImmOp",
@ -1078,12 +1078,12 @@ let {{
''' '''
for reg in range(4): for reg in range(4):
eWalkCode += ''' eWalkCode += '''
srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw); srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
''' % { "reg" : reg } ''' % { "reg" : reg }
if readDest: if readDest:
for reg in range(2): for reg in range(2):
eWalkCode += ''' eWalkCode += '''
destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw); destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
''' % { "reg" : reg } ''' % { "reg" : reg }
readDestCode = '' readDestCode = ''
if readDest: if readDest:
@ -1099,7 +1099,7 @@ let {{
''' % { "op" : op, "readDest" : readDestCode } ''' % { "op" : op, "readDest" : readDestCode }
for reg in range(2): for reg in range(2):
eWalkCode += ''' eWalkCode += '''
FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]); FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
''' % { "reg" : reg } ''' % { "reg" : reg }
iop = InstObjParams(name, Name, iop = InstObjParams(name, Name,
"RegRegImmOp", "RegRegImmOp",
@ -1122,12 +1122,12 @@ let {{
''' '''
for reg in range(2): for reg in range(2):
eWalkCode += ''' eWalkCode += '''
srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw); srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
''' % { "reg" : reg } ''' % { "reg" : reg }
if readDest: if readDest:
for reg in range(4): for reg in range(4):
eWalkCode += ''' eWalkCode += '''
destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw); destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
''' % { "reg" : reg } ''' % { "reg" : reg }
readDestCode = '' readDestCode = ''
if readDest: if readDest:
@ -1143,7 +1143,7 @@ let {{
''' % { "op" : op, "readDest" : readDestCode } ''' % { "op" : op, "readDest" : readDestCode }
for reg in range(4): for reg in range(4):
eWalkCode += ''' eWalkCode += '''
FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]); FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
''' % { "reg" : reg } ''' % { "reg" : reg }
iop = InstObjParams(name, Name, iop = InstObjParams(name, Name,
"RegRegImmOp", "RegRegImmOp",
@ -1165,11 +1165,11 @@ let {{
''' '''
for reg in range(rCount): for reg in range(rCount):
eWalkCode += ''' eWalkCode += '''
srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw); srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
''' % { "reg" : reg } ''' % { "reg" : reg }
if readDest: if readDest:
eWalkCode += ''' eWalkCode += '''
destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw); destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
''' % { "reg" : reg } ''' % { "reg" : reg }
readDestCode = '' readDestCode = ''
if readDest: if readDest:
@ -1186,7 +1186,7 @@ let {{
''' % { "op" : op, "readDest" : readDestCode } ''' % { "op" : op, "readDest" : readDestCode }
for reg in range(rCount): for reg in range(rCount):
eWalkCode += ''' eWalkCode += '''
FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]); FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
''' % { "reg" : reg } ''' % { "reg" : reg }
iop = InstObjParams(name, Name, iop = InstObjParams(name, Name,
"RegRegOp", "RegRegOp",
@ -1208,11 +1208,11 @@ let {{
''' '''
for reg in range(rCount): for reg in range(rCount):
eWalkCode += ''' eWalkCode += '''
srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw); srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
''' % { "reg" : reg } ''' % { "reg" : reg }
if readDest: if readDest:
eWalkCode += ''' eWalkCode += '''
destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw); destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
''' % { "reg" : reg } ''' % { "reg" : reg }
readDestCode = '' readDestCode = ''
if readDest: if readDest:
@ -1228,7 +1228,7 @@ let {{
''' % { "op" : op, "readDest" : readDestCode } ''' % { "op" : op, "readDest" : readDestCode }
for reg in range(rCount): for reg in range(rCount):
eWalkCode += ''' eWalkCode += '''
FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]); FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
''' % { "reg" : reg } ''' % { "reg" : reg }
iop = InstObjParams(name, Name, iop = InstObjParams(name, Name,
"RegRegImmOp", "RegRegImmOp",
@ -1250,8 +1250,8 @@ let {{
''' '''
for reg in range(rCount): for reg in range(rCount):
eWalkCode += ''' eWalkCode += '''
srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw); srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw); destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
''' % { "reg" : reg } ''' % { "reg" : reg }
if readDest: if readDest:
eWalkCode += ''' eWalkCode += '''
@ -1262,8 +1262,8 @@ let {{
eWalkCode += op eWalkCode += op
for reg in range(rCount): for reg in range(rCount):
eWalkCode += ''' eWalkCode += '''
FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]); FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
FpOp1P%(reg)d.uw = gtoh(srcReg1.regs[%(reg)d]); FpOp1P%(reg)d_uw = gtoh(srcReg1.regs[%(reg)d]);
''' % { "reg" : reg } ''' % { "reg" : reg }
iop = InstObjParams(name, Name, iop = InstObjParams(name, Name,
"RegRegOp", "RegRegOp",
@ -1325,7 +1325,7 @@ let {{
for reg in range(rCount): for reg in range(rCount):
if toInt: if toInt:
eWalkCode += ''' eWalkCode += '''
FpDestP%(reg)d.uw = destRegs.regs[%(reg)d]; FpDestP%(reg)d_uw = destRegs.regs[%(reg)d];
''' % { "reg" : reg } ''' % { "reg" : reg }
else: else:
eWalkCode += ''' eWalkCode += '''
@ -1352,11 +1352,11 @@ let {{
''' '''
for reg in range(rCount): for reg in range(rCount):
eWalkCode += ''' eWalkCode += '''
srcRegs.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw); srcRegs.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
''' % { "reg" : reg } ''' % { "reg" : reg }
if readDest: if readDest:
eWalkCode += ''' eWalkCode += '''
destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw); destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
''' % { "reg" : reg } ''' % { "reg" : reg }
readDestCode = '' readDestCode = ''
if readDest: if readDest:
@ -1373,7 +1373,7 @@ let {{
''' % { "op" : op, "readDest" : readDestCode } ''' % { "op" : op, "readDest" : readDestCode }
for reg in range(rCount): for reg in range(rCount):
eWalkCode += ''' eWalkCode += '''
FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]); FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
''' % { "reg" : reg } ''' % { "reg" : reg }
iop = InstObjParams(name, Name, iop = InstObjParams(name, Name,
"RegRegOp", "RegRegOp",
@ -1396,12 +1396,12 @@ let {{
''' '''
for reg in range(4): for reg in range(4):
eWalkCode += ''' eWalkCode += '''
srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw); srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
''' % { "reg" : reg } ''' % { "reg" : reg }
if readDest: if readDest:
for reg in range(2): for reg in range(2):
eWalkCode += ''' eWalkCode += '''
destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw); destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
''' % { "reg" : reg } ''' % { "reg" : reg }
readDestCode = '' readDestCode = ''
if readDest: if readDest:
@ -1417,7 +1417,7 @@ let {{
''' % { "op" : op, "readDest" : readDestCode } ''' % { "op" : op, "readDest" : readDestCode }
for reg in range(2): for reg in range(2):
eWalkCode += ''' eWalkCode += '''
FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]); FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
''' % { "reg" : reg } ''' % { "reg" : reg }
iop = InstObjParams(name, Name, iop = InstObjParams(name, Name,
"RegRegOp", "RegRegOp",
@ -1440,7 +1440,7 @@ let {{
if readDest: if readDest:
for reg in range(rCount): for reg in range(rCount):
eWalkCode += ''' eWalkCode += '''
destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw); destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
''' % { "reg" : reg } ''' % { "reg" : reg }
readDestCode = '' readDestCode = ''
if readDest: if readDest:
@ -1455,7 +1455,7 @@ let {{
''' % { "op" : op, "readDest" : readDestCode } ''' % { "op" : op, "readDest" : readDestCode }
for reg in range(rCount): for reg in range(rCount):
eWalkCode += ''' eWalkCode += '''
FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]); FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
''' % { "reg" : reg } ''' % { "reg" : reg }
iop = InstObjParams(name, Name, iop = InstObjParams(name, Name,
"RegImmOp", "RegImmOp",
@ -1478,12 +1478,12 @@ let {{
''' '''
for reg in range(2): for reg in range(2):
eWalkCode += ''' eWalkCode += '''
srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw); srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
''' % { "reg" : reg } ''' % { "reg" : reg }
if readDest: if readDest:
for reg in range(4): for reg in range(4):
eWalkCode += ''' eWalkCode += '''
destReg.regs[%(reg)d] = htog(FpDestP%(reg)d.uw); destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw);
''' % { "reg" : reg } ''' % { "reg" : reg }
readDestCode = '' readDestCode = ''
if readDest: if readDest:
@ -1499,7 +1499,7 @@ let {{
''' % { "op" : op, "readDest" : readDestCode } ''' % { "op" : op, "readDest" : readDestCode }
for reg in range(4): for reg in range(4):
eWalkCode += ''' eWalkCode += '''
FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]); FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
''' % { "reg" : reg } ''' % { "reg" : reg }
iop = InstObjParams(name, Name, iop = InstObjParams(name, Name,
"RegRegOp", "RegRegOp",
@ -3190,7 +3190,7 @@ let {{
''' '''
for reg in range(rCount): for reg in range(rCount):
eWalkCode += ''' eWalkCode += '''
FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]); FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
''' % { "reg" : reg } ''' % { "reg" : reg }
iop = InstObjParams(name, Name, iop = InstObjParams(name, Name,
"RegRegOp", "RegRegOp",
@ -3270,13 +3270,13 @@ let {{
''' '''
for reg in range(rCount): for reg in range(rCount):
eWalkCode += simdEnabledCheckCode + ''' eWalkCode += simdEnabledCheckCode + '''
srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw); srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);
srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d.uw); srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw);
''' % { "reg" : reg } ''' % { "reg" : reg }
eWalkCode += op eWalkCode += op
for reg in range(rCount): for reg in range(rCount):
eWalkCode += ''' eWalkCode += '''
FpDestP%(reg)d.uw = gtoh(destReg.regs[%(reg)d]); FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]);
''' % { "reg" : reg } ''' % { "reg" : reg }
iop = InstObjParams(name, Name, iop = InstObjParams(name, Name,
"RegRegRegImmOp", "RegRegRegImmOp",
@ -3330,15 +3330,15 @@ let {{
const unsigned length = %(length)d; const unsigned length = %(length)d;
const bool isVtbl = %(isVtbl)s; const bool isVtbl = %(isVtbl)s;
srcReg2.regs[0] = htog(FpOp2P0.uw); srcReg2.regs[0] = htog(FpOp2P0_uw);
srcReg2.regs[1] = htog(FpOp2P1.uw); srcReg2.regs[1] = htog(FpOp2P1_uw);
destReg.regs[0] = htog(FpDestP0.uw); destReg.regs[0] = htog(FpDestP0_uw);
destReg.regs[1] = htog(FpDestP1.uw); destReg.regs[1] = htog(FpDestP1_uw);
''' % { "length" : length, "isVtbl" : isVtbl } ''' % { "length" : length, "isVtbl" : isVtbl }
for reg in range(8): for reg in range(8):
if reg < length * 2: if reg < length * 2:
code += 'table.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw);\n' % \ code += 'table.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);\n' % \
{ "reg" : reg } { "reg" : reg }
else: else:
code += 'table.regs[%(reg)d] = 0;\n' % { "reg" : reg } code += 'table.regs[%(reg)d] = 0;\n' % { "reg" : reg }
@ -3354,8 +3354,8 @@ let {{
} }
} }
FpDestP0.uw = gtoh(destReg.regs[0]); FpDestP0_uw = gtoh(destReg.regs[0]);
FpDestP1.uw = gtoh(destReg.regs[1]); FpDestP1_uw = gtoh(destReg.regs[1]);
''' '''
iop = InstObjParams(name, Name, iop = InstObjParams(name, Name,
"RegRegRegOp", "RegRegRegOp",

16
src/arch/arm/isa/insts/str.isa
View file

@ -110,8 +110,8 @@ let {{
wbDiff = 8 wbDiff = 8
accCode = ''' accCode = '''
CPSR cpsr = Cpsr; CPSR cpsr = Cpsr;
Mem.ud = (uint64_t)cSwap(LR.uw, cpsr.e) | Mem_ud = (uint64_t)cSwap(LR_uw, cpsr.e) |
((uint64_t)cSwap(Spsr.uw, cpsr.e) << 32); ((uint64_t)cSwap(Spsr_uw, cpsr.e) << 32);
''' '''
global header_output, decoder_output, exec_output global header_output, decoder_output, exec_output
@ -198,7 +198,7 @@ let {{
# Code that actually handles the access # Code that actually handles the access
if self.flavor == "fp": if self.flavor == "fp":
accCode = 'Mem%(suffix)s = cSwap(FpDest.uw, ((CPSR)Cpsr).e);' accCode = 'Mem%(suffix)s = cSwap(FpDest_uw, ((CPSR)Cpsr).e);'
else: else:
accCode = \ accCode = \
'Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);' 'Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);'
@ -273,15 +273,15 @@ let {{
# Code that actually handles the access # Code that actually handles the access
if self.flavor == "fp": if self.flavor == "fp":
accCode = ''' accCode = '''
uint64_t swappedMem = (uint64_t)FpDest.uw | uint64_t swappedMem = (uint64_t)FpDest_uw |
((uint64_t)FpDest2.uw << 32); ((uint64_t)FpDest2_uw << 32);
Mem.ud = cSwap(swappedMem, ((CPSR)Cpsr).e); Mem_ud = cSwap(swappedMem, ((CPSR)Cpsr).e);
''' '''
else: else:
accCode = ''' accCode = '''
CPSR cpsr = Cpsr; CPSR cpsr = Cpsr;
Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) | Mem_ud = (uint64_t)cSwap(Dest_uw, cpsr.e) |
((uint64_t)cSwap(Dest2.uw, cpsr.e) << 32); ((uint64_t)cSwap(Dest2_uw, cpsr.e) << 32);
''' '''
self.codeBlobs["memacc_code"] = accCode self.codeBlobs["memacc_code"] = accCode

6
src/arch/arm/isa/insts/swap.isa
View file

@ -82,7 +82,7 @@ let {{
''' '''
SwapInst('swp', 'Swp', 'EA = Base;', SwapInst('swp', 'Swp', 'EA = Base;',
swpPreAccCode + 'Mem = cSwap(Op1.uw, ((CPSR)Cpsr).e);', swpPreAccCode + 'Mem = cSwap(Op1_uw, ((CPSR)Cpsr).e);',
'Dest = cSwap((uint32_t)memData, ((CPSR)Cpsr).e);', 'Dest = cSwap((uint32_t)memData, ((CPSR)Cpsr).e);',
['Request::MEM_SWAP', ['Request::MEM_SWAP',
'ArmISA::TLB::AlignWord', 'ArmISA::TLB::AlignWord',
@ -90,8 +90,8 @@ let {{
['IsStoreConditional']).emit() ['IsStoreConditional']).emit()
SwapInst('swpb', 'Swpb', 'EA = Base;', SwapInst('swpb', 'Swpb', 'EA = Base;',
swpPreAccCode + 'Mem.ub = cSwap(Op1.ub, ((CPSR)Cpsr).e);', swpPreAccCode + 'Mem_ub = cSwap(Op1_ub, ((CPSR)Cpsr).e);',
'Dest.ub = cSwap((uint8_t)memData, ((CPSR)Cpsr).e);', 'Dest_ub = cSwap((uint8_t)memData, ((CPSR)Cpsr).e);',
['Request::MEM_SWAP', ['Request::MEM_SWAP',
'ArmISA::TLB::AlignByte', 'ArmISA::TLB::AlignByte',
'ArmISA::TLB::MustBeOne'], 'ArmISA::TLB::MustBeOne'],

16
src/arch/isa_parser.py
View file

@ -1851,21 +1851,21 @@ StaticInstPtr
# Define operand variables. # Define operand variables.
operands = user_dict.keys() operands = user_dict.keys()
extensions = self.operandTypeMap.keys()
operandsREString = (r''' operandsREString = r'''
(?<![\w\.]) # neg. lookbehind assertion: prevent partial matches (?<!\w) # neg. lookbehind assertion: prevent partial matches
((%s)(?:\.(\w+))?) # match: operand with optional '.' then suffix ((%s)(?:_(%s))?) # match: operand with optional '_' then suffix
(?![\w\.]) # neg. lookahead assertion: prevent partial matches (?!\w) # neg. lookahead assertion: prevent partial matches
''' ''' % (string.join(operands, '|'), string.join(extensions, '|'))
% string.join(operands, '|'))
self.operandsRE = re.compile(operandsREString, re.MULTILINE|re.VERBOSE) self.operandsRE = re.compile(operandsREString, re.MULTILINE|re.VERBOSE)
# Same as operandsREString, but extension is mandatory, and only two # Same as operandsREString, but extension is mandatory, and only two
# groups are returned (base and ext, not full name as above). # groups are returned (base and ext, not full name as above).
# Used for subtituting '_' for '.' to make C++ identifiers. # Used for subtituting '_' for '.' to make C++ identifiers.
operandsWithExtREString = (r'(?<![\w\.])(%s)\.(\w+)(?![\w\.])' operandsWithExtREString = r'(?<!\w)(%s)_(%s)(?!\w)' \
% string.join(operands, '|')) % (string.join(operands, '|'), string.join(extensions, '|'))
self.operandsWithExtRE = \ self.operandsWithExtRE = \
re.compile(operandsWithExtREString, re.MULTILINE) re.compile(operandsWithExtREString, re.MULTILINE)

844
src/arch/mips/isa/decoder.isa
View file

File diff suppressed because it is too large Load diff

36
src/arch/mips/isa/formats/fp.isa
View file

@ -217,20 +217,20 @@ def format FloatCompareOp(cond_code, *flags) {{
import sys import sys
code = 'bool cond;\n' code = 'bool cond;\n'
if '.sf' in cond_code or 'SinglePrecision' in flags: if '_sf' in cond_code or 'SinglePrecision' in flags:
if 'QnanException' in flags: if 'QnanException' in flags:
code += 'if (isQnan(&Fs.sf, 32) || isQnan(&Ft.sf, 32)) {\n' code += 'if (isQnan(&Fs_sf, 32) || isQnan(&Ft_sf, 32)) {\n'
code += '\tFCSR = genInvalidVector(FCSR);\n' code += '\tFCSR = genInvalidVector(FCSR);\n'
code += '\treturn NoFault;' code += '\treturn NoFault;'
code += '}\n else ' code += '}\n else '
code += 'if (isNan(&Fs.sf, 32) || isNan(&Ft.sf, 32)) {\n' code += 'if (isNan(&Fs_sf, 32) || isNan(&Ft_sf, 32)) {\n'
elif '.df' in cond_code or 'DoublePrecision' in flags: elif '_df' in cond_code or 'DoublePrecision' in flags:
if 'QnanException' in flags: if 'QnanException' in flags:
code += 'if (isQnan(&Fs.df, 64) || isQnan(&Ft.df, 64)) {\n' code += 'if (isQnan(&Fs_df, 64) || isQnan(&Ft_df, 64)) {\n'
code += '\tFCSR = genInvalidVector(FCSR);\n' code += '\tFCSR = genInvalidVector(FCSR);\n'
code += '\treturn NoFault;' code += '\treturn NoFault;'
code += '}\n else ' code += '}\n else '
code += 'if (isNan(&Fs.df, 64) || isNan(&Ft.df, 64)) {\n' code += 'if (isNan(&Fs_df, 64) || isNan(&Ft_df, 64)) {\n'
else: else:
sys.exit('Decoder Failed: Can\'t Determine Operand Type\n') sys.exit('Decoder Failed: Can\'t Determine Operand Type\n')
@ -257,16 +257,16 @@ def format FloatConvertOp(code, *flags) {{
#Determine Source Type #Determine Source Type
convert = 'fpConvert(' convert = 'fpConvert('
if '.sf' in code: if '_sf' in code:
code = 'float ' + code + '\n' code = 'float ' + code + '\n'
convert += 'SINGLE_TO_' convert += 'SINGLE_TO_'
elif '.df' in code: elif '_df' in code:
code = 'double ' + code + '\n' code = 'double ' + code + '\n'
convert += 'DOUBLE_TO_' convert += 'DOUBLE_TO_'
elif '.uw' in code: elif '_uw' in code:
code = 'uint32_t ' + code + '\n' code = 'uint32_t ' + code + '\n'
convert += 'WORD_TO_' convert += 'WORD_TO_'
elif '.ud' in code: elif '_ud' in code:
code = 'uint64_t ' + code + '\n' code = 'uint64_t ' + code + '\n'
convert += 'LONG_TO_' convert += 'LONG_TO_'
else: else:
@ -274,13 +274,13 @@ def format FloatConvertOp(code, *flags) {{
#Determine Destination Type #Determine Destination Type
if 'ToSingle' in flags: if 'ToSingle' in flags:
code += 'Fd.uw = ' + convert + 'SINGLE, ' code += 'Fd_uw = ' + convert + 'SINGLE, '
elif 'ToDouble' in flags: elif 'ToDouble' in flags:
code += 'Fd.ud = ' + convert + 'DOUBLE, ' code += 'Fd_ud = ' + convert + 'DOUBLE, '
elif 'ToWord' in flags: elif 'ToWord' in flags:
code += 'Fd.uw = ' + convert + 'WORD, ' code += 'Fd_uw = ' + convert + 'WORD, '
elif 'ToLong' in flags: elif 'ToLong' in flags:
code += 'Fd.ud = ' + convert + 'LONG, ' code += 'Fd_ud = ' + convert + 'LONG, '
else: else:
sys.exit("Error Determining Destination Type for Conversion") sys.exit("Error Determining Destination Type for Conversion")
@ -328,17 +328,17 @@ def format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{
code += 'code_block1 = code_block2 = true;\n' code += 'code_block1 = code_block2 = true;\n'
if 'QnanException' in flags: if 'QnanException' in flags:
code += 'if (isQnan(&Fs1.sf, 32) || isQnan(&Ft1.sf, 32)) {\n' code += 'if (isQnan(&Fs1_sf, 32) || isQnan(&Ft1_sf, 32)) {\n'
code += '\tFCSR = genInvalidVector(FCSR);\n' code += '\tFCSR = genInvalidVector(FCSR);\n'
code += 'code_block1 = false;' code += 'code_block1 = false;'
code += '}\n' code += '}\n'
code += 'if (isQnan(&Fs2.sf, 32) || isQnan(&Ft2.sf, 32)) {\n' code += 'if (isQnan(&Fs2_sf, 32) || isQnan(&Ft2_sf, 32)) {\n'
code += '\tFCSR = genInvalidVector(FCSR);\n' code += '\tFCSR = genInvalidVector(FCSR);\n'
code += 'code_block2 = false;' code += 'code_block2 = false;'
code += '}\n' code += '}\n'
code += 'if (code_block1) {' code += 'if (code_block1) {'
code += '\tif (isNan(&Fs1.sf, 32) || isNan(&Ft1.sf, 32)) {\n' code += '\tif (isNan(&Fs1_sf, 32) || isNan(&Ft1_sf, 32)) {\n'
if 'UnorderedTrue' in flags: if 'UnorderedTrue' in flags:
code += 'cond1 = 1;\n' code += 'cond1 = 1;\n'
elif 'UnorderedFalse' in flags: elif 'UnorderedFalse' in flags:
@ -350,7 +350,7 @@ def format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{
code += 'FCSR = genCCVector(FCSR, CC, cond1);}\n}\n' code += 'FCSR = genCCVector(FCSR, CC, cond1);}\n}\n'
code += 'if (code_block2) {' code += 'if (code_block2) {'
code += '\tif (isNan(&Fs2.sf, 32) || isNan(&Ft2.sf, 32)) {\n' code += '\tif (isNan(&Fs2_sf, 32) || isNan(&Ft2_sf, 32)) {\n'
if 'UnorderedTrue' in flags: if 'UnorderedTrue' in flags:
code += 'cond2 = 1;\n' code += 'cond2 = 1;\n'
elif 'UnorderedFalse' in flags: elif 'UnorderedFalse' in flags:

4
src/arch/mips/isa/formats/int.isa
View file

@ -357,9 +357,9 @@ def format HiLoRdSelOp(code, *opt_flags) {{
def format HiLoRdSelValOp(code, *opt_flags) {{ def format HiLoRdSelValOp(code, *opt_flags) {{
if '.sd' in code: if '_sd' in code:
code = 'int64_t ' + code code = 'int64_t ' + code
elif '.ud' in code: elif '_ud' in code:
code = 'uint64_t ' + code code = 'uint64_t ' + code
code += 'HI_RD_SEL = val<63:32>;\n' code += 'HI_RD_SEL = val<63:32>;\n'

2
src/arch/mips/isa/formats/mem.isa
View file

@ -543,7 +543,7 @@ def format StoreFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
mem_flags = [], inst_flags = []) {{ mem_flags = [], inst_flags = []) {{
decl_code = ''' decl_code = '''
uint32_t mem_word = Mem.uw; uint32_t mem_word = Mem_uw;
uint32_t unalign_addr = Rs + disp; uint32_t unalign_addr = Rs + disp;
uint32_t byte_offset = unalign_addr & 3; uint32_t byte_offset = unalign_addr & 3;
if (GuestByteOrder == BigEndianByteOrder) if (GuestByteOrder == BigEndianByteOrder)

136
src/arch/power/isa/decoder.isa
View file

@ -46,7 +46,7 @@ decode OPCODE default Unknown::unknown() {
}}); }});
11: cmpi({{ 11: cmpi({{
Xer xer = XER; Xer xer = XER;
uint32_t cr = makeCRField(Ra.sw, (int32_t)imm, xer.so); uint32_t cr = makeCRField(Ra_sw, (int32_t)imm, xer.so);
CR = insertCRField(CR, BF, cr); CR = insertCRField(CR, BF, cr);
}}); }});
} }
@ -88,15 +88,15 @@ decode OPCODE default Unknown::unknown() {
// Arithmetic instructions all use source registers Ra and Rb, // Arithmetic instructions all use source registers Ra and Rb,
// with destination register Rt. // with destination register Rt.
format IntArithOp { format IntArithOp {
75: mulhw({{ int64_t prod = Ra.sq * Rb.sq; Rt = prod >> 32; }}); 75: mulhw({{ int64_t prod = Ra_sq * Rb_sq; Rt = prod >> 32; }});
11: mulhwu({{ uint64_t prod = Ra.uq * Rb.uq; Rt = prod >> 32; }}); 11: mulhwu({{ uint64_t prod = Ra_uq * Rb_uq; Rt = prod >> 32; }});
235: mullw({{ int64_t prod = Ra.sq * Rb.sq; Rt = prod; }}); 235: mullw({{ int64_t prod = Ra_sq * Rb_sq; Rt = prod; }});
747: mullwo({{ int64_t src1 = Ra.sq; int64_t src2 = Rb; int64_t prod = src1 * src2; Rt = prod; }}, 747: mullwo({{ int64_t src1 = Ra_sq; int64_t src2 = Rb; int64_t prod = src1 * src2; Rt = prod; }},
true); true);
491: divw({{ 491: divw({{
int32_t src1 = Ra.sw; int32_t src1 = Ra_sw;
int32_t src2 = Rb.sw; int32_t src2 = Rb_sw;
if ((src1 != 0x80000000 || src2 != 0xffffffff) if ((src1 != 0x80000000 || src2 != 0xffffffff)
&& src2 != 0) { && src2 != 0) {
Rt = src1 / src2; Rt = src1 / src2;
@ -106,8 +106,8 @@ decode OPCODE default Unknown::unknown() {
}}); }});
1003: divwo({{ 1003: divwo({{
int32_t src1 = Ra.sw; int32_t src1 = Ra_sw;
int32_t src2 = Rb.sw; int32_t src2 = Rb_sw;
if ((src1 != 0x80000000 || src2 != 0xffffffff) if ((src1 != 0x80000000 || src2 != 0xffffffff)
&& src2 != 0) { && src2 != 0) {
Rt = src1 / src2; Rt = src1 / src2;
@ -119,8 +119,8 @@ decode OPCODE default Unknown::unknown() {
true); true);
459: divwu({{ 459: divwu({{
uint32_t src1 = Ra.sw; uint32_t src1 = Ra_sw;
uint32_t src2 = Rb.sw; uint32_t src2 = Rb_sw;
if (src2 != 0) { if (src2 != 0) {
Rt = src1 / src2; Rt = src1 / src2;
} else { } else {
@ -129,8 +129,8 @@ decode OPCODE default Unknown::unknown() {
}}); }});
971: divwuo({{ 971: divwuo({{
uint32_t src1 = Ra.sw; uint32_t src1 = Ra_sw;
uint32_t src2 = Rb.sw; uint32_t src2 = Rb_sw;
if (src2 != 0) { if (src2 != 0) {
Rt = src1 / src2; Rt = src1 / src2;
} else { } else {
@ -247,7 +247,7 @@ decode OPCODE default Unknown::unknown() {
format IntOp { format IntOp {
0: cmp({{ 0: cmp({{
Xer xer = XER; Xer xer = XER;
uint32_t cr = makeCRField(Ra.sw, Rb.sw, xer.so); uint32_t cr = makeCRField(Ra_sw, Rb_sw, xer.so);
CR = insertCRField(CR, BF, cr); CR = insertCRField(CR, BF, cr);
}}); }});
32: cmpl({{ 32: cmpl({{
@ -282,30 +282,30 @@ decode OPCODE default Unknown::unknown() {
// R0. Others update Ra with the effective address. In all cases, // R0. Others update Ra with the effective address. In all cases,
// Ra and Rb are source registers, Rt is the destintation. // Ra and Rb are source registers, Rt is the destintation.
format LoadIndexOp { format LoadIndexOp {
87: lbzx({{ Rt = Mem.ub; }}); 87: lbzx({{ Rt = Mem_ub; }});
279: lhzx({{ Rt = Mem.uh; }}); 279: lhzx({{ Rt = Mem_uh; }});
343: lhax({{ Rt = Mem.sh; }}); 343: lhax({{ Rt = Mem_sh; }});
23: lwzx({{ Rt = Mem; }}); 23: lwzx({{ Rt = Mem; }});
341: lwax({{ Rt = Mem.sw; }}); 341: lwax({{ Rt = Mem_sw; }});
20: lwarx({{ Rt = Mem.sw; Rsv = 1; RsvLen = 4; RsvAddr = EA; }}); 20: lwarx({{ Rt = Mem_sw; Rsv = 1; RsvLen = 4; RsvAddr = EA; }});
535: lfsx({{ Ft.sf = Mem.sf; }}); 535: lfsx({{ Ft_sf = Mem_sf; }});
599: lfdx({{ Ft = Mem.df; }}); 599: lfdx({{ Ft = Mem_df; }});
855: lfiwax({{ Ft.uw = Mem; }}); 855: lfiwax({{ Ft_uw = Mem; }});
} }
format LoadIndexUpdateOp { format LoadIndexUpdateOp {
119: lbzux({{ Rt = Mem.ub; }}); 119: lbzux({{ Rt = Mem_ub; }});
311: lhzux({{ Rt = Mem.uh; }}); 311: lhzux({{ Rt = Mem_uh; }});
375: lhaux({{ Rt = Mem.sh; }}); 375: lhaux({{ Rt = Mem_sh; }});
55: lwzux({{ Rt = Mem; }}); 55: lwzux({{ Rt = Mem; }});
373: lwaux({{ Rt = Mem.sw; }}); 373: lwaux({{ Rt = Mem_sw; }});
567: lfsux({{ Ft.sf = Mem.sf; }}); 567: lfsux({{ Ft_sf = Mem_sf; }});
631: lfdux({{ Ft = Mem.df; }}); 631: lfdux({{ Ft = Mem_df; }});
} }
format StoreIndexOp { format StoreIndexOp {
215: stbx({{ Mem.ub = Rs.ub; }}); 215: stbx({{ Mem_ub = Rs_ub; }});
407: sthx({{ Mem.uh = Rs.uh; }}); 407: sthx({{ Mem_uh = Rs_uh; }});
151: stwx({{ Mem = Rs; }}); 151: stwx({{ Mem = Rs; }});
150: stwcx({{ 150: stwcx({{
bool store_performed = false; bool store_performed = false;
@ -323,17 +323,17 @@ decode OPCODE default Unknown::unknown() {
CR = cr; CR = cr;
Rsv = 0; Rsv = 0;
}}); }});
663: stfsx({{ Mem.sf = Fs.sf; }}); 663: stfsx({{ Mem_sf = Fs_sf; }});
727: stfdx({{ Mem.df = Fs; }}); 727: stfdx({{ Mem_df = Fs; }});
983: stfiwx({{ Mem = Fs.uw; }}); 983: stfiwx({{ Mem = Fs_uw; }});
} }
format StoreIndexUpdateOp { format StoreIndexUpdateOp {
247: stbux({{ Mem.ub = Rs.ub; }}); 247: stbux({{ Mem_ub = Rs_ub; }});
439: sthux({{ Mem.uh = Rs.uh; }}); 439: sthux({{ Mem_uh = Rs_uh; }});
183: stwux({{ Mem = Rs; }}); 183: stwux({{ Mem = Rs; }});
695: stfsux({{ Mem.sf = Fs.sf; }}); 695: stfsux({{ Mem_sf = Fs_sf; }});
759: stfdux({{ Mem.df = Fs; }}); 759: stfdux({{ Mem_df = Fs; }});
} }
// These instructions all provide data cache hints // These instructions all provide data cache hints
@ -360,7 +360,7 @@ decode OPCODE default Unknown::unknown() {
8: subfic({{ int32_t src = ~Ra; Rt = src + imm + 1; }}, 8: subfic({{ int32_t src = ~Ra; Rt = src + imm + 1; }},
[computeCA]); [computeCA]);
7: mulli({{ 7: mulli({{
int32_t src = Ra.sw; int32_t src = Ra_sw;
int64_t prod = src * imm; int64_t prod = src * imm;
Rt = (uint32_t)prod; Rt = (uint32_t)prod;
}}); }});
@ -476,40 +476,40 @@ decode OPCODE default Unknown::unknown() {
} }
format LoadDispOp { format LoadDispOp {
34: lbz({{ Rt = Mem.ub; }}); 34: lbz({{ Rt = Mem_ub; }});
40: lhz({{ Rt = Mem.uh; }}); 40: lhz({{ Rt = Mem_uh; }});
42: lha({{ Rt = Mem.sh; }}); 42: lha({{ Rt = Mem_sh; }});
32: lwz({{ Rt = Mem; }}); 32: lwz({{ Rt = Mem; }});
58: lwa({{ Rt = Mem.sw; }}, 58: lwa({{ Rt = Mem_sw; }},
{{ EA = Ra + (disp & 0xfffffffc); }}, {{ EA = Ra + (disp & 0xfffffffc); }},
{{ EA = disp & 0xfffffffc; }}); {{ EA = disp & 0xfffffffc; }});
48: lfs({{ Ft.sf = Mem.sf; }}); 48: lfs({{ Ft_sf = Mem_sf; }});
50: lfd({{ Ft = Mem.df; }}); 50: lfd({{ Ft = Mem_df; }});
} }
format LoadDispUpdateOp { format LoadDispUpdateOp {
35: lbzu({{ Rt = Mem.ub; }}); 35: lbzu({{ Rt = Mem_ub; }});
41: lhzu({{ Rt = Mem.uh; }}); 41: lhzu({{ Rt = Mem_uh; }});
43: lhau({{ Rt = Mem.sh; }}); 43: lhau({{ Rt = Mem_sh; }});
33: lwzu({{ Rt = Mem; }}); 33: lwzu({{ Rt = Mem; }});
49: lfsu({{ Ft.sf = Mem.sf; }}); 49: lfsu({{ Ft_sf = Mem_sf; }});
51: lfdu({{ Ft = Mem.df; }}); 51: lfdu({{ Ft = Mem_df; }});
} }
format StoreDispOp { format StoreDispOp {
38: stb({{ Mem.ub = Rs.ub; }}); 38: stb({{ Mem_ub = Rs_ub; }});
44: sth({{ Mem.uh = Rs.uh; }}); 44: sth({{ Mem_uh = Rs_uh; }});
36: stw({{ Mem = Rs; }}); 36: stw({{ Mem = Rs; }});
52: stfs({{ Mem.sf = Fs.sf; }}); 52: stfs({{ Mem_sf = Fs_sf; }});
54: stfd({{ Mem.df = Fs; }}); 54: stfd({{ Mem_df = Fs; }});
} }
format StoreDispUpdateOp { format StoreDispUpdateOp {
39: stbu({{ Mem.ub = Rs.ub; }}); 39: stbu({{ Mem_ub = Rs_ub; }});
45: sthu({{ Mem.uh = Rs.uh; }}); 45: sthu({{ Mem_uh = Rs_uh; }});
37: stwu({{ Mem = Rs; }}); 37: stwu({{ Mem = Rs; }});
53: stfsu({{ Mem.sf = Fs.sf; }}); 53: stfsu({{ Mem_sf = Fs_sf; }});
55: stfdu({{ Mem.df = Fs; }}); 55: stfdu({{ Mem_df = Fs; }});
} }
17: IntOp::sc({{ xc->syscall(R0); }}, 17: IntOp::sc({{ xc->syscall(R0); }},
@ -542,8 +542,8 @@ decode OPCODE default Unknown::unknown() {
default: decode XO_XO { default: decode XO_XO {
format FloatConvertOp { format FloatConvertOp {
12: frsp({{ Ft.sf = Fb; }}); 12: frsp({{ Ft_sf = Fb; }});
15: fctiwz({{ Ft.sw = (int32_t)trunc(Fb); }}); 15: fctiwz({{ Ft_sw = (int32_t)trunc(Fb); }});
} }
format FloatOp { format FloatOp {
@ -559,28 +559,28 @@ decode OPCODE default Unknown::unknown() {
format FloatRCCheckOp { format FloatRCCheckOp {
72: fmr({{ Ft = Fb; }}); 72: fmr({{ Ft = Fb; }});
264: fabs({{ 264: fabs({{
Ft.uq = Fb.uq; Ft_uq = Fb_uq;
Ft.uq = insertBits(Ft.uq, 63, 0); }}); Ft_uq = insertBits(Ft_uq, 63, 0); }});
136: fnabs({{ 136: fnabs({{
Ft.uq = Fb.uq; Ft_uq = Fb_uq;
Ft.uq = insertBits(Ft.uq, 63, 1); }}); Ft_uq = insertBits(Ft_uq, 63, 1); }});
40: fneg({{ Ft = -Fb; }}); 40: fneg({{ Ft = -Fb; }});
8: fcpsgn({{ 8: fcpsgn({{
Ft.uq = Fb.uq; Ft_uq = Fb_uq;
Ft.uq = insertBits(Ft.uq, 63, Fa.uq<63:63>); Ft_uq = insertBits(Ft_uq, 63, Fa_uq<63:63>);
}}); }});
583: mffs({{ Ft.uq = FPSCR; }}); 583: mffs({{ Ft_uq = FPSCR; }});
134: mtfsfi({{ 134: mtfsfi({{
FPSCR = insertCRField(FPSCR, BF + (8 * (1 - W)), U_FIELD); FPSCR = insertCRField(FPSCR, BF + (8 * (1 - W)), U_FIELD);
}}); }});
711: mtfsf({{ 711: mtfsf({{
if (L == 1) { FPSCR = Fb.uq; } if (L == 1) { FPSCR = Fb_uq; }
else { else {
for (int i = 0; i < 8; ++i) { for (int i = 0; i < 8; ++i) {
if (bits(FLM, i) == 1) { if (bits(FLM, i) == 1) {
int k = 4 * (i + (8 * (1 - W))); int k = 4 * (i + (8 * (1 - W)));
FPSCR = insertBits(FPSCR, k, k + 3, FPSCR = insertBits(FPSCR, k, k + 3,
bits(Fb.uq, k, k + 3)); bits(Fb_uq, k, k + 3));
} }
} }
} }

4
src/arch/power/isa/formats/fp.isa
View file

@ -84,7 +84,7 @@ def format FloatRCCheckOp(code, inst_flags = []) {{
// Floating point elementary arithmetic operations. Besides having two // Floating point elementary arithmetic operations. Besides having two
// versions of each instruction for when Rc is set or not, we also have // versions of each instruction for when Rc is set or not, we also have
// to alter lots of special registers depending on the result of the // to alter lots of special registers depending on the result of the
// operation. The result is always in Ft.sf. // operation. The result is always in Ft_sf.
def format FloatArithOp(code, inst_flags = []) {{ def format FloatArithOp(code, inst_flags = []) {{
# Code when Rc is set # Code when Rc is set
@ -109,7 +109,7 @@ def format FloatArithOp(code, inst_flags = []) {{
// Floating point rounding and conversion operations. Besides having two // Floating point rounding and conversion operations. Besides having two
// versions of each instruction for when Rc is set or not, we also have // versions of each instruction for when Rc is set or not, we also have
// to alter lots of special registers depending on the result of the // to alter lots of special registers depending on the result of the
// operation. The result is always in Ft.sf. // operation. The result is always in Ft_sf.
def format FloatConvertOp(code, inst_flags = []) {{ def format FloatConvertOp(code, inst_flags = []) {{
# Code when Rc is set # Code when Rc is set

8
src/arch/sparc/isa/base.isa
View file

@ -181,9 +181,9 @@ let {{
for opName in ("Frd", "Frs1", "Frs2", "Frd_N"): for opName in ("Frd", "Frs1", "Frs2", "Frd_N"):
next_pos = 0 next_pos = 0
operandsREString = (r''' operandsREString = (r'''
(?<![\w\.]) # neg. lookbehind assertion: prevent partial matches (?<!\w) # neg. lookbehind assertion: prevent partial matches
((%s)(?:\.(\w+))?) # match: operand with optional '.' then suffix ((%s)(?:_([^\W_]+))?) # match: operand with optional '.' then suffix
(?![\w\.]) # neg. lookahead assertion: prevent partial matches (?!\w) # neg. lookahead assertion: prevent partial matches
''' % opName) ''' % opName)
operandsRE = re.compile(operandsREString, re.MULTILINE|re.VERBOSE) operandsRE = re.compile(operandsREString, re.MULTILINE|re.VERBOSE)
is_src = False is_src = False
@ -229,7 +229,7 @@ let {{
let {{ let {{
def splitOutImm(code): def splitOutImm(code):
matcher = re.compile(r'Rs(?P<rNum>\d)_or_imm(?P<iNum>\d+)(?P<typeQual>\.\w+)?') matcher = re.compile(r'Rs(?P<rNum>\d)_or_imm(?P<iNum>\d+)(?P<typeQual>_[^\W_]+)?')
rOrImmMatch = matcher.search(code) rOrImmMatch = matcher.search(code)
if (rOrImmMatch == None): if (rOrImmMatch == None):
return (False, code, '', '', '') return (False, code, '', '', '')

362
src/arch/sparc/isa/decoder.isa
View file

@ -82,16 +82,16 @@ decode OP default Unknown::unknown()
{ {
format BranchSplit format BranchSplit
{ {
0x1: bpreq(test={{Rs1.sdw == 0}}); 0x1: bpreq(test={{Rs1_sdw == 0}});
0x2: bprle(test={{Rs1.sdw <= 0}}); 0x2: bprle(test={{Rs1_sdw <= 0}});
0x3: bprl(test={{Rs1.sdw < 0}}); 0x3: bprl(test={{Rs1_sdw < 0}});
0x5: bprne(test={{Rs1.sdw != 0}}); 0x5: bprne(test={{Rs1_sdw != 0}});
0x6: bprg(test={{Rs1.sdw > 0}}); 0x6: bprg(test={{Rs1_sdw > 0}});
0x7: bprge(test={{Rs1.sdw >= 0}}); 0x7: bprge(test={{Rs1_sdw >= 0}});
} }
} }
// SETHI (or NOP if rd == 0 and imm == 0) // SETHI (or NOP if rd == 0 and imm == 0)
0x4: SetHi::sethi({{Rd.udw = imm;}}); 0x4: SetHi::sethi({{Rd_udw = imm;}});
// fbpfcc // fbpfcc
0x5: decode COND2 { 0x5: decode COND2 {
format BranchN { format BranchN {
@ -144,52 +144,52 @@ decode OP default Unknown::unknown()
}},None, None, IsIndirectControl, IsCall); }},None, None, IsIndirectControl, IsCall);
0x2: decode OP3 { 0x2: decode OP3 {
format IntOp { format IntOp {
0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); 0x00: add({{Rd = Rs1_sdw + Rs2_or_imm13;}});
0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}}); 0x01: and({{Rd = Rs1_sdw & Rs2_or_imm13;}});
0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}}); 0x02: or({{Rd = Rs1_sdw | Rs2_or_imm13;}});
0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}}); 0x03: xor({{Rd = Rs1_sdw ^ Rs2_or_imm13;}});
0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}}); 0x04: sub({{Rd = Rs1_sdw - Rs2_or_imm13;}});
0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}}); 0x05: andn({{Rd = Rs1_sdw & ~Rs2_or_imm13;}});
0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}}); 0x06: orn({{Rd = Rs1_sdw | ~Rs2_or_imm13;}});
0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}}); 0x07: xnor({{Rd = ~(Rs1_sdw ^ Rs2_or_imm13);}});
0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}}); 0x08: addc({{Rd = Rs1_sdw + Rs2_or_imm13 + Ccr<0:0>;}});
0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}}); 0x09: mulx({{Rd = Rs1_sdw * Rs2_or_imm13;}});
0x0A: umul({{ 0x0A: umul({{
Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; Rd = Rs1_udw<31:0> * Rs2_or_imm13<31:0>;
Y = Rd<63:32>; Y = Rd<63:32>;
}}); }});
0x0B: smul({{ 0x0B: smul({{
Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); Rd_sdw = sext<32>(Rs1_sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>);
Y = Rd.sdw<63:32>; Y = Rd_sdw<63:32>;
}}); }});
0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); 0x0C: subc({{Rd_sdw = Rs1_sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
0x0D: udivx({{ 0x0D: udivx({{
if (Rs2_or_imm13 == 0) if (Rs2_or_imm13 == 0)
fault = new DivisionByZero; fault = new DivisionByZero;
else else
Rd.udw = Rs1.udw / Rs2_or_imm13; Rd_udw = Rs1_udw / Rs2_or_imm13;
}}); }});
0x0E: udiv({{ 0x0E: udiv({{
if (Rs2_or_imm13 == 0) { if (Rs2_or_imm13 == 0) {
fault = new DivisionByZero; fault = new DivisionByZero;
} else { } else {
Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; Rd_udw = ((Y << 32) | Rs1_udw<31:0>) / Rs2_or_imm13;
if (Rd.udw >> 32 != 0) if (Rd_udw >> 32 != 0)
Rd.udw = 0xFFFFFFFF; Rd_udw = 0xFFFFFFFF;
} }
}}); }});
0x0F: sdiv({{ 0x0F: sdiv({{
if (Rs2_or_imm13.sdw == 0) { if (Rs2_or_imm13_sdw == 0) {
fault = new DivisionByZero; fault = new DivisionByZero;
} else { } else {
Rd.udw = ((int64_t)((Y << 32) | Rd_udw = ((int64_t)((Y << 32) |
Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; Rs1_sdw<31:0>)) / Rs2_or_imm13_sdw;
if ((int64_t)Rd.udw >= if ((int64_t)Rd_udw >=
std::numeric_limits<int32_t>::max()) { std::numeric_limits<int32_t>::max()) {
Rd.udw = 0x7FFFFFFF; Rd_udw = 0x7FFFFFFF;
} else if ((int64_t)Rd.udw <= } else if ((int64_t)Rd_udw <=
std::numeric_limits<int32_t>::min()) { std::numeric_limits<int32_t>::min()) {
Rd.udw = ULL(0xFFFFFFFF80000000); Rd_udw = ULL(0xFFFFFFFF80000000);
} }
} }
}}); }});
@ -215,29 +215,29 @@ decode OP default Unknown::unknown()
}}); }});
0x1A: IntOpCcRes::umulcc({{ 0x1A: IntOpCcRes::umulcc({{
uint64_t resTemp; uint64_t resTemp;
Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>; Rd = resTemp = Rs1_udw<31:0> * Rs2_or_imm13_udw<31:0>;
Y = resTemp<63:32>;}}); Y = resTemp<63:32>;}});
0x1B: IntOpCcRes::smulcc({{ 0x1B: IntOpCcRes::smulcc({{
int64_t resTemp; int64_t resTemp;
Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); Rd = resTemp = sext<32>(Rs1_sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>);
Y = resTemp<63:32>;}}); Y = resTemp<63:32>;}});
0x1C: subccc({{ 0x1C: subccc({{
int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; int64_t res, op1 = Rs1, op2 = Rs2_or_imm13;
Rd = res = op1 - op2 - Ccr<0:>; Rd = res = op1 - op2 - Ccr<0:>;
}}, sub=True); }}, sub=True);
0x1D: IntOpCcRes::udivxcc({{ 0x1D: IntOpCcRes::udivxcc({{
if (Rs2_or_imm13.udw == 0) if (Rs2_or_imm13_udw == 0)
fault = new DivisionByZero; fault = new DivisionByZero;
else else
Rd = Rs1.udw / Rs2_or_imm13.udw;}}); Rd = Rs1_udw / Rs2_or_imm13_udw;}});
0x1E: IntOpCcRes::udivcc({{ 0x1E: IntOpCcRes::udivcc({{
uint64_t resTemp; uint64_t resTemp;
uint32_t val2 = Rs2_or_imm13.udw; uint32_t val2 = Rs2_or_imm13_udw;
int32_t overflow = 0; int32_t overflow = 0;
if (val2 == 0) { if (val2 == 0) {
fault = new DivisionByZero; fault = new DivisionByZero;
} else { } else {
resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2; resTemp = (uint64_t)((Y << 32) | Rs1_udw<31:0>) / val2;
overflow = (resTemp<63:32> != 0); overflow = (resTemp<63:32> != 0);
if (overflow) if (overflow)
Rd = resTemp = 0xFFFFFFFF; Rd = resTemp = 0xFFFFFFFF;
@ -246,12 +246,12 @@ decode OP default Unknown::unknown()
} }
}}, iv={{overflow}}); }}, iv={{overflow}});
0x1F: IntOpCcRes::sdivcc({{ 0x1F: IntOpCcRes::sdivcc({{
int64_t val2 = Rs2_or_imm13.sdw<31:0>; int64_t val2 = Rs2_or_imm13_sdw<31:0>;
bool overflow = false, underflow = false; bool overflow = false, underflow = false;
if (val2 == 0) { if (val2 == 0) {
fault = new DivisionByZero; fault = new DivisionByZero;
} else { } else {
Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; Rd = (int64_t)((Y << 32) | Rs1_sdw<31:0>) / val2;
overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max()); overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max());
underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min()); underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min());
if (overflow) if (overflow)
@ -313,12 +313,12 @@ decode OP default Unknown::unknown()
0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
} }
0x26: decode X { 0x26: decode X {
0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); 0x0: srl({{Rd = Rs1_uw >> (I ? SHCNT32 : Rs2<4:0>);}});
0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); 0x1: srlx({{Rd = Rs1_udw >> (I ? SHCNT64 : Rs2<5:0>);}});
} }
0x27: decode X { 0x27: decode X {
0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 0x0: sra({{Rd = Rs1_sw >> (I ? SHCNT32 : Rs2<4:0>);}});
0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); 0x1: srax({{Rd = Rs1_sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
} }
0x28: decode RS1 { 0x28: decode RS1 {
0x00: NoPriv::rdy({{Rd = Y<31:0>;}}); 0x00: NoPriv::rdy({{Rd = Y<31:0>;}});
@ -450,20 +450,20 @@ decode OP default Unknown::unknown()
} }
} }
0x2D: sdivx({{ 0x2D: sdivx({{
if (Rs2_or_imm13.sdw == 0) if (Rs2_or_imm13_sdw == 0)
fault = new DivisionByZero; fault = new DivisionByZero;
else else
Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw; Rd_sdw = Rs1_sdw / Rs2_or_imm13_sdw;
}}); }});
0x2E: Trap::popc({{fault = new IllegalInstruction;}}); 0x2E: Trap::popc({{fault = new IllegalInstruction;}});
0x2F: decode RCOND3 0x2F: decode RCOND3
{ {
0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}}); 0x1: movreq({{Rd = (Rs1_sdw == 0) ? Rs2_or_imm10 : Rd;}});
0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}}); 0x2: movrle({{Rd = (Rs1_sdw <= 0) ? Rs2_or_imm10 : Rd;}});
0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}}); 0x3: movrl({{Rd = (Rs1_sdw < 0) ? Rs2_or_imm10 : Rd;}});
0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}}); 0x5: movrne({{Rd = (Rs1_sdw != 0) ? Rs2_or_imm10 : Rd;}});
0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}}); 0x6: movrg({{Rd = (Rs1_sdw > 0) ? Rs2_or_imm10 : Rd;}});
0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}}); 0x7: movrge({{Rd = (Rs1_sdw >= 0) ? Rs2_or_imm10 : Rd;}});
} }
0x30: decode RD { 0x30: decode RD {
0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}}); 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}});
@ -570,57 +570,57 @@ decode OP default Unknown::unknown()
} }
0x34: decode OPF{ 0x34: decode OPF{
format FpBasic{ format FpBasic{
0x01: fmovs({{Frds.uw = Frs2s.uw;}}); 0x01: fmovs({{Frds_uw = Frs2s_uw;}});
0x02: fmovd({{Frd.udw = Frs2.udw;}}); 0x02: fmovd({{Frd_udw = Frs2_udw;}});
0x03: FpUnimpl::fmovq(); 0x03: FpUnimpl::fmovq();
0x05: fnegs({{Frds.uw = Frs2s.uw ^ (1UL << 31);}}); 0x05: fnegs({{Frds_uw = Frs2s_uw ^ (1UL << 31);}});
0x06: fnegd({{Frd.udw = Frs2.udw ^ (1ULL << 63);}}); 0x06: fnegd({{Frd_udw = Frs2_udw ^ (1ULL << 63);}});
0x07: FpUnimpl::fnegq(); 0x07: FpUnimpl::fnegq();
0x09: fabss({{Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;}}); 0x09: fabss({{Frds_uw = ((1UL << 31) - 1) & Frs2s_uw;}});
0x0A: fabsd({{Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;}}); 0x0A: fabsd({{Frd_udw = ((1ULL << 63) - 1) & Frs2_udw;}});
0x0B: FpUnimpl::fabsq(); 0x0B: FpUnimpl::fabsq();
0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}}); 0x29: fsqrts({{Frds_sf = std::sqrt(Frs2s_sf);}});
0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}}); 0x2A: fsqrtd({{Frd_df = std::sqrt(Frs2_df);}});
0x2B: FpUnimpl::fsqrtq(); 0x2B: FpUnimpl::fsqrtq();
0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}}); 0x41: fadds({{Frds_sf = Frs1s_sf + Frs2s_sf;}});
0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}}); 0x42: faddd({{Frd_df = Frs1_df + Frs2_df;}});
0x43: FpUnimpl::faddq(); 0x43: FpUnimpl::faddq();
0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}}); 0x45: fsubs({{Frds_sf = Frs1s_sf - Frs2s_sf;}});
0x46: fsubd({{Frd.df = Frs1.df - Frs2.df; }}); 0x46: fsubd({{Frd_df = Frs1_df - Frs2_df; }});
0x47: FpUnimpl::fsubq(); 0x47: FpUnimpl::fsubq();
0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}}); 0x49: fmuls({{Frds_sf = Frs1s_sf * Frs2s_sf;}});
0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}}); 0x4A: fmuld({{Frd_df = Frs1_df * Frs2_df;}});
0x4B: FpUnimpl::fmulq(); 0x4B: FpUnimpl::fmulq();
0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}}); 0x4D: fdivs({{Frds_sf = Frs1s_sf / Frs2s_sf;}});
0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}}); 0x4E: fdivd({{Frd_df = Frs1_df / Frs2_df;}});
0x4F: FpUnimpl::fdivq(); 0x4F: FpUnimpl::fdivq();
0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}}); 0x69: fsmuld({{Frd_df = Frs1s_sf * Frs2s_sf;}});
0x6E: FpUnimpl::fdmulq(); 0x6E: FpUnimpl::fdmulq();
0x81: fstox({{Frd.sdw = static_cast<int64_t>(Frs2s.sf);}}); 0x81: fstox({{Frd_sdw = static_cast<int64_t>(Frs2s_sf);}});
0x82: fdtox({{Frd.sdw = static_cast<int64_t>(Frs2.df);}}); 0x82: fdtox({{Frd_sdw = static_cast<int64_t>(Frs2_df);}});
0x83: FpUnimpl::fqtox(); 0x83: FpUnimpl::fqtox();
0x84: fxtos({{Frds.sf = static_cast<float>(Frs2.sdw);}}); 0x84: fxtos({{Frds_sf = static_cast<float>(Frs2_sdw);}});
0x88: fxtod({{Frd.df = static_cast<double>(Frs2.sdw);}}); 0x88: fxtod({{Frd_df = static_cast<double>(Frs2_sdw);}});
0x8C: FpUnimpl::fxtoq(); 0x8C: FpUnimpl::fxtoq();
0xC4: fitos({{Frds.sf = static_cast<float>(Frs2s.sw);}}); 0xC4: fitos({{Frds_sf = static_cast<float>(Frs2s_sw);}});
0xC6: fdtos({{Frds.sf = Frs2.df;}}); 0xC6: fdtos({{Frds_sf = Frs2_df;}});
0xC7: FpUnimpl::fqtos(); 0xC7: FpUnimpl::fqtos();
0xC8: fitod({{Frd.df = static_cast<double>(Frs2s.sw);}}); 0xC8: fitod({{Frd_df = static_cast<double>(Frs2s_sw);}});
0xC9: fstod({{Frd.df = Frs2s.sf;}}); 0xC9: fstod({{Frd_df = Frs2s_sf;}});
0xCB: FpUnimpl::fqtod(); 0xCB: FpUnimpl::fqtod();
0xCC: FpUnimpl::fitoq(); 0xCC: FpUnimpl::fitoq();
0xCD: FpUnimpl::fstoq(); 0xCD: FpUnimpl::fstoq();
0xCE: FpUnimpl::fdtoq(); 0xCE: FpUnimpl::fdtoq();
0xD1: fstoi({{ 0xD1: fstoi({{
Frds.sw = static_cast<int32_t>(Frs2s.sf); Frds_sw = static_cast<int32_t>(Frs2s_sf);
float t = Frds.sw; float t = Frds_sw;
if (t != Frs2s.sf) if (t != Frs2s_sf)
Fsr = insertBits(Fsr, 4,0, 0x01); Fsr = insertBits(Fsr, 4,0, 0x01);
}}); }});
0xD2: fdtoi({{ 0xD2: fdtoi({{
Frds.sw = static_cast<int32_t>(Frs2.df); Frds_sw = static_cast<int32_t>(Frs2_df);
double t = Frds.sw; double t = Frds_sw;
if (t != Frs2.df) if (t != Frs2_df)
Fsr = insertBits(Fsr, 4,0, 0x01); Fsr = insertBits(Fsr, 4,0, 0x01);
}}); }});
0xD3: FpUnimpl::fqtoi(); 0xD3: FpUnimpl::fqtoi();
@ -895,8 +895,8 @@ decode OP default Unknown::unknown()
0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}}); 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}});
0x3E: Trap::pdist({{fault = new IllegalInstruction;}}); 0x3E: Trap::pdist({{fault = new IllegalInstruction;}});
0x48: BasicOperate::faligndata({{ 0x48: BasicOperate::faligndata({{
uint64_t msbX = Frs1.udw; uint64_t msbX = Frs1_udw;
uint64_t lsbX = Frs2.udw; uint64_t lsbX = Frs2_udw;
// Some special cases need to be split out, first // Some special cases need to be split out, first
// because they're the most likely to be used, and // because they're the most likely to be used, and
// second because otherwise, we end up shifting by // second because otherwise, we end up shifting by
@ -905,17 +905,17 @@ decode OP default Unknown::unknown()
// according to the C standard. // according to the C standard.
switch (Gsr<2:0>) { switch (Gsr<2:0>) {
case 0: case 0:
Frd.udw = msbX; Frd_udw = msbX;
break; break;
case 8: case 8:
Frd.udw = lsbX; Frd_udw = lsbX;
break; break;
default: default:
uint64_t msbShift = Gsr<2:0> * 8; uint64_t msbShift = Gsr<2:0> * 8;
uint64_t lsbShift = (8 - Gsr<2:0>) * 8; uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
uint64_t msbMask = ((uint64_t)(-1)) >> msbShift; uint64_t msbMask = ((uint64_t)(-1)) >> msbShift;
uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift; uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
Frd.udw = ((msbX & msbMask) << msbShift) | Frd_udw = ((msbX & msbMask) << msbShift) |
((lsbX & lsbMask) >> lsbShift); ((lsbX & lsbMask) >> lsbShift);
} }
}}); }});
@ -930,25 +930,25 @@ decode OP default Unknown::unknown()
0x55: FailUnimpl::fpsub16s(); 0x55: FailUnimpl::fpsub16s();
0x56: FailUnimpl::fpsub32(); 0x56: FailUnimpl::fpsub32();
0x57: FailUnimpl::fpsub32s(); 0x57: FailUnimpl::fpsub32s();
0x60: FpBasic::fzero({{Frd.df = 0;}}); 0x60: FpBasic::fzero({{Frd_df = 0;}});
0x61: FpBasic::fzeros({{Frds.sf = 0;}}); 0x61: FpBasic::fzeros({{Frds_sf = 0;}});
0x62: FailUnimpl::fnor(); 0x62: FailUnimpl::fnor();
0x63: FailUnimpl::fnors(); 0x63: FailUnimpl::fnors();
0x64: FailUnimpl::fandnot2(); 0x64: FailUnimpl::fandnot2();
0x65: FailUnimpl::fandnot2s(); 0x65: FailUnimpl::fandnot2s();
0x66: FpBasic::fnot2({{ 0x66: FpBasic::fnot2({{
Frd.df = (double)(~((uint64_t)Frs2.df)); Frd_df = (double)(~((uint64_t)Frs2_df));
}}); }});
0x67: FpBasic::fnot2s({{ 0x67: FpBasic::fnot2s({{
Frds.sf = (float)(~((uint32_t)Frs2s.sf)); Frds_sf = (float)(~((uint32_t)Frs2s_sf));
}}); }});
0x68: FailUnimpl::fandnot1(); 0x68: FailUnimpl::fandnot1();
0x69: FailUnimpl::fandnot1s(); 0x69: FailUnimpl::fandnot1s();
0x6A: FpBasic::fnot1({{ 0x6A: FpBasic::fnot1({{
Frd.df = (double)(~((uint64_t)Frs1.df)); Frd_df = (double)(~((uint64_t)Frs1_df));
}}); }});
0x6B: FpBasic::fnot1s({{ 0x6B: FpBasic::fnot1s({{
Frds.sf = (float)(~((uint32_t)Frs1s.sf)); Frds_sf = (float)(~((uint32_t)Frs1s_sf));
}}); }});
0x6C: FailUnimpl::fxor(); 0x6C: FailUnimpl::fxor();
0x6D: FailUnimpl::fxors(); 0x6D: FailUnimpl::fxors();
@ -958,18 +958,18 @@ decode OP default Unknown::unknown()
0x71: FailUnimpl::fands(); 0x71: FailUnimpl::fands();
0x72: FailUnimpl::fxnor(); 0x72: FailUnimpl::fxnor();
0x73: FailUnimpl::fxnors(); 0x73: FailUnimpl::fxnors();
0x74: FpBasic::fsrc1({{Frd.udw = Frs1.udw;}}); 0x74: FpBasic::fsrc1({{Frd_udw = Frs1_udw;}});
0x75: FpBasic::fsrc1s({{Frds.uw = Frs1s.uw;}}); 0x75: FpBasic::fsrc1s({{Frds_uw = Frs1s_uw;}});
0x76: FailUnimpl::fornot2(); 0x76: FailUnimpl::fornot2();
0x77: FailUnimpl::fornot2s(); 0x77: FailUnimpl::fornot2s();
0x78: FpBasic::fsrc2({{Frd.udw = Frs2.udw;}}); 0x78: FpBasic::fsrc2({{Frd_udw = Frs2_udw;}});
0x79: FpBasic::fsrc2s({{Frds.uw = Frs2s.uw;}}); 0x79: FpBasic::fsrc2s({{Frds_uw = Frs2s_uw;}});
0x7A: FailUnimpl::fornot1(); 0x7A: FailUnimpl::fornot1();
0x7B: FailUnimpl::fornot1s(); 0x7B: FailUnimpl::fornot1s();
0x7C: FailUnimpl::for(); 0x7C: FailUnimpl::for();
0x7D: FailUnimpl::fors(); 0x7D: FailUnimpl::fors();
0x7E: FpBasic::fone({{Frd.udw = std::numeric_limits<uint64_t>::max();}}); 0x7E: FpBasic::fone({{Frd_udw = std::numeric_limits<uint64_t>::max();}});
0x7F: FpBasic::fones({{Frds.uw = std::numeric_limits<uint32_t>::max();}}); 0x7F: FpBasic::fones({{Frds_uw = std::numeric_limits<uint32_t>::max();}});
0x80: Trap::shutdown({{fault = new IllegalInstruction;}}); 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
0x81: FailUnimpl::siam(); 0x81: FailUnimpl::siam();
} }
@ -1099,18 +1099,18 @@ decode OP default Unknown::unknown()
} }
0x3: decode OP3 { 0x3: decode OP3 {
format Load { format Load {
0x00: lduw({{Rd = Mem.uw;}}); 0x00: lduw({{Rd = Mem_uw;}});
0x01: ldub({{Rd = Mem.ub;}}); 0x01: ldub({{Rd = Mem_ub;}});
0x02: lduh({{Rd = Mem.uhw;}}); 0x02: lduh({{Rd = Mem_uhw;}});
0x03: ldtw({{ 0x03: ldtw({{
RdLow = (Mem.tuw).a; RdLow = (Mem_tuw).a;
RdHigh = (Mem.tuw).b; RdHigh = (Mem_tuw).b;
}}); }});
} }
format Store { format Store {
0x04: stw({{Mem.uw = Rd.sw;}}); 0x04: stw({{Mem_uw = Rd_sw;}});
0x05: stb({{Mem.ub = Rd.sb;}}); 0x05: stb({{Mem_ub = Rd_sb;}});
0x06: sth({{Mem.uhw = Rd.shw;}}); 0x06: sth({{Mem_uhw = Rd_shw;}});
0x07: sttw({{ 0x07: sttw({{
// This temporary needs to be here so that the parser // This temporary needs to be here so that the parser
// will correctly identify this instruction as a store. // will correctly identify this instruction as a store.
@ -1119,96 +1119,96 @@ decode OP default Unknown::unknown()
Twin32_t temp; Twin32_t temp;
temp.a = RdLow<31:0>; temp.a = RdLow<31:0>;
temp.b = RdHigh<31:0>; temp.b = RdHigh<31:0>;
Mem.tuw = temp; Mem_tuw = temp;
}}); }});
} }
format Load { format Load {
0x08: ldsw({{Rd = Mem.sw;}}); 0x08: ldsw({{Rd = Mem_sw;}});
0x09: ldsb({{Rd = Mem.sb;}}); 0x09: ldsb({{Rd = Mem_sb;}});
0x0A: ldsh({{Rd = Mem.shw;}}); 0x0A: ldsh({{Rd = Mem_shw;}});
0x0B: ldx({{Rd = Mem.sdw;}}); 0x0B: ldx({{Rd = Mem_sdw;}});
} }
0x0D: Swap::ldstub({{Mem.ub = 0xFF;}}, 0x0D: Swap::ldstub({{Mem_ub = 0xFF;}},
{{ {{
uint8_t tmp = mem_data; uint8_t tmp = mem_data;
Rd.ub = tmp; Rd_ub = tmp;
}}, MEM_SWAP); }}, MEM_SWAP);
0x0E: Store::stx({{Mem.udw = Rd}}); 0x0E: Store::stx({{Mem_udw = Rd}});
0x0F: Swap::swap({{Mem.uw = Rd.uw}}, 0x0F: Swap::swap({{Mem_uw = Rd_uw}},
{{ {{
uint32_t tmp = mem_data; uint32_t tmp = mem_data;
Rd.uw = tmp; Rd_uw = tmp;
}}, MEM_SWAP); }}, MEM_SWAP);
format LoadAlt { format LoadAlt {
0x10: lduwa({{Rd = Mem.uw;}}); 0x10: lduwa({{Rd = Mem_uw;}});
0x11: lduba({{Rd = Mem.ub;}}); 0x11: lduba({{Rd = Mem_ub;}});
0x12: lduha({{Rd = Mem.uhw;}}); 0x12: lduha({{Rd = Mem_uhw;}});
0x13: decode EXT_ASI { 0x13: decode EXT_ASI {
// ASI_LDTD_AIUP // ASI_LDTD_AIUP
0x22: TwinLoad::ldtx_aiup( 0x22: TwinLoad::ldtx_aiup(
{{RdLow.udw = (Mem.tudw).a; {{RdLow_udw = (Mem_tudw).a;
RdHigh.udw = (Mem.tudw).b;}}); RdHigh_udw = (Mem_tudw).b;}});
// ASI_LDTD_AIUS // ASI_LDTD_AIUS
0x23: TwinLoad::ldtx_aius( 0x23: TwinLoad::ldtx_aius(
{{RdLow.udw = (Mem.tudw).a; {{RdLow_udw = (Mem_tudw).a;
RdHigh.udw = (Mem.tudw).b;}}); RdHigh_udw = (Mem_tudw).b;}});
// ASI_QUAD_LDD // ASI_QUAD_LDD
0x24: TwinLoad::ldtx_quad_ldd( 0x24: TwinLoad::ldtx_quad_ldd(
{{RdLow.udw = (Mem.tudw).a; {{RdLow_udw = (Mem_tudw).a;
RdHigh.udw = (Mem.tudw).b;}}); RdHigh_udw = (Mem_tudw).b;}});
// ASI_LDTX_REAL // ASI_LDTX_REAL
0x26: TwinLoad::ldtx_real( 0x26: TwinLoad::ldtx_real(
{{RdLow.udw = (Mem.tudw).a; {{RdLow_udw = (Mem_tudw).a;
RdHigh.udw = (Mem.tudw).b;}}); RdHigh_udw = (Mem_tudw).b;}});
// ASI_LDTX_N // ASI_LDTX_N
0x27: TwinLoad::ldtx_n( 0x27: TwinLoad::ldtx_n(
{{RdLow.udw = (Mem.tudw).a; {{RdLow_udw = (Mem_tudw).a;
RdHigh.udw = (Mem.tudw).b;}}); RdHigh_udw = (Mem_tudw).b;}});
// ASI_LDTX_AIUP_L // ASI_LDTX_AIUP_L
0x2A: TwinLoad::ldtx_aiup_l( 0x2A: TwinLoad::ldtx_aiup_l(
{{RdLow.udw = (Mem.tudw).a; {{RdLow_udw = (Mem_tudw).a;
RdHigh.udw = (Mem.tudw).b;}}); RdHigh_udw = (Mem_tudw).b;}});
// ASI_LDTX_AIUS_L // ASI_LDTX_AIUS_L
0x2B: TwinLoad::ldtx_aius_l( 0x2B: TwinLoad::ldtx_aius_l(
{{RdLow.udw = (Mem.tudw).a; {{RdLow_udw = (Mem_tudw).a;
RdHigh.udw = (Mem.tudw).b;}}); RdHigh_udw = (Mem_tudw).b;}});
// ASI_LDTX_L // ASI_LDTX_L
0x2C: TwinLoad::ldtx_l( 0x2C: TwinLoad::ldtx_l(
{{RdLow.udw = (Mem.tudw).a; {{RdLow_udw = (Mem_tudw).a;
RdHigh.udw = (Mem.tudw).b;}}); RdHigh_udw = (Mem_tudw).b;}});
// ASI_LDTX_REAL_L // ASI_LDTX_REAL_L
0x2E: TwinLoad::ldtx_real_l( 0x2E: TwinLoad::ldtx_real_l(
{{RdLow.udw = (Mem.tudw).a; {{RdLow_udw = (Mem_tudw).a;
RdHigh.udw = (Mem.tudw).b;}}); RdHigh_udw = (Mem_tudw).b;}});
// ASI_LDTX_N_L // ASI_LDTX_N_L
0x2F: TwinLoad::ldtx_n_l( 0x2F: TwinLoad::ldtx_n_l(
{{RdLow.udw = (Mem.tudw).a; {{RdLow_udw = (Mem_tudw).a;
RdHigh.udw = (Mem.tudw).b;}}); RdHigh_udw = (Mem_tudw).b;}});
// ASI_LDTX_P // ASI_LDTX_P
0xE2: TwinLoad::ldtx_p( 0xE2: TwinLoad::ldtx_p(
{{RdLow.udw = (Mem.tudw).a; {{RdLow_udw = (Mem_tudw).a;
RdHigh.udw = (Mem.tudw).b;}}); RdHigh_udw = (Mem_tudw).b;}});
// ASI_LDTX_S // ASI_LDTX_S
0xE3: TwinLoad::ldtx_s( 0xE3: TwinLoad::ldtx_s(
{{RdLow.udw = (Mem.tudw).a; {{RdLow_udw = (Mem_tudw).a;
RdHigh.udw = (Mem.tudw).b;}}); RdHigh_udw = (Mem_tudw).b;}});
// ASI_LDTX_PL // ASI_LDTX_PL
0xEA: TwinLoad::ldtx_pl( 0xEA: TwinLoad::ldtx_pl(
{{RdLow.udw = (Mem.tudw).a; {{RdLow_udw = (Mem_tudw).a;
RdHigh.udw = (Mem.tudw).b;}}); RdHigh_udw = (Mem_tudw).b;}});
// ASI_LDTX_SL // ASI_LDTX_SL
0xEB: TwinLoad::ldtx_sl( 0xEB: TwinLoad::ldtx_sl(
{{RdLow.udw = (Mem.tudw).a; {{RdLow_udw = (Mem_tudw).a;
RdHigh.udw = (Mem.tudw).b;}}); RdHigh_udw = (Mem_tudw).b;}});
default: ldtwa({{ default: ldtwa({{
RdLow = (Mem.tuw).a; RdLow = (Mem_tuw).a;
RdHigh = (Mem.tuw).b;}}); RdHigh = (Mem_tuw).b;}});
} }
} }
format StoreAlt { format StoreAlt {
0x14: stwa({{Mem.uw = Rd;}}); 0x14: stwa({{Mem_uw = Rd;}});
0x15: stba({{Mem.ub = Rd;}}); 0x15: stba({{Mem_ub = Rd;}});
0x16: stha({{Mem.uhw = Rd;}}); 0x16: stha({{Mem_uhw = Rd;}});
0x17: sttwa({{ 0x17: sttwa({{
// This temporary needs to be here so that the parser // This temporary needs to be here so that the parser
// will correctly identify this instruction as a store. // will correctly identify this instruction as a store.
@ -1217,58 +1217,58 @@ decode OP default Unknown::unknown()
Twin32_t temp; Twin32_t temp;
temp.a = RdLow<31:0>; temp.a = RdLow<31:0>;
temp.b = RdHigh<31:0>; temp.b = RdHigh<31:0>;
Mem.tuw = temp; Mem_tuw = temp;
}}); }});
} }
format LoadAlt { format LoadAlt {
0x18: ldswa({{Rd = Mem.sw;}}); 0x18: ldswa({{Rd = Mem_sw;}});
0x19: ldsba({{Rd = Mem.sb;}}); 0x19: ldsba({{Rd = Mem_sb;}});
0x1A: ldsha({{Rd = Mem.shw;}}); 0x1A: ldsha({{Rd = Mem_shw;}});
0x1B: ldxa({{Rd = Mem.sdw;}}); 0x1B: ldxa({{Rd = Mem_sdw;}});
} }
0x1D: SwapAlt::ldstuba({{Mem.ub = 0xFF;}}, 0x1D: SwapAlt::ldstuba({{Mem_ub = 0xFF;}},
{{ {{
uint8_t tmp = mem_data; uint8_t tmp = mem_data;
Rd.ub = tmp; Rd_ub = tmp;
}}, MEM_SWAP); }}, MEM_SWAP);
0x1E: StoreAlt::stxa({{Mem.udw = Rd}}); 0x1E: StoreAlt::stxa({{Mem_udw = Rd}});
0x1F: SwapAlt::swapa({{Mem.uw = Rd.uw}}, 0x1F: SwapAlt::swapa({{Mem_uw = Rd_uw}},
{{ {{
uint32_t tmp = mem_data; uint32_t tmp = mem_data;
Rd.uw = tmp; Rd_uw = tmp;
}}, MEM_SWAP); }}, MEM_SWAP);
format Trap { format Trap {
0x20: Load::ldf({{Frds.uw = Mem.uw;}}); 0x20: Load::ldf({{Frds_uw = Mem_uw;}});
0x21: decode RD { 0x21: decode RD {
0x0: Load::ldfsr({{fault = checkFpEnableFault(xc); 0x0: Load::ldfsr({{fault = checkFpEnableFault(xc);
if (fault) if (fault)
return fault; return fault;
Fsr = Mem.uw | Fsr<63:32>;}}); Fsr = Mem_uw | Fsr<63:32>;}});
0x1: Load::ldxfsr({{fault = checkFpEnableFault(xc); 0x1: Load::ldxfsr({{fault = checkFpEnableFault(xc);
if (fault) if (fault)
return fault; return fault;
Fsr = Mem.udw;}}); Fsr = Mem_udw;}});
default: FailUnimpl::ldfsrOther(); default: FailUnimpl::ldfsrOther();
} }
0x22: ldqf({{fault = new FpDisabled;}}); 0x22: ldqf({{fault = new FpDisabled;}});
0x23: Load::lddf({{Frd.udw = Mem.udw;}}); 0x23: Load::lddf({{Frd_udw = Mem_udw;}});
0x24: Store::stf({{Mem.uw = Frds.uw;}}); 0x24: Store::stf({{Mem_uw = Frds_uw;}});
0x25: decode RD { 0x25: decode RD {
0x0: StoreFsr::stfsr({{fault = checkFpEnableFault(xc); 0x0: StoreFsr::stfsr({{fault = checkFpEnableFault(xc);
if (fault) if (fault)
return fault; return fault;
Mem.uw = Fsr<31:0>;}}); Mem_uw = Fsr<31:0>;}});
0x1: StoreFsr::stxfsr({{fault = checkFpEnableFault(xc); 0x1: StoreFsr::stxfsr({{fault = checkFpEnableFault(xc);
if (fault) if (fault)
return fault; return fault;
Mem.udw = Fsr;}}); Mem_udw = Fsr;}});
default: FailUnimpl::stfsrOther(); default: FailUnimpl::stfsrOther();
} }
0x26: stqf({{fault = new FpDisabled;}}); 0x26: stqf({{fault = new FpDisabled;}});
0x27: Store::stdf({{Mem.udw = Frd.udw;}}); 0x27: Store::stdf({{Mem_udw = Frd_udw;}});
0x2D: Nop::prefetch({{ }}); 0x2D: Nop::prefetch({{ }});
0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}); 0x30: LoadAlt::ldfa({{Frds_uw = Mem_uw;}});
0x32: ldqfa({{fault = new FpDisabled;}}); 0x32: ldqfa({{fault = new FpDisabled;}});
format LoadAlt { format LoadAlt {
0x33: decode EXT_ASI { 0x33: decode EXT_ASI {
@ -1320,7 +1320,7 @@ decode OP default Unknown::unknown()
// ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE // ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
0x1F: FailUnimpl::ldblockf_aiusl(); 0x1F: FailUnimpl::ldblockf_aiusl();
// ASI_BLOCK_PRIMARY // ASI_BLOCK_PRIMARY
0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}); 0xF0: ldblockf_p({{Frd_N_udw = Mem_udw;}});
// ASI_BLOCK_SECONDARY // ASI_BLOCK_SECONDARY
0xF1: FailUnimpl::ldblockf_s(); 0xF1: FailUnimpl::ldblockf_s();
// ASI_BLOCK_PRIMARY_LITTLE // ASI_BLOCK_PRIMARY_LITTLE
@ -1351,7 +1351,7 @@ decode OP default Unknown::unknown()
{{fault = new DataAccessException;}}); {{fault = new DataAccessException;}});
} }
} }
0x34: Store::stfa({{Mem.uw = Frds.uw;}}); 0x34: Store::stfa({{Mem_uw = Frds_uw;}});
0x36: stqfa({{fault = new FpDisabled;}}); 0x36: stqfa({{fault = new FpDisabled;}});
format StoreAlt { format StoreAlt {
0x37: decode EXT_ASI { 0x37: decode EXT_ASI {
@ -1403,7 +1403,7 @@ decode OP default Unknown::unknown()
// ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE // ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
0x1F: FailUnimpl::stblockf_aiusl(); 0x1F: FailUnimpl::stblockf_aiusl();
// ASI_BLOCK_PRIMARY // ASI_BLOCK_PRIMARY
0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}); 0xF0: stblockf_p({{Mem_udw = Frd_N_udw;}});
// ASI_BLOCK_SECONDARY // ASI_BLOCK_SECONDARY
0xF1: FailUnimpl::stblockf_s(); 0xF1: FailUnimpl::stblockf_s();
// ASI_BLOCK_PRIMARY_LITTLE // ASI_BLOCK_PRIMARY_LITTLE
@ -1435,16 +1435,16 @@ decode OP default Unknown::unknown()
} }
} }
0x3C: CasAlt::casa({{ 0x3C: CasAlt::casa({{
mem_data = htog(Rs2.uw); mem_data = htog(Rs2_uw);
Mem.uw = Rd.uw;}}, Mem_uw = Rd_uw;}},
{{ {{
uint32_t tmp = mem_data; uint32_t tmp = mem_data;
Rd.uw = tmp; Rd_uw = tmp;
}}, MEM_SWAP_COND); }}, MEM_SWAP_COND);
0x3D: Nop::prefetcha({{ }}); 0x3D: Nop::prefetcha({{ }});
0x3E: CasAlt::casxa({{mem_data = gtoh(Rs2); 0x3E: CasAlt::casxa({{mem_data = gtoh(Rs2);
Mem.udw = Rd.udw; }}, Mem_udw = Rd_udw; }},
{{ Rd.udw = mem_data; }}, MEM_SWAP_COND); {{ Rd_udw = mem_data; }}, MEM_SWAP_COND);
} }
} }
} }

6
src/arch/x86/isa/microops/fpop.isa
View file

@ -213,12 +213,12 @@ let {{
SetStatus=False, dataSize="env.dataSize"): SetStatus=False, dataSize="env.dataSize"):
super(Movfp, self).__init__(dest, src1, "InstRegIndex(0)", \ super(Movfp, self).__init__(dest, src1, "InstRegIndex(0)", \
spm, SetStatus, dataSize) spm, SetStatus, dataSize)
code = 'FpDestReg.uqw = FpSrcReg1.uqw;' code = 'FpDestReg_uqw = FpSrcReg1_uqw;'
else_code = 'FpDestReg.uqw = FpDestReg.uqw;' else_code = 'FpDestReg_uqw = FpDestReg_uqw;'
cond_check = "checkCondition(ccFlagBits, src2)" cond_check = "checkCondition(ccFlagBits, src2)"
class Xorfp(FpOp): class Xorfp(FpOp):
code = 'FpDestReg.uqw = FpSrcReg1.uqw ^ FpSrcReg2.uqw;' code = 'FpDestReg_uqw = FpSrcReg1_uqw ^ FpSrcReg2_uqw;'
class Sqrtfp(FpOp): class Sqrtfp(FpOp):
code = 'FpDestReg = sqrt(FpSrcReg2);' code = 'FpDestReg = sqrt(FpSrcReg2);'

4
src/arch/x86/isa/microops/ldstop.isa
View file

@ -410,7 +410,7 @@ let {{
defineMicroLoadOp('Ldstl', 'Data = merge(Data, Mem, dataSize);', defineMicroLoadOp('Ldstl', 'Data = merge(Data, Mem, dataSize);',
'Data = Mem & mask(dataSize * 8);', 'Data = Mem & mask(dataSize * 8);',
'(StoreCheck << FlagShift) | Request::LOCKED') '(StoreCheck << FlagShift) | Request::LOCKED')
defineMicroLoadOp('Ldfp', 'FpData.uqw = Mem;', big = False) defineMicroLoadOp('Ldfp', 'FpData_uqw = Mem;', big = False)
def defineMicroStoreOp(mnemonic, code, completeCode="", mem_flags="0"): def defineMicroStoreOp(mnemonic, code, completeCode="", mem_flags="0"):
global header_output global header_output
@ -447,7 +447,7 @@ let {{
defineMicroStoreOp('St', 'Mem = pick(Data, 2, dataSize);') defineMicroStoreOp('St', 'Mem = pick(Data, 2, dataSize);')
defineMicroStoreOp('Stul', 'Mem = pick(Data, 2, dataSize);', defineMicroStoreOp('Stul', 'Mem = pick(Data, 2, dataSize);',
mem_flags="Request::LOCKED") mem_flags="Request::LOCKED")
defineMicroStoreOp('Stfp', 'Mem = FpData.uqw;') defineMicroStoreOp('Stfp', 'Mem = FpData_uqw;')
defineMicroStoreOp('Cda', 'Mem = 0;', mem_flags="Request::NO_ACCESS") defineMicroStoreOp('Cda', 'Mem = 0;', mem_flags="Request::NO_ACCESS")
iop = InstObjParams("lea", "Lea", 'X86ISA::LdStOp', iop = InstObjParams("lea", "Lea", 'X86ISA::LdStOp',

2
src/arch/x86/isa/microops/limmop.isa
View file

@ -171,7 +171,7 @@ let {{
exec_output += MicroLimmOpExecute.subst(iop) exec_output += MicroLimmOpExecute.subst(iop)
iop = InstObjParams("lfpimm", "Lfpimm", 'X86MicroopBase', iop = InstObjParams("lfpimm", "Lfpimm", 'X86MicroopBase',
{"code" : "FpDestReg.uqw = imm"}) {"code" : "FpDestReg_uqw = imm"})
header_output += MicroLimmOpDeclare.subst(iop) header_output += MicroLimmOpDeclare.subst(iop)
decoder_output += MicroLimmOpConstructor.subst(iop) decoder_output += MicroLimmOpConstructor.subst(iop)
decoder_output += MicroLimmOpDisassembly.subst(iop) decoder_output += MicroLimmOpDisassembly.subst(iop)

218
src/arch/x86/isa/microops/mediaop.isa
View file

@ -126,7 +126,7 @@ let {{
# If op2 is used anywhere, make register and immediate versions # If op2 is used anywhere, make register and immediate versions
# of this code. # of this code.
matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?") matcher = re.compile(r"(?<!\w)(?P<prefix>s?)op2(?P<typeQual>_[^\W_]+)?")
match = matcher.search(code) match = matcher.search(code)
if match: if match:
typeQual = "" typeQual = ""
@ -182,7 +182,7 @@ let {{
# If op2 is used anywhere, make register and immediate versions # If op2 is used anywhere, make register and immediate versions
# of this code. # of this code.
matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") matcher = re.compile(r"op2(?P<typeQual>_[^\W_]+)?")
if matcher.search(code): if matcher.search(code):
microopClasses[name + 'i'] = cls microopClasses[name + 'i'] = cls
return cls return cls
@ -242,7 +242,7 @@ let {{
offset -= items; offset -= items;
if (offset >= 0 && offset < items) { if (offset >= 0 && offset < items) {
uint64_t fpSrcReg1 = uint64_t fpSrcReg1 =
bits(FpSrcReg1.uqw, bits(FpSrcReg1_uqw,
(offset + 1) * srcSize * 8 - 1, (offset + 1) * srcSize * 8 - 1,
(offset + 0) * srcSize * 8); (offset + 0) * srcSize * 8);
DestReg = merge(0, fpSrcReg1, destSize); DestReg = merge(0, fpSrcReg1, destSize);
@ -263,12 +263,12 @@ let {{
offset -= items; offset -= items;
if (offset >= 0 && offset < items) { if (offset >= 0 && offset < items) {
uint64_t srcReg1 = pick(SrcReg1, 0, srcSize); uint64_t srcReg1 = pick(SrcReg1, 0, srcSize);
FpDestReg.uqw = FpDestReg_uqw =
insertBits(FpDestReg.uqw, insertBits(FpDestReg_uqw,
(offset + 1) * destSize * 8 - 1, (offset + 1) * destSize * 8 - 1,
(offset + 0) * destSize * 8, srcReg1); (offset + 0) * destSize * 8, srcReg1);
} else { } else {
FpDestReg.uqw = FpDestReg.uqw; FpDestReg_uqw = FpDestReg_uqw;
} }
''' '''
@ -283,7 +283,7 @@ let {{
int offset = (ext & 0x1) ? items : 0; int offset = (ext & 0x1) ? items : 0;
for (int i = 0; i < items; i++) { for (int i = 0; i < items; i++) {
uint64_t picked = uint64_t picked =
bits(FpSrcReg1.uqw, (i + 1) * 8 * srcSize - 1); bits(FpSrcReg1_uqw, (i + 1) * 8 * srcSize - 1);
result = insertBits(result, i + offset, i + offset, picked); result = insertBits(result, i + offset, i + offset, picked);
} }
DestReg = DestReg | result; DestReg = DestReg | result;
@ -295,16 +295,16 @@ let {{
int size = srcSize; int size = srcSize;
int sizeBits = size * 8; int sizeBits = size * 8;
int items = numItems(size); int items = numItems(size);
uint64_t result = FpDestReg.uqw; uint64_t result = FpDestReg_uqw;
for (int i = 0; i < items; i++) { for (int i = 0; i < items; i++) {
int hiIndex = (i + 1) * sizeBits - 1; int hiIndex = (i + 1) * sizeBits - 1;
int loIndex = (i + 0) * sizeBits; int loIndex = (i + 0) * sizeBits;
uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex);
if (bits(FpSrcReg2.uqw, hiIndex)) if (bits(FpSrcReg2_uqw, hiIndex))
result = insertBits(result, hiIndex, loIndex, arg1Bits); result = insertBits(result, hiIndex, loIndex, arg1Bits);
} }
FpDestReg.uqw = result; FpDestReg_uqw = result;
''' '''
class shuffle(MediaOp): class shuffle(MediaOp):
@ -331,11 +331,11 @@ let {{
uint8_t lsel = sel & mask(optionBits); uint8_t lsel = sel & mask(optionBits);
if (lsel * size >= sizeof(FloatRegBits)) { if (lsel * size >= sizeof(FloatRegBits)) {
lsel -= options / 2; lsel -= options / 2;
resBits = bits(FpSrcReg2.uqw, resBits = bits(FpSrcReg2_uqw,
(lsel + 1) * sizeBits - 1, (lsel + 1) * sizeBits - 1,
(lsel + 0) * sizeBits); (lsel + 0) * sizeBits);
} else { } else {
resBits = bits(FpSrcReg1.uqw, resBits = bits(FpSrcReg1_uqw,
(lsel + 1) * sizeBits - 1, (lsel + 1) * sizeBits - 1,
(lsel + 0) * sizeBits); (lsel + 0) * sizeBits);
} }
@ -346,7 +346,7 @@ let {{
int loIndex = (i + 0) * sizeBits; int loIndex = (i + 0) * sizeBits;
result = insertBits(result, hiIndex, loIndex, resBits); result = insertBits(result, hiIndex, loIndex, resBits);
} }
FpDestReg.uqw = result; FpDestReg_uqw = result;
''' '''
class Unpack(MediaOp): class Unpack(MediaOp):
@ -358,21 +358,21 @@ let {{
uint64_t result = 0; uint64_t result = 0;
for (int i = 0; i < items; i++) { for (int i = 0; i < items; i++) {
uint64_t pickedLow = uint64_t pickedLow =
bits(FpSrcReg1.uqw, (i + offset + 1) * 8 * size - 1, bits(FpSrcReg1_uqw, (i + offset + 1) * 8 * size - 1,
(i + offset) * 8 * size); (i + offset) * 8 * size);
result = insertBits(result, result = insertBits(result,
(2 * i + 1) * 8 * size - 1, (2 * i + 1) * 8 * size - 1,
(2 * i + 0) * 8 * size, (2 * i + 0) * 8 * size,
pickedLow); pickedLow);
uint64_t pickedHigh = uint64_t pickedHigh =
bits(FpSrcReg2.uqw, (i + offset + 1) * 8 * size - 1, bits(FpSrcReg2_uqw, (i + offset + 1) * 8 * size - 1,
(i + offset) * 8 * size); (i + offset) * 8 * size);
result = insertBits(result, result = insertBits(result,
(2 * i + 2) * 8 * size - 1, (2 * i + 2) * 8 * size - 1,
(2 * i + 1) * 8 * size, (2 * i + 1) * 8 * size,
pickedHigh); pickedHigh);
} }
FpDestReg.uqw = result; FpDestReg_uqw = result;
''' '''
class Pack(MediaOp): class Pack(MediaOp):
@ -385,7 +385,7 @@ let {{
int i; int i;
for (i = 0; i < items / 2; i++) { for (i = 0; i < items / 2; i++) {
uint64_t picked = uint64_t picked =
bits(FpSrcReg1.uqw, (i + 1) * srcBits - 1, bits(FpSrcReg1_uqw, (i + 1) * srcBits - 1,
(i + 0) * srcBits); (i + 0) * srcBits);
unsigned signBit = bits(picked, srcBits - 1); unsigned signBit = bits(picked, srcBits - 1);
uint64_t overflow = bits(picked, srcBits - 1, destBits - 1); uint64_t overflow = bits(picked, srcBits - 1, destBits - 1);
@ -413,7 +413,7 @@ let {{
} }
for (;i < items; i++) { for (;i < items; i++) {
uint64_t picked = uint64_t picked =
bits(FpSrcReg2.uqw, (i - items + 1) * srcBits - 1, bits(FpSrcReg2_uqw, (i - items + 1) * srcBits - 1,
(i - items + 0) * srcBits); (i - items + 0) * srcBits);
unsigned signBit = bits(picked, srcBits - 1); unsigned signBit = bits(picked, srcBits - 1);
uint64_t overflow = bits(picked, srcBits - 1, destBits - 1); uint64_t overflow = bits(picked, srcBits - 1, destBits - 1);
@ -439,35 +439,35 @@ let {{
(i + 0) * destBits, (i + 0) * destBits,
picked); picked);
} }
FpDestReg.uqw = result; FpDestReg_uqw = result;
''' '''
class Mxor(MediaOp): class Mxor(MediaOp):
def __init__(self, dest, src1, src2): def __init__(self, dest, src1, src2):
super(Mxor, self).__init__(dest, src1, src2, 1) super(Mxor, self).__init__(dest, src1, src2, 1)
code = ''' code = '''
FpDestReg.uqw = FpSrcReg1.uqw ^ FpSrcReg2.uqw; FpDestReg_uqw = FpSrcReg1_uqw ^ FpSrcReg2_uqw;
''' '''
class Mor(MediaOp): class Mor(MediaOp):
def __init__(self, dest, src1, src2): def __init__(self, dest, src1, src2):
super(Mor, self).__init__(dest, src1, src2, 1) super(Mor, self).__init__(dest, src1, src2, 1)
code = ''' code = '''
FpDestReg.uqw = FpSrcReg1.uqw | FpSrcReg2.uqw; FpDestReg_uqw = FpSrcReg1_uqw | FpSrcReg2_uqw;
''' '''
class Mand(MediaOp): class Mand(MediaOp):
def __init__(self, dest, src1, src2): def __init__(self, dest, src1, src2):
super(Mand, self).__init__(dest, src1, src2, 1) super(Mand, self).__init__(dest, src1, src2, 1)
code = ''' code = '''
FpDestReg.uqw = FpSrcReg1.uqw & FpSrcReg2.uqw; FpDestReg_uqw = FpSrcReg1_uqw & FpSrcReg2_uqw;
''' '''
class Mandn(MediaOp): class Mandn(MediaOp):
def __init__(self, dest, src1, src2): def __init__(self, dest, src1, src2):
super(Mandn, self).__init__(dest, src1, src2, 1) super(Mandn, self).__init__(dest, src1, src2, 1)
code = ''' code = '''
FpDestReg.uqw = ~FpSrcReg1.uqw & FpSrcReg2.uqw; FpDestReg_uqw = ~FpSrcReg1_uqw & FpSrcReg2_uqw;
''' '''
class Mminf(MediaOp): class Mminf(MediaOp):
@ -488,14 +488,14 @@ let {{
int sizeBits = size * 8; int sizeBits = size * 8;
assert(srcSize == 4 || srcSize == 8); assert(srcSize == 4 || srcSize == 8);
int items = numItems(size); int items = numItems(size);
uint64_t result = FpDestReg.uqw; uint64_t result = FpDestReg_uqw;
for (int i = 0; i < items; i++) { for (int i = 0; i < items; i++) {
double arg1, arg2; double arg1, arg2;
int hiIndex = (i + 1) * sizeBits - 1; int hiIndex = (i + 1) * sizeBits - 1;
int loIndex = (i + 0) * sizeBits; int loIndex = (i + 0) * sizeBits;
uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex);
uint64_t arg2Bits = bits(FpSrcReg2.uqw, hiIndex, loIndex); uint64_t arg2Bits = bits(FpSrcReg2_uqw, hiIndex, loIndex);
if (size == 4) { if (size == 4) {
floatInt fi; floatInt fi;
@ -517,7 +517,7 @@ let {{
result = insertBits(result, hiIndex, loIndex, arg2Bits); result = insertBits(result, hiIndex, loIndex, arg2Bits);
} }
} }
FpDestReg.uqw = result; FpDestReg_uqw = result;
''' '''
class Mmaxf(MediaOp): class Mmaxf(MediaOp):
@ -538,14 +538,14 @@ let {{
int sizeBits = size * 8; int sizeBits = size * 8;
assert(srcSize == 4 || srcSize == 8); assert(srcSize == 4 || srcSize == 8);
int items = numItems(size); int items = numItems(size);
uint64_t result = FpDestReg.uqw; uint64_t result = FpDestReg_uqw;
for (int i = 0; i < items; i++) { for (int i = 0; i < items; i++) {
double arg1, arg2; double arg1, arg2;
int hiIndex = (i + 1) * sizeBits - 1; int hiIndex = (i + 1) * sizeBits - 1;
int loIndex = (i + 0) * sizeBits; int loIndex = (i + 0) * sizeBits;
uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex);
uint64_t arg2Bits = bits(FpSrcReg2.uqw, hiIndex, loIndex); uint64_t arg2Bits = bits(FpSrcReg2_uqw, hiIndex, loIndex);
if (size == 4) { if (size == 4) {
floatInt fi; floatInt fi;
@ -567,7 +567,7 @@ let {{
result = insertBits(result, hiIndex, loIndex, arg2Bits); result = insertBits(result, hiIndex, loIndex, arg2Bits);
} }
} }
FpDestReg.uqw = result; FpDestReg_uqw = result;
''' '''
class Mmini(MediaOp): class Mmini(MediaOp):
@ -577,15 +577,15 @@ let {{
int size = srcSize; int size = srcSize;
int sizeBits = size * 8; int sizeBits = size * 8;
int items = numItems(size); int items = numItems(size);
uint64_t result = FpDestReg.uqw; uint64_t result = FpDestReg_uqw;
for (int i = 0; i < items; i++) { for (int i = 0; i < items; i++) {
int hiIndex = (i + 1) * sizeBits - 1; int hiIndex = (i + 1) * sizeBits - 1;
int loIndex = (i + 0) * sizeBits; int loIndex = (i + 0) * sizeBits;
uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex);
int64_t arg1 = arg1Bits | int64_t arg1 = arg1Bits |
(0 - (arg1Bits & (ULL(1) << (sizeBits - 1)))); (0 - (arg1Bits & (ULL(1) << (sizeBits - 1))));
uint64_t arg2Bits = bits(FpSrcReg2.uqw, hiIndex, loIndex); uint64_t arg2Bits = bits(FpSrcReg2_uqw, hiIndex, loIndex);
int64_t arg2 = arg2Bits | int64_t arg2 = arg2Bits |
(0 - (arg2Bits & (ULL(1) << (sizeBits - 1)))); (0 - (arg2Bits & (ULL(1) << (sizeBits - 1))));
uint64_t resBits; uint64_t resBits;
@ -605,7 +605,7 @@ let {{
} }
result = insertBits(result, hiIndex, loIndex, resBits); result = insertBits(result, hiIndex, loIndex, resBits);
} }
FpDestReg.uqw = result; FpDestReg_uqw = result;
''' '''
class Mmaxi(MediaOp): class Mmaxi(MediaOp):
@ -615,15 +615,15 @@ let {{
int size = srcSize; int size = srcSize;
int sizeBits = size * 8; int sizeBits = size * 8;
int items = numItems(size); int items = numItems(size);
uint64_t result = FpDestReg.uqw; uint64_t result = FpDestReg_uqw;
for (int i = 0; i < items; i++) { for (int i = 0; i < items; i++) {
int hiIndex = (i + 1) * sizeBits - 1; int hiIndex = (i + 1) * sizeBits - 1;
int loIndex = (i + 0) * sizeBits; int loIndex = (i + 0) * sizeBits;
uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex);
int64_t arg1 = arg1Bits | int64_t arg1 = arg1Bits |
(0 - (arg1Bits & (ULL(1) << (sizeBits - 1)))); (0 - (arg1Bits & (ULL(1) << (sizeBits - 1))));
uint64_t arg2Bits = bits(FpSrcReg2.uqw, hiIndex, loIndex); uint64_t arg2Bits = bits(FpSrcReg2_uqw, hiIndex, loIndex);
int64_t arg2 = arg2Bits | int64_t arg2 = arg2Bits |
(0 - (arg2Bits & (ULL(1) << (sizeBits - 1)))); (0 - (arg2Bits & (ULL(1) << (sizeBits - 1))));
uint64_t resBits; uint64_t resBits;
@ -643,7 +643,7 @@ let {{
} }
result = insertBits(result, hiIndex, loIndex, resBits); result = insertBits(result, hiIndex, loIndex, resBits);
} }
FpDestReg.uqw = result; FpDestReg_uqw = result;
''' '''
class Msqrt(MediaOp): class Msqrt(MediaOp):
@ -668,12 +668,12 @@ let {{
int sizeBits = size * 8; int sizeBits = size * 8;
assert(srcSize == 4 || srcSize == 8); assert(srcSize == 4 || srcSize == 8);
int items = numItems(size); int items = numItems(size);
uint64_t result = FpDestReg.uqw; uint64_t result = FpDestReg_uqw;
for (int i = 0; i < items; i++) { for (int i = 0; i < items; i++) {
int hiIndex = (i + 1) * sizeBits - 1; int hiIndex = (i + 1) * sizeBits - 1;
int loIndex = (i + 0) * sizeBits; int loIndex = (i + 0) * sizeBits;
uint64_t argBits = bits(FpSrcReg1.uqw, hiIndex, loIndex); uint64_t argBits = bits(FpSrcReg1_uqw, hiIndex, loIndex);
if (size == 4) { if (size == 4) {
floatInt fi; floatInt fi;
@ -688,7 +688,7 @@ let {{
} }
result = insertBits(result, hiIndex, loIndex, argBits); result = insertBits(result, hiIndex, loIndex, argBits);
} }
FpDestReg.uqw = result; FpDestReg_uqw = result;
''' '''
class Maddf(MediaOp): class Maddf(MediaOp):
@ -709,13 +709,13 @@ let {{
int sizeBits = size * 8; int sizeBits = size * 8;
assert(srcSize == 4 || srcSize == 8); assert(srcSize == 4 || srcSize == 8);
int items = numItems(size); int items = numItems(size);
uint64_t result = FpDestReg.uqw; uint64_t result = FpDestReg_uqw;
for (int i = 0; i < items; i++) { for (int i = 0; i < items; i++) {
int hiIndex = (i + 1) * sizeBits - 1; int hiIndex = (i + 1) * sizeBits - 1;
int loIndex = (i + 0) * sizeBits; int loIndex = (i + 0) * sizeBits;
uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex);
uint64_t arg2Bits = bits(FpSrcReg2.uqw, hiIndex, loIndex); uint64_t arg2Bits = bits(FpSrcReg2_uqw, hiIndex, loIndex);
uint64_t resBits; uint64_t resBits;
if (size == 4) { if (size == 4) {
@ -734,7 +734,7 @@ let {{
result = insertBits(result, hiIndex, loIndex, resBits); result = insertBits(result, hiIndex, loIndex, resBits);
} }
FpDestReg.uqw = result; FpDestReg_uqw = result;
''' '''
class Msubf(MediaOp): class Msubf(MediaOp):
@ -755,13 +755,13 @@ let {{
int sizeBits = size * 8; int sizeBits = size * 8;
assert(srcSize == 4 || srcSize == 8); assert(srcSize == 4 || srcSize == 8);
int items = numItems(size); int items = numItems(size);
uint64_t result = FpDestReg.uqw; uint64_t result = FpDestReg_uqw;
for (int i = 0; i < items; i++) { for (int i = 0; i < items; i++) {
int hiIndex = (i + 1) * sizeBits - 1; int hiIndex = (i + 1) * sizeBits - 1;
int loIndex = (i + 0) * sizeBits; int loIndex = (i + 0) * sizeBits;
uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex);
uint64_t arg2Bits = bits(FpSrcReg2.uqw, hiIndex, loIndex); uint64_t arg2Bits = bits(FpSrcReg2_uqw, hiIndex, loIndex);
uint64_t resBits; uint64_t resBits;
if (size == 4) { if (size == 4) {
@ -780,7 +780,7 @@ let {{
result = insertBits(result, hiIndex, loIndex, resBits); result = insertBits(result, hiIndex, loIndex, resBits);
} }
FpDestReg.uqw = result; FpDestReg_uqw = result;
''' '''
class Mmulf(MediaOp): class Mmulf(MediaOp):
@ -801,13 +801,13 @@ let {{
int sizeBits = size * 8; int sizeBits = size * 8;
assert(srcSize == 4 || srcSize == 8); assert(srcSize == 4 || srcSize == 8);
int items = numItems(size); int items = numItems(size);
uint64_t result = FpDestReg.uqw; uint64_t result = FpDestReg_uqw;
for (int i = 0; i < items; i++) { for (int i = 0; i < items; i++) {
int hiIndex = (i + 1) * sizeBits - 1; int hiIndex = (i + 1) * sizeBits - 1;
int loIndex = (i + 0) * sizeBits; int loIndex = (i + 0) * sizeBits;
uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex);
uint64_t arg2Bits = bits(FpSrcReg2.uqw, hiIndex, loIndex); uint64_t arg2Bits = bits(FpSrcReg2_uqw, hiIndex, loIndex);
uint64_t resBits; uint64_t resBits;
if (size == 4) { if (size == 4) {
@ -826,7 +826,7 @@ let {{
result = insertBits(result, hiIndex, loIndex, resBits); result = insertBits(result, hiIndex, loIndex, resBits);
} }
FpDestReg.uqw = result; FpDestReg_uqw = result;
''' '''
class Mdivf(MediaOp): class Mdivf(MediaOp):
@ -847,13 +847,13 @@ let {{
int sizeBits = size * 8; int sizeBits = size * 8;
assert(srcSize == 4 || srcSize == 8); assert(srcSize == 4 || srcSize == 8);
int items = numItems(size); int items = numItems(size);
uint64_t result = FpDestReg.uqw; uint64_t result = FpDestReg_uqw;
for (int i = 0; i < items; i++) { for (int i = 0; i < items; i++) {
int hiIndex = (i + 1) * sizeBits - 1; int hiIndex = (i + 1) * sizeBits - 1;
int loIndex = (i + 0) * sizeBits; int loIndex = (i + 0) * sizeBits;
uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex);
uint64_t arg2Bits = bits(FpSrcReg2.uqw, hiIndex, loIndex); uint64_t arg2Bits = bits(FpSrcReg2_uqw, hiIndex, loIndex);
uint64_t resBits; uint64_t resBits;
if (size == 4) { if (size == 4) {
@ -872,7 +872,7 @@ let {{
result = insertBits(result, hiIndex, loIndex, resBits); result = insertBits(result, hiIndex, loIndex, resBits);
} }
FpDestReg.uqw = result; FpDestReg_uqw = result;
''' '''
class Maddi(MediaOp): class Maddi(MediaOp):
@ -881,13 +881,13 @@ let {{
int size = srcSize; int size = srcSize;
int sizeBits = size * 8; int sizeBits = size * 8;
int items = numItems(size); int items = numItems(size);
uint64_t result = FpDestReg.uqw; uint64_t result = FpDestReg_uqw;
for (int i = 0; i < items; i++) { for (int i = 0; i < items; i++) {
int hiIndex = (i + 1) * sizeBits - 1; int hiIndex = (i + 1) * sizeBits - 1;
int loIndex = (i + 0) * sizeBits; int loIndex = (i + 0) * sizeBits;
uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex);
uint64_t arg2Bits = bits(FpSrcReg2.uqw, hiIndex, loIndex); uint64_t arg2Bits = bits(FpSrcReg2_uqw, hiIndex, loIndex);
uint64_t resBits = arg1Bits + arg2Bits; uint64_t resBits = arg1Bits + arg2Bits;
if (ext & 0x2) { if (ext & 0x2) {
@ -909,7 +909,7 @@ let {{
result = insertBits(result, hiIndex, loIndex, resBits); result = insertBits(result, hiIndex, loIndex, resBits);
} }
FpDestReg.uqw = result; FpDestReg_uqw = result;
''' '''
class Msubi(MediaOp): class Msubi(MediaOp):
@ -918,13 +918,13 @@ let {{
int size = srcSize; int size = srcSize;
int sizeBits = size * 8; int sizeBits = size * 8;
int items = numItems(size); int items = numItems(size);
uint64_t result = FpDestReg.uqw; uint64_t result = FpDestReg_uqw;
for (int i = 0; i < items; i++) { for (int i = 0; i < items; i++) {
int hiIndex = (i + 1) * sizeBits - 1; int hiIndex = (i + 1) * sizeBits - 1;
int loIndex = (i + 0) * sizeBits; int loIndex = (i + 0) * sizeBits;
uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex);
uint64_t arg2Bits = bits(FpSrcReg2.uqw, hiIndex, loIndex); uint64_t arg2Bits = bits(FpSrcReg2_uqw, hiIndex, loIndex);
uint64_t resBits = arg1Bits - arg2Bits; uint64_t resBits = arg1Bits - arg2Bits;
if (ext & 0x2) { if (ext & 0x2) {
@ -950,7 +950,7 @@ let {{
result = insertBits(result, hiIndex, loIndex, resBits); result = insertBits(result, hiIndex, loIndex, resBits);
} }
FpDestReg.uqw = result; FpDestReg_uqw = result;
''' '''
class Mmuli(MediaOp): class Mmuli(MediaOp):
@ -960,7 +960,7 @@ let {{
assert(destBits <= 64); assert(destBits <= 64);
assert(destSize >= srcSize); assert(destSize >= srcSize);
int items = numItems(destSize); int items = numItems(destSize);
uint64_t result = FpDestReg.uqw; uint64_t result = FpDestReg_uqw;
for (int i = 0; i < items; i++) { for (int i = 0; i < items; i++) {
int offset = 0; int offset = 0;
@ -972,8 +972,8 @@ let {{
} }
int srcHiIndex = (i + 1) * srcBits - 1 + offset; int srcHiIndex = (i + 1) * srcBits - 1 + offset;
int srcLoIndex = (i + 0) * srcBits + offset; int srcLoIndex = (i + 0) * srcBits + offset;
uint64_t arg1Bits = bits(FpSrcReg1.uqw, srcHiIndex, srcLoIndex); uint64_t arg1Bits = bits(FpSrcReg1_uqw, srcHiIndex, srcLoIndex);
uint64_t arg2Bits = bits(FpSrcReg2.uqw, srcHiIndex, srcLoIndex); uint64_t arg2Bits = bits(FpSrcReg2_uqw, srcHiIndex, srcLoIndex);
uint64_t resBits; uint64_t resBits;
if (signedOp()) { if (signedOp()) {
@ -996,7 +996,7 @@ let {{
int destLoIndex = (i + 0) * destBits; int destLoIndex = (i + 0) * destBits;
result = insertBits(result, destHiIndex, destLoIndex, resBits); result = insertBits(result, destHiIndex, destLoIndex, resBits);
} }
FpDestReg.uqw = result; FpDestReg_uqw = result;
''' '''
class Mavg(MediaOp): class Mavg(MediaOp):
@ -1005,18 +1005,18 @@ let {{
int size = srcSize; int size = srcSize;
int sizeBits = size * 8; int sizeBits = size * 8;
int items = numItems(size); int items = numItems(size);
uint64_t result = FpDestReg.uqw; uint64_t result = FpDestReg_uqw;
for (int i = 0; i < items; i++) { for (int i = 0; i < items; i++) {
int hiIndex = (i + 1) * sizeBits - 1; int hiIndex = (i + 1) * sizeBits - 1;
int loIndex = (i + 0) * sizeBits; int loIndex = (i + 0) * sizeBits;
uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex);
uint64_t arg2Bits = bits(FpSrcReg2.uqw, hiIndex, loIndex); uint64_t arg2Bits = bits(FpSrcReg2_uqw, hiIndex, loIndex);
uint64_t resBits = (arg1Bits + arg2Bits + 1) / 2; uint64_t resBits = (arg1Bits + arg2Bits + 1) / 2;
result = insertBits(result, hiIndex, loIndex, resBits); result = insertBits(result, hiIndex, loIndex, resBits);
} }
FpDestReg.uqw = result; FpDestReg_uqw = result;
''' '''
class Msad(MediaOp): class Msad(MediaOp):
@ -1028,14 +1028,14 @@ let {{
for (int i = 0; i < items; i++) { for (int i = 0; i < items; i++) {
int hiIndex = (i + 1) * srcBits - 1; int hiIndex = (i + 1) * srcBits - 1;
int loIndex = (i + 0) * srcBits; int loIndex = (i + 0) * srcBits;
uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex);
uint64_t arg2Bits = bits(FpSrcReg2.uqw, hiIndex, loIndex); uint64_t arg2Bits = bits(FpSrcReg2_uqw, hiIndex, loIndex);
int64_t resBits = arg1Bits - arg2Bits; int64_t resBits = arg1Bits - arg2Bits;
if (resBits < 0) if (resBits < 0)
resBits = -resBits; resBits = -resBits;
sum += resBits; sum += resBits;
} }
FpDestReg.uqw = sum & mask(destSize * 8); FpDestReg_uqw = sum & mask(destSize * 8);
''' '''
class Msrl(MediaOp): class Msrl(MediaOp):
@ -1045,13 +1045,13 @@ let {{
int size = srcSize; int size = srcSize;
int sizeBits = size * 8; int sizeBits = size * 8;
int items = numItems(size); int items = numItems(size);
uint64_t shiftAmt = op2.uqw; uint64_t shiftAmt = op2_uqw;
uint64_t result = FpDestReg.uqw; uint64_t result = FpDestReg_uqw;
for (int i = 0; i < items; i++) { for (int i = 0; i < items; i++) {
int hiIndex = (i + 1) * sizeBits - 1; int hiIndex = (i + 1) * sizeBits - 1;
int loIndex = (i + 0) * sizeBits; int loIndex = (i + 0) * sizeBits;
uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex);
uint64_t resBits; uint64_t resBits;
if (shiftAmt >= sizeBits) { if (shiftAmt >= sizeBits) {
resBits = 0; resBits = 0;
@ -1062,7 +1062,7 @@ let {{
result = insertBits(result, hiIndex, loIndex, resBits); result = insertBits(result, hiIndex, loIndex, resBits);
} }
FpDestReg.uqw = result; FpDestReg_uqw = result;
''' '''
class Msra(MediaOp): class Msra(MediaOp):
@ -1072,13 +1072,13 @@ let {{
int size = srcSize; int size = srcSize;
int sizeBits = size * 8; int sizeBits = size * 8;
int items = numItems(size); int items = numItems(size);
uint64_t shiftAmt = op2.uqw; uint64_t shiftAmt = op2_uqw;
uint64_t result = FpDestReg.uqw; uint64_t result = FpDestReg_uqw;
for (int i = 0; i < items; i++) { for (int i = 0; i < items; i++) {
int hiIndex = (i + 1) * sizeBits - 1; int hiIndex = (i + 1) * sizeBits - 1;
int loIndex = (i + 0) * sizeBits; int loIndex = (i + 0) * sizeBits;
uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex);
uint64_t resBits; uint64_t resBits;
if (shiftAmt >= sizeBits) { if (shiftAmt >= sizeBits) {
if (bits(arg1Bits, sizeBits - 1)) if (bits(arg1Bits, sizeBits - 1))
@ -1093,7 +1093,7 @@ let {{
result = insertBits(result, hiIndex, loIndex, resBits); result = insertBits(result, hiIndex, loIndex, resBits);
} }
FpDestReg.uqw = result; FpDestReg_uqw = result;
''' '''
class Msll(MediaOp): class Msll(MediaOp):
@ -1103,13 +1103,13 @@ let {{
int size = srcSize; int size = srcSize;
int sizeBits = size * 8; int sizeBits = size * 8;
int items = numItems(size); int items = numItems(size);
uint64_t shiftAmt = op2.uqw; uint64_t shiftAmt = op2_uqw;
uint64_t result = FpDestReg.uqw; uint64_t result = FpDestReg_uqw;
for (int i = 0; i < items; i++) { for (int i = 0; i < items; i++) {
int hiIndex = (i + 1) * sizeBits - 1; int hiIndex = (i + 1) * sizeBits - 1;
int loIndex = (i + 0) * sizeBits; int loIndex = (i + 0) * sizeBits;
uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex);
uint64_t resBits; uint64_t resBits;
if (shiftAmt >= sizeBits) { if (shiftAmt >= sizeBits) {
resBits = 0; resBits = 0;
@ -1119,7 +1119,7 @@ let {{
result = insertBits(result, hiIndex, loIndex, resBits); result = insertBits(result, hiIndex, loIndex, resBits);
} }
FpDestReg.uqw = result; FpDestReg_uqw = result;
''' '''
class Cvtf2i(MediaOp): class Cvtf2i(MediaOp):
@ -1157,12 +1157,12 @@ let {{
} else { } else {
items = numItems(destSize); items = numItems(destSize);
} }
uint64_t result = FpDestReg.uqw; uint64_t result = FpDestReg_uqw;
for (int i = 0; i < items; i++) { for (int i = 0; i < items; i++) {
int srcHiIndex = srcStart + (i + 1) * srcSizeBits - 1; int srcHiIndex = srcStart + (i + 1) * srcSizeBits - 1;
int srcLoIndex = srcStart + (i + 0) * srcSizeBits; int srcLoIndex = srcStart + (i + 0) * srcSizeBits;
uint64_t argBits = bits(FpSrcReg1.uqw, srcHiIndex, srcLoIndex); uint64_t argBits = bits(FpSrcReg1_uqw, srcHiIndex, srcLoIndex);
double arg; double arg;
if (srcSize == 4) { if (srcSize == 4) {
@ -1191,7 +1191,7 @@ let {{
int destLoIndex = destStart + (i + 0) * destSizeBits; int destLoIndex = destStart + (i + 0) * destSizeBits;
result = insertBits(result, destHiIndex, destLoIndex, argBits); result = insertBits(result, destHiIndex, destLoIndex, argBits);
} }
FpDestReg.uqw = result; FpDestReg_uqw = result;
''' '''
class Cvti2f(MediaOp): class Cvti2f(MediaOp):
@ -1229,12 +1229,12 @@ let {{
} else { } else {
items = numItems(destSize); items = numItems(destSize);
} }
uint64_t result = FpDestReg.uqw; uint64_t result = FpDestReg_uqw;
for (int i = 0; i < items; i++) { for (int i = 0; i < items; i++) {
int srcHiIndex = srcStart + (i + 1) * srcSizeBits - 1; int srcHiIndex = srcStart + (i + 1) * srcSizeBits - 1;
int srcLoIndex = srcStart + (i + 0) * srcSizeBits; int srcLoIndex = srcStart + (i + 0) * srcSizeBits;
uint64_t argBits = bits(FpSrcReg1.uqw, srcHiIndex, srcLoIndex); uint64_t argBits = bits(FpSrcReg1_uqw, srcHiIndex, srcLoIndex);
int64_t sArg = argBits | int64_t sArg = argBits |
(0 - (argBits & (ULL(1) << (srcSizeBits - 1)))); (0 - (argBits & (ULL(1) << (srcSizeBits - 1))));
@ -1253,7 +1253,7 @@ let {{
int destLoIndex = destStart + (i + 0) * destSizeBits; int destLoIndex = destStart + (i + 0) * destSizeBits;
result = insertBits(result, destHiIndex, destLoIndex, argBits); result = insertBits(result, destHiIndex, destLoIndex, argBits);
} }
FpDestReg.uqw = result; FpDestReg_uqw = result;
''' '''
class Cvtf2f(MediaOp): class Cvtf2f(MediaOp):
@ -1291,12 +1291,12 @@ let {{
} else { } else {
items = numItems(destSize); items = numItems(destSize);
} }
uint64_t result = FpDestReg.uqw; uint64_t result = FpDestReg_uqw;
for (int i = 0; i < items; i++) { for (int i = 0; i < items; i++) {
int srcHiIndex = srcStart + (i + 1) * srcSizeBits - 1; int srcHiIndex = srcStart + (i + 1) * srcSizeBits - 1;
int srcLoIndex = srcStart + (i + 0) * srcSizeBits; int srcLoIndex = srcStart + (i + 0) * srcSizeBits;
uint64_t argBits = bits(FpSrcReg1.uqw, srcHiIndex, srcLoIndex); uint64_t argBits = bits(FpSrcReg1_uqw, srcHiIndex, srcLoIndex);
double arg; double arg;
if (srcSize == 4) { if (srcSize == 4) {
@ -1321,7 +1321,7 @@ let {{
int destLoIndex = destStart + (i + 0) * destSizeBits; int destLoIndex = destStart + (i + 0) * destSizeBits;
result = insertBits(result, destHiIndex, destLoIndex, argBits); result = insertBits(result, destHiIndex, destLoIndex, argBits);
} }
FpDestReg.uqw = result; FpDestReg_uqw = result;
''' '''
class Mcmpi2r(MediaOp): class Mcmpi2r(MediaOp):
@ -1341,15 +1341,15 @@ let {{
int size = srcSize; int size = srcSize;
int sizeBits = size * 8; int sizeBits = size * 8;
int items = numItems(size); int items = numItems(size);
uint64_t result = FpDestReg.uqw; uint64_t result = FpDestReg_uqw;
for (int i = 0; i < items; i++) { for (int i = 0; i < items; i++) {
int hiIndex = (i + 1) * sizeBits - 1; int hiIndex = (i + 1) * sizeBits - 1;
int loIndex = (i + 0) * sizeBits; int loIndex = (i + 0) * sizeBits;
uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex);
int64_t arg1 = arg1Bits | int64_t arg1 = arg1Bits |
(0 - (arg1Bits & (ULL(1) << (sizeBits - 1)))); (0 - (arg1Bits & (ULL(1) << (sizeBits - 1))));
uint64_t arg2Bits = bits(FpSrcReg2.uqw, hiIndex, loIndex); uint64_t arg2Bits = bits(FpSrcReg2_uqw, hiIndex, loIndex);
int64_t arg2 = arg2Bits | int64_t arg2 = arg2Bits |
(0 - (arg2Bits & (ULL(1) << (sizeBits - 1)))); (0 - (arg2Bits & (ULL(1) << (sizeBits - 1))));
@ -1360,7 +1360,7 @@ let {{
result = insertBits(result, hiIndex, loIndex, resBits); result = insertBits(result, hiIndex, loIndex, resBits);
} }
FpDestReg.uqw = result; FpDestReg_uqw = result;
''' '''
class Mcmpf2r(MediaOp): class Mcmpf2r(MediaOp):
@ -1380,13 +1380,13 @@ let {{
int size = srcSize; int size = srcSize;
int sizeBits = size * 8; int sizeBits = size * 8;
int items = numItems(size); int items = numItems(size);
uint64_t result = FpDestReg.uqw; uint64_t result = FpDestReg_uqw;
for (int i = 0; i < items; i++) { for (int i = 0; i < items; i++) {
int hiIndex = (i + 1) * sizeBits - 1; int hiIndex = (i + 1) * sizeBits - 1;
int loIndex = (i + 0) * sizeBits; int loIndex = (i + 0) * sizeBits;
uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex);
uint64_t arg2Bits = bits(FpSrcReg2.uqw, hiIndex, loIndex); uint64_t arg2Bits = bits(FpSrcReg2_uqw, hiIndex, loIndex);
double arg1, arg2; double arg1, arg2;
if (size == 4) { if (size == 4) {
@ -1442,7 +1442,7 @@ let {{
result = insertBits(result, hiIndex, loIndex, resBits); result = insertBits(result, hiIndex, loIndex, resBits);
} }
FpDestReg.uqw = result; FpDestReg_uqw = result;
''' '''
class Mcmpf2rf(MediaOp): class Mcmpf2rf(MediaOp):
@ -1468,8 +1468,8 @@ let {{
int sizeBits = size * 8; int sizeBits = size * 8;
double arg1, arg2; double arg1, arg2;
uint64_t arg1Bits = bits(FpSrcReg1.uqw, sizeBits - 1, 0); uint64_t arg1Bits = bits(FpSrcReg1_uqw, sizeBits - 1, 0);
uint64_t arg2Bits = bits(FpSrcReg2.uqw, sizeBits - 1, 0); uint64_t arg2Bits = bits(FpSrcReg2_uqw, sizeBits - 1, 0);
if (size == 4) { if (size == 4) {
floatInt fi; floatInt fi;
fi.i = arg1Bits; fi.i = arg1Bits;

4
src/arch/x86/isa/microops/regop.isa
View file

@ -244,7 +244,7 @@ let {{
# If op2 is used anywhere, make register and immediate versions # If op2 is used anywhere, make register and immediate versions
# of this code. # of this code.
matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?") matcher = re.compile(r"(?<!\w)(?P<prefix>s?)op2(?P<typeQual>_[^\W_]+)?")
match = matcher.search(allCode + allBigCode) match = matcher.search(allCode + allBigCode)
if match: if match:
typeQual = "" typeQual = ""
@ -364,7 +364,7 @@ let {{
# If op2 is used anywhere, make register and immediate versions # If op2 is used anywhere, make register and immediate versions
# of this code. # of this code.
matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") matcher = re.compile(r"op2(?P<typeQual>_[^\W_]+)?")
if matcher.search(allCode): if matcher.search(allCode):
microopClasses[name + 'i'] = cls microopClasses[name + 'i'] = cls
return cls return cls