Fix some more mem leaks, still some left
Update retry mechanism src/mem/cache/base_cache.cc: Rework the retry mechanism src/mem/cache/base_cache.hh: Rework the retry mechanism Try to fix memory bug src/mem/cache/cache_impl.hh: Rework upgrades to not be blocked by slave src/mem/cache/miss/mshr_queue.cc: Fix mem leak on writebacks --HG-- extra : convert_revision : 3cec234ee441edf398ec8d0f51a0c5d7ada1e2be
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9e008d73d5
commit
995146ead7
4 changed files with 68 additions and 54 deletions
55
src/mem/cache/base_cache.cc
vendored
55
src/mem/cache/base_cache.cc
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@ -45,6 +45,7 @@ BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache,
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{
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blocked = false;
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cshrRetry = NULL;
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waitingOnRetry = false;
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//Start ports at null if more than one is created we should panic
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//cpuSidePort = NULL;
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//memSidePort = NULL;
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@ -113,25 +114,30 @@ void
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BaseCache::CachePort::recvRetry()
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{
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Packet *pkt;
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assert(waitingOnRetry);
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if (!drainList.empty()) {
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//We have some responses to drain first
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bool result = true;
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while (result && !drainList.empty()) {
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result = sendTiming(drainList.front());
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if (result)
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if (sendTiming(drainList.front())) {
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drainList.pop_front();
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if (!drainList.empty() ||
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!isCpuSide && cache->doMasterRequest() ||
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isCpuSide && cache->doSlaveRequest()) {
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BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this);
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reqCpu->schedule(curTick + 1);
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}
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waitingOnRetry = false;
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}
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if (!result) return;
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}
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else if (!isCpuSide)
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{
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if (!cache->doMasterRequest()) return;
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assert(cache->doMasterRequest());
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pkt = cache->getPacket();
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MSHR* mshr = (MSHR*)pkt->senderState;
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bool success = sendTiming(pkt);
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DPRINTF(Cache, "Address %x was %s in sending the timing request\n",
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pkt->getAddr(), success ? "succesful" : "unsuccesful");
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cache->sendResult(pkt, mshr, success);
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waitingOnRetry = !success;
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if (success && cache->doMasterRequest())
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{
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//Still more to issue, rerequest in 1 cycle
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@ -140,12 +146,14 @@ BaseCache::CachePort::recvRetry()
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reqCpu->schedule(curTick + 1);
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}
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}
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else if (cshrRetry)
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else
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{
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assert(cshrRetry);
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//pkt = cache->getCoherencePacket();
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//We save the packet, no reordering on CSHRS
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pkt = cshrRetry;
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bool success = sendTiming(pkt);
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waitingOnRetry = !success;
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if (success && cache->doSlaveRequest())
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{
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//Still more to issue, rerequest in 1 cycle
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@ -154,7 +162,6 @@ BaseCache::CachePort::recvRetry()
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reqCpu->schedule(curTick + 1);
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cshrRetry = NULL;
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}
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}
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return;
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}
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@ -198,23 +205,22 @@ BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort, Packet *_pkt)
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void
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BaseCache::CacheEvent::process()
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{
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if (!cachePort->drainList.empty()) {
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//We have some responses to drain first
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bool result = true;
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while (result && !cachePort->drainList.empty()) {
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result = cachePort->sendTiming(cachePort->drainList.front());
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if (result)
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cachePort->drainList.pop_front();
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}
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if (!result) return;
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}
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if (!pkt)
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{
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if (!cachePort->isCpuSide)
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if (cachePort->waitingOnRetry) return;
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//We have some responses to drain first
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if (!cachePort->drainList.empty()) {
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if (cachePort->sendTiming(cachePort->drainList.front())) {
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cachePort->drainList.pop_front();
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if (!cachePort->drainList.empty() ||
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!cachePort->isCpuSide && cachePort->cache->doMasterRequest() ||
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cachePort->isCpuSide && cachePort->cache->doSlaveRequest())
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this->schedule(curTick + 1);
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}
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else cachePort->waitingOnRetry = true;
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}
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else if (!cachePort->isCpuSide)
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{
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//For now, doMasterRequest somehow is still getting set
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if (!cachePort->cache->doMasterRequest()) return;
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//MSHR
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pkt = cachePort->cache->getPacket();
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MSHR* mshr = (MSHR*) pkt->senderState;
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@ -222,6 +228,7 @@ BaseCache::CacheEvent::process()
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DPRINTF(Cache, "Address %x was %s in sending the timing request\n",
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pkt->getAddr(), success ? "succesful" : "unsuccesful");
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cachePort->cache->sendResult(pkt, mshr, success);
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cachePort->waitingOnRetry = !success;
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if (success && cachePort->cache->doMasterRequest())
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{
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//Still more to issue, rerequest in 1 cycle
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@ -237,6 +244,7 @@ BaseCache::CacheEvent::process()
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if (!success) {
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//Need to send on a retry
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cachePort->cshrRetry = pkt;
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cachePort->waitingOnRetry = true;
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}
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else if (cachePort->cache->doSlaveRequest())
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{
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@ -255,12 +263,13 @@ BaseCache::CacheEvent::process()
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pkt->result = Packet::Success;
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pkt->makeTimingResponse();
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if (!cachePort->drainList.empty()) {
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//Already blocked waiting for bus, just append
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//Already have a list, just append
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cachePort->drainList.push_back(pkt);
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}
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else if (!cachePort->sendTiming(pkt)) {
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//It failed, save it to list of drain events
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cachePort->drainList.push_back(pkt);
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cachePort->waitingOnRetry = true;
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}
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}
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12
src/mem/cache/base_cache.hh
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12
src/mem/cache/base_cache.hh
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@ -112,6 +112,8 @@ class BaseCache : public MemObject
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bool isCpuSide;
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bool waitingOnRetry;
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std::list<Packet *> drainList;
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Packet *cshrRetry;
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@ -465,7 +467,7 @@ class BaseCache : public MemObject
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*/
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void setMasterRequest(RequestCause cause, Tick time)
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{
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if (!doMasterRequest())
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if (!doMasterRequest() && memSidePort->drainList.empty())
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{
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BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(memSidePort);
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reqCpu->schedule(time);
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@ -527,6 +529,10 @@ class BaseCache : public MemObject
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CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
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reqCpu->schedule(time);
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}
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else {
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if (pkt->cmd == Packet::Writeback) delete pkt->req;
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delete pkt;
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}
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}
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/**
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@ -543,6 +549,10 @@ class BaseCache : public MemObject
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CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
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reqCpu->schedule(time);
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}
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else {
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if (pkt->cmd == Packet::Writeback) delete pkt->req;
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delete pkt;
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}
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}
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/**
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18
src/mem/cache/cache_impl.hh
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18
src/mem/cache/cache_impl.hh
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@ -193,19 +193,6 @@ Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
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prefetcher->handleMiss(pkt, curTick);
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}
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if (!pkt->req->isUncacheable()) {
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if (pkt->isInvalidate() && !pkt->isRead()
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&& !pkt->isWrite()) {
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//Upgrade or Invalidate
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//Look into what happens if two slave caches on bus
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DPRINTF(Cache, "%s %x ? blk_addr: %x\n", pkt->cmdString(),
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pkt->getAddr() & (((ULL(1))<<48)-1),
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pkt->getAddr() & ~((Addr)blkSize - 1));
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pkt->flags |= SATISFIED;
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//Invalidates/Upgrades need no response if they get the bus
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// return MA_HIT; //@todo, return values
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return true;
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}
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blk = tags->handleAccess(pkt, lat, writebacks);
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} else {
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size = pkt->getSize();
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@ -241,7 +228,10 @@ Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
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// clear dirty bit if write through
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if (pkt->needsResponse())
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respond(pkt, curTick+lat);
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// return MA_HIT;
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if (pkt->cmd == Packet::Writeback) {
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//Signal that you can kill the pkt/req
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pkt->flags |= SATISFIED;
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}
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return true;
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}
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5
src/mem/cache/miss/mshr_queue.cc
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5
src/mem/cache/miss/mshr_queue.cc
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@ -215,6 +215,11 @@ MSHRQueue::markInService(MSHR* mshr)
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//assert(mshr == pendingList.front());
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if (!(mshr->pkt->needsResponse() || mshr->pkt->cmd == Packet::UpgradeReq)) {
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assert(mshr->getNumTargets() == 0);
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if ((mshr->pkt->flags & SATISFIED) && (mshr->pkt->cmd == Packet::Writeback)) {
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//Writeback hit, so delete it
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//otherwise the consumer will delete it
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delete mshr->pkt->req;
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}
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deallocate(mshr);
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return;
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}
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