diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index fe256a291..e3424a85b 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -20,7 +20,7 @@ eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/usr/local/google/home/gabeblack/gem5/x86_system_files/binaries/x86_64-vmlinux-2.6.22.9 kernel_addr_check=true load_addr_mask=18446744073709551615 load_offset=0 @@ -28,7 +28,7 @@ mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/usr/local/google/home/gabeblack/gem5/hg/gem5/tests/halt.sh smbios_table=system.smbios_table symbolfile= work_begin_ckpt_count=0 @@ -1560,7 +1560,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-x86.img +image_file=/usr/local/google/home/gabeblack/gem5/x86_system_files/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1583,7 +1583,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-bigswap2.img +image_file=/usr/local/google/home/gabeblack/gem5/x86_system_files/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr index 0a8bc6fbe..0aaa4f921 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr @@ -1,7 +1,7 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting terminal connections -warn: Reading current count from inactive timer. warn: Sockets disabled, not accepting gdb connections +warn: Reading current count from inactive timer. warn: Don't know what interrupt to clear for console. warn: x86 cpuid: unknown family 0x8086 warn: x86 cpuid: unknown family 0x8086 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index 3b996a550..91003600d 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 29 2014 09:18:07 -gem5 started Oct 29 2014 09:27:02 -gem5 executing on u200540-lin -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re /work/gem5.latest/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing +gem5 compiled Nov 16 2014 23:19:52 +gem5 started Nov 16 2014 23:20:03 +gem5 executing on gabeblackz620.mtv.corp.google.com +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re /usr/local/google/home/gabeblack/gem5/hg/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /usr/local/google/home/gabeblack/gem5/x86_system_files/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 5125902116500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 560862ac3..a6e63eaeb 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.125902 # Nu sim_ticks 5125902116500 # Number of ticks simulated final_tick 5125902116500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 182847 # Simulator instruction rate (inst/s) -host_op_rate 361437 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2297162464 # Simulator tick rate (ticks/s) -host_mem_usage 805240 # Number of bytes of host memory used -host_seconds 2231.41 # Real time elapsed on the host +host_inst_rate 225212 # Simulator instruction rate (inst/s) +host_op_rate 445179 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2829401321 # Simulator tick rate (ticks/s) +host_mem_usage 748772 # Number of bytes of host memory used +host_seconds 1811.66 # Real time elapsed on the host sim_insts 408006726 # Number of instructions simulated sim_ops 806511598 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini index 5c0ccd72f..d43104caf 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini @@ -20,7 +20,7 @@ eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/usr/local/google/home/gabeblack/gem5/x86_system_files/binaries/x86_64-vmlinux-2.6.22.9 kernel_addr_check=true load_addr_mask=18446744073709551615 load_offset=0 @@ -28,7 +28,7 @@ mem_mode=atomic mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/usr/local/google/home/gabeblack/gem5/hg/gem5/tests/halt.sh smbios_table=system.smbios_table symbolfile= work_begin_ckpt_count=0 @@ -1616,7 +1616,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-x86.img +image_file=/usr/local/google/home/gabeblack/gem5/x86_system_files/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1639,7 +1639,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-bigswap2.img +image_file=/usr/local/google/home/gabeblack/gem5/x86_system_files/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json index 3c9f7ff5e..3be878044 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json @@ -2,7 +2,7 @@ "name": null, "sim_quantum": 0, "system": { - "kernel": "/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9", + "kernel": "/usr/local/google/home/gabeblack/gem5/x86_system_files/binaries/x86_64-vmlinux-2.6.22.9", "l2c": { "is_top_level": false, "prefetcher": null, @@ -145,7 +145,7 @@ "type": "Bridge" }, "symbolfile": "", - "readfile": "/scratch/nilay/GEM5/gem5/tests/halt.sh", + "readfile": "/usr/local/google/home/gabeblack/gem5/hg/gem5/tests/halt.sh", "intel_mp_table": { "oem_table_addr": 0, "name": "intel_mp_table", @@ -1176,7 +1176,7 @@ "eventq_index": 0, "cxx_class": "RawDiskImage", "path": "system.pc.south_bridge.ide.disks0.image.child", - "image_file": "/scratch/nilay/GEM5/system/disks/linux-x86.img", + "image_file": "/usr/local/google/home/gabeblack/gem5/x86_system_files/disks/linux-x86.img", "type": "RawDiskImage" }, "path": "system.pc.south_bridge.ide.disks0.image", @@ -1204,7 +1204,7 @@ "eventq_index": 0, "cxx_class": "RawDiskImage", "path": "system.pc.south_bridge.ide.disks1.image.child", - "image_file": "/scratch/nilay/GEM5/system/disks/linux-bigswap2.img", + "image_file": "/usr/local/google/home/gabeblack/gem5/x86_system_files/disks/linux-bigswap2.img", "type": "RawDiskImage" }, "path": "system.pc.south_bridge.ide.disks1.image", @@ -1629,8 +1629,9 @@ "IDD3N": "0.057", "name": "physmem", "tXSDLL": 0, - "tXAW": 30000, + "device_size": 536870912, "dll": true, + "tXAW": 30000, "write_low_thresh_perc": 50, "range": "0:134217727", "VDD2": "0.0", diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr index b4d02041b..2cf33b630 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr @@ -1,7 +1,7 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting terminal connections -warn: Reading current count from inactive timer. warn: Sockets disabled, not accepting gdb connections +warn: Reading current count from inactive timer. warn: Don't know what interrupt to clear for console. warn: x86 cpuid: unknown family 0x8086 warn: x86 cpuid: unknown family 0x8086 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout index ca2891ded..498a02071 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 29 2014 09:18:07 -gem5 started Oct 29 2014 09:28:19 -gem5 executing on u200540-lin -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /work/gem5.latest/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full +gem5 compiled Nov 16 2014 23:19:52 +gem5 started Nov 16 2014 23:20:03 +gem5 executing on gabeblackz620.mtv.corp.google.com +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /usr/local/google/home/gabeblack/gem5/hg/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full Global frequency set at 1000000000000 ticks per second 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index 847df0bf1..4de64b96e 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -4,16 +4,15 @@ sim_seconds 5.137752 # Nu sim_ticks 5137751757500 # Number of ticks simulated final_tick 5137751757500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 311526 # Simulator instruction rate (inst/s) -host_op_rate 619354 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6572918502 # Simulator tick rate (ticks/s) -host_mem_usage 927072 # Number of bytes of host memory used -host_seconds 781.65 # Real time elapsed on the host +host_inst_rate 342085 # Simulator instruction rate (inst/s) +host_op_rate 680107 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7217672543 # Simulator tick rate (ticks/s) +host_mem_usage 932836 # Number of bytes of host memory used +host_seconds 711.83 # Real time elapsed on the host sim_insts 243506025 # Number of instructions simulated sim_ops 484120527 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 475328 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 5564736 # Number of bytes read from this memory @@ -23,6 +22,7 @@ system.physmem.bytes_read::cpu1.data 2113344 # Nu system.physmem.bytes_read::cpu2.dtb.walker 2688 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.inst 362880 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 2752000 # Number of bytes read from this memory +system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory system.physmem.bytes_read::total 11429696 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 475328 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 130048 # Number of instructions bytes read from this memory @@ -31,7 +31,6 @@ system.physmem.bytes_inst_read::total 968256 # Nu system.physmem.bytes_written::writebacks 6180416 # Number of bytes written to this memory system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory system.physmem.bytes_written::total 9170496 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 7427 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 86949 # Number of read requests responded to by this memory @@ -41,11 +40,11 @@ system.physmem.num_reads::cpu1.data 33021 # Nu system.physmem.num_reads::cpu2.dtb.walker 42 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.inst 5670 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 43000 # Number of read requests responded to by this memory +system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory system.physmem.num_reads::total 178589 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 96569 # Number of write requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory system.physmem.num_writes::total 143289 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 5518 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.inst 92517 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.data 1083107 # Total read bandwidth from this memory (bytes/s) @@ -55,6 +54,7 @@ system.physmem.bw_read::cpu1.data 411336 # To system.physmem.bw_read::cpu2.dtb.walker 523 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.inst 70630 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.data 535643 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5518 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 2224649 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 92517 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 25312 # Instruction read bandwidth from this memory (bytes/s) @@ -64,7 +64,6 @@ system.physmem.bw_write::writebacks 1202942 # Wr system.physmem.bw_write::pc.south_bridge.ide 581982 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 1784924 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 1202942 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 587501 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 92517 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.data 1083107 # Total bandwidth to/from this memory (bytes/s) @@ -74,6 +73,7 @@ system.physmem.bw_total::cpu1.data 411336 # To system.physmem.bw_total::cpu2.dtb.walker 523 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.inst 70630 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.data 535643 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 587501 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 4009573 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 84209 # Number of read requests accepted system.physmem.writeReqs 74716 # Number of write requests accepted @@ -329,68 +329,982 @@ system.physmem.totalEnergy::0 3434046565050 # T system.physmem.totalEnergy::1 3434197896405 # Total energy per rank (pJ) system.physmem.averagePower::0 668.395092 # Core power per rank (mW) system.physmem.averagePower::1 668.424547 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 5119571 # Transaction distribution -system.membus.trans_dist::ReadResp 5119569 # Transaction distribution -system.membus.trans_dist::WriteReq 13900 # Transaction distribution -system.membus.trans_dist::WriteResp 13900 # Transaction distribution -system.membus.trans_dist::Writeback 96569 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1658 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1658 # Transaction distribution -system.membus.trans_dist::ReadExReq 130179 # Transaction distribution -system.membus.trans_dist::ReadExResp 130179 # Transaction distribution -system.membus.trans_dist::MessageReq 1687 # Transaction distribution -system.membus.trans_dist::MessageResp 1687 # Transaction distribution -system.membus.trans_dist::BadAddressError 2 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3374 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3374 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7129206 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3039990 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 456177 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 10625377 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94957 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 94957 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10723708 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6748 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6748 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3570760 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6079977 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17581760 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 27232497 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3029312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 3029312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 30268557 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 291 # Total snoops (count) -system.membus.snoop_fanout::samples 323999 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 323999 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 323999 # Request fanout histogram -system.membus.reqLayer0.occupancy 162958500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 314938500 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 2254000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 804193000 # Layer occupancy (ticks) -system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 2000 # Layer occupancy (ticks) -system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1127000 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1664243698 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 28678745 # Layer occupancy (ticks) -system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu0.numCycles 818767223 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.committedInsts 72040073 # Number of instructions committed +system.cpu0.committedOps 146798683 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 134677148 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu0.num_func_calls 957492 # number of times a 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WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.032789 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018926 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.858602 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.851553 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.538331 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.048955 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.067467 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.034849 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.061749 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.089507 # mshr miss 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latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14500.945786 # average SoftPFReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18961.110333 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17122.063777 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17689.433539 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17814.154316 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16491.045652 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16881.648825 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency 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Cycle average of tags in use +system.cpu0.icache.tags.total_refs 130156159 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 866925 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 150.135432 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 149014386250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 138.994027 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 266.522548 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 105.323634 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.271473 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.520552 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.205710 # Average percentage of cache occupancy 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number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.847328 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 22465 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 22465 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 22465 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 22465 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 22465 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 22465 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 162109 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 376303 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 538412 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 162109 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 376303 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 538412 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 162109 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 376303 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 538412 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1920905250 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4627637688 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6548542938 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1920905250 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4627637688 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6548542938 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1920905250 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4627637688 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6548542938 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004084 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.111225 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004109 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004084 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.111225 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.004109 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004084 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.111225 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.004109 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11849.467025 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12297.636979 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12162.698710 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11849.467025 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12297.636979 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12162.698710 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11849.467025 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12297.636979 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12162.698710 # average overall mshr miss latency +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.numCycles 2606022983 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.committedInsts 35939339 # Number of instructions committed +system.cpu1.committedOps 69774923 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 64844483 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu1.num_func_calls 499287 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6580388 # number of instructions that are conditional controls +system.cpu1.num_int_insts 64844483 # number of integer instructions +system.cpu1.num_fp_insts 0 # number of float instructions +system.cpu1.num_int_register_reads 120226227 # number of times the integer registers were read +system.cpu1.num_int_register_writes 55826198 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 36586824 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 27309791 # number of times the CC registers were written +system.cpu1.num_mem_refs 4927873 # number of memory refs +system.cpu1.num_load_insts 3050339 # Number of load instructions +system.cpu1.num_store_insts 1877534 # Number of store instructions +system.cpu1.num_idle_cycles 2477290986.248718 # Number of idle cycles +system.cpu1.num_busy_cycles 128731996.751282 # Number of busy cycles +system.cpu1.not_idle_fraction 0.049398 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.950602 # Percentage of idle cycles +system.cpu1.Branches 7259898 # Number of branches fetched +system.cpu1.op_class::No_OpClass 35461 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 64754697 92.80% 92.86% # Class of executed instruction +system.cpu1.op_class::IntMult 31756 0.05% 92.90% # Class of executed instruction +system.cpu1.op_class::IntDiv 25505 0.04% 92.94% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 92.94% # Class of executed instruction +system.cpu1.op_class::MemRead 3050339 4.37% 97.31% # Class of executed instruction +system.cpu1.op_class::MemWrite 1877534 2.69% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 69775292 # Class of executed instruction +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu2.branchPred.lookups 29000272 # Number of BP lookups +system.cpu2.branchPred.condPredicted 29000272 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 311632 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26370508 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25723888 # Number of BTB hits +system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu2.branchPred.BTBHitPct 97.547943 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 573459 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 63282 # Number of incorrect RAS predictions. +system.cpu2.numCycles 153009050 # number of cpu cycles simulated +system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu2.fetch.icacheStallCycles 10521285 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 142969715 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 29000272 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26297347 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 141031314 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 650011 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 92984 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 4408 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 9006 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 47091 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 2529 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 579 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3383247 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 163781 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 3234 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 152033550 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.852472 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.031588 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 97124192 63.88% 63.88% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 819598 0.54% 64.42% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23594190 15.52% 79.94% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 577537 0.38% 80.32% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 790978 0.52% 80.84% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 823076 0.54% 81.38% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 560198 0.37% 81.75% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 693420 0.46% 82.21% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27050361 17.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::total 152033550 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.189533 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.934387 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9712542 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 92934302 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 23280371 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5017317 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 325657 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 278875678 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 325657 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 11857648 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 75889768 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4419845 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 25919685 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 12857653 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 277706863 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 221466 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 5888159 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 42783 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 4808995 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 331833488 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 605194394 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 371618079 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 36 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 320107208 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11726280 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 151218 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 152719 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 24489304 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6338862 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3553328 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 367719 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 319565 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 275826769 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 413139 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 273878584 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 98557 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 8364175 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 12972199 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 61453 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 152033550 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.801435 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.398557 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 89826062 59.08% 59.08% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5325607 3.50% 62.59% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3883778 2.55% 65.14% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 3618974 2.38% 67.52% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 22318323 14.68% 82.20% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 2568868 1.69% 83.89% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23837030 15.68% 99.57% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 450577 0.30% 99.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 204331 0.13% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 152033550 # Number of insts issued each cycle +system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 1765790 86.71% 86.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 6 0.00% 86.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 95 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 86.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 213483 10.48% 97.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 57008 2.80% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu2.iq.FU_type_0::No_OpClass 75484 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 263736524 96.30% 96.32% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 54819 0.02% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 47031 0.02% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6686249 2.44% 98.80% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3278477 1.20% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::total 273878584 # Type of FU issued +system.cpu2.iq.rate 1.789950 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 2036382 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.007435 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 701925596 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 284608270 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 272313229 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 61 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 68 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 275839453 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 29 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 685704 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu2.iew.lsq.thread0.squashedLoads 1161006 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 6104 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4803 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 634153 # Number of stores squashed +system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu2.iew.lsq.thread0.rescheduledLoads 755552 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 21313 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu2.iew.iewSquashCycles 325657 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 70767994 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 1741893 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 276239908 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 40444 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6338884 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3553328 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 236248 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 194416 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 1250638 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4803 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 177191 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 184398 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 361589 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 273320009 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6554812 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 510377 # Number of squashed instructions skipped in execute +system.cpu2.iew.exec_swp 0 # number of swp insts executed +system.cpu2.iew.exec_nop 0 # number of nop insts executed +system.cpu2.iew.exec_refs 9748811 # number of memory reference insts executed +system.cpu2.iew.exec_branches 27755327 # Number of branches executed +system.cpu2.iew.exec_stores 3193999 # Number of stores executed +system.cpu2.iew.exec_rate 1.786300 # Inst execution rate +system.cpu2.iew.wb_sent 273134840 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 272313245 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 212432379 # num instructions producing a value +system.cpu2.iew.wb_consumers 348339663 # num instructions consuming a value +system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu2.iew.wb_rate 1.779720 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.609843 # average fanout of values written-back +system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu2.commit.commitSquashedInsts 8691419 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 351686 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 314047 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 150733678 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.774964 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.652543 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 93656646 62.13% 62.13% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4148238 2.75% 64.89% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1235888 0.82% 65.71% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24514613 16.26% 81.97% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1002757 0.67% 82.63% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 665638 0.44% 83.08% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 467092 0.31% 83.39% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23101150 15.33% 98.71% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1941656 1.29% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::total 150733678 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 135526613 # Number of instructions committed +system.cpu2.commit.committedOps 267546921 # Number of ops (including micro ops) committed +system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu2.commit.refs 8097053 # Number of memory references committed +system.cpu2.commit.loads 5177878 # Number of loads committed +system.cpu2.commit.membars 162019 # Number of memory barriers committed +system.cpu2.commit.branches 27358633 # Number of branches committed +system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 244351653 # Number of committed integer instructions. +system.cpu2.commit.function_calls 425746 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 44568 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 259307312 96.92% 96.94% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 52493 0.02% 96.96% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 45495 0.02% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5177878 1.94% 98.91% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2919175 1.09% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::total 267546921 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1941656 # number cycles where commit BW limit reached +system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu2.rob.rob_reads 425004820 # The number of ROB reads +system.cpu2.rob.rob_writes 553782312 # The number of ROB writes +system.cpu2.timesIdled 113608 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 975500 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4910108147 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 135526613 # Number of Instructions Simulated +system.cpu2.committedOps 267546921 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.128996 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.128996 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.885742 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.885742 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 363608614 # number of integer regfile reads +system.cpu2.int_regfile_writes 218247524 # number of integer regfile writes +system.cpu2.fp_regfile_reads 72984 # number of floating regfile reads +system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes +system.cpu2.cc_regfile_reads 138904210 # number of cc regfile reads +system.cpu2.cc_regfile_writes 106846664 # number of cc regfile writes +system.cpu2.misc_regfile_reads 88678814 # number of misc regfile reads +system.cpu2.misc_regfile_writes 129757 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 3554542 # Transaction distribution +system.iobus.trans_dist::ReadResp 3554542 # Transaction distribution +system.iobus.trans_dist::WriteReq 57685 # Transaction distribution +system.iobus.trans_dist::WriteResp 33021 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 24664 # Transaction distribution +system.iobus.trans_dist::MessageReq 1687 # Transaction distribution +system.iobus.trans_dist::MessageResp 1687 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7085054 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1126 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27782 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 7129206 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95248 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95248 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3374 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3374 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 7227828 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3542527 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2252 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13891 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 3570760 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027776 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027776 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6748 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6748 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 6605284 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2693792 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 27000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 4846000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 4000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 25000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) +system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 142528000 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 333000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 134000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 10264000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 199614020 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 1032000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 303080000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer1.occupancy 27344255 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer2.occupancy 1127000 # Layer occupancy (ticks) +system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) +system.iocache.tags.replacements 47569 # number of replacements +system.iocache.tags.tagsinuse 0.092434 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 5000571333009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.092434 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005777 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005777 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 428616 # Number of tag accesses +system.iocache.tags.data_accesses 428616 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses +system.iocache.ReadReq_misses::total 904 # number of ReadReq misses +system.iocache.demand_misses::pc.south_bridge.ide 904 # number of demand (read+write) misses +system.iocache.demand_misses::total 904 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 904 # number of overall misses +system.iocache.overall_misses::total 904 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 131931527 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 131931527 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 131931527 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 131931527 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 131931527 # number of overall miss cycles +system.iocache.overall_miss_latency::total 131931527 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::pc.south_bridge.ide 904 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 904 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 904 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 904 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145941.954646 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 145941.954646 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 145941.954646 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 145941.954646 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 145941.954646 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 145941.954646 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.076923 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 46720 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 734 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 734 # number of ReadReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 734 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 734 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 734 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 734 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 93740027 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 93740027 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 1329860248 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1329860248 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 93740027 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 93740027 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 93740027 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 93740027 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.811947 # mshr miss rate for ReadReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.811947 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.811947 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 127711.208447 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 127711.208447 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 127711.208447 # average overall mshr miss latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 104648 # number of replacements system.l2c.tags.tagsinuse 64825.327064 # Cycle average of tags in use system.l2c.tags.total_refs 3691316 # Total number of references to valid blocks. @@ -796,91 +1710,67 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 47569 # number of replacements -system.iocache.tags.tagsinuse 0.092434 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000571333009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.092434 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005777 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005777 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428616 # Number of tag accesses -system.iocache.tags.data_accesses 428616 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses -system.iocache.ReadReq_misses::total 904 # number of ReadReq misses -system.iocache.demand_misses::pc.south_bridge.ide 904 # number of demand (read+write) misses -system.iocache.demand_misses::total 904 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 904 # number of overall misses -system.iocache.overall_misses::total 904 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 131931527 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 131931527 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 131931527 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 131931527 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 131931527 # number of overall miss cycles -system.iocache.overall_miss_latency::total 131931527 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 904 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 904 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 904 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 904 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145941.954646 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 145941.954646 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 145941.954646 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 145941.954646 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 145941.954646 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 145941.954646 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.076923 # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 46720 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 734 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 734 # number of ReadReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 734 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 734 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 734 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 734 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 93740027 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 93740027 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 1329860248 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1329860248 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 93740027 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 93740027 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 93740027 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 93740027 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.811947 # mshr miss rate for ReadReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.811947 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.811947 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 127711.208447 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 127711.208447 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 127711.208447 # average overall mshr miss latency -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 5119571 # Transaction distribution +system.membus.trans_dist::ReadResp 5119569 # Transaction distribution +system.membus.trans_dist::WriteReq 13900 # Transaction distribution +system.membus.trans_dist::WriteResp 13900 # Transaction distribution +system.membus.trans_dist::Writeback 96569 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1658 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1658 # Transaction distribution +system.membus.trans_dist::ReadExReq 130179 # Transaction distribution +system.membus.trans_dist::ReadExResp 130179 # Transaction distribution +system.membus.trans_dist::MessageReq 1687 # Transaction distribution +system.membus.trans_dist::MessageResp 1687 # Transaction distribution +system.membus.trans_dist::BadAddressError 2 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3374 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3374 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7129206 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3039990 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 456177 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 10625377 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94957 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 94957 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10723708 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6748 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6748 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3570760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6079977 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17581760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 27232497 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3029312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 3029312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30268557 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 291 # Total snoops (count) +system.membus.snoop_fanout::samples 323999 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 323999 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 323999 # Request fanout histogram +system.membus.reqLayer0.occupancy 162958500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 314938500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 2254000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer3.occupancy 804193000 # Layer occupancy (ticks) +system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer4.occupancy 2000 # Layer occupancy (ticks) +system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.membus.respLayer0.occupancy 1127000 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 1664243698 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer4.occupancy 28678745 # Layer occupancy (ticks) +system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). @@ -940,896 +1830,6 @@ system.toL2Bus.respLayer2.occupancy 24091410 # La system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer3.occupancy 80681637 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 3554542 # Transaction distribution -system.iobus.trans_dist::ReadResp 3554542 # Transaction distribution -system.iobus.trans_dist::WriteReq 57685 # Transaction distribution -system.iobus.trans_dist::WriteResp 33021 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 24664 # Transaction distribution -system.iobus.trans_dist::MessageReq 1687 # Transaction distribution -system.iobus.trans_dist::MessageResp 1687 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7085054 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1126 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27782 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 7129206 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95248 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95248 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3374 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3374 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 7227828 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3542527 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2252 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13891 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 3570760 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027776 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027776 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6748 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6748 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 6605284 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2693792 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 27000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 4846000 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 4000 # Layer occupancy (ticks) -system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks) -system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 25000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) -system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 142528000 # Layer occupancy (ticks) -system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 333000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 134000 # Layer occupancy (ticks) -system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 10264000 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 199614020 # Layer occupancy (ticks) -system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 1032000 # Layer occupancy (ticks) -system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 303080000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 27344255 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1127000 # Layer occupancy (ticks) -system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 818767223 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 72040073 # Number of instructions committed -system.cpu0.committedOps 146798683 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 134677148 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 957492 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14259376 # number of instructions that are conditional controls -system.cpu0.num_int_insts 134677148 # number of integer instructions -system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 247199145 # number of times the integer registers were read -system.cpu0.num_int_register_writes 115729599 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 83822967 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 55940767 # number of times the CC registers were written -system.cpu0.num_mem_refs 13836630 # number of memory refs -system.cpu0.num_load_insts 10218166 # Number of load instructions -system.cpu0.num_store_insts 3618464 # Number of store instructions -system.cpu0.num_idle_cycles 776544159.837226 # Number of idle cycles -system.cpu0.num_busy_cycles 42223063.162775 # Number of busy cycles -system.cpu0.not_idle_fraction 0.051569 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.948431 # Percentage of idle cycles -system.cpu0.Branches 15573109 # Number of branches fetched -system.cpu0.op_class::No_OpClass 95028 0.06% 0.06% # Class of executed instruction -system.cpu0.op_class::IntAlu 132757091 90.43% 90.50% # Class of executed instruction -system.cpu0.op_class::IntMult 59427 0.04% 90.54% # Class of executed instruction -system.cpu0.op_class::IntDiv 51115 0.03% 90.57% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::MemRead 10218166 6.96% 97.54% # Class of executed instruction -system.cpu0.op_class::MemWrite 3618464 2.46% 100.00% # Class of executed instruction -system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 146799291 # Class of executed instruction -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 866413 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.840210 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 130156159 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 866925 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 150.135432 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 149014386250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 138.994027 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 266.522548 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 105.323634 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.271473 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.520552 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.205710 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997735 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 131912504 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 131912504 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 87639896 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 39531787 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2984476 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 130156159 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 87639896 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 39531787 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2984476 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 130156159 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 87639896 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 39531787 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2984476 # number of overall hits -system.cpu0.icache.overall_hits::total 130156159 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 328528 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 162109 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 398768 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 889405 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 328528 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 162109 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 398768 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 889405 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 328528 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 162109 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 398768 # number of overall misses -system.cpu0.icache.overall_misses::total 889405 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2245844750 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5606326194 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 7852170944 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 2245844750 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 5606326194 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 7852170944 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 2245844750 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 5606326194 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 7852170944 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 87968424 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 39693896 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 3383244 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 131045564 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 87968424 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 39693896 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 3383244 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 131045564 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 87968424 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 39693896 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 3383244 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 131045564 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003735 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004084 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.117866 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.006787 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003735 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004084 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.117866 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.006787 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003735 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004084 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.117866 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.006787 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13853.917734 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14059.117567 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8828.566226 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13853.917734 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14059.117567 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8828.566226 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13853.917734 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14059.117567 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8828.566226 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4938 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 262 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.847328 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 22465 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 22465 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 22465 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 22465 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 22465 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 22465 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 162109 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 376303 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 538412 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 162109 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 376303 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 538412 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 162109 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 376303 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 538412 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1920905250 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4627637688 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6548542938 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1920905250 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4627637688 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6548542938 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1920905250 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4627637688 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6548542938 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004084 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.111225 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004109 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004084 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.111225 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.004109 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004084 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.111225 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.004109 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11849.467025 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12297.636979 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12162.698710 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11849.467025 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12297.636979 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12162.698710 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11849.467025 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12297.636979 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12162.698710 # average overall mshr miss latency -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1637866 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999423 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 19673585 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1638378 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 12.007965 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 126.297276 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 280.648639 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 105.053508 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.246674 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.548142 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.205183 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 270 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 221 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88453877 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88453877 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5010669 # number of ReadReq hits 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of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 6686897 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 19611911 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8511278 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 4444586 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 6715926 # number of overall hits -system.cpu0.dcache.overall_hits::total 19671790 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 362952 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 164891 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 772037 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1299880 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 133960 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 65129 # number of WriteReq misses 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overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1088915 # number of overall misses -system.cpu0.dcache.overall_misses::total 2032078 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2296036750 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 11919855793 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 14215892543 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2581335822 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 3855689962 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 6437025784 # number of WriteReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 4877372572 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 15775545755 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 20652918327 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 4877372572 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 15775545755 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 20652918327 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5373621 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 2788153 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4670620 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 12832394 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3614306 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1875866 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2914829 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 8405001 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 172200 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 74881 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 219392 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 466473 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8987927 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 4664019 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7585449 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 21237395 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 9160127 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 4738900 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7804841 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 21703868 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.067543 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.059140 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.165296 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.101297 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.037064 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.034719 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.043404 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.038739 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.882329 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.858616 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.867684 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.871635 # miss rate for SoftPFReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.055287 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.049318 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.118457 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.076539 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.070834 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.062106 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.139518 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.093627 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13924.572900 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15439.487736 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 10936.311462 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39634.200157 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30476.148773 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 19769.492340 # average WriteReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21204.123867 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17556.630841 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 12705.703856 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16572.003275 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14487.398700 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 10163.447627 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 128010 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 27734 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4.615634 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 1547592 # number of writebacks -system.cpu0.dcache.writebacks::total 1547592 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 59 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 355847 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 355906 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1633 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 30941 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 32574 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1692 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 386788 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 388480 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 1692 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 386788 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 388480 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 164832 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 416190 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 581022 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 63496 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 95574 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 159070 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 64293 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 186824 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 251117 # number of SoftPFReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 228328 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 511764 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 740092 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 292621 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 698588 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 991209 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1964999750 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5660700319 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7625700069 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2364352650 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3101755528 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5466108178 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 883443250 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2757990753 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3641434003 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4329352400 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 8762455847 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13091808247 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 5212795650 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11520446600 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 16733242250 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30452050000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 32985877000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63437927000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 577982500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 687759500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1265742000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31030032500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33673636500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64703669000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.059119 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.089108 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.045278 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033849 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.032789 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018926 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.858602 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.851553 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.538331 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.048955 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.067467 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.034849 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.061749 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.089507 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.045670 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11921.227371 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13601.240585 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13124.632233 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 37236.245590 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32453.967899 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34362.910530 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13740.893254 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14762.507777 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14500.945786 # average SoftPFReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18961.110333 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17122.063777 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17689.433539 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17814.154316 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16491.045652 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16881.648825 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2606022983 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 35939339 # Number of instructions committed -system.cpu1.committedOps 69774923 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 64844483 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 499287 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6580388 # number of instructions that are conditional controls -system.cpu1.num_int_insts 64844483 # number of integer instructions -system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 120226227 # number of times the integer registers were read -system.cpu1.num_int_register_writes 55826198 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 36586824 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 27309791 # number of times the CC registers were written -system.cpu1.num_mem_refs 4927873 # number of memory refs -system.cpu1.num_load_insts 3050339 # Number of load instructions -system.cpu1.num_store_insts 1877534 # Number of store instructions -system.cpu1.num_idle_cycles 2477290986.248718 # Number of idle cycles -system.cpu1.num_busy_cycles 128731996.751282 # Number of busy cycles -system.cpu1.not_idle_fraction 0.049398 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.950602 # Percentage of idle cycles -system.cpu1.Branches 7259898 # Number of branches fetched -system.cpu1.op_class::No_OpClass 35461 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 64754697 92.80% 92.86% # Class of executed instruction -system.cpu1.op_class::IntMult 31756 0.05% 92.90% # Class of executed instruction -system.cpu1.op_class::IntDiv 25505 0.04% 92.94% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 92.94% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 92.94% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 92.94% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 92.94% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 92.94% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 92.94% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 92.94% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 92.94% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 92.94% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 92.94% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 92.94% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 92.94% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 92.94% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 92.94% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 92.94% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 92.94% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 92.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 92.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 92.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 92.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 92.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 92.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 92.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 92.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 92.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 92.94% # Class of executed instruction -system.cpu1.op_class::MemRead 3050339 4.37% 97.31% # Class of executed instruction -system.cpu1.op_class::MemWrite 1877534 2.69% 100.00% # Class of executed instruction -system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 69775292 # Class of executed instruction -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 29000272 # Number of BP lookups -system.cpu2.branchPred.condPredicted 29000272 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 311632 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26370508 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25723888 # Number of BTB hits -system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.547943 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 573459 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 63282 # Number of incorrect RAS predictions. -system.cpu2.numCycles 153009050 # number of cpu cycles simulated -system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 10521285 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 142969715 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 29000272 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26297347 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 141031314 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 650011 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 92984 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 4408 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 9006 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 47091 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 2529 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 579 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3383247 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 163781 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 3234 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 152033550 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.852472 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.031588 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 97124192 63.88% 63.88% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 819598 0.54% 64.42% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23594190 15.52% 79.94% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 577537 0.38% 80.32% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 790978 0.52% 80.84% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 823076 0.54% 81.38% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 560198 0.37% 81.75% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 693420 0.46% 82.21% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27050361 17.79% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 152033550 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.189533 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.934387 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9712542 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 92934302 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 23280371 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 5017317 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 325657 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 278875678 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 325657 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 11857648 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 75889768 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4419845 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 25919685 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 12857653 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 277706863 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 221466 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 5888159 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 42783 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 4808995 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 331833488 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 605194394 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 371618079 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 36 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 320107208 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 11726280 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 151218 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 152719 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 24489304 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6338862 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3553328 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 367719 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 319565 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 275826769 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 413139 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 273878584 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 98557 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 8364175 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 12972199 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 61453 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 152033550 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.801435 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.398557 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 89826062 59.08% 59.08% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5325607 3.50% 62.59% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3883778 2.55% 65.14% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 3618974 2.38% 67.52% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 22318323 14.68% 82.20% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 2568868 1.69% 83.89% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23837030 15.68% 99.57% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 450577 0.30% 99.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 204331 0.13% 100.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 152033550 # Number of insts issued each cycle -system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 1765790 86.71% 86.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 6 0.00% 86.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 95 0.00% 86.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 86.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 86.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 86.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 86.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 86.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 86.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 86.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 86.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 86.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 86.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 86.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 86.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 86.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 86.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 86.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 86.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 86.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 86.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 86.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 86.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 86.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 86.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 86.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 86.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 86.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 86.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 213483 10.48% 97.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 57008 2.80% 100.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 75484 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 263736524 96.30% 96.32% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 54819 0.02% 96.34% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 47031 0.02% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6686249 2.44% 98.80% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3278477 1.20% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 273878584 # Type of FU issued -system.cpu2.iq.rate 1.789950 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 2036382 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.007435 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 701925596 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 284608270 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 272313229 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 61 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 68 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 275839453 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 29 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 685704 # Number of loads that had data forwarded from stores -system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1161006 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6104 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4803 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 634153 # Number of stores squashed -system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 755552 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 21313 # Number of times an access to memory failed due to the cache being blocked -system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 325657 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 70767994 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 1741893 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 276239908 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 40444 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6338884 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3553328 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 236248 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 194416 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 1250638 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4803 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 177191 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 184398 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 361589 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 273320009 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6554812 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 510377 # Number of squashed instructions skipped in execute -system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 9748811 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27755327 # Number of branches executed -system.cpu2.iew.exec_stores 3193999 # Number of stores executed -system.cpu2.iew.exec_rate 1.786300 # Inst execution rate -system.cpu2.iew.wb_sent 273134840 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 272313245 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 212432379 # num instructions producing a value -system.cpu2.iew.wb_consumers 348339663 # num instructions consuming a value -system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.779720 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.609843 # average fanout of values written-back -system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 8691419 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 351686 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 314047 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 150733678 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.774964 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.652543 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 93656646 62.13% 62.13% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4148238 2.75% 64.89% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1235888 0.82% 65.71% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24514613 16.26% 81.97% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1002757 0.67% 82.63% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 665638 0.44% 83.08% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 467092 0.31% 83.39% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23101150 15.33% 98.71% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1941656 1.29% 100.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 150733678 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 135526613 # Number of instructions committed -system.cpu2.commit.committedOps 267546921 # Number of ops (including micro ops) committed -system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8097053 # Number of memory references committed -system.cpu2.commit.loads 5177878 # Number of loads committed -system.cpu2.commit.membars 162019 # Number of memory barriers committed -system.cpu2.commit.branches 27358633 # Number of branches committed -system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 244351653 # Number of committed integer instructions. -system.cpu2.commit.function_calls 425746 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 44568 0.02% 0.02% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 259307312 96.92% 96.94% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 52493 0.02% 96.96% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 45495 0.02% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5177878 1.94% 98.91% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2919175 1.09% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 267546921 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1941656 # number cycles where commit BW limit reached -system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 425004820 # The number of ROB reads -system.cpu2.rob.rob_writes 553782312 # The number of ROB writes -system.cpu2.timesIdled 113608 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 975500 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4910108147 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 135526613 # Number of Instructions Simulated -system.cpu2.committedOps 267546921 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.128996 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.128996 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.885742 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.885742 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 363608614 # number of integer regfile reads -system.cpu2.int_regfile_writes 218247524 # number of integer regfile writes -system.cpu2.fp_regfile_reads 72984 # number of floating regfile reads -system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes -system.cpu2.cc_regfile_reads 138904210 # number of cc regfile reads -system.cpu2.cc_regfile_writes 106846664 # number of cc regfile writes -system.cpu2.misc_regfile_reads 88678814 # number of misc regfile reads -system.cpu2.misc_regfile_writes 129757 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini index 9627624a2..e4451124c 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini @@ -20,7 +20,7 @@ eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/usr/local/google/home/gabeblack/gem5/x86_system_files/binaries/x86_64-vmlinux-2.6.22.9 kernel_addr_check=true load_addr_mask=18446744073709551615 load_offset=0 @@ -28,7 +28,7 @@ mem_mode=atomic mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +readfile=/usr/local/google/home/gabeblack/gem5/hg/gem5/tests/halt.sh smbios_table=system.smbios_table symbolfile= work_begin_ckpt_count=0 @@ -1184,7 +1184,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img +image_file=/usr/local/google/home/gabeblack/gem5/x86_system_files/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1207,7 +1207,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/usr/local/google/home/gabeblack/gem5/x86_system_files/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr index bb1874a4f..49ecbe6ac 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr @@ -1,6 +1,6 @@ warn: Sockets disabled, not accepting terminal connections -warn: Reading current count from inactive timer. warn: Sockets disabled, not accepting gdb connections +warn: Reading current count from inactive timer. warn: Don't know what interrupt to clear for console. warn: x86 cpuid: unknown family 0x8086 warn: Tried to clear PCI interrupt 14 diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout index 04f5d2889..b2d8b456f 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:10:34 -gem5 started Jan 22 2014 17:30:13 -gem5 executing on u200540-lin -command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic +gem5 compiled Nov 16 2014 23:19:52 +gem5 started Nov 16 2014 23:20:03 +gem5 executing on gabeblackz620.mtv.corp.google.com +command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re /usr/local/google/home/gabeblack/gem5/hg/gem5/tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /usr/local/google/home/gabeblack/gem5/x86_system_files/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5112126264500 because m5_exit instruction encountered +Exiting @ tick 5112155173500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 52d540f15..1c8458cfb 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,40 +4,40 @@ sim_seconds 5.112155 # Nu sim_ticks 5112155173500 # Number of ticks simulated final_tick 5112155173500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1096092 # Simulator instruction rate (inst/s) -host_op_rate 2244090 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28012193632 # Simulator tick rate (ticks/s) -host_mem_usage 637772 # Number of bytes of host memory used -host_seconds 182.50 # Real time elapsed on the host +host_inst_rate 1971048 # Simulator instruction rate (inst/s) +host_op_rate 4035436 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50372945560 # Simulator tick rate (ticks/s) +host_mem_usage 594916 # Number of bytes of host memory used +host_seconds 101.49 # Real time elapsed on the host sim_insts 200033988 # Number of instructions simulated sim_ops 409540726 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 852288 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10678208 # Number of bytes read from this memory +system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory system.physmem.bytes_read::total 11559232 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 852288 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 852288 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 6294336 # Number of bytes written to this memory system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory system.physmem.bytes_written::total 9284416 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 13317 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 166847 # Number of read requests responded to by this memory +system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory system.physmem.num_reads::total 180613 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 98349 # Number of write requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory system.physmem.num_writes::total 145069 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 166718 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 2088788 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 2261127 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 166718 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 166718 # Instruction read bandwidth from this memory (bytes/s) @@ -45,167 +45,12 @@ system.physmem.bw_write::writebacks 1231249 # Wr system.physmem.bw_write::pc.south_bridge.ide 584896 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 1816145 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 1231249 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 590442 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 166718 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2088788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 590442 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 4077272 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 13903768 # Transaction distribution -system.membus.trans_dist::ReadResp 13903768 # Transaction distribution -system.membus.trans_dist::WriteReq 13911 # Transaction distribution -system.membus.trans_dist::WriteResp 13911 # Transaction distribution -system.membus.trans_dist::Writeback 98349 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2525 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2096 # Transaction distribution -system.membus.trans_dist::ReadExReq 134620 # Transaction distribution -system.membus.trans_dist::ReadExResp 134615 # Transaction distribution -system.membus.trans_dist::MessageReq 1696 # Transaction distribution -system.membus.trans_dist::MessageResp 1696 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3392 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044188 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 463315 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28205747 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95256 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 95256 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28304395 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028212 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 15396485 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17825216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43249913 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3048192 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 3048192 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 46304889 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 328677 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 328677 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 328677 # Request fanout histogram -system.iocache.tags.replacements 47573 # number of replacements -system.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47589 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4994875221009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042448 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428652 # Number of tag accesses -system.iocache.tags.data_accesses 428652 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::pc.south_bridge.ide 908 # number of ReadReq misses -system.iocache.ReadReq_misses::total 908 # number of ReadReq misses -system.iocache.demand_misses::pc.south_bridge.ide 908 # number of demand (read+write) misses -system.iocache.demand_misses::total 908 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 908 # number of overall misses -system.iocache.overall_misses::total 908 # number of overall misses -system.iocache.ReadReq_accesses::pc.south_bridge.ide 908 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 908 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 908 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 908 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 908 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 46720 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). -system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. -system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. -system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. -system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. -system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. -system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 10012030 # Transaction distribution -system.iobus.trans_dist::ReadResp 10012030 # Transaction distribution -system.iobus.trans_dist::WriteReq 57692 # Transaction distribution -system.iobus.trans_dist::WriteResp 10972 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.iobus.trans_dist::MessageReq 1696 # Transaction distribution -system.iobus.trans_dist::MessageResp 1696 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 19999988 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1098 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27812 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 20044188 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95256 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95256 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3392 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3392 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 20142836 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 9999994 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2196 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13906 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 10028212 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027808 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027808 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6784 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6784 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 13062804 # Cumulative packet size per connected master and slave (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.numCycles 10224314318 # number of cpu cycles simulated @@ -270,6 +115,124 @@ system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class::total 409541761 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu.dcache.tags.replacements 1623441 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.999462 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20193263 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1623953 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.434635 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.999462 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 233 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 88892882 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88892882 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 12028464 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12028464 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8103633 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8103633 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 58902 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 58902 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 20132097 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20132097 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20190999 # number of overall hits +system.cpu.dcache.overall_hits::total 20190999 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 905998 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 905998 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 317173 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 317173 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 403059 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 403059 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1223171 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1223171 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1626230 # number of overall misses +system.cpu.dcache.overall_misses::total 1626230 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 12934462 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12934462 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8420806 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8420806 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 461961 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 461961 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21355268 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21355268 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21817229 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21817229 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070045 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070045 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037665 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037665 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872496 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.872496 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.057277 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.057277 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074539 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074539 # miss rate for overall accesses +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 1536849 # number of writebacks +system.cpu.dcache.writebacks::total 1536849 # number of writebacks +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dtb_walker_cache.tags.replacements 8174 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.013947 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 12516 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 8188 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.528578 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5101311942500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.013947 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313372 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313372 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 53153 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 53153 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12517 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 12517 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12517 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 12517 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12517 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 12517 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9373 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 9373 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9373 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 9373 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9373 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 9373 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21890 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21890 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21890 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21890 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21890 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21890 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.428186 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.428186 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.428186 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.428186 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.428186 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.428186 # miss rate for overall accesses +system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed +system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed +system.cpu.dtb_walker_cache.writebacks::writebacks 2794 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2794 # number of writebacks +system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 791952 # number of replacements system.cpu.icache.tags.tagsinuse 510.663108 # Cycle average of tags in use system.cpu.icache.tags.total_refs 243645979 # Total number of references to valid blocks. @@ -376,157 +339,6 @@ system.cpu.itb_walker_cache.cache_copies 0 # nu system.cpu.itb_walker_cache.writebacks::writebacks 802 # number of writebacks system.cpu.itb_walker_cache.writebacks::total 802 # number of writebacks system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 8174 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.013947 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 12516 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 8188 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.528578 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5101311942500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.013947 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313372 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313372 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 53153 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 53153 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12517 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 12517 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12517 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 12517 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12517 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 12517 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9373 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 9373 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9373 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 9373 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9373 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 9373 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21890 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21890 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21890 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21890 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21890 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21890 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.428186 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.428186 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.428186 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.428186 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.428186 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.428186 # miss rate for overall accesses -system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed -system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2794 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2794 # number of writebacks -system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1623441 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.999462 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20193263 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1623953 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.434635 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.999462 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 233 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88892882 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88892882 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 12028464 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12028464 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8103633 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8103633 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 58902 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 58902 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 20132097 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20132097 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20190999 # number of overall hits -system.cpu.dcache.overall_hits::total 20190999 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 905998 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 905998 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 317173 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 317173 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 403059 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 403059 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1223171 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1223171 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1626230 # number of overall misses -system.cpu.dcache.overall_misses::total 1626230 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 12934462 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12934462 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8420806 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8420806 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 461961 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 461961 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21355268 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21355268 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21817229 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21817229 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070045 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070045 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037665 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037665 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872496 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.872496 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.057277 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.057277 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074539 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074539 # miss rate for overall accesses -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1536849 # number of writebacks -system.cpu.dcache.writebacks::total 1536849 # number of writebacks -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 15972786 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 15972786 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13911 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13911 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1540445 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2264 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2264 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 314909 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 314909 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1584942 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32531741 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9962 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 21540 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 34148185 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50718144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227716857 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 344448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 778688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 279558137 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 48008 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4020727 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.011846 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.108191 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 3973099 98.82% 98.82% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 47628 1.18% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4020727 # Request fanout histogram system.cpu.l2cache.tags.replacements 106197 # number of replacements system.cpu.l2cache.tags.tagsinuse 64825.457913 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3461872 # Total number of references to valid blocks. @@ -644,5 +456,193 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 98349 # number of writebacks system.cpu.l2cache.writebacks::total 98349 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 15972786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 15972786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13911 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13911 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1540445 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2264 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2264 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 314909 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 314909 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1584942 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32531741 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9962 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 21540 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 34148185 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50718144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227716857 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 344448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 778688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 279558137 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 48008 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4020727 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.011846 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.108191 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 3973099 98.82% 98.82% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 47628 1.18% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4020727 # Request fanout histogram +system.iobus.trans_dist::ReadReq 10012030 # Transaction distribution +system.iobus.trans_dist::ReadResp 10012030 # Transaction distribution +system.iobus.trans_dist::WriteReq 57692 # Transaction distribution +system.iobus.trans_dist::WriteResp 10972 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution +system.iobus.trans_dist::MessageReq 1696 # Transaction distribution +system.iobus.trans_dist::MessageResp 1696 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 19999988 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1098 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27812 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 20044188 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95256 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95256 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3392 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3392 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 20142836 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 9999994 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2196 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13906 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 10028212 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027808 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027808 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6784 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6784 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 13062804 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.replacements 47573 # number of replacements +system.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 47589 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 4994875221009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042448 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 428652 # Number of tag accesses +system.iocache.tags.data_accesses 428652 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::pc.south_bridge.ide 908 # number of ReadReq misses +system.iocache.ReadReq_misses::total 908 # number of ReadReq misses +system.iocache.demand_misses::pc.south_bridge.ide 908 # number of demand (read+write) misses +system.iocache.demand_misses::total 908 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 908 # number of overall misses +system.iocache.overall_misses::total 908 # number of overall misses +system.iocache.ReadReq_accesses::pc.south_bridge.ide 908 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::pc.south_bridge.ide 908 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 908 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 908 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 908 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 46720 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 13903768 # Transaction distribution +system.membus.trans_dist::ReadResp 13903768 # Transaction distribution +system.membus.trans_dist::WriteReq 13911 # Transaction distribution +system.membus.trans_dist::WriteResp 13911 # Transaction distribution +system.membus.trans_dist::Writeback 98349 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2525 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2096 # Transaction distribution +system.membus.trans_dist::ReadExReq 134620 # Transaction distribution +system.membus.trans_dist::ReadExResp 134615 # Transaction distribution +system.membus.trans_dist::MessageReq 1696 # Transaction distribution +system.membus.trans_dist::MessageResp 1696 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3392 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044188 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 463315 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28205747 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95256 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 95256 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28304395 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028212 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 15396485 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17825216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43249913 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3048192 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 3048192 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 46304889 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 328677 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 328677 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 328677 # Request fanout histogram +system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. +system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. +system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. +system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. +system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. +system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini index b395adf7f..ccaf4ac7e 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini @@ -20,7 +20,7 @@ eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/usr/local/google/home/gabeblack/gem5/x86_system_files/binaries/x86_64-vmlinux-2.6.22.9 kernel_addr_check=true load_addr_mask=18446744073709551615 load_offset=0 @@ -28,7 +28,7 @@ mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/usr/local/google/home/gabeblack/gem5/hg/gem5/tests/halt.sh smbios_table=system.smbios_table symbolfile= work_begin_ckpt_count=0 @@ -1180,7 +1180,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-x86.img +image_file=/usr/local/google/home/gabeblack/gem5/x86_system_files/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1203,7 +1203,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-bigswap2.img +image_file=/usr/local/google/home/gabeblack/gem5/x86_system_files/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr index f30c0bc17..231efd798 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr @@ -1,7 +1,7 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting terminal connections -warn: Reading current count from inactive timer. warn: Sockets disabled, not accepting gdb connections +warn: Reading current count from inactive timer. warn: Don't know what interrupt to clear for console. warn: x86 cpuid: unknown family 0x8086 warn: Tried to clear PCI interrupt 14 diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout index a4565b1b8..f0d75ee6e 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 29 2014 09:18:07 -gem5 started Oct 29 2014 09:26:24 -gem5 executing on u200540-lin -command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re /work/gem5.latest/tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing +gem5 compiled Nov 16 2014 23:19:52 +gem5 started Nov 16 2014 23:20:03 +gem5 executing on gabeblackz620.mtv.corp.google.com +command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re /usr/local/google/home/gabeblack/gem5/hg/gem5/tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /usr/local/google/home/gabeblack/gem5/x86_system_files/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 5194410635000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 8675b3331..83f38fa06 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -4,40 +4,40 @@ sim_seconds 5.194411 # Nu sim_ticks 5194410635000 # Number of ticks simulated final_tick 5194410635000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1079720 # Simulator instruction rate (inst/s) -host_op_rate 2081347 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43672253601 # Simulator tick rate (ticks/s) -host_mem_usage 589096 # Number of bytes of host memory used -host_seconds 118.94 # Real time elapsed on the host +host_inst_rate 1282120 # Simulator instruction rate (inst/s) +host_op_rate 2471507 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51858853246 # Simulator tick rate (ticks/s) +host_mem_usage 594916 # Number of bytes of host memory used +host_seconds 100.16 # Real time elapsed on the host sim_insts 128422722 # Number of instructions simulated sim_ops 247557000 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 829440 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9099264 # Number of bytes read from this memory +system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory system.physmem.bytes_read::total 9957440 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 829440 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 829440 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 5149824 # Number of bytes written to this memory system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory system.physmem.bytes_written::total 8139904 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 12960 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 142176 # Number of read requests responded to by this memory +system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory system.physmem.num_reads::total 155585 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 80466 # Number of write requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory system.physmem.num_writes::total 127186 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 5458 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 159679 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 1751741 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5458 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 1916953 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 159679 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 159679 # Instruction read bandwidth from this memory (bytes/s) @@ -45,11 +45,11 @@ system.physmem.bw_write::writebacks 991416 # Wr system.physmem.bw_write::pc.south_bridge.ide 575634 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 1567051 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 991416 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 581092 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 159679 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1751741 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 581092 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 3484003 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 155585 # Number of read requests accepted system.physmem.writeReqs 127186 # Number of write requests accepted @@ -305,265 +305,6 @@ system.physmem.totalEnergy::0 3473770745370 # T system.physmem.totalEnergy::1 3473748494505 # Total energy per rank (pJ) system.physmem.averagePower::0 668.751736 # Core power per rank (mW) system.physmem.averagePower::1 668.747452 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 624009 # Transaction distribution -system.membus.trans_dist::ReadResp 624009 # Transaction distribution -system.membus.trans_dist::WriteReq 13889 # Transaction distribution -system.membus.trans_dist::WriteResp 13889 # Transaction distribution -system.membus.trans_dist::Writeback 80466 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2168 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1629 # Transaction distribution -system.membus.trans_dist::ReadExReq 113541 # Transaction distribution -system.membus.trans_dist::ReadExResp 113541 # Transaction distribution -system.membus.trans_dist::MessageReq 1655 # Transaction distribution -system.membus.trans_dist::MessageResp 1655 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3310 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480788 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710112 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394547 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1585447 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94730 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 94730 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1683487 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6620 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246674 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420221 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15078912 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16745807 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19770859 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 943 # Total snoops (count) -system.membus.snoop_fanout::samples 285344 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 285344 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 285344 # Request fanout histogram -system.membus.reqLayer0.occupancy 257196000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 358105500 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3310000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1311782500 # Layer occupancy (ticks) -system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1655000 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2622169871 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 54356499 # Layer occupancy (ticks) -system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47512 # number of replacements -system.iocache.tags.tagsinuse 0.118180 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47528 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5045851318000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.118180 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007386 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.007386 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428111 # Number of tag accesses -system.iocache.tags.data_accesses 428111 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::pc.south_bridge.ide 847 # number of ReadReq misses -system.iocache.ReadReq_misses::total 847 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 1 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 1 # number of WriteInvalidateReq misses -system.iocache.demand_misses::pc.south_bridge.ide 847 # number of demand (read+write) misses -system.iocache.demand_misses::total 847 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 847 # number of overall misses -system.iocache.overall_misses::total 847 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 141540186 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 141540186 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 141540186 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 141540186 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 141540186 # number of overall miss cycles -system.iocache.overall_miss_latency::total 141540186 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 847 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 847 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46721 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 46721 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 847 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 847 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 847 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 847 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 0.000021 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000021 # miss rate for WriteInvalidateReq accesses -system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 167107.657615 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 167107.657615 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 167107.657615 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.076923 # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 46720 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 847 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 847 # number of ReadReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 847 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 847 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 847 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 847 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 97471186 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2827609160 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2827609160 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 97471186 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 97471186 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 115078.141677 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 115078.141677 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 115078.141677 # average overall mshr miss latency -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). -system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. -system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. -system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. -system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. -system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. -system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 230267 # Transaction distribution -system.iobus.trans_dist::ReadResp 230267 # Transaction distribution -system.iobus.trans_dist::WriteReq 57693 # Transaction distribution -system.iobus.trans_dist::WriteResp 57694 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 1 # Transaction distribution -system.iobus.trans_dist::MessageReq 1655 # Transaction distribution -system.iobus.trans_dist::MessageResp 1655 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27696 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 480788 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95134 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95134 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3310 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 579232 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13848 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 246674 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6620 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3280614 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3947664 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8813000 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) -system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) -system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 77000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) -system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 218343000 # Layer occupancy (ticks) -system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) -system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) -system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 20719000 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 421906845 # Layer occupancy (ticks) -system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) -system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 469814000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 52234501 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1655000 # Layer occupancy (ticks) -system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.numCycles 10388821270 # number of cpu cycles simulated @@ -628,6 +369,237 @@ system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class::total 247558577 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu.dcache.tags.replacements 1622351 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.996907 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20038370 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1622863 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.347543 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.996907 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 88306374 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88306374 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 11941774 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11941774 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8035174 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8035174 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 59224 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 59224 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 19976948 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19976948 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20036172 # number of overall hits +system.cpu.dcache.overall_hits::total 20036172 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 907115 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 907115 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 325077 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 325077 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 402500 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 402500 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1232192 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1232192 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1634692 # number of overall misses +system.cpu.dcache.overall_misses::total 1634692 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12725992750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12725992750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11362158354 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11362158354 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24088151104 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24088151104 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24088151104 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24088151104 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 12848889 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12848889 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8360251 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8360251 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 461724 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 461724 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21209140 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21209140 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21670864 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21670864 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070599 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070599 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038884 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.038884 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871733 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.871733 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.058097 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.058097 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.075433 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.075433 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14029.084240 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14029.084240 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34952.206259 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34952.206259 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19549.024100 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19549.024100 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14735.590010 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14735.590010 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 7616 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 81 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 94.024691 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 1538923 # number of writebacks +system.cpu.dcache.writebacks::total 1538923 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 288 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 288 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9252 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9252 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 9540 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 9540 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 9540 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 9540 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906827 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 906827 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315825 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 315825 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402464 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 402464 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1222652 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1222652 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1625116 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1625116 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10904887500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10904887500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10229869846 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10229869846 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5337291000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5337291000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21134757346 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21134757346 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26472048346 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26472048346 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94240373000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94240373000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2561690500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2561690500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96802063500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96802063500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070576 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070576 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037777 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037777 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871655 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871655 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057647 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057647 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074991 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074991 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12025.322912 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12025.322912 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32390.943864 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32390.943864 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13261.536436 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13261.536436 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17285.995807 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17285.995807 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16289.328482 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16289.328482 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dtb_walker_cache.tags.replacements 7576 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.056356 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 13259 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 7591 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.746674 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5163552885000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.056356 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.316022 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.316022 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 52917 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 52917 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13260 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13260 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13260 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13260 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13260 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13260 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8799 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8799 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8799 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8799 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8799 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8799 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 94478000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 94478000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 94478000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 94478000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 94478000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 94478000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22059 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 22059 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22059 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 22059 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22059 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 22059 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.398885 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.398885 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.398885 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.398885 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.398885 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.398885 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10737.356518 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10737.356518 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10737.356518 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10737.356518 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10737.356518 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10737.356518 # average overall miss latency +system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed +system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed +system.cpu.dtb_walker_cache.writebacks::writebacks 3010 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 3010 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8799 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8799 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8799 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 8799 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8799 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 8799 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 76879500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 76879500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 76879500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 76879500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 76879500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 76879500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.398885 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.398885 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.398885 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8737.299693 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8737.299693 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8737.299693 # average overall mshr miss latency +system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 791372 # number of replacements system.cpu.icache.tags.tagsinuse 510.348934 # Cycle average of tags in use system.cpu.icache.tags.total_refs 144679417 # Total number of references to valid blocks. @@ -806,283 +778,6 @@ system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8275.416396 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8275.416396 # average overall mshr miss latency system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8275.416396 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 7576 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.056356 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 13259 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 7591 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.746674 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5163552885000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.056356 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.316022 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.316022 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 52917 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 52917 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13260 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13260 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13260 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13260 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13260 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13260 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8799 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8799 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8799 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8799 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8799 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8799 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 94478000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 94478000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 94478000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 94478000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 94478000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 94478000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22059 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 22059 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22059 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 22059 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22059 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 22059 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.398885 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.398885 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.398885 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.398885 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.398885 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.398885 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10737.356518 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10737.356518 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10737.356518 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10737.356518 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10737.356518 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10737.356518 # average overall miss latency -system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed -system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 3010 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 3010 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8799 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8799 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8799 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8799 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8799 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 8799 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 76879500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 76879500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 76879500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 76879500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 76879500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 76879500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.398885 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.398885 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.398885 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8737.299693 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8737.299693 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8737.299693 # average overall mshr miss latency -system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1622351 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.996907 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20038370 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1622863 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.347543 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.996907 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88306374 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88306374 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 11941774 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11941774 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8035174 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8035174 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 59224 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 59224 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 19976948 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19976948 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20036172 # number of overall hits -system.cpu.dcache.overall_hits::total 20036172 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 907115 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 907115 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 325077 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 325077 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 402500 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 402500 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1232192 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1232192 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1634692 # number of overall misses -system.cpu.dcache.overall_misses::total 1634692 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12725992750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12725992750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11362158354 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11362158354 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24088151104 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24088151104 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24088151104 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24088151104 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12848889 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12848889 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8360251 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8360251 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 461724 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 461724 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21209140 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21209140 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21670864 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21670864 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070599 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070599 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038884 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.038884 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871733 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.871733 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.058097 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.058097 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.075433 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.075433 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14029.084240 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14029.084240 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34952.206259 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34952.206259 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19549.024100 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19549.024100 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14735.590010 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14735.590010 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 7616 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 81 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 94.024691 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1538923 # number of writebacks -system.cpu.dcache.writebacks::total 1538923 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 288 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 288 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9252 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9252 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 9540 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 9540 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 9540 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 9540 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906827 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 906827 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315825 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 315825 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402464 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 402464 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1222652 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1222652 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1625116 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1625116 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10904887500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10904887500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10229869846 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10229869846 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5337291000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5337291000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21134757346 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21134757346 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26472048346 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26472048346 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94240373000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94240373000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2561690500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2561690500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96802063500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96802063500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070576 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070576 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037777 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037777 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871655 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871655 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057647 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.057647 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074991 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074991 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12025.322912 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12025.322912 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32390.943864 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32390.943864 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13261.536436 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13261.536436 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17285.995807 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17285.995807 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16289.328482 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16289.328482 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2697012 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2696490 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13889 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13889 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1542758 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46721 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2211 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2211 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 313627 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 313627 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1583769 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5979028 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8638 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18387 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7589822 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50680192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203991823 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 256960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 613632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 255542607 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 52938 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4020768 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.011831 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.108123 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 3973200 98.82% 98.82% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 47568 1.18% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4020768 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3834027500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 487500 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1190285118 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3054401379 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 6935250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 13198750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 87384 # number of replacements system.cpu.l2cache.tags.tagsinuse 64746.924059 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3489247 # Total number of references to valid blocks. @@ -1326,5 +1021,310 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 2697012 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2696490 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13889 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13889 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1542758 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46721 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2211 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2211 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 313627 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 313627 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1583769 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5979028 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8638 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18387 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7589822 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50680192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203991823 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 256960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 613632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 255542607 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 52938 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4020768 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.011831 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.108123 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 3973200 98.82% 98.82% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 47568 1.18% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4020768 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3834027500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 487500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1190285118 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3054401379 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer2.occupancy 6935250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer3.occupancy 13198750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 230267 # Transaction distribution +system.iobus.trans_dist::ReadResp 230267 # Transaction distribution +system.iobus.trans_dist::WriteReq 57693 # Transaction distribution +system.iobus.trans_dist::WriteResp 57694 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 1 # Transaction distribution +system.iobus.trans_dist::MessageReq 1655 # Transaction distribution +system.iobus.trans_dist::MessageResp 1655 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27696 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 480788 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3310 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 579232 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13848 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 246674 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027320 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027320 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6620 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3280614 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3947664 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 8813000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 77000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 218343000 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 20719000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 421906845 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 469814000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer1.occupancy 52234501 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer2.occupancy 1655000 # Layer occupancy (ticks) +system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) +system.iocache.tags.replacements 47512 # number of replacements +system.iocache.tags.tagsinuse 0.118180 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 47528 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 5045851318000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.118180 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007386 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.007386 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 428111 # Number of tag accesses +system.iocache.tags.data_accesses 428111 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::pc.south_bridge.ide 847 # number of ReadReq misses +system.iocache.ReadReq_misses::total 847 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 1 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 1 # number of WriteInvalidateReq misses +system.iocache.demand_misses::pc.south_bridge.ide 847 # number of demand (read+write) misses +system.iocache.demand_misses::total 847 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 847 # number of overall misses +system.iocache.overall_misses::total 847 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 141540186 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 141540186 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 141540186 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 141540186 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 141540186 # number of overall miss cycles +system.iocache.overall_miss_latency::total 141540186 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 847 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 847 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46721 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 46721 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::pc.south_bridge.ide 847 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 847 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 847 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 847 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 0.000021 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000021 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 167107.657615 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 167107.657615 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 167107.657615 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.076923 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 46720 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 847 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 847 # number of ReadReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 847 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 847 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 847 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 847 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 97471186 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2827609160 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2827609160 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 97471186 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 97471186 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 115078.141677 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 115078.141677 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 115078.141677 # average overall mshr miss latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 624009 # Transaction distribution +system.membus.trans_dist::ReadResp 624009 # Transaction distribution +system.membus.trans_dist::WriteReq 13889 # Transaction distribution +system.membus.trans_dist::WriteResp 13889 # Transaction distribution +system.membus.trans_dist::Writeback 80466 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2168 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1629 # Transaction distribution +system.membus.trans_dist::ReadExReq 113541 # Transaction distribution +system.membus.trans_dist::ReadExResp 113541 # Transaction distribution +system.membus.trans_dist::MessageReq 1655 # Transaction distribution +system.membus.trans_dist::MessageResp 1655 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3310 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480788 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710112 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394547 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1585447 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94730 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 94730 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1683487 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6620 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246674 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420221 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15078912 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16745807 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19770859 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 943 # Total snoops (count) +system.membus.snoop_fanout::samples 285344 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 285344 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 285344 # Request fanout histogram +system.membus.reqLayer0.occupancy 257196000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 358105500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 3310000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer3.occupancy 1311782500 # Layer occupancy (ticks) +system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.membus.respLayer0.occupancy 1655000 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 2622169871 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.1 # Layer utilization (%) +system.membus.respLayer4.occupancy 54356499 # Layer occupancy (ticks) +system.membus.respLayer4.utilization 0.0 # Layer utilization (%) +system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. +system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. +system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. +system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. +system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. +system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. ---------- End Simulation Statistics ----------