ARM: Set the value of the MVFR0 and MVFR1 registers.
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@ -134,6 +134,27 @@ namespace ArmISA
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// Separate Instruction and Data TLBs.
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// Separate Instruction and Data TLBs.
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miscRegs[MISCREG_TLBTR] = 1;
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miscRegs[MISCREG_TLBTR] = 1;
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MVFR0 mvfr0 = 0;
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mvfr0.advSimdRegisters = 2;
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mvfr0.singlePrecision = 2;
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mvfr0.doublePrecision = 2;
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mvfr0.vfpExceptionTrapping = 0;
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mvfr0.divide = 1;
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mvfr0.squareRoot = 1;
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mvfr0.shortVectors = 1;
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mvfr0.roundingModes = 1;
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miscRegs[MISCREG_MVFR0] = mvfr0;
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MVFR1 mvfr1 = 0;
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mvfr1.flushToZero = 1;
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mvfr1.defaultNaN = 1;
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mvfr1.advSimdLoadStore = 1;
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mvfr1.advSimdInteger = 1;
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mvfr1.advSimdSinglePrecision = 1;
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mvfr1.advSimdHalfPrecision = 1;
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mvfr1.vfpHalfPrecision = 1;
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miscRegs[MISCREG_MVFR1] = mvfr1;
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//XXX We need to initialize the rest of the state.
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//XXX We need to initialize the rest of the state.
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}
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}
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@ -273,6 +294,8 @@ namespace ArmISA
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warn("The csselr register isn't implemented.\n");
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warn("The csselr register isn't implemented.\n");
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break;
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break;
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case MISCREG_TLBTR:
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case MISCREG_TLBTR:
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case MISCREG_MVFR0:
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case MISCREG_MVFR1:
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return;
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return;
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}
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}
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return setMiscRegNoEffect(misc_reg, newVal);
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return setMiscRegNoEffect(misc_reg, newVal);
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@ -320,6 +320,28 @@ namespace ArmISA
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Bitfield<30> z;
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Bitfield<30> z;
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Bitfield<31> n;
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Bitfield<31> n;
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EndBitUnion(FPSCR)
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EndBitUnion(FPSCR)
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BitUnion32(MVFR0)
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Bitfield<3, 0> advSimdRegisters;
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Bitfield<7, 4> singlePrecision;
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Bitfield<11, 8> doublePrecision;
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Bitfield<15, 12> vfpExceptionTrapping;
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Bitfield<19, 16> divide;
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Bitfield<23, 20> squareRoot;
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Bitfield<27, 24> shortVectors;
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Bitfield<31, 28> roundingModes;
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EndBitUnion(MVFR0)
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BitUnion32(MVFR1)
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Bitfield<3, 0> flushToZero;
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Bitfield<7, 4> defaultNaN;
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Bitfield<11, 8> advSimdLoadStore;
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Bitfield<15, 12> advSimdInteger;
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Bitfield<19, 16> advSimdSinglePrecision;
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Bitfield<23, 20> advSimdHalfPrecision;
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Bitfield<27, 24> vfpHalfPrecision;
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Bitfield<31, 28> raz;
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EndBitUnion(MVFR1)
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};
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};
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#endif // __ARCH_ARM_MISCREGS_HH__
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#endif // __ARCH_ARM_MISCREGS_HH__
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