CheckerCPU: Add function stubs to non-ARM ISA source to compile with CheckerCPU
Making the CheckerCPU a runtime time option requires the code to be compatible with ISAs other than ARM. This patch adds the appropriate function stubs to allow compilation.
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@ -600,6 +600,13 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
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translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
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translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
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}
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}
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Fault
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TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
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{
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panic("Not implemented\n");
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return NoFault;
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}
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} // namespace AlphaISA
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} // namespace AlphaISA
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AlphaISA::TLB *
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AlphaISA::TLB *
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@ -144,6 +144,10 @@ class TLB : public BaseTLB
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Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
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Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
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void translateTiming(RequestPtr req, ThreadContext *tc,
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void translateTiming(RequestPtr req, ThreadContext *tc,
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Translation *translation, Mode mode);
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Translation *translation, Mode mode);
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/**
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* translateFunctional stub function for future CheckerCPU support
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*/
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Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
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};
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};
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} // namespace AlphaISA
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} // namespace AlphaISA
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@ -339,6 +339,13 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
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translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
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translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
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}
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}
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Fault
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TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
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{
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panic("Not implemented\n");
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return NoFault;
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}
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MipsISA::PTE &
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MipsISA::PTE &
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TLB::index(bool advance)
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TLB::index(bool advance)
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@ -114,6 +114,11 @@ class TLB : public BaseTLB
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void translateTiming(RequestPtr req, ThreadContext *tc,
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void translateTiming(RequestPtr req, ThreadContext *tc,
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Translation *translation, Mode mode);
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Translation *translation, Mode mode);
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/** Function stub for CheckerCPU compilation issues. MIPS does not
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* support the Checker model at the moment.
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*/
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Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
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private:
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private:
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Fault translateInst(RequestPtr req, ThreadContext *tc);
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Fault translateInst(RequestPtr req, ThreadContext *tc);
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Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
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Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
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@ -326,6 +326,13 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
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translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
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translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
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}
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}
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Fault
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TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
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{
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panic("Not implemented\n");
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return NoFault;
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}
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PowerISA::PTE &
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PowerISA::PTE &
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TLB::index(bool advance)
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TLB::index(bool advance)
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{
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{
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@ -160,6 +160,10 @@ class TLB : public BaseTLB
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Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
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Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
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void translateTiming(RequestPtr req, ThreadContext *tc,
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void translateTiming(RequestPtr req, ThreadContext *tc,
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Translation *translation, Mode mode);
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Translation *translation, Mode mode);
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/** Stub function for CheckerCPU compilation support. Power ISA not
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* supported by Checker at the moment
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*/
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Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
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// Checkpointing
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// Checkpointing
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void serialize(std::ostream &os);
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void serialize(std::ostream &os);
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@ -841,6 +841,13 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
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translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
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translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
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}
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}
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Fault
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TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
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{
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panic("Not implemented\n");
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return NoFault;
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}
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Tick
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Tick
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TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
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TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
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{
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{
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@ -164,6 +164,10 @@ class TLB : public BaseTLB
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Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
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Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
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void translateTiming(RequestPtr req, ThreadContext *tc,
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void translateTiming(RequestPtr req, ThreadContext *tc,
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Translation *translation, Mode mode);
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Translation *translation, Mode mode);
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/** Stub function for compilation support with CheckerCPU. SPARC ISA
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* does not support the Checker model at the moment
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*/
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Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
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Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
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Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
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Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
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Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
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void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
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void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
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@ -405,6 +405,13 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
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translation->finish(fault, req, tc, mode);
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translation->finish(fault, req, tc, mode);
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}
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}
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Fault
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TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
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{
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panic("Not implemented\n");
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return NoFault;
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}
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Walker *
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Walker *
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TLB::getWalker()
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TLB::getWalker()
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{
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{
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@ -114,6 +114,10 @@ namespace X86ISA
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Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
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Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
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void translateTiming(RequestPtr req, ThreadContext *tc,
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void translateTiming(RequestPtr req, ThreadContext *tc,
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Translation *translation, Mode mode);
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Translation *translation, Mode mode);
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/** Stub function for compilation support of CheckerCPU. x86 ISA does
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* not support Checker model at the moment
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*/
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Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
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TlbEntry * insert(Addr vpn, TlbEntry &entry);
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TlbEntry * insert(Addr vpn, TlbEntry &entry);
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@ -311,6 +311,20 @@ class CheckerCPU : public BaseCPU
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int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
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int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
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return thread->setMiscReg(reg_idx, val);
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return thread->setMiscReg(reg_idx, val);
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}
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}
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#if THE_ISA == MIPS_ISA
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uint64_t readRegOtherThread(int misc_reg)
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{
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panic("MIPS MT not defined for CheckerCPU.\n");
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return 0;
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}
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void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val)
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{
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panic("MIPS MT not defined for CheckerCPU.\n");
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}
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#endif
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/////////////////////////////////////////
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/////////////////////////////////////////
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void recordPCChange(const TheISA::PCState &val)
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void recordPCChange(const TheISA::PCState &val)
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@ -44,6 +44,7 @@
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#include <list>
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#include <list>
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#include <string>
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#include <string>
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#include "arch/isa_traits.hh"
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#include "arch/vtophys.hh"
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#include "arch/vtophys.hh"
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#include "base/refcnt.hh"
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#include "base/refcnt.hh"
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#include "config/the_isa.hh"
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#include "config/the_isa.hh"
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@ -201,9 +202,9 @@ Checker<Impl>::verify(DynInstPtr &completed_inst)
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// maintain $r0 semantics
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// maintain $r0 semantics
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thread->setIntReg(ZeroReg, 0);
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thread->setIntReg(ZeroReg, 0);
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#ifdef TARGET_ALPHA
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#if THE_ISA == ALPHA_ISA
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thread->setFloatRegDouble(ZeroReg, 0.0);
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thread->setFloatReg(ZeroReg, 0.0);
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#endif // TARGET_ALPHA
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#endif
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// Check if any recent PC changes match up with anything we
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// Check if any recent PC changes match up with anything we
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// expect to happen. This is mostly to check if traps or
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// expect to happen. This is mostly to check if traps or
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@ -320,7 +321,9 @@ Checker<Impl>::verify(DynInstPtr &completed_inst)
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thread->pcState(pcState);
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thread->pcState(pcState);
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instPtr = thread->decoder.decode(newMachInst,
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instPtr = thread->decoder.decode(newMachInst,
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pcState.instAddr());
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pcState.instAddr());
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machInst = newMachInst;
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#if THE_ISA != X86_ISA
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machInst = newMachInst;
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#endif
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} else {
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} else {
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fetchDone = false;
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fetchDone = false;
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fetchOffset += sizeof(TheISA::MachInst);
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fetchOffset += sizeof(TheISA::MachInst);
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@ -476,7 +479,11 @@ Checker<Impl>::validateInst(DynInstPtr &inst)
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}
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}
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}
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}
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MachInst mi = static_cast<MachInst>(inst->staticInst->machInst);
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MachInst mi;
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#if THE_ISA != X86_ISA
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mi = static_cast<MachInst>(inst->staticInst->machInst);
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#endif
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if (mi != machInst) {
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if (mi != machInst) {
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panic("%lli: Binary instructions do not match! Inst: %#x, "
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panic("%lli: Binary instructions do not match! Inst: %#x, "
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@ -40,6 +40,7 @@
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#include "arch/kernel_stats.hh"
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#include "arch/kernel_stats.hh"
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class EndQuiesceEvent;
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class EndQuiesceEvent;
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class CheckerCPU;
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namespace Kernel {
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namespace Kernel {
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class Statistics;
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class Statistics;
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};
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};
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/** @TODO: PERF: Should we bind this to a pointer in constructor? */
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/** @TODO: PERF: Should we bind this to a pointer in constructor? */
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TheISA::TLB *getDTBPtr() { return cpu->getDTBPtr(); }
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TheISA::TLB *getDTBPtr() { return cpu->getDTBPtr(); }
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/** Currently InOrder model does not support CheckerCPU, this is
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* merely here for supporting compilation of gem5 with the Checker
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* as a runtime option
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*/
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CheckerCPU *getCheckerCpuPtr() { return NULL; }
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Decoder *getDecoderPtr() { return cpu->getDecoderPtr(); }
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Decoder *getDecoderPtr() { return cpu->getDecoderPtr(); }
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System *getSystemPtr() { return cpu->system; }
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System *getSystemPtr() { return cpu->system; }
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void pcState(const TheISA::PCState &val)
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void pcState(const TheISA::PCState &val)
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{ cpu->pcState(val, thread->threadId()); }
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{ cpu->pcState(val, thread->threadId()); }
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/** Needs to be implemented for future CheckerCPU support.
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* See O3CPU for examples on how to integrate Checker.
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*/
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void pcStateNoRecord(const TheISA::PCState &val)
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{}
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Addr instAddr()
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Addr instAddr()
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{ return cpu->instAddr(thread->threadId()); }
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{ return cpu->instAddr(thread->threadId()); }
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