inorder-miscregs: Fix indexing for misc. reg operands and update result-types for better tracing of these types of values
This commit is contained in:
parent
2012202b06
commit
98b1452058
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@ -247,6 +247,7 @@ class InOrderCPU : public BaseCPU
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/** The Pipeline Stages for the CPU */
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PipelineStage *pipelineStage[ThePipeline::NumStages];
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/** Program Counters */
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TheISA::IntReg PC[ThePipeline::MaxThreads];
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TheISA::IntReg nextPC[ThePipeline::MaxThreads];
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TheISA::IntReg nextNPC[ThePipeline::MaxThreads];
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@ -359,7 +359,7 @@ void
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InOrderDynInst::setFloatSrc(int idx, FloatReg val, int width)
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{
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if (width == 32)
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instSrc[idx].fp = val;
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instSrc[idx].dbl = val;
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else if (width == 64)
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instSrc[idx].dbl = val;
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else
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@ -386,7 +386,14 @@ InOrderDynInst::readIntRegOperand(const StaticInst *si, int idx, unsigned tid)
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FloatReg
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InOrderDynInst::readFloatRegOperand(const StaticInst *si, int idx, int width)
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{
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return instSrc[idx].fp;
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if (width == 32)
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return (float)instSrc[idx].dbl;
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else if (width == 64)
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return instSrc[idx].dbl;
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else {
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panic("Unsupported Floating Point Width!");
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return 0;
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}
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}
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@ -417,8 +424,10 @@ InOrderDynInst::readMiscRegNoEffect(int misc_reg)
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MiscReg
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InOrderDynInst::readMiscRegOperandNoEffect(const StaticInst *si, int idx)
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{
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int reg = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
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return cpu->readMiscRegNoEffect(reg, this->threadNumber);
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DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Misc. Reg Source Value %i"
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" read as %#x.\n", threadNumber, seqNum, idx,
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instSrc[idx].integer);
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return instSrc[idx].integer;
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}
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/** Reads a misc. register, including any side-effects the read
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@ -427,20 +436,23 @@ InOrderDynInst::readMiscRegOperandNoEffect(const StaticInst *si, int idx)
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MiscReg
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InOrderDynInst::readMiscRegOperand(const StaticInst *si, int idx)
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{
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int reg = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
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return this->cpu->readMiscReg(reg, this->threadNumber);
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// For In-Order, the side-effect of reading a register happens
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// when explicitly executing a "ReadSrc" command. This simply returns
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// a value.
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return readMiscRegOperandNoEffect(si, idx);
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}
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/** Sets a misc. register. */
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void
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InOrderDynInst::setMiscRegOperandNoEffect(const StaticInst * si, int idx, const MiscReg &val)
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InOrderDynInst::setMiscRegOperandNoEffect(const StaticInst * si, int idx,
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const MiscReg &val)
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{
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instResult[si->destRegIdx(idx)].val.integer = val;
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instResult[si->destRegIdx(idx)].tick = curTick;
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instResult[idx].type = Integer;
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instResult[idx].val.integer = val;
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instResult[idx].tick = curTick;
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this->cpu->setMiscRegNoEffect(
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si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
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val, this->threadNumber);
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DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Misc Reg. Operand %i "
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"being set to %#x.\n", threadNumber, seqNum, idx, val);
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}
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/** Sets a misc. register, including any side-effects the write
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@ -450,12 +462,10 @@ void
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InOrderDynInst::setMiscRegOperand(const StaticInst *si, int idx,
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const MiscReg &val)
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{
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instResult[si->destRegIdx(idx)].val.integer = val;
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instResult[si->destRegIdx(idx)].tick = curTick;
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this->cpu->setMiscReg(
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si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
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val, this->threadNumber);
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// For In-Order, the side-effect of setting a register happens
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// when explicitly writing back the register value. This
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// simply maintains the operand value.
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setMiscRegOperandNoEffect(si, idx, val);
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}
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MiscReg
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@ -480,6 +490,7 @@ InOrderDynInst::readRegOtherThread(unsigned reg_idx, int tid)
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void
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InOrderDynInst::setIntRegOperand(const StaticInst *si, int idx, IntReg val)
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{
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instResult[idx].type = Integer;
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instResult[idx].val.integer = val;
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instResult[idx].tick = curTick;
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}
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@ -488,12 +499,15 @@ InOrderDynInst::setIntRegOperand(const StaticInst *si, int idx, IntReg val)
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void
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InOrderDynInst::setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, int width)
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{
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if (width == 32)
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instResult[idx].val.fp = val;
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else if (width == 64)
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if (width == 32) {
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instResult[idx].val.dbl = (float)val;
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instResult[idx].type = Float;
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} else if (width == 64) {
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instResult[idx].val.dbl = val;
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else
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instResult[idx].type = Double;
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} else {
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panic("Unsupported Floating Point Width!");
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}
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instResult[idx].tick = curTick;
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}
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@ -503,6 +517,11 @@ void
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InOrderDynInst::setFloatRegOperandBits(const StaticInst *si, int idx,
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FloatRegBits val, int width)
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{
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if (width == 32)
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instResult[idx].type = Float;
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else if (width == 64)
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instResult[idx].type = Double;
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instResult[idx].val.integer = val;
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instResult[idx].tick = curTick;
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}
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@ -226,14 +226,27 @@ class InOrderDynInst : public FastAlloc, public RefCounted
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/** An instruction src/dest has to be one of these types */
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union InstValue {
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uint64_t integer;
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float fp;
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double dbl;
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};
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//@TODO: Naming Convention for Enums?
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enum ResultType {
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None,
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Integer,
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Float,
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Double
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};
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/** Result of an instruction execution */
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struct InstResult {
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ResultType type;
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InstValue val;
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Tick tick;
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InstResult()
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: type(None), tick(0)
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{}
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};
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/** The source of the instruction; assumes for now that there's only one
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@ -315,6 +328,9 @@ class InOrderDynInst : public FastAlloc, public RefCounted
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// BASE INSTRUCTION INFORMATION.
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//
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////////////////////////////////////////////////////////////
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std::string instName() { return staticInst->getName(); }
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void setMachInst(ExtMachInst inst);
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/** Sets the StaticInst. */
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@ -827,9 +843,31 @@ class InOrderDynInst : public FastAlloc, public RefCounted
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MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx);
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/** Returns the result value instruction. */
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uint64_t readIntResult(int idx) { return instResult[idx].val.integer; }
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float readFloatResult(int idx) { return instResult[idx].val.fp; }
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double readDoubleResult(int idx) { return instResult[idx].val.dbl; }
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ResultType resultType(int idx)
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{
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return instResult[idx].type;
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}
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uint64_t readIntResult(int idx)
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{
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return instResult[idx].val.integer;
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}
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/** Depending on type, return Float or Double */
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double readFloatResult(int idx)
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{
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//assert(instResult[idx].type != Integer && instResult[idx].type != None);
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//@todo: TypeCast FLOAT onto DOUBLE instead of separate value
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return (instResult[idx].type == Float) ?
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(float) instResult[idx].val.dbl : instResult[idx].val.dbl;
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}
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double readDoubleResult(int idx)
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{
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assert(instResult[idx].type == Double);
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return instResult[idx].val.dbl;
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}
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Tick readResultTime(int idx) { return instResult[idx].tick; }
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uint64_t* getIntResultPtr(int idx) { return &instResult[idx].val.integer; }
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@ -483,6 +483,9 @@ CacheUnit::processCacheCompletion(PacketPtr pkt)
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DPRINTF(InOrderCachePort,
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"[tid:%u]: [sn:%i]: Data loaded was: %08p\n",
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tid, inst->seqNum, inst->readIntResult(0));
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DPRINTF(InOrderCachePort,
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"[tid:%u]: [sn:%i]: FP Data loaded was: %08p\n",
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tid, inst->seqNum, inst->readFloatResult(0));
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} else if(inst->isStore()) {
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assert(cache_pkt->isWrite());
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@ -594,7 +597,7 @@ CacheUnit::getMemData(Packet *packet)
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case 32:
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return packet->get<uint32_t>();
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case 864:
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case 64:
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return packet->get<uint64_t>();
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default:
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@ -68,8 +68,8 @@ ExecutionUnit::execute(int slot_num)
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exec_req->fault = NoFault;
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DPRINTF(InOrderExecute, "[tid:%i] Executing [sn:%i] [PC:%#x] .\n",
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tid, seq_num, inst->readPC());
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DPRINTF(InOrderExecute, "[tid:%i] Executing [sn:%i] [PC:%#x] %s.\n",
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tid, seq_num, inst->readPC(), inst->instName());
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switch (exec_req->cmd)
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{
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@ -163,11 +163,9 @@ ExecutionUnit::execute(int slot_num)
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}
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} else {
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DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Prediction Correct.\n",
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inst->readTid(), seq_num, inst->readIntResult(0));
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inst->readTid(), seq_num);
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}
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DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: The result of execution is 0x%x.\n",
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inst->readTid(), seq_num, inst->readIntResult(0));
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exec_req->done();
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} else {
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warn("inst [sn:%i] had a %s fault", seq_num, fault->name());
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@ -178,10 +176,13 @@ ExecutionUnit::execute(int slot_num)
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if (fault == NoFault) {
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inst->setExecuted();
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exec_req->done();
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DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: The result of execution is 0x%x.\n",
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inst->readTid(), seq_num, inst->readIntResult(0));
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inst->readTid(), seq_num, (inst->resultType(0) == InOrderDynInst::Float) ?
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inst->readFloatResult(0) : (inst->resultType(0) == InOrderDynInst::Double) ?
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inst->readDoubleResult(0) : inst->readIntResult(0));
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exec_req->done();
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} else {
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warn("inst [sn:%i] had a %s fault", seq_num, fault->name());
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cpu->trap(fault, tid);
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@ -119,28 +119,28 @@ UseDefUnit::execute(int slot_idx)
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{
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int reg_idx = inst->_srcRegIdx[ud_idx];
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DPRINTF(InOrderUseDef, "[tid:%i]: Attempting to read source register idx %i.\n",
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tid, ud_idx);
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DPRINTF(InOrderUseDef, "[tid:%i]: Attempting to read source register idx %i (reg #%i).\n",
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tid, ud_idx, reg_idx);
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// Ask register dependency map if it is OK to read from Arch. Reg. File
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if (regDepMap[tid]->canRead(reg_idx, inst)) {
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// Read From Register File
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if (inst->seqNum <= outReadSeqNum[tid]) {
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if (reg_idx <= FP_Base_DepTag) {
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DPRINTF(InOrderUseDef, "[tid:%i]: Reading Int Reg %i from Register File.\n",
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tid, reg_idx);
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DPRINTF(InOrderUseDef, "[tid:%i]: Reading Int Reg %i from Register File:%i.\n",
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tid, reg_idx, cpu->readIntReg(reg_idx,inst->readTid()));
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inst->setIntSrc(ud_idx,
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cpu->readIntReg(reg_idx,inst->readTid()));
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} else if (reg_idx <= Ctrl_Base_DepTag) {
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reg_idx -= FP_Base_DepTag;
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DPRINTF(InOrderUseDef, "[tid:%i]: Reading Float Reg %i from Register File.\n",
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tid, reg_idx);
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DPRINTF(InOrderUseDef, "[tid:%i]: Reading Float Reg %i from Register File:%x.\n",
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tid, reg_idx, cpu->readFloatRegBits(reg_idx, inst->readTid()));
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inst->setIntSrc(ud_idx, // Always Read FloatRegBits For Now
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cpu->readFloatRegBits(reg_idx, inst->readTid()));
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} else {
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reg_idx -= Ctrl_Base_DepTag;
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DPRINTF(InOrderUseDef, "[tid:%i]: Reading Misc Reg %i from Register File.\n",
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tid, reg_idx);
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DPRINTF(InOrderUseDef, "[tid:%i]: Reading Misc Reg %i from Register File:%i.\n",
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tid, reg_idx, cpu->readMiscReg(reg_idx, inst->readTid()));
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inst->setIntSrc(ud_idx,
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cpu->readMiscReg(reg_idx, inst->readTid()));
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}
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@ -208,12 +208,12 @@ UseDefUnit::execute(int slot_idx)
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int reg_idx = inst->_destRegIdx[ud_idx];
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if (regDepMap[tid]->canWrite(reg_idx, inst)) {
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DPRINTF(InOrderUseDef, "[tid:%i]: Attempting to write to Register File.\n",
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tid);
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DPRINTF(InOrderUseDef, "[tid:%i]: Flattening register idx %i & Attempting to write to Register File.\n",
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tid, reg_idx);
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if (inst->seqNum <= outReadSeqNum[tid]) {
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if (reg_idx <= FP_Base_DepTag) {
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DPRINTF(InOrderUseDef, "[tid:%i]: Writing 0x%x to register idx %i.\n",
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DPRINTF(InOrderUseDef, "[tid:%i]: Writing Int. Result 0x%x to register idx %i.\n",
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tid, inst->readIntResult(ud_idx), reg_idx);
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// Remove Dependencies
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@ -223,6 +223,8 @@ UseDefUnit::execute(int slot_idx)
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inst->readIntResult(ud_idx),
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inst->readTid());
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} else if(reg_idx <= Ctrl_Base_DepTag) {
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DPRINTF(InOrderUseDef, "[tid:%i]: Writing FP Result 0x%x (bits:0x%x) to register idx %i.\n",
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tid, inst->readFloatResult(ud_idx), inst->readIntResult(ud_idx), reg_idx);
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// Remove Dependencies
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regDepMap[tid]->removeFront(reg_idx, inst);
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@ -233,10 +235,14 @@ UseDefUnit::execute(int slot_idx)
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inst->readFloatResult(ud_idx),
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inst->readTid());
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} else {
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DPRINTF(InOrderUseDef, "[tid:%i]: Writing Misc. 0x%x to register idx %i.\n",
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tid, inst->readIntResult(ud_idx), reg_idx);
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// Remove Dependencies
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regDepMap[tid]->removeFront(reg_idx, inst);
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reg_idx -= Ctrl_Base_DepTag;
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cpu->setMiscReg(reg_idx,
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inst->readIntResult(ud_idx),
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inst->readTid());
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