X86: Implement mov from control register.
--HG-- extra : convert_revision : c8280f0686a3ae6d5c405327540ad15a3a5531f9
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3 changed files with 17 additions and 1 deletions
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@ -216,7 +216,7 @@
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0x04: decode LEGACY_DECODEVAL {
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0x04: decode LEGACY_DECODEVAL {
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// no prefix
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// no prefix
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0x0: decode OPCODE_OP_BOTTOM3 {
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0x0: decode OPCODE_OP_BOTTOM3 {
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0x0: mov_Rd_Cd();
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0x0: Inst::MOV(Rd,Cd);
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0x1: mov_Rd_Dd();
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0x1: mov_Rd_Dd();
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0x2: Inst::MOV(Cd,Rd);
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0x2: Inst::MOV(Cd,Rd);
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0x3: mov_Dd_Rd();
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0x3: mov_Dd_Rd();
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@ -193,6 +193,10 @@ def macroop MOV_C_R {
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wrcr reg, regm
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wrcr reg, regm
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};
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};
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def macroop MOV_R_C {
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rdcr reg, regm
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};
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def macroop MOV_R_S {
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def macroop MOV_R_S {
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rdsel reg, regm
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rdsel reg, regm
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};
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};
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@ -885,6 +885,18 @@ let {{
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class Zext(RegOp):
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class Zext(RegOp):
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code = 'DestReg = bits(psrc1, op2, 0);'
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code = 'DestReg = bits(psrc1, op2, 0);'
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class Rdcr(RegOp):
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def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
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super(Rdcr, self).__init__(dest, \
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src1, "NUM_INTREGS", flags, dataSize)
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code = '''
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if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) {
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fault = new InvalidOpcode();
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} else {
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DestReg = ControlSrc1;
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}
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'''
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class Wrcr(RegOp):
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class Wrcr(RegOp):
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def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
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def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
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super(Wrcr, self).__init__(dest, \
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super(Wrcr, self).__init__(dest, \
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