configs: cache: add cache line size option
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fb92578415
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981e1dd7ee
2 changed files with 7 additions and 3 deletions
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@ -35,7 +35,8 @@ from Caches import *
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def config_cache(options, system):
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def config_cache(options, system):
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if options.l2cache:
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if options.l2cache:
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system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc)
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system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc,
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block_size=options.cacheline_size)
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system.tol2bus = Bus()
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system.tol2bus = Bus()
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system.l2.cpu_side = system.tol2bus.port
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system.l2.cpu_side = system.tol2bus.port
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system.l2.mem_side = system.membus.port
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system.l2.mem_side = system.membus.port
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@ -43,8 +44,10 @@ def config_cache(options, system):
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for i in xrange(options.num_cpus):
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for i in xrange(options.num_cpus):
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if options.caches:
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if options.caches:
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icache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc)
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icache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc,
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dcache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc)
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block_size=options.cacheline_size)
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dcache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc,
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block_size=options.cacheline_size)
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if buildEnv['TARGET_ISA'] == 'x86':
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if buildEnv['TARGET_ISA'] == 'x86':
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system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
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system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
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PageTableWalkerCache(),
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PageTableWalkerCache(),
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@ -46,6 +46,7 @@ parser.add_option("--l1d_assoc", type="int", default=2)
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parser.add_option("--l1i_assoc", type="int", default=2)
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parser.add_option("--l1i_assoc", type="int", default=2)
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parser.add_option("--l2_assoc", type="int", default=8)
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parser.add_option("--l2_assoc", type="int", default=8)
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parser.add_option("--l3_assoc", type="int", default=16)
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parser.add_option("--l3_assoc", type="int", default=16)
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parser.add_option("--cacheline_size", type="int", default=64)
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# Run duration options
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# Run duration options
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parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
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parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
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