IGbE: Some fixes to the intel nic model.
--HG-- extra : convert_revision : 1c1275a9fb99966398b3add09da04bd53399ed2b
This commit is contained in:
parent
4e89518817
commit
9791b0f927
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@ -57,7 +57,7 @@ using namespace Net;
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IGbE::IGbE(const Params *p)
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IGbE::IGbE(const Params *p)
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: EtherDevice(p), etherInt(NULL), drainEvent(NULL), useFlowControl(p->use_flow_control),
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: EtherDevice(p), etherInt(NULL), drainEvent(NULL), useFlowControl(p->use_flow_control),
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rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size), rxTick(false),
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rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size), rxTick(false),
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txTick(false), txFifoTick(false), rdtrEvent(this), radvEvent(this),
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txTick(false), txFifoTick(false), rxDmaPacket(false), rdtrEvent(this), radvEvent(this),
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tadvEvent(this), tidvEvent(this), tickEvent(this), interEvent(this),
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tadvEvent(this), tidvEvent(this), tickEvent(this), interEvent(this),
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rxDescCache(this, name()+".RxDesc", p->rx_desc_cache_size),
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rxDescCache(this, name()+".RxDesc", p->rx_desc_cache_size),
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txDescCache(this, name()+".TxDesc", p->tx_desc_cache_size), clock(p->clock)
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txDescCache(this, name()+".TxDesc", p->tx_desc_cache_size), clock(p->clock)
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@ -113,7 +113,7 @@ EtherInt*
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IGbE::getEthPort(const std::string &if_name, int idx)
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IGbE::getEthPort(const std::string &if_name, int idx)
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{
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{
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if (if_name == "interface" && !etherInt) {
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if (if_name == "interface") {
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if (etherInt->getPeer())
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if (etherInt->getPeer())
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panic("Port already connected to\n");
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panic("Port already connected to\n");
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return etherInt;
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return etherInt;
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@ -504,8 +504,13 @@ IGbE::write(PacketPtr pkt)
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break;
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break;
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case REG_RDT:
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case REG_RDT:
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regs.rdt = val;
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regs.rdt = val;
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rxTick = true;
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DPRINTF(EthernetSM, "RXS: RDT Updated.\n");
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restartClock();
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if (getState() == SimObject::Running) {
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DPRINTF(EthernetSM, "RXS: RDT Fetching Descriptors!\n");
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rxDescCache.fetchDescriptors();
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} else {
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DPRINTF(EthernetSM, "RXS: RDT NOT Fetching Desc b/c draining!\n");
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}
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break;
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break;
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case REG_RDTR:
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case REG_RDTR:
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regs.rdtr = val;
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regs.rdtr = val;
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@ -531,8 +536,13 @@ IGbE::write(PacketPtr pkt)
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break;
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break;
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case REG_TDT:
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case REG_TDT:
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regs.tdt = val;
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regs.tdt = val;
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txTick = true;
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DPRINTF(EthernetSM, "TXS: TX Tail pointer updated\n");
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restartClock();
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if (getState() == SimObject::Running) {
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DPRINTF(EthernetSM, "TXS: TDT Fetching Descriptors!\n");
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txDescCache.fetchDescriptors();
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} else {
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DPRINTF(EthernetSM, "TXS: TDT NOT Fetching Desc b/c draining!\n");
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}
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break;
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break;
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case REG_TIDV:
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case REG_TIDV:
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regs.tidv = val;
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regs.tidv = val;
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@ -566,33 +576,47 @@ IGbE::postInterrupt(IntTypes t, bool now)
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assert(t);
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assert(t);
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// Interrupt is already pending
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// Interrupt is already pending
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if (t & regs.icr())
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if (t & regs.icr() && !now)
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return;
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return;
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if (regs.icr() & regs.imr)
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regs.icr = regs.icr() | t;
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{
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if (regs.itr.interval() == 0 || now) {
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regs.icr = regs.icr() | t;
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if (interEvent.scheduled()) {
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if (!interEvent.scheduled())
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interEvent.deschedule();
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interEvent.schedule(curTick + Clock::Int::ns * 256 *
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regs.itr.interval());
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} else {
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regs.icr = regs.icr() | t;
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if (regs.itr.interval() == 0 || now) {
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if (interEvent.scheduled())
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interEvent.deschedule();
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cpuPostInt();
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} else {
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DPRINTF(EthernetIntr, "EINT: Scheduling timer interrupt for %d ticks\n",
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Clock::Int::ns * 256 * regs.itr.interval());
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if (!interEvent.scheduled())
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interEvent.schedule(curTick + Clock::Int::ns * 256 * regs.itr.interval());
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}
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}
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cpuPostInt();
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} else {
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DPRINTF(EthernetIntr, "EINT: Scheduling timer interrupt for %d ticks\n",
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Clock::Int::ns * 256 * regs.itr.interval());
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if (!interEvent.scheduled()) {
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interEvent.schedule(curTick + Clock::Int::ns * 256 * regs.itr.interval());
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}
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}
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}
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}
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}
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void
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IGbE::delayIntEvent()
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{
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cpuPostInt();
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}
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void
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void
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IGbE::cpuPostInt()
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IGbE::cpuPostInt()
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{
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{
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if (!(regs.icr() & regs.imr)) {
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DPRINTF(Ethernet, "Interrupt Masked. Not Posting\n");
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return;
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}
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DPRINTF(Ethernet, "Posting Interrupt\n");
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if (interEvent.scheduled()) {
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interEvent.deschedule();
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}
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if (rdtrEvent.scheduled()) {
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if (rdtrEvent.scheduled()) {
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regs.icr.rxt0(1);
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regs.icr.rxt0(1);
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rdtrEvent.deschedule();
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rdtrEvent.deschedule();
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@ -613,7 +637,9 @@ IGbE::cpuPostInt()
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regs.icr.int_assert(1);
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regs.icr.int_assert(1);
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DPRINTF(EthernetIntr, "EINT: Posting interrupt to CPU now. Vector %#x\n",
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DPRINTF(EthernetIntr, "EINT: Posting interrupt to CPU now. Vector %#x\n",
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regs.icr());
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regs.icr());
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intrPost();
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intrPost();
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}
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}
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void
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void
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@ -630,20 +656,28 @@ IGbE::cpuClearInt()
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void
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void
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IGbE::chkInterrupt()
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IGbE::chkInterrupt()
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{
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{
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DPRINTF(Ethernet, "Checking interrupts icr: %#x imr: %#x\n", regs.icr(),
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regs.imr);
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// Check if we need to clear the cpu interrupt
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// Check if we need to clear the cpu interrupt
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if (!(regs.icr() & regs.imr)) {
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if (!(regs.icr() & regs.imr)) {
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DPRINTF(Ethernet, "Mask cleaned all interrupts\n");
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if (interEvent.scheduled())
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if (interEvent.scheduled())
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interEvent.deschedule();
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interEvent.deschedule();
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if (regs.icr.int_assert())
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if (regs.icr.int_assert())
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cpuClearInt();
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cpuClearInt();
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}
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}
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DPRINTF(Ethernet, "ITR = %#X itr.interval = %#X\n", regs.itr(), regs.itr.interval());
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if (regs.icr() & regs.imr) {
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if (regs.icr() & regs.imr) {
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if (regs.itr.interval() == 0) {
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if (regs.itr.interval() == 0) {
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cpuPostInt();
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cpuPostInt();
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} else {
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} else {
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if (!interEvent.scheduled())
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DPRINTF(Ethernet, "Possibly scheduling interrupt because of imr write\n");
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if (!interEvent.scheduled()) {
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DPRINTF(Ethernet, "Scheduling for %d\n", curTick + Clock::Int::ns
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* 256 * regs.itr.interval());
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interEvent.schedule(curTick + Clock::Int::ns * 256 * regs.itr.interval());
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interEvent.schedule(curTick + Clock::Int::ns * 256 * regs.itr.interval());
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}
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}
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}
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}
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}
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@ -682,6 +716,7 @@ IGbE::RxDescCache::pktComplete()
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RxDesc *desc;
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RxDesc *desc;
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desc = unusedCache.front();
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desc = unusedCache.front();
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uint16_t crcfixup = igbe->regs.rctl.secrc() ? 0 : 4 ;
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uint16_t crcfixup = igbe->regs.rctl.secrc() ? 0 : 4 ;
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desc->len = htole((uint16_t)(pktPtr->length + crcfixup));
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desc->len = htole((uint16_t)(pktPtr->length + crcfixup));
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DPRINTF(EthernetDesc, "pktPtr->length: %d stripcrc offset: %d value written: %d %d\n",
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DPRINTF(EthernetDesc, "pktPtr->length: %d stripcrc offset: %d value written: %d %d\n",
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@ -754,9 +789,10 @@ IGbE::RxDescCache::pktComplete()
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if (igbe->regs.radv.idv() && igbe->regs.rdtr.delay()) {
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if (igbe->regs.radv.idv() && igbe->regs.rdtr.delay()) {
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DPRINTF(EthernetSM, "RXS: Scheduling ADV for %d\n",
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DPRINTF(EthernetSM, "RXS: Scheduling ADV for %d\n",
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igbe->regs.radv.idv() * igbe->intClock());
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igbe->regs.radv.idv() * igbe->intClock());
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if (!igbe->radvEvent.scheduled())
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if (!igbe->radvEvent.scheduled()) {
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igbe->radvEvent.schedule(curTick + igbe->regs.radv.idv() *
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igbe->radvEvent.schedule(curTick + igbe->regs.radv.idv() *
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igbe->intClock());
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igbe->intClock());
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}
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}
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}
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// if neither radv or rdtr, maybe itr is set...
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// if neither radv or rdtr, maybe itr is set...
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@ -775,10 +811,13 @@ IGbE::RxDescCache::pktComplete()
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DPRINTF(EthernetDesc, "Processing of this descriptor complete\n");
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DPRINTF(EthernetDesc, "Processing of this descriptor complete\n");
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unusedCache.pop_front();
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unusedCache.pop_front();
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usedCache.push_back(desc);
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usedCache.push_back(desc);
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pktPtr = NULL;
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pktPtr = NULL;
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enableSm();
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enableSm();
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pktDone = true;
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pktDone = true;
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igbe->checkDrain();
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igbe->checkDrain();
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}
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}
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void
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void
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@ -843,11 +882,13 @@ IGbE::TxDescCache::getPacketSize()
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// I think we can just ignore these for now?
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// I think we can just ignore these for now?
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desc = unusedCache.front();
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desc = unusedCache.front();
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DPRINTF(EthernetDesc, "Descriptor upper: %#x lower: %#X\n", desc->d1,
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desc->d2);
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// is this going to be a tcp or udp packet?
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// is this going to be a tcp or udp packet?
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isTcp = TxdOp::tcp(desc) ? true : false;
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isTcp = TxdOp::tcp(desc) ? true : false;
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// make sure it's ipv4
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// make sure it's ipv4
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assert(TxdOp::ip(desc));
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//assert(TxdOp::ip(desc));
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TxdOp::setDd(desc);
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TxdOp::setDd(desc);
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unusedCache.pop_front();
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unusedCache.pop_front();
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@ -894,7 +935,6 @@ IGbE::TxDescCache::pktComplete()
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DPRINTF(EthernetDesc, "DMA of packet complete\n");
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DPRINTF(EthernetDesc, "DMA of packet complete\n");
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desc = unusedCache.front();
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desc = unusedCache.front();
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assert((TxdOp::isLegacy(desc) || TxdOp::isData(desc)) && TxdOp::getLen(desc));
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assert((TxdOp::isLegacy(desc) || TxdOp::isData(desc)) && TxdOp::getLen(desc));
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@ -951,20 +991,21 @@ IGbE::TxDescCache::pktComplete()
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ip->sum(cksum(ip));
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ip->sum(cksum(ip));
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DPRINTF(EthernetDesc, "Calculated IP checksum\n");
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DPRINTF(EthernetDesc, "Calculated IP checksum\n");
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}
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}
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if (TxdOp::txsm(desc)) {
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if (TxdOp::txsm(desc)) {
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if (isTcp) {
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TcpPtr tcp(ip);
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TcpPtr tcp(ip);
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UdpPtr udp(ip);
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assert(tcp);
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if (tcp) {
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tcp->sum(0);
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tcp->sum(0);
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tcp->sum(cksum(tcp));
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tcp->sum(cksum(tcp));
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DPRINTF(EthernetDesc, "Calculated TCP checksum\n");
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DPRINTF(EthernetDesc, "Calculated TCP checksum\n");
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} else {
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} else if (udp) {
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UdpPtr udp(ip);
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assert(udp);
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assert(udp);
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udp->sum(0);
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udp->sum(0);
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udp->sum(cksum(udp));
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udp->sum(cksum(udp));
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DPRINTF(EthernetDesc, "Calculated UDP checksum\n");
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DPRINTF(EthernetDesc, "Calculated UDP checksum\n");
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} else {
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}
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panic("Told to checksum, but don't know how\n");
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}
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}
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}
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}
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}
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@ -979,9 +1020,10 @@ IGbE::TxDescCache::pktComplete()
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if (igbe->regs.tadv.idv() && igbe->regs.tidv.idv()) {
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if (igbe->regs.tadv.idv() && igbe->regs.tidv.idv()) {
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DPRINTF(EthernetDesc, "setting tadv\n");
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DPRINTF(EthernetDesc, "setting tadv\n");
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if (!igbe->tadvEvent.scheduled())
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if (!igbe->tadvEvent.scheduled()) {
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igbe->tadvEvent.schedule(curTick + igbe->regs.tadv.idv() *
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igbe->tadvEvent.schedule(curTick + igbe->regs.tadv.idv() *
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igbe->intClock());
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igbe->intClock());
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}
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}
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}
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}
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}
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@ -1103,8 +1145,11 @@ IGbE::checkDrain()
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if (!drainEvent)
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if (!drainEvent)
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return;
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return;
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if (rxDescCache.hasOutstandingEvents() ||
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txFifoTick = false;
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txDescCache.hasOutstandingEvents()) {
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txTick = false;
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rxTick = false;
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if (!rxDescCache.hasOutstandingEvents() &&
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!txDescCache.hasOutstandingEvents()) {
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drainEvent->process();
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drainEvent->process();
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drainEvent = NULL;
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drainEvent = NULL;
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}
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}
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@ -1124,6 +1169,7 @@ IGbE::txStateMachine()
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// iteration we'll get the rest of the data
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// iteration we'll get the rest of the data
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if (txPacket && txDescCache.packetAvailable() && txPacket->length) {
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if (txPacket && txDescCache.packetAvailable() && txPacket->length) {
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bool success;
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bool success;
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DPRINTF(EthernetSM, "TXS: packet placed in TX FIFO\n");
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DPRINTF(EthernetSM, "TXS: packet placed in TX FIFO\n");
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success = txFifo.push(txPacket);
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success = txFifo.push(txPacket);
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txFifoTick = true;
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txFifoTick = true;
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@ -1146,11 +1192,12 @@ IGbE::txStateMachine()
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if (!txDescCache.packetWaiting()) {
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if (!txDescCache.packetWaiting()) {
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if (txDescCache.descLeft() == 0) {
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if (txDescCache.descLeft() == 0) {
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postInterrupt(IT_TXQE);
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txDescCache.writeback(0);
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DPRINTF(EthernetSM, "TXS: No descriptors left in ring, forcing "
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DPRINTF(EthernetSM, "TXS: No descriptors left in ring, forcing "
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"writeback stopping ticking and posting TXQE\n");
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"writeback stopping ticking and posting TXQE\n");
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txDescCache.writeback(0);
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txDescCache.fetchDescriptors();
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txTick = false;
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txTick = false;
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postInterrupt(IT_TXQE, true);
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return;
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return;
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}
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}
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@ -1170,12 +1217,13 @@ IGbE::txStateMachine()
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txFifo.reserve(size);
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txFifo.reserve(size);
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txDescCache.getPacketData(txPacket);
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txDescCache.getPacketData(txPacket);
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} else if (size <= 0) {
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} else if (size <= 0) {
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DPRINTF(EthernetSM, "TXS: getPacketSize returned: %d\n", size);
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DPRINTF(EthernetSM, "TXS: No packets to get, writing back used descriptors\n");
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DPRINTF(EthernetSM, "TXS: No packets to get, writing back used descriptors\n");
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txDescCache.writeback(0);
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txDescCache.writeback(0);
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} else {
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} else {
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txDescCache.writeback((cacheBlockSize()-1)>>4);
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DPRINTF(EthernetSM, "TXS: FIFO full, stopping ticking until space "
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DPRINTF(EthernetSM, "TXS: FIFO full, stopping ticking until space "
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"available in FIFO\n");
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"available in FIFO\n");
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txDescCache.writeback((cacheBlockSize()-1)>>4);
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|
||||||
txTick = false;
|
txTick = false;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1190,6 +1238,7 @@ bool
|
||||||
IGbE::ethRxPkt(EthPacketPtr pkt)
|
IGbE::ethRxPkt(EthPacketPtr pkt)
|
||||||
{
|
{
|
||||||
DPRINTF(Ethernet, "RxFIFO: Receiving pcakte from wire\n");
|
DPRINTF(Ethernet, "RxFIFO: Receiving pcakte from wire\n");
|
||||||
|
|
||||||
if (!regs.rctl.en()) {
|
if (!regs.rctl.en()) {
|
||||||
DPRINTF(Ethernet, "RxFIFO: RX not enabled, dropping\n");
|
DPRINTF(Ethernet, "RxFIFO: RX not enabled, dropping\n");
|
||||||
return true;
|
return true;
|
||||||
|
@ -1235,8 +1284,6 @@ IGbE::rxStateMachine()
|
||||||
}
|
}
|
||||||
|
|
||||||
if (descLeft == 0) {
|
if (descLeft == 0) {
|
||||||
DPRINTF(EthernetSM, "RXS: No descriptors left in ring, forcing"
|
|
||||||
" writeback and stopping ticking\n");
|
|
||||||
rxDescCache.writeback(0);
|
rxDescCache.writeback(0);
|
||||||
rxTick = false;
|
rxTick = false;
|
||||||
}
|
}
|
||||||
|
@ -1310,16 +1357,26 @@ IGbE::txWire()
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (etherInt->askBusy()) {
|
||||||
|
// We'll get woken up when the packet ethTxDone() gets called
|
||||||
|
txFifoTick = false;
|
||||||
|
} else {
|
||||||
|
if (DTRACE(EthernetSM)) {
|
||||||
|
IpPtr ip(txFifo.front());
|
||||||
|
if (ip)
|
||||||
|
DPRINTF(EthernetSM, "Transmitting Ip packet with Id=%d\n",
|
||||||
|
ip->id());
|
||||||
|
else
|
||||||
|
DPRINTF(EthernetSM, "Transmitting Non-Ip packet\n");
|
||||||
|
}
|
||||||
|
|
||||||
if (etherInt->sendPacket(txFifo.front())) {
|
bool r = etherInt->sendPacket(txFifo.front());
|
||||||
|
assert(r);
|
||||||
|
r += 1;
|
||||||
DPRINTF(EthernetSM, "TxFIFO: Successful transmit, bytes available in fifo: %d\n",
|
DPRINTF(EthernetSM, "TxFIFO: Successful transmit, bytes available in fifo: %d\n",
|
||||||
txFifo.avail());
|
txFifo.avail());
|
||||||
txFifo.pop();
|
txFifo.pop();
|
||||||
} else {
|
|
||||||
// We'll get woken up when the packet ethTxDone() gets called
|
|
||||||
txFifoTick = false;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
|
@ -1348,7 +1405,8 @@ IGbE::ethTxDone()
|
||||||
// fifo to send another packet
|
// fifo to send another packet
|
||||||
// tx sm to put more data into the fifo
|
// tx sm to put more data into the fifo
|
||||||
txFifoTick = true;
|
txFifoTick = true;
|
||||||
txTick = true;
|
if (txDescCache.descLeft() != 0)
|
||||||
|
txTick = true;
|
||||||
|
|
||||||
restartClock();
|
restartClock();
|
||||||
DPRINTF(EthernetSM, "TxFIFO: Transmission complete\n");
|
DPRINTF(EthernetSM, "TxFIFO: Transmission complete\n");
|
||||||
|
@ -1387,15 +1445,15 @@ IGbE::serialize(std::ostream &os)
|
||||||
SERIALIZE_SCALAR(radv_time);
|
SERIALIZE_SCALAR(radv_time);
|
||||||
|
|
||||||
if (tidvEvent.scheduled())
|
if (tidvEvent.scheduled())
|
||||||
rdtr_time = tidvEvent.when();
|
tidv_time = tidvEvent.when();
|
||||||
SERIALIZE_SCALAR(tidv_time);
|
SERIALIZE_SCALAR(tidv_time);
|
||||||
|
|
||||||
if (tadvEvent.scheduled())
|
if (tadvEvent.scheduled())
|
||||||
rdtr_time = tadvEvent.when();
|
tadv_time = tadvEvent.when();
|
||||||
SERIALIZE_SCALAR(tadv_time);
|
SERIALIZE_SCALAR(tadv_time);
|
||||||
|
|
||||||
if (interEvent.scheduled())
|
if (interEvent.scheduled())
|
||||||
rdtr_time = interEvent.when();
|
inter_time = interEvent.when();
|
||||||
SERIALIZE_SCALAR(inter_time);
|
SERIALIZE_SCALAR(inter_time);
|
||||||
|
|
||||||
nameOut(os, csprintf("%s.TxDescCache", name()));
|
nameOut(os, csprintf("%s.TxDescCache", name()));
|
||||||
|
|
|
@ -147,9 +147,10 @@ class IGbE : public EtherDevice
|
||||||
|
|
||||||
/** Send an interrupt to the cpu
|
/** Send an interrupt to the cpu
|
||||||
*/
|
*/
|
||||||
|
void delayIntEvent();
|
||||||
void cpuPostInt();
|
void cpuPostInt();
|
||||||
// Event to moderate interrupts
|
// Event to moderate interrupts
|
||||||
EventWrapper<IGbE, &IGbE::cpuPostInt> interEvent;
|
EventWrapper<IGbE, &IGbE::delayIntEvent> interEvent;
|
||||||
|
|
||||||
/** Clear the interupt line to the cpu
|
/** Clear the interupt line to the cpu
|
||||||
*/
|
*/
|
||||||
|
@ -177,6 +178,7 @@ class IGbE : public EtherDevice
|
||||||
virtual void updateHead(long h) = 0;
|
virtual void updateHead(long h) = 0;
|
||||||
virtual void enableSm() = 0;
|
virtual void enableSm() = 0;
|
||||||
virtual void intAfterWb() const {}
|
virtual void intAfterWb() const {}
|
||||||
|
virtual void fetchAfterWb() = 0;
|
||||||
|
|
||||||
std::deque<T*> usedCache;
|
std::deque<T*> usedCache;
|
||||||
std::deque<T*> unusedCache;
|
std::deque<T*> unusedCache;
|
||||||
|
@ -283,12 +285,6 @@ class IGbE : public EtherDevice
|
||||||
for (int x = 0; x < wbOut; x++)
|
for (int x = 0; x < wbOut; x++)
|
||||||
memcpy(&wbBuf[x], usedCache[x], sizeof(T));
|
memcpy(&wbBuf[x], usedCache[x], sizeof(T));
|
||||||
|
|
||||||
for (int x = 0; x < wbOut; x++) {
|
|
||||||
assert(usedCache.size());
|
|
||||||
delete usedCache[0];
|
|
||||||
usedCache.pop_front();
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
assert(wbOut);
|
assert(wbOut);
|
||||||
igbe->dmaWrite(igbe->platform->pciToDma(descBase() + curHead * sizeof(T)),
|
igbe->dmaWrite(igbe->platform->pciToDma(descBase() + curHead * sizeof(T)),
|
||||||
|
@ -307,7 +303,6 @@ class IGbE : public EtherDevice
|
||||||
else
|
else
|
||||||
max_to_fetch = descLen() - cachePnt;
|
max_to_fetch = descLen() - cachePnt;
|
||||||
|
|
||||||
|
|
||||||
max_to_fetch = std::min(max_to_fetch, (size - usedCache.size() -
|
max_to_fetch = std::min(max_to_fetch, (size - usedCache.size() -
|
||||||
unusedCache.size()));
|
unusedCache.size()));
|
||||||
|
|
||||||
|
@ -369,10 +364,16 @@ class IGbE : public EtherDevice
|
||||||
*/
|
*/
|
||||||
void wbComplete()
|
void wbComplete()
|
||||||
{
|
{
|
||||||
|
|
||||||
long curHead = descHead();
|
long curHead = descHead();
|
||||||
#ifndef NDEBUG
|
#ifndef NDEBUG
|
||||||
long oldHead = curHead;
|
long oldHead = curHead;
|
||||||
#endif
|
#endif
|
||||||
|
for (int x = 0; x < wbOut; x++) {
|
||||||
|
assert(usedCache.size());
|
||||||
|
delete usedCache[0];
|
||||||
|
usedCache.pop_front();
|
||||||
|
};
|
||||||
|
|
||||||
curHead += wbOut;
|
curHead += wbOut;
|
||||||
wbOut = 0;
|
wbOut = 0;
|
||||||
|
@ -387,12 +388,17 @@ class IGbE : public EtherDevice
|
||||||
oldHead, curHead);
|
oldHead, curHead);
|
||||||
|
|
||||||
// If we still have more to wb, call wb now
|
// If we still have more to wb, call wb now
|
||||||
|
bool oldMoreToWb = moreToWb;
|
||||||
if (moreToWb) {
|
if (moreToWb) {
|
||||||
DPRINTF(EthernetDesc, "Writeback has more todo\n");
|
DPRINTF(EthernetDesc, "Writeback has more todo\n");
|
||||||
writeback(wbAlignment);
|
writeback(wbAlignment);
|
||||||
}
|
}
|
||||||
|
|
||||||
intAfterWb();
|
intAfterWb();
|
||||||
igbe->checkDrain();
|
if (!oldMoreToWb) {
|
||||||
|
igbe->checkDrain();
|
||||||
|
}
|
||||||
|
fetchAfterWb();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
@ -502,6 +508,10 @@ class IGbE : public EtherDevice
|
||||||
virtual long descTail() const { return igbe->regs.rdt(); }
|
virtual long descTail() const { return igbe->regs.rdt(); }
|
||||||
virtual void updateHead(long h) { igbe->regs.rdh(h); }
|
virtual void updateHead(long h) { igbe->regs.rdh(h); }
|
||||||
virtual void enableSm();
|
virtual void enableSm();
|
||||||
|
virtual void fetchAfterWb() {
|
||||||
|
if (!igbe->rxTick && igbe->getState() == SimObject::Running)
|
||||||
|
fetchDescriptors();
|
||||||
|
}
|
||||||
|
|
||||||
bool pktDone;
|
bool pktDone;
|
||||||
|
|
||||||
|
@ -544,7 +554,13 @@ class IGbE : public EtherDevice
|
||||||
virtual long descLen() const { return igbe->regs.tdlen() >> 4; }
|
virtual long descLen() const { return igbe->regs.tdlen() >> 4; }
|
||||||
virtual void updateHead(long h) { igbe->regs.tdh(h); }
|
virtual void updateHead(long h) { igbe->regs.tdh(h); }
|
||||||
virtual void enableSm();
|
virtual void enableSm();
|
||||||
virtual void intAfterWb() const { igbe->postInterrupt(iGbReg::IT_TXDW);}
|
virtual void intAfterWb() const {
|
||||||
|
igbe->postInterrupt(iGbReg::IT_TXDW);
|
||||||
|
}
|
||||||
|
virtual void fetchAfterWb() {
|
||||||
|
if (!igbe->txTick && igbe->getState() == SimObject::Running)
|
||||||
|
fetchDescriptors();
|
||||||
|
}
|
||||||
|
|
||||||
bool pktDone;
|
bool pktDone;
|
||||||
bool isTcp;
|
bool isTcp;
|
||||||
|
|
Loading…
Reference in a new issue