Alpha: Get rid of some #if FULL_SYSTEMs in the Alpha ISA description.
The remaining ones are more complicated and may require adjustments in other parts of the simulator.
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@ -203,21 +203,13 @@ decode OPCODE default Unknown::unknown() {
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31: decode IMM {
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31: decode IMM {
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1: decode INTIMM {
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1: decode INTIMM {
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// return EV5 for FULL_SYSTEM and EV6 otherwise
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// return EV5 for FULL_SYSTEM and EV6 otherwise
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1: implver({{
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1: implver({{ Rc = FULL_SYSTEM ? 1 : 2 }});
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#if FULL_SYSTEM
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Rc = 1;
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#else
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Rc = 2;
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#endif
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}});
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}
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}
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}
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}
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}
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}
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#if FULL_SYSTEM
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// The mysterious 11.25...
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// The mysterious 11.25...
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0x25: WarnUnimpl::eleven25();
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0x25: WarnUnimpl::eleven25();
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#endif
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}
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}
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0x12: decode INTFUNC {
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0x12: decode INTFUNC {
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@ -784,15 +776,11 @@ decode OPCODE default Unknown::unknown() {
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format BasicOperate {
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format BasicOperate {
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0xc000: rpcc({{
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0xc000: rpcc({{
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#if FULL_SYSTEM
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/* Rb is a fake dependency so here is a fun way to get
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/* Rb is a fake dependency so here is a fun way to get
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* the parser to understand that.
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* the parser to understand that.
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*/
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*/
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uint64_t unused_var M5_VAR_USED = Rb;
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Ra = xc->readMiscReg(IPR_CC) + (Rb & 0);
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Ra = FULL_SYSTEM ? xc->readMiscReg(IPR_CC) : curTick();
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#else
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Ra = curTick();
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#endif
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}}, IsUnverifiable);
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}}, IsUnverifiable);
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// All of the barrier instructions below do nothing in
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// All of the barrier instructions below do nothing in
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@ -817,23 +805,20 @@ decode OPCODE default Unknown::unknown() {
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0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
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0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
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}
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}
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#if FULL_SYSTEM
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0xe000: decode FULL_SYSTEM {
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format BasicOperate {
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0: FailUnimpl::rc_se();
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0xe000: rc({{
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default: BasicOperate::rc({{
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Ra = IntrFlag;
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Ra = IntrFlag;
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IntrFlag = 0;
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IntrFlag = 0;
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}}, IsNonSpeculative, IsUnverifiable);
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}}, IsNonSpeculative, IsUnverifiable);
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0xf000: rs({{
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}
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0xf000: decode FULL_SYSTEM {
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0: FailUnimpl::rs_se();
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default: BasicOperate::rs({{
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Ra = IntrFlag;
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Ra = IntrFlag;
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IntrFlag = 1;
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IntrFlag = 1;
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}}, IsNonSpeculative, IsUnverifiable);
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}}, IsNonSpeculative, IsUnverifiable);
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}
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}
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#else
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format FailUnimpl {
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0xe000: rc();
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0xf000: rs();
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}
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#endif
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}
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}
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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@ -42,21 +42,14 @@ output exec {{
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/// instruction in full-system mode.
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/// instruction in full-system mode.
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/// @retval Full-system mode: NoFault if FP is enabled, FenFault
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/// @retval Full-system mode: NoFault if FP is enabled, FenFault
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/// if not. Non-full-system mode: always returns NoFault.
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/// if not. Non-full-system mode: always returns NoFault.
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#if FULL_SYSTEM
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inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
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inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
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{
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{
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Fault fault = NoFault; // dummy... this ipr access should not fault
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Fault fault = NoFault; // dummy... this ipr access should not fault
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if (!ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
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if (FULL_SYSTEM && !ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
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fault = new FloatEnableFault;
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fault = new FloatEnableFault;
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}
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}
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return fault;
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return fault;
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}
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}
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#else
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inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
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{
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return NoFault;
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}
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#endif
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}};
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}};
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output header {{
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output header {{
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