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Alpha: Get rid of some #if FULL_SYSTEMs in the Alpha ISA description.

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The remaining ones are more complicated and may require adjustments in other
parts of the simulator.
This commit is contained in:
Gabe Black 2011-09-19 03:40:30 -07:00
parent 44659cb608
commit 978e41eab0
2 changed files with 14 additions and 36 deletions
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35
src/arch/alpha/isa/decoder.isa
View file

@ -203,21 +203,13 @@ decode OPCODE default Unknown::unknown() {
31: decode IMM { 31: decode IMM {
1: decode INTIMM { 1: decode INTIMM {
// return EV5 for FULL_SYSTEM and EV6 otherwise // return EV5 for FULL_SYSTEM and EV6 otherwise
1: implver({{ 1: implver({{ Rc = FULL_SYSTEM ? 1 : 2 }});
#if FULL_SYSTEM
Rc = 1;
#else
Rc = 2;
#endif
}});
} }
} }
} }
#if FULL_SYSTEM
// The mysterious 11.25... // The mysterious 11.25...
0x25: WarnUnimpl::eleven25(); 0x25: WarnUnimpl::eleven25();
#endif
} }
0x12: decode INTFUNC { 0x12: decode INTFUNC {
@ -784,15 +776,11 @@ decode OPCODE default Unknown::unknown() {
format BasicOperate { format BasicOperate {
0xc000: rpcc({{ 0xc000: rpcc({{
#if FULL_SYSTEM
/* Rb is a fake dependency so here is a fun way to get /* Rb is a fake dependency so here is a fun way to get
* the parser to understand that. * the parser to understand that.
*/ */
Ra = xc->readMiscReg(IPR_CC) + (Rb & 0); uint64_t unused_var M5_VAR_USED = Rb;
Ra = FULL_SYSTEM ? xc->readMiscReg(IPR_CC) : curTick();
#else
Ra = curTick();
#endif
}}, IsUnverifiable); }}, IsUnverifiable);
// All of the barrier instructions below do nothing in // All of the barrier instructions below do nothing in
@ -817,23 +805,20 @@ decode OPCODE default Unknown::unknown() {
0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp); 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
} }
#if FULL_SYSTEM 0xe000: decode FULL_SYSTEM {
format BasicOperate { 0: FailUnimpl::rc_se();
0xe000: rc({{ default: BasicOperate::rc({{
Ra = IntrFlag; Ra = IntrFlag;
IntrFlag = 0; IntrFlag = 0;
}}, IsNonSpeculative, IsUnverifiable); }}, IsNonSpeculative, IsUnverifiable);
0xf000: rs({{ }
0xf000: decode FULL_SYSTEM {
0: FailUnimpl::rs_se();
default: BasicOperate::rs({{
Ra = IntrFlag; Ra = IntrFlag;
IntrFlag = 1; IntrFlag = 1;
}}, IsNonSpeculative, IsUnverifiable); }}, IsNonSpeculative, IsUnverifiable);
} }
#else
format FailUnimpl {
0xe000: rc();
0xf000: rs();
}
#endif
} }
#if FULL_SYSTEM #if FULL_SYSTEM

9
src/arch/alpha/isa/fp.isa
View file

@ -42,21 +42,14 @@ output exec {{
/// instruction in full-system mode. /// instruction in full-system mode.
/// @retval Full-system mode: NoFault if FP is enabled, FenFault /// @retval Full-system mode: NoFault if FP is enabled, FenFault
/// if not. Non-full-system mode: always returns NoFault. /// if not. Non-full-system mode: always returns NoFault.
#if FULL_SYSTEM
inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
{ {
Fault fault = NoFault; // dummy... this ipr access should not fault Fault fault = NoFault; // dummy... this ipr access should not fault
if (!ICSR_FPE(xc->readMiscReg(IPR_ICSR))) { if (FULL_SYSTEM && !ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
fault = new FloatEnableFault; fault = new FloatEnableFault;
} }
return fault; return fault;
} }
#else
inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
{
return NoFault;
}
#endif
}}; }};
output header {{ output header {{