diff --git a/cpu/beta_cpu/full_cpu.hh b/cpu/beta_cpu/full_cpu.hh
index a7916f9ae..42370f1e7 100644
--- a/cpu/beta_cpu/full_cpu.hh
+++ b/cpu/beta_cpu/full_cpu.hh
@@ -40,7 +40,7 @@ class BaseFullCPU : public BaseCPU
     BaseFullCPU(Params &params);
 #endif // FULL_SYSTEM
 
-  private:
+  protected:
     int cpu_id;
 };
 
diff --git a/cpu/beta_cpu/regfile.hh b/cpu/beta_cpu/regfile.hh
index d7664707d..b88a33bfb 100644
--- a/cpu/beta_cpu/regfile.hh
+++ b/cpu/beta_cpu/regfile.hh
@@ -428,11 +428,6 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
         break;
 
       case ISA::IPR_IPLR:
-#ifdef DEBUG
-        if (break_ipl != -1 && break_ipl == (val & 0x1f))
-            debug_break();
-#endif
-
         // only write least significant five bits - interrupt level
         ipr[idx] = val & 0x1f;
         break;