O3: Fixes fetch deadlock when the interrupt clears before CPU handles it.
When this condition occurs the cpu should restart the fetch stage to fetch from the original execution path. Fault handling in the commit stage is cleaned up a little bit so the control flow is simplier. Finally, if an instruction is being used to carry a fault it isn't executed, so the fault propagates appropriately.
This commit is contained in:
parent
965a01d913
commit
96375409ea
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@ -102,7 +102,7 @@ class Interrupts : public SimObject
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void
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clear(int int_num, int index)
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{
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DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
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DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
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if (int_num < 0 || int_num >= NumInterruptTypes)
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panic("int_num out of bounds\n");
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@ -112,7 +112,6 @@ class Interrupts : public SimObject
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interrupts[int_num] = false;
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intStatus &= ~(ULL(1) << int_num);
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}
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void
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@ -255,6 +255,9 @@ class DefaultCommit
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#if FULL_SYSTEM
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/** Handles processing an interrupt. */
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void handleInterrupt();
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/** Get fetch redirecting so we can handle an interrupt */
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void propagateInterrupt();
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#endif // FULL_SYSTEM
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/** Commits as many instructions as possible. */
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@ -674,7 +674,15 @@ template <class Impl>
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void
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DefaultCommit<Impl>::handleInterrupt()
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{
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if (interrupt != NoFault) {
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// Verify that we still have an interrupt to handle
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if (!cpu->checkInterrupts(cpu->tcBase(0))) {
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DPRINTF(Commit, "Pending interrupt is cleared by master before "
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"it got handled. Restart fetching from the orig path.\n");
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toIEW->commitInfo[0].clearInterrupt = true;
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interrupt = NoFault;
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return;
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}
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// Wait until the ROB is empty and all stores have drained in
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// order to enter the interrupt.
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if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
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@ -702,10 +710,16 @@ DefaultCommit<Impl>::handleInterrupt()
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} else {
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DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
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}
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} else if (commitStatus[0] != TrapPending &&
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cpu->checkInterrupts(cpu->tcBase(0)) &&
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!trapSquash[0] &&
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!tcSquash[0]) {
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}
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template <class Impl>
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void
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DefaultCommit<Impl>::propagateInterrupt()
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{
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if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
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tcSquash[0])
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return;
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// Process interrupts if interrupts are enabled, not in PAL
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// mode, and no other traps or external squashes are currently
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// pending.
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@ -714,14 +728,13 @@ DefaultCommit<Impl>::handleInterrupt()
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// Get any interrupt that happened
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interrupt = cpu->getInterrupts();
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if (interrupt != NoFault) {
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// Tell fetch that there is an interrupt pending. This
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// will make fetch wait until it sees a non PAL-mode PC,
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// at which point it stops fetching instructions.
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if (interrupt != NoFault)
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toIEW->commitInfo[0].interruptPending = true;
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}
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}
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}
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#endif // FULL_SYSTEM
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template <class Impl>
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@ -730,12 +743,13 @@ DefaultCommit<Impl>::commit()
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{
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#if FULL_SYSTEM
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// Check for any interrupt, and start processing it. Or if we
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// have an outstanding interrupt and are at a point when it is
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// valid to take an interrupt, process it.
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if (cpu->checkInterrupts(cpu->tcBase(0))) {
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// Check for any interrupt that we've already squashed for and start processing it.
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if (interrupt != NoFault)
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handleInterrupt();
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}
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// Check if we have a interrupt and get read to handle it
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if (cpu->checkInterrupts(cpu->tcBase(0)))
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propagateInterrupt();
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#endif // FULL_SYSTEM
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////////////////////////////////////
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@ -244,6 +244,15 @@ class DefaultFetch
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*/
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bool fetchCacheLine(Addr vaddr, Fault &ret_fault, ThreadID tid, Addr pc);
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/** Check if an interrupt is pending and that we need to handle
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*/
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bool
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checkInterrupt(Addr pc)
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{
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return (interruptPending && (THE_ISA != ALPHA_ISA || !(pc & 0x3)));
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}
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/** Squashes a specific thread and resets the PC. */
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inline void doSquash(const TheISA::PCState &newPC, ThreadID tid);
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@ -1,4 +1,16 @@
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/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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@ -550,7 +562,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, Fault &ret_fault, ThreadID tid,
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DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n",
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tid);
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return false;
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} else if (interruptPending && !(pc & 0x3)) {
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} else if (checkInterrupt(pc)) {
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// Hold off fetch from getting new instructions when:
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// Cache is blocked, or
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// while an interrupt is pending and we're not in PAL mode, or
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@ -1250,8 +1262,8 @@ DefaultFetch<Impl>::fetch(bool &status_change)
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fetchStatus[tid] = TrapPending;
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status_change = true;
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DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %s",
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tid, fault->name(), thisPC);
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DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %s, sending nop "
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"[sn:%lli]\n", tid, fault->name(), thisPC, inst_seq);
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}
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}
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@ -1255,7 +1255,13 @@ DefaultIEW<Impl>::executeInsts()
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}
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} else {
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// If the instruction has already faulted, then skip executing it.
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// Such case can happen when it faulted during ITLB translation.
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// If we execute the instruction (even if it's a nop) the fault
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// will be replaced and we will lose it.
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if (inst->getFault() == NoFault) {
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inst->execute();
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}
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inst->setExecuted();
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