X86: Implement MSR reads and writes and the wrsmr and rdmsr instructions.
There are no priviledge checks, so these instructions will all work in all modes. --HG-- extra : convert_revision : ff893eb569313d8aecbfffb47bcbd1c2d65cd393
This commit is contained in:
parent
8b35bd6fe7
commit
9498e536c0
10 changed files with 401 additions and 19 deletions
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@ -179,6 +179,7 @@ if env['TARGET_ISA'] == 'x86':
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'general_purpose/system_calls.py',
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'general_purpose/system_calls.py',
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'system/__init__.py',
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'system/__init__.py',
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'system/undefined_operation.py',
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'system/undefined_operation.py',
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'system/msrs.py',
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'simd128/__init__.py',
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'simd128/__init__.py',
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'simd128/integer/__init__.py',
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'simd128/integer/__init__.py',
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'simd128/integer/data_transfer/__init__.py',
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'simd128/integer/data_transfer/__init__.py',
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@ -211,9 +211,9 @@
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default: Inst::UD2();
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default: Inst::UD2();
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}
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}
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0x06: decode OPCODE_OP_BOTTOM3 {
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0x06: decode OPCODE_OP_BOTTOM3 {
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0x0: wrmsr();
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0x0: Inst::WRMSR();
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0x1: rdtsc();
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0x1: rdtsc();
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0x2: rdmsr();
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0x2: Inst::RDMSR();
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0x3: rdpmc();
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0x3: rdpmc();
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0x4: sysenter();
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0x4: sysenter();
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0x5: sysexit();
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0x5: sysexit();
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@ -53,7 +53,8 @@
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#
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#
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# Authors: Gabe Black
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# Authors: Gabe Black
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categories = ["undefined_operation"]
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categories = ["undefined_operation",
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"msrs"]
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microcode = ""
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microcode = ""
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for category in categories:
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for category in categories:
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74
src/arch/x86/isa/insts/system/msrs.py
Normal file
74
src/arch/x86/isa/insts/system/msrs.py
Normal file
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@ -0,0 +1,74 @@
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# Copyright (c) 2007 The Hewlett-Packard Development Company
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# All rights reserved.
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#
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# Redistribution and use of this software in source and binary forms,
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# with or without modification, are permitted provided that the
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# following conditions are met:
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#
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# The software must be used only for Non-Commercial Use which means any
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# use which is NOT directed to receiving any direct monetary
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# compensation for, or commercial advantage from such use. Illustrative
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# examples of non-commercial use are academic research, personal study,
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# teaching, education and corporate research & development.
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# Illustrative examples of commercial use are distributing products for
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# commercial advantage and providing services using the software for
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# commercial advantage.
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#
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# If you wish to use this software or functionality therein that may be
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# covered by patents for commercial use, please contact:
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# Director of Intellectual Property Licensing
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# Office of Strategy and Technology
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# Hewlett-Packard Company
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# 1501 Page Mill Road
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# Palo Alto, California 94304
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#
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# Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer. Redistributions
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# in binary form must reproduce the above copyright notice, this list of
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# conditions and the following disclaimer in the documentation and/or
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# other materials provided with the distribution. Neither the name of
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# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission. No right of
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# sublicense is granted herewith. Derivatives of the software and
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# output created using the software may be prepared, but only for
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# Non-Commercial Uses. Derivatives of the software may be shared with
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# others provided: (i) the others agree to abide by the list of
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# conditions herein which includes the Non-Commercial Use restrictions;
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# and (ii) such Derivatives of the software include the above copyright
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# notice to acknowledge the contribution from this software where
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# applicable, this list of conditions and the disclaimer below.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Gabe Black
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microcode = '''
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def macroop WRMSR
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{
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limm t1, "IntAddrPrefixMSR >> 3"
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ld t2, intseg, [8, t1, rcx], dataSize=8, addressSize=4
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mov rax, rax, t2, dataSize=4
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srli t2, t2, 32, dataSize=8
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mov rdx, rdx, t2, dataSize=4
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};
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def macroop RDMSR
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{
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limm t1, "IntAddrPrefixMSR >> 3"
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mov t2, t2, rdx, dataSize=4
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slli t2, t2, 32, dataSize=8
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mov t2, t2, rax, dataSize=4
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st t2, intseg, [8, t1, rcx], dataSize=8, addressSize=4
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};
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'''
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@ -106,6 +106,10 @@ let {{
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assembler.symbols["riprel"] = \
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assembler.symbols["riprel"] = \
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["1", assembler.symbols["t0"], assembler.symbols["t7"]]
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["1", assembler.symbols["t0"], assembler.symbols["t7"]]
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# This segment selects an internal address space mapped to MSRs,
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# CPUID info, etc.
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assembler.symbols["intseg"] = "NUM_SEGMENTREGS"
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for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di'):
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for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di'):
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assembler.symbols["r%s" % reg] = "INTREG_R%s" % reg.upper()
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assembler.symbols["r%s" % reg] = "INTREG_R%s" % reg.upper()
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@ -325,13 +325,13 @@ def template MicroLdStOpConstructor {{
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let {{
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let {{
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class LdStOp(X86Microop):
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class LdStOp(X86Microop):
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def __init__(self, data, segment, addr, disp, dataSize):
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def __init__(self, data, segment, addr, disp, dataSize, addressSize):
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self.data = data
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self.data = data
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[self.scale, self.index, self.base] = addr
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[self.scale, self.index, self.base] = addr
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self.disp = disp
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self.disp = disp
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self.segment = segment
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self.segment = segment
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self.dataSize = dataSize
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self.dataSize = dataSize
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self.addressSize = "env.addressSize"
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self.addressSize = addressSize
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def getAllocator(self, *microFlags):
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def getAllocator(self, *microFlags):
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allocator = '''new %(class_name)s(machInst, mnemonic
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allocator = '''new %(class_name)s(machInst, mnemonic
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@ -378,10 +378,10 @@ let {{
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exec_output += MicroLoadCompleteAcc.subst(iop)
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exec_output += MicroLoadCompleteAcc.subst(iop)
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class LoadOp(LdStOp):
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class LoadOp(LdStOp):
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def __init__(self, data, segment, addr,
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def __init__(self, data, segment, addr, disp = 0,
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disp = 0, dataSize="env.dataSize"):
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dataSize="env.dataSize", addressSize="env.addressSize"):
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super(LoadOp, self).__init__(data, segment,
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super(LoadOp, self).__init__(data, segment,
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addr, disp, dataSize)
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addr, disp, dataSize, addressSize)
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self.className = Name
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self.className = Name
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self.mnemonic = name
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self.mnemonic = name
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@ -411,10 +411,10 @@ let {{
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exec_output += MicroStoreCompleteAcc.subst(iop)
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exec_output += MicroStoreCompleteAcc.subst(iop)
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class StoreOp(LdStOp):
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class StoreOp(LdStOp):
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def __init__(self, data, segment, addr,
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def __init__(self, data, segment, addr, disp = 0,
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disp = 0, dataSize="env.dataSize"):
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dataSize="env.dataSize", addressSize="env.addressSize"):
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super(StoreOp, self).__init__(data, segment,
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super(StoreOp, self).__init__(data, segment,
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addr, disp, dataSize)
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addr, disp, dataSize, addressSize)
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self.className = Name
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self.className = Name
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self.mnemonic = name
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self.mnemonic = name
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@ -432,10 +432,10 @@ let {{
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exec_output += MicroLeaExecute.subst(iop)
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exec_output += MicroLeaExecute.subst(iop)
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class LeaOp(LdStOp):
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class LeaOp(LdStOp):
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def __init__(self, data, segment, addr,
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def __init__(self, data, segment, addr, disp = 0,
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disp = 0, dataSize="env.dataSize"):
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dataSize="env.dataSize", addressSize="env.addressSize"):
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super(LeaOp, self).__init__(data, segment,
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super(LeaOp, self).__init__(data, segment,
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addr, disp, dataSize)
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addr, disp, dataSize, addressSize)
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self.className = "Lea"
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self.className = "Lea"
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self.mnemonic = "lea"
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self.mnemonic = "lea"
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@ -164,7 +164,7 @@ namespace X86ISA
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MISCREG_MTRR_FIX_16K_80000,
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MISCREG_MTRR_FIX_16K_80000,
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MISCREG_MTRR_FIX_16K_A0000,
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MISCREG_MTRR_FIX_16K_A0000,
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MISCREG_MTRR_FIX_4K_C0000,
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MISCREG_MTRR_FIX_4K_C0000,
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MISCREG_MTRR_FIX_4k_C8000,
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MISCREG_MTRR_FIX_4K_C8000,
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MISCREG_MTRR_FIX_4K_D0000,
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MISCREG_MTRR_FIX_4K_D0000,
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MISCREG_MTRR_FIX_4K_D8000,
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MISCREG_MTRR_FIX_4K_D8000,
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MISCREG_MTRR_FIX_4K_E0000,
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MISCREG_MTRR_FIX_4K_E0000,
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@ -76,7 +76,7 @@ namespace X86ISA
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#if !FULL_SYSTEM
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#if !FULL_SYSTEM
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panic("Shouldn't have a memory mapped register in SE\n");
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panic("Shouldn't have a memory mapped register in SE\n");
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#else
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#else
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panic("Memory mapped registers aren't implemented for x86!\n");
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pkt->set(xc->readMiscReg(pkt->getAddr() / sizeof(MiscReg)));
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#endif
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#endif
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}
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}
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@ -86,7 +86,8 @@ namespace X86ISA
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#if !FULL_SYSTEM
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#if !FULL_SYSTEM
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panic("Shouldn't have a memory mapped register in SE\n");
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panic("Shouldn't have a memory mapped register in SE\n");
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#else
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#else
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panic("Memory mapped registers aren't implemented for x86!\n");
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xc->setMiscReg(pkt->getAddr() / sizeof(MiscReg),
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gtoh(pkt->get<uint64_t>()));
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#endif
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#endif
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}
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}
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};
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};
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@ -61,6 +61,7 @@
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#include "arch/x86/pagetable.hh"
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#include "arch/x86/pagetable.hh"
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#include "arch/x86/tlb.hh"
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#include "arch/x86/tlb.hh"
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#include "arch/x86/x86_traits.hh"
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#include "base/bitfield.hh"
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#include "base/bitfield.hh"
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#include "base/trace.hh"
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#include "base/trace.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/thread_context.hh"
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@ -142,10 +143,304 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
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uint32_t flags = req->getFlags();
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uint32_t flags = req->getFlags();
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bool storeCheck = flags & StoreCheck;
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bool storeCheck = flags & StoreCheck;
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int seg = flags & (mask(NUM_SEGMENTREGS));
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int seg = flags & mask(3);
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//XXX Junk code to surpress the warning
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//XXX Junk code to surpress the warning
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if (storeCheck) seg = seg;
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if (storeCheck);
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// If this is true, we're dealing with a request to read an internal
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// value.
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if (seg == NUM_SEGMENTREGS) {
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Addr prefix = vaddr & IntAddrPrefixMask;
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if (prefix == IntAddrPrefixCPUID) {
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panic("CPUID memory space not yet implemented!\n");
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} else if (prefix == IntAddrPrefixMSR) {
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req->setMmapedIpr(true);
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Addr regNum = 0;
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switch (vaddr & ~IntAddrPrefixMask) {
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case 0x10:
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regNum = MISCREG_TSC;
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break;
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case 0xFE:
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regNum = MISCREG_MTRRCAP;
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break;
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case 0x174:
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regNum = MISCREG_SYSENTER_CS;
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break;
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case 0x175:
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regNum = MISCREG_SYSENTER_ESP;
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break;
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case 0x176:
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regNum = MISCREG_SYSENTER_EIP;
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break;
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case 0x179:
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regNum = MISCREG_MCG_CAP;
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break;
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case 0x17A:
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regNum = MISCREG_MCG_STATUS;
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break;
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case 0x17B:
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regNum = MISCREG_MCG_CTL;
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break;
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case 0x1D9:
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regNum = MISCREG_DEBUG_CTL_MSR;
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break;
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case 0x1DB:
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regNum = MISCREG_LAST_BRANCH_FROM_IP;
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break;
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case 0x1DC:
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regNum = MISCREG_LAST_BRANCH_TO_IP;
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break;
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case 0x1DD:
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regNum = MISCREG_LAST_EXCEPTION_FROM_IP;
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break;
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case 0x1DE:
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regNum = MISCREG_LAST_EXCEPTION_TO_IP;
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break;
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case 0x200:
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regNum = MISCREG_MTRR_PHYS_BASE_0;
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break;
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case 0x201:
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regNum = MISCREG_MTRR_PHYS_MASK_0;
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break;
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case 0x202:
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regNum = MISCREG_MTRR_PHYS_BASE_1;
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break;
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case 0x203:
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regNum = MISCREG_MTRR_PHYS_MASK_1;
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break;
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case 0x204:
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regNum = MISCREG_MTRR_PHYS_BASE_2;
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break;
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case 0x205:
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regNum = MISCREG_MTRR_PHYS_MASK_2;
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break;
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case 0x206:
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regNum = MISCREG_MTRR_PHYS_BASE_3;
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break;
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case 0x207:
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regNum = MISCREG_MTRR_PHYS_MASK_3;
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break;
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case 0x208:
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regNum = MISCREG_MTRR_PHYS_BASE_4;
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break;
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case 0x209:
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regNum = MISCREG_MTRR_PHYS_MASK_4;
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break;
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case 0x20A:
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regNum = MISCREG_MTRR_PHYS_BASE_5;
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break;
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case 0x20B:
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regNum = MISCREG_MTRR_PHYS_MASK_5;
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break;
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case 0x20C:
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regNum = MISCREG_MTRR_PHYS_BASE_6;
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break;
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case 0x20D:
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regNum = MISCREG_MTRR_PHYS_MASK_6;
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break;
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case 0x20E:
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regNum = MISCREG_MTRR_PHYS_BASE_7;
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break;
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case 0x20F:
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regNum = MISCREG_MTRR_PHYS_MASK_7;
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break;
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case 0x250:
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regNum = MISCREG_MTRR_FIX_64K_00000;
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break;
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case 0x258:
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regNum = MISCREG_MTRR_FIX_16K_80000;
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break;
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case 0x259:
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regNum = MISCREG_MTRR_FIX_16K_A0000;
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||||||
|
break;
|
||||||
|
case 0x268:
|
||||||
|
regNum = MISCREG_MTRR_FIX_4K_C0000;
|
||||||
|
break;
|
||||||
|
case 0x269:
|
||||||
|
regNum = MISCREG_MTRR_FIX_4K_C8000;
|
||||||
|
break;
|
||||||
|
case 0x26A:
|
||||||
|
regNum = MISCREG_MTRR_FIX_4K_D0000;
|
||||||
|
break;
|
||||||
|
case 0x26B:
|
||||||
|
regNum = MISCREG_MTRR_FIX_4K_D8000;
|
||||||
|
break;
|
||||||
|
case 0x26C:
|
||||||
|
regNum = MISCREG_MTRR_FIX_4K_E0000;
|
||||||
|
break;
|
||||||
|
case 0x26D:
|
||||||
|
regNum = MISCREG_MTRR_FIX_4K_E8000;
|
||||||
|
break;
|
||||||
|
case 0x26E:
|
||||||
|
regNum = MISCREG_MTRR_FIX_4K_F0000;
|
||||||
|
break;
|
||||||
|
case 0x26F:
|
||||||
|
regNum = MISCREG_MTRR_FIX_4K_F8000;
|
||||||
|
break;
|
||||||
|
case 0x277:
|
||||||
|
regNum = MISCREG_PAT;
|
||||||
|
break;
|
||||||
|
case 0x2FF:
|
||||||
|
regNum = MISCREG_DEF_TYPE;
|
||||||
|
break;
|
||||||
|
case 0x400:
|
||||||
|
regNum = MISCREG_MC0_CTL;
|
||||||
|
break;
|
||||||
|
case 0x404:
|
||||||
|
regNum = MISCREG_MC1_CTL;
|
||||||
|
break;
|
||||||
|
case 0x408:
|
||||||
|
regNum = MISCREG_MC2_CTL;
|
||||||
|
break;
|
||||||
|
case 0x40C:
|
||||||
|
regNum = MISCREG_MC3_CTL;
|
||||||
|
break;
|
||||||
|
case 0x410:
|
||||||
|
regNum = MISCREG_MC4_CTL;
|
||||||
|
break;
|
||||||
|
case 0x401:
|
||||||
|
regNum = MISCREG_MC0_STATUS;
|
||||||
|
break;
|
||||||
|
case 0x405:
|
||||||
|
regNum = MISCREG_MC1_STATUS;
|
||||||
|
break;
|
||||||
|
case 0x409:
|
||||||
|
regNum = MISCREG_MC2_STATUS;
|
||||||
|
break;
|
||||||
|
case 0x40D:
|
||||||
|
regNum = MISCREG_MC3_STATUS;
|
||||||
|
break;
|
||||||
|
case 0x411:
|
||||||
|
regNum = MISCREG_MC4_STATUS;
|
||||||
|
break;
|
||||||
|
case 0x402:
|
||||||
|
regNum = MISCREG_MC0_ADDR;
|
||||||
|
break;
|
||||||
|
case 0x406:
|
||||||
|
regNum = MISCREG_MC1_ADDR;
|
||||||
|
break;
|
||||||
|
case 0x40A:
|
||||||
|
regNum = MISCREG_MC2_ADDR;
|
||||||
|
break;
|
||||||
|
case 0x40E:
|
||||||
|
regNum = MISCREG_MC3_ADDR;
|
||||||
|
break;
|
||||||
|
case 0x412:
|
||||||
|
regNum = MISCREG_MC4_ADDR;
|
||||||
|
break;
|
||||||
|
case 0x403:
|
||||||
|
regNum = MISCREG_MC0_MISC;
|
||||||
|
break;
|
||||||
|
case 0x407:
|
||||||
|
regNum = MISCREG_MC1_MISC;
|
||||||
|
break;
|
||||||
|
case 0x40B:
|
||||||
|
regNum = MISCREG_MC2_MISC;
|
||||||
|
break;
|
||||||
|
case 0x40F:
|
||||||
|
regNum = MISCREG_MC3_MISC;
|
||||||
|
break;
|
||||||
|
case 0x413:
|
||||||
|
regNum = MISCREG_MC4_MISC;
|
||||||
|
break;
|
||||||
|
case 0xC0000080:
|
||||||
|
regNum = MISCREG_EFER;
|
||||||
|
break;
|
||||||
|
case 0xC0000081:
|
||||||
|
regNum = MISCREG_STAR;
|
||||||
|
break;
|
||||||
|
case 0xC0000082:
|
||||||
|
regNum = MISCREG_LSTAR;
|
||||||
|
break;
|
||||||
|
case 0xC0000083:
|
||||||
|
regNum = MISCREG_CSTAR;
|
||||||
|
break;
|
||||||
|
case 0xC0000084:
|
||||||
|
regNum = MISCREG_SF_MASK;
|
||||||
|
break;
|
||||||
|
case 0xC0000100:
|
||||||
|
regNum = MISCREG_FS_BASE;
|
||||||
|
break;
|
||||||
|
case 0xC0000101:
|
||||||
|
regNum = MISCREG_GS_BASE;
|
||||||
|
break;
|
||||||
|
case 0xC0000102:
|
||||||
|
regNum = MISCREG_KERNEL_GS_BASE;
|
||||||
|
break;
|
||||||
|
case 0xC0000103:
|
||||||
|
regNum = MISCREG_TSC_AUX;
|
||||||
|
break;
|
||||||
|
case 0xC0010000:
|
||||||
|
regNum = MISCREG_PERF_EVT_SEL0;
|
||||||
|
break;
|
||||||
|
case 0xC0010001:
|
||||||
|
regNum = MISCREG_PERF_EVT_SEL1;
|
||||||
|
break;
|
||||||
|
case 0xC0010002:
|
||||||
|
regNum = MISCREG_PERF_EVT_SEL2;
|
||||||
|
break;
|
||||||
|
case 0xC0010003:
|
||||||
|
regNum = MISCREG_PERF_EVT_SEL3;
|
||||||
|
break;
|
||||||
|
case 0xC0010004:
|
||||||
|
regNum = MISCREG_PERF_EVT_CTR0;
|
||||||
|
break;
|
||||||
|
case 0xC0010005:
|
||||||
|
regNum = MISCREG_PERF_EVT_CTR1;
|
||||||
|
break;
|
||||||
|
case 0xC0010006:
|
||||||
|
regNum = MISCREG_PERF_EVT_CTR2;
|
||||||
|
break;
|
||||||
|
case 0xC0010007:
|
||||||
|
regNum = MISCREG_PERF_EVT_CTR3;
|
||||||
|
break;
|
||||||
|
case 0xC0010010:
|
||||||
|
regNum = MISCREG_SYSCFG;
|
||||||
|
break;
|
||||||
|
case 0xC0010016:
|
||||||
|
regNum = MISCREG_IORR_BASE0;
|
||||||
|
break;
|
||||||
|
case 0xC0010017:
|
||||||
|
regNum = MISCREG_IORR_BASE1;
|
||||||
|
break;
|
||||||
|
case 0xC0010018:
|
||||||
|
regNum = MISCREG_IORR_MASK0;
|
||||||
|
break;
|
||||||
|
case 0xC0010019:
|
||||||
|
regNum = MISCREG_IORR_MASK1;
|
||||||
|
break;
|
||||||
|
case 0xC001001A:
|
||||||
|
regNum = MISCREG_TOP_MEM;
|
||||||
|
break;
|
||||||
|
case 0xC001001D:
|
||||||
|
regNum = MISCREG_TOP_MEM2;
|
||||||
|
break;
|
||||||
|
case 0xC0010114:
|
||||||
|
regNum = MISCREG_VM_CR;
|
||||||
|
break;
|
||||||
|
case 0xC0010115:
|
||||||
|
regNum = MISCREG_IGNNE;
|
||||||
|
break;
|
||||||
|
case 0xC0010116:
|
||||||
|
regNum = MISCREG_SMM_CTL;
|
||||||
|
break;
|
||||||
|
case 0xC0010117:
|
||||||
|
regNum = MISCREG_VM_HSAVE_PA;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
return new GeneralProtection(0);
|
||||||
|
}
|
||||||
|
//The index is multiplied by the size of a MiscReg so that
|
||||||
|
//any memory dependence calculations will not see these as
|
||||||
|
//overlapping.
|
||||||
|
req->setPaddr(regNum * sizeof(MiscReg));
|
||||||
|
return NoFault;
|
||||||
|
} else {
|
||||||
|
panic("Access to unrecognized internal address space %#x.\n",
|
||||||
|
prefix);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
// Get cr0. This will tell us how to do translation. We'll assume it was
|
// Get cr0. This will tell us how to do translation. We'll assume it was
|
||||||
// verified to be correct and consistent when set.
|
// verified to be correct and consistent when set.
|
||||||
|
|
|
@ -55,6 +55,8 @@
|
||||||
* Authors: Gabe Black
|
* Authors: Gabe Black
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#include "sim/host.hh"
|
||||||
|
|
||||||
#ifndef __ARCH_X86_X86TRAITS_HH__
|
#ifndef __ARCH_X86_X86TRAITS_HH__
|
||||||
#define __ARCH_X86_X86TRAITS_HH__
|
#define __ARCH_X86_X86TRAITS_HH__
|
||||||
|
|
||||||
|
@ -80,6 +82,10 @@ namespace X86ISA
|
||||||
|
|
||||||
const int NumSegments = 6;
|
const int NumSegments = 6;
|
||||||
const int NumSysSegments = 4;
|
const int NumSysSegments = 4;
|
||||||
|
|
||||||
|
const Addr IntAddrPrefixMask = ULL(0xffffffff00000000);
|
||||||
|
const Addr IntAddrPrefixCPUID = ULL(0x100000000);
|
||||||
|
const Addr IntAddrPrefixMSR = ULL(0x200000000);
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif //__ARCH_X86_X86TRAITS_HH__
|
#endif //__ARCH_X86_X86TRAITS_HH__
|
||||||
|
|
Loading…
Reference in a new issue