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Regression: Add an I/O Cache to the full system regressions that have a cache.

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--HG--
extra : convert_revision : 8ba96e21be2f602eed8258d410038dbe998ef176
This commit is contained in:
Ali Saidi 2007-08-10 16:14:02 -04:00
parent 06a9f58c68
commit 9493501fdb
30 changed files with 1316 additions and 805 deletions
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18
tests/configs/tsunami-simple-atomic-dual.py
View file

@ -52,10 +52,28 @@ class L2(BaseCache):
tgts_per_mshr = 16
write_buffers = 8
# ---------------------
# I/O Cache
# ---------------------
class IOCache(BaseCache):
assoc = 8
block_size = 64
latency = '50ns'
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
mem_side_filter_ranges=[AddrRange(0, Addr.max)]
cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]
#cpu
cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]
#the system
system = FSConfig.makeLinuxAlphaSystem('atomic')
system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
system.iocache = IOCache()
system.iocache.cpu_side = system.iobus.port
system.iocache.mem_side = system.membus.port
system.cpu = cpus
#create the l1/l2 bus

18
tests/configs/tsunami-simple-atomic.py
View file

@ -52,10 +52,28 @@ class L2(BaseCache):
tgts_per_mshr = 16
write_buffers = 8
# ---------------------
# I/O Cache
# ---------------------
class IOCache(BaseCache):
assoc = 8
block_size = 64
latency = '50ns'
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
mem_side_filter_ranges=[AddrRange(0, Addr.max)]
cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]
#cpu
cpu = AtomicSimpleCPU(cpu_id=0)
#the system
system = FSConfig.makeLinuxAlphaSystem('atomic')
system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
system.iocache = IOCache()
system.iocache.cpu_side = system.iobus.port
system.iocache.mem_side = system.membus.port
system.cpu = cpu
#create the l1/l2 bus

18
tests/configs/tsunami-simple-timing-dual.py
View file

@ -52,10 +52,28 @@ class L2(BaseCache):
tgts_per_mshr = 16
write_buffers = 8
# ---------------------
# I/O Cache
# ---------------------
class IOCache(BaseCache):
assoc = 8
block_size = 64
latency = '50ns'
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
mem_side_filter_ranges=[AddrRange(0, Addr.max)]
cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]
#cpu
cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ]
#the system
system = FSConfig.makeLinuxAlphaSystem('timing')
system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
system.iocache = IOCache()
system.iocache.cpu_side = system.iobus.port
system.iocache.mem_side = system.membus.port
system.cpu = cpus
#create the l1/l2 bus

19
tests/configs/tsunami-simple-timing.py
View file

@ -53,6 +53,19 @@ class L2(BaseCache):
tgts_per_mshr = 16
write_buffers = 8
# ---------------------
# I/O Cache
# ---------------------
class IOCache(BaseCache):
assoc = 8
block_size = 64
latency = '50ns'
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
mem_side_filter_ranges=[AddrRange(0, Addr.max)]
cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]
#cpu
cpu = TimingSimpleCPU(cpu_id=0)
#the system
@ -61,6 +74,12 @@ system = FSConfig.makeLinuxAlphaSystem('timing')
system.cpu = cpu
#create the l1/l2 bus
system.toL2Bus = Bus()
system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
system.iocache = IOCache()
system.iocache.cpu_side = system.iobus.port
system.iocache.mem_side = system.membus.port
#connect up the l2 cache
system.l2c = L2(size='4MB', assoc=8)

66
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
View file

@ -5,7 +5,7 @@ dummy=0
[system]
type=LinuxAlphaSystem
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem sim_console simple_disk toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
console=/dist/m5/system/binaries/console
@ -22,8 +22,8 @@ system_type=34
[system.bridge]
type=Bridge
delay=50000
fix_partial_write_a=false
fix_partial_write_b=true
filter_ranges_a=0:18446744073709551615
filter_ranges_b=0:8589934591
nack_delay=4000
req_size_a=16
req_size_b=16
@ -65,10 +65,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=4
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_access=false
prefetch_cache_check_push=true
@ -103,10 +105,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=1
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_access=false
prefetch_cache_check_push=true
@ -171,10 +175,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=4
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_access=false
prefetch_cache_check_push=true
@ -209,10 +215,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=1
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_access=false
prefetch_cache_check_push=true
@ -295,17 +303,55 @@ clock=1000
responder_set=true
width=64
default=system.tsunami.pciconfig.pio
port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
[system.iocache]
type=BaseCache
addr_range=0:18446744073709551615
assoc=8
block_size=64
cpu_side_filter_ranges=549755813888:18446744073709551615
hash_delay=1
latency=50000
lifo=false
max_miss_count=0
mem_side_filter_ranges=0:18446744073709551615
mshrs=20
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=500000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=1024
split=false
split_size=0
subblock_size=0
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.port[28]
mem_side=system.membus.port[2]
[system.l2c]
type=BaseCache
addr_range=0:18446744073709551615
assoc=8
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=92
prefetch_access=false
prefetch_cache_check_push=true
@ -329,7 +375,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.port[0]
mem_side=system.membus.port[2]
mem_side=system.membus.port[3]
[system.membus]
type=Bus
@ -340,7 +386,7 @@ clock=1000
responder_set=false
width=64
default=system.membus.responder.pio
port=system.bridge.side_b system.physmem.port[0] system.l2c.mem_side
port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
[system.membus.responder]
type=IsaFake
@ -474,8 +520,8 @@ system=system
tx_delay=1000000
tx_fifo_size=524288
tx_thread=false
config=system.iobus.port[28]
dma=system.iobus.port[29]
config=system.iobus.port[29]
dma=system.iobus.port[30]
pio=system.iobus.port[27]
[system.tsunami.ethernet.configdata]
@ -840,8 +886,8 @@ pci_func=0
pio_latency=1000
platform=system.tsunami
system=system
config=system.iobus.port[30]
dma=system.iobus.port[31]
config=system.iobus.port[31]
dma=system.iobus.port[32]
pio=system.iobus.port[26]
[system.tsunami.ide.configdata]

7
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console
View file

@ -77,7 +77,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
hdb: M5 IDE Disk, ATA DISK drive
ide0 at 0x8410-0x8417,0x8422 on irq 31
hda: max request size: 128KiB
hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33)
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33)
hda: cache flushes not supported
hda: hda1
hdb: max request size: 128KiB
@ -104,6 +104,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
All bugs added by David S. Miller <davem@redhat.com>
VFS: Mounted root (ext2 filesystem) readonly.
Freeing unused kernel memory: 224k freed
init started: BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary
init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary
mounting filesystems...
loading script...
EXT2-fs warning: checktime reached, running e2fsck is recommended
loading script...

66
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1258571 # Simulator instruction rate (inst/s)
host_mem_usage 256444 # Number of bytes of host memory used
host_seconds 50.16 # Real time elapsed on the host
host_tick_rate 37289409683 # Simulator tick rate (ticks/s)
host_inst_rate 2271343 # Simulator instruction rate (inst/s)
host_mem_usage 326380 # Number of bytes of host memory used
host_seconds 27.79 # Real time elapsed on the host
host_tick_rate 67296173797 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 63125943 # Number of instructions simulated
sim_seconds 1.870335 # Number of seconds simulated
@ -471,6 +471,64 @@ system.disk2.dma_read_txs 0 # Nu
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.iocache.ReadReq_accesses 175 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_misses 175 # number of ReadReq misses
system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_misses 41552 # number of WriteReq misses
system.iocache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.blocked_no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_no_targets 0 # number of cycles access was blocked
system.iocache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.demand_accesses 41727 # number of demand (read+write) accesses
system.iocache.demand_avg_miss_latency 0 # average overall miss latency
system.iocache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.iocache.demand_hits 0 # number of demand (read+write) hits
system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.iocache.demand_miss_rate 1 # miss rate for demand accesses
system.iocache.demand_misses 41727 # number of demand (read+write) misses
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.overall_accesses 41727 # number of overall (read+write) accesses
system.iocache.overall_avg_miss_latency 0 # average overall miss latency
system.iocache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.iocache.overall_hits 0 # number of overall hits
system.iocache.overall_miss_latency 0 # number of overall miss cycles
system.iocache.overall_miss_rate 1 # miss rate for overall accesses
system.iocache.overall_misses 41727 # number of overall misses
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.iocache.replacements 41695 # number of replacements
system.iocache.sampled_refs 41711 # Sample count of references to valid blocks.
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.iocache.tagsinuse 0.435433 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit.
system.iocache.writebacks 41520 # number of writebacks
system.l2c.ReadExReq_accesses 306246 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses 306246 # number of ReadExReq misses

4
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr
View file

@ -1,5 +1,5 @@
Listening for system connection on port 3457
Listening for system connection on port 3456
0: system.remote_gdb.listener: listening for remote gdb on port 7000
0: system.remote_gdb.listener: listening for remote gdb on port 7001
0: system.remote_gdb.listener: listening for remote gdb on port 7002
warn: Entering event queue @ 0. Starting simulation...
warn: 97861500: Trying to launch CPU number 1!

6
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 3 2007 04:02:11
M5 started Fri Aug 3 04:22:43 2007
M5 executing on zizzer.eecs.umich.edu
M5 compiled Aug 10 2007 16:03:34
M5 started Fri Aug 10 16:04:07 2007
M5 executing on zeep
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 1870335101500 because m5_exit instruction encountered

62
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
View file

@ -5,7 +5,7 @@ dummy=0
[system]
type=LinuxAlphaSystem
children=bridge cpu disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami
children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem sim_console simple_disk toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
console=/dist/m5/system/binaries/console
@ -22,8 +22,8 @@ system_type=34
[system.bridge]
type=Bridge
delay=50000
fix_partial_write_a=false
fix_partial_write_b=true
filter_ranges_a=0:18446744073709551615
filter_ranges_b=0:8589934591
nack_delay=4000
req_size_a=16
req_size_b=16
@ -65,10 +65,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=4
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_access=false
prefetch_cache_check_push=true
@ -103,10 +105,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=1
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_access=false
prefetch_cache_check_push=true
@ -189,17 +193,55 @@ clock=1000
responder_set=true
width=64
default=system.tsunami.pciconfig.pio
port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
[system.iocache]
type=BaseCache
addr_range=0:18446744073709551615
assoc=8
block_size=64
cpu_side_filter_ranges=549755813888:18446744073709551615
hash_delay=1
latency=50000
lifo=false
max_miss_count=0
mem_side_filter_ranges=0:18446744073709551615
mshrs=20
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=500000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=1024
split=false
split_size=0
subblock_size=0
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.port[28]
mem_side=system.membus.port[2]
[system.l2c]
type=BaseCache
addr_range=0:18446744073709551615
assoc=8
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=92
prefetch_access=false
prefetch_cache_check_push=true
@ -223,7 +265,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.port[0]
mem_side=system.membus.port[2]
mem_side=system.membus.port[3]
[system.membus]
type=Bus
@ -234,7 +276,7 @@ clock=1000
responder_set=false
width=64
default=system.membus.responder.pio
port=system.bridge.side_b system.physmem.port[0] system.l2c.mem_side
port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
[system.membus.responder]
type=IsaFake
@ -368,8 +410,8 @@ system=system
tx_delay=1000000
tx_fifo_size=524288
tx_thread=false
config=system.iobus.port[28]
dma=system.iobus.port[29]
config=system.iobus.port[29]
dma=system.iobus.port[30]
pio=system.iobus.port[27]
[system.tsunami.ethernet.configdata]
@ -734,8 +776,8 @@ pci_func=0
pio_latency=1000
platform=system.tsunami
system=system
config=system.iobus.port[30]
dma=system.iobus.port[31]
config=system.iobus.port[31]
dma=system.iobus.port[32]
pio=system.iobus.port[26]
[system.tsunami.ide.configdata]

7
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console
View file

@ -72,7 +72,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
hdb: M5 IDE Disk, ATA DISK drive
ide0 at 0x8410-0x8417,0x8422 on irq 31
hda: max request size: 128KiB
hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33)
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33)
hda: cache flushes not supported
hda: hda1
hdb: max request size: 128KiB
@ -99,6 +99,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
All bugs added by David S. Miller <davem@redhat.com>
VFS: Mounted root (ext2 filesystem) readonly.
Freeing unused kernel memory: 224k freed
init started: BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary
init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary
mounting filesystems...
loading script...
EXT2-fs warning: checktime reached, running e2fsck is recommended
loading script...

66
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1294756 # Simulator instruction rate (inst/s)
host_mem_usage 255900 # Number of bytes of host memory used
host_seconds 46.35 # Real time elapsed on the host
host_tick_rate 39449403667 # Simulator tick rate (ticks/s)
host_inst_rate 2322212 # Simulator instruction rate (inst/s)
host_mem_usage 325356 # Number of bytes of host memory used
host_seconds 25.84 # Real time elapsed on the host
host_tick_rate 70754225205 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 60007317 # Number of instructions simulated
sim_seconds 1.828355 # Number of seconds simulated
@ -249,6 +249,64 @@ system.disk2.dma_read_txs 0 # Nu
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.iocache.ReadReq_accesses 174 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_misses 174 # number of ReadReq misses
system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_misses 41552 # number of WriteReq misses
system.iocache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.blocked_no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_no_targets 0 # number of cycles access was blocked
system.iocache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.demand_accesses 41726 # number of demand (read+write) accesses
system.iocache.demand_avg_miss_latency 0 # average overall miss latency
system.iocache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.iocache.demand_hits 0 # number of demand (read+write) hits
system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.iocache.demand_miss_rate 1 # miss rate for demand accesses
system.iocache.demand_misses 41726 # number of demand (read+write) misses
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.overall_accesses 41726 # number of overall (read+write) accesses
system.iocache.overall_avg_miss_latency 0 # average overall miss latency
system.iocache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.iocache.overall_hits 0 # number of overall hits
system.iocache.overall_miss_latency 0 # number of overall miss cycles
system.iocache.overall_miss_rate 1 # miss rate for overall accesses
system.iocache.overall_misses 41726 # number of overall misses
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.iocache.replacements 41686 # number of replacements
system.iocache.sampled_refs 41702 # Sample count of references to valid blocks.
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.iocache.tagsinuse 1.226223 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.warmup_cycle 1684804097017 # Cycle when the warmup percentage was hit.
system.iocache.writebacks 41512 # number of writebacks
system.l2c.ReadExReq_accesses 304342 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses 304342 # number of ReadExReq misses

4
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr
View file

@ -1,3 +1,3 @@
Listening for system connection on port 3457
0: system.remote_gdb.listener: listening for remote gdb on port 7001
Listening for system connection on port 3456
0: system.remote_gdb.listener: listening for remote gdb on port 7000
warn: Entering event queue @ 0. Starting simulation...

6
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 3 2007 04:02:11
M5 started Fri Aug 3 04:21:55 2007
M5 executing on zizzer.eecs.umich.edu
M5 compiled Aug 10 2007 16:03:34
M5 started Fri Aug 10 16:03:39 2007
M5 executing on zeep
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 1828355476000 because m5_exit instruction encountered

66
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
View file

@ -5,7 +5,7 @@ dummy=0
[system]
type=LinuxAlphaSystem
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem sim_console simple_disk toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
console=/dist/m5/system/binaries/console
@ -22,8 +22,8 @@ system_type=34
[system.bridge]
type=Bridge
delay=50000
fix_partial_write_a=false
fix_partial_write_b=true
filter_ranges_a=0:18446744073709551615
filter_ranges_b=0:8589934591
nack_delay=4000
req_size_a=16
req_size_b=16
@ -63,10 +63,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=4
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_access=false
prefetch_cache_check_push=true
@ -101,10 +103,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=1
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_access=false
prefetch_cache_check_push=true
@ -167,10 +171,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=4
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_access=false
prefetch_cache_check_push=true
@ -205,10 +211,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=1
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_access=false
prefetch_cache_check_push=true
@ -291,17 +299,55 @@ clock=1000
responder_set=true
width=64
default=system.tsunami.pciconfig.pio
port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
[system.iocache]
type=BaseCache
addr_range=0:18446744073709551615
assoc=8
block_size=64
cpu_side_filter_ranges=549755813888:18446744073709551615
hash_delay=1
latency=50000
lifo=false
max_miss_count=0
mem_side_filter_ranges=0:18446744073709551615
mshrs=20
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=500000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=1024
split=false
split_size=0
subblock_size=0
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.port[28]
mem_side=system.membus.port[2]
[system.l2c]
type=BaseCache
addr_range=0:18446744073709551615
assoc=8
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=92
prefetch_access=false
prefetch_cache_check_push=true
@ -325,7 +371,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.port[0]
mem_side=system.membus.port[2]
mem_side=system.membus.port[3]
[system.membus]
type=Bus
@ -336,7 +382,7 @@ clock=1000
responder_set=false
width=64
default=system.membus.responder.pio
port=system.bridge.side_b system.physmem.port[0] system.l2c.mem_side
port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
[system.membus.responder]
type=IsaFake
@ -470,8 +516,8 @@ system=system
tx_delay=1000000
tx_fifo_size=524288
tx_thread=false
config=system.iobus.port[28]
dma=system.iobus.port[29]
config=system.iobus.port[29]
dma=system.iobus.port[30]
pio=system.iobus.port[27]
[system.tsunami.ethernet.configdata]
@ -836,8 +882,8 @@ pci_func=0
pio_latency=1000
platform=system.tsunami
system=system
config=system.iobus.port[30]
dma=system.iobus.port[31]
config=system.iobus.port[31]
dma=system.iobus.port[32]
pio=system.iobus.port[26]
[system.tsunami.ide.configdata]

9
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console
View file

@ -17,8 +17,8 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
unix_boot_mem ends at FFFFFC0000078000
k_argc = 0
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400
CallbackFixup 0 18000, t7=FFFFFC000070C000
Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
Major Options: SMP LEGACY_START VERBOSE_MCHECK
@ -77,7 +77,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
hdb: M5 IDE Disk, ATA DISK drive
ide0 at 0x8410-0x8417,0x8422 on irq 31
hda: max request size: 128KiB
hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33)
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33)
hda: cache flushes not supported
hda: hda1
hdb: max request size: 128KiB
@ -104,6 +104,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
All bugs added by David S. Miller <davem@redhat.com>
VFS: Mounted root (ext2 filesystem) readonly.
Freeing unused kernel memory: 224k freed
init started: BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary
init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary
mounting filesystems...
loading script...
EXT2-fs warning: checktime reached, running e2fsck is recommended
loading script...

986
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt
View file

File diff suppressed because it is too large Load diff

4
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr
View file

@ -1,5 +1,5 @@
Listening for system connection on port 3457
Listening for system connection on port 3456
0: system.remote_gdb.listener: listening for remote gdb on port 7000
0: system.remote_gdb.listener: listening for remote gdb on port 7001
0: system.remote_gdb.listener: listening for remote gdb on port 7002
warn: Entering event queue @ 0. Starting simulation...
warn: 427086000: Trying to launch CPU number 1!

8
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 3 2007 04:02:11
M5 started Fri Aug 3 04:25:10 2007
M5 executing on zizzer.eecs.umich.edu
M5 compiled Aug 10 2007 16:03:34
M5 started Fri Aug 10 16:05:34 2007
M5 executing on zeep
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 1951367346000 because m5_exit instruction encountered
Exiting @ tick 1950343222000 because m5_exit instruction encountered

62
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
View file

@ -5,7 +5,7 @@ dummy=0
[system]
type=LinuxAlphaSystem
children=bridge cpu disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami
children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem sim_console simple_disk toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
console=/dist/m5/system/binaries/console
@ -22,8 +22,8 @@ system_type=34
[system.bridge]
type=Bridge
delay=50000
fix_partial_write_a=false
fix_partial_write_b=true
filter_ranges_a=0:18446744073709551615
filter_ranges_b=0:8589934591
nack_delay=4000
req_size_a=16
req_size_b=16
@ -63,10 +63,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=4
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_access=false
prefetch_cache_check_push=true
@ -101,10 +103,12 @@ type=BaseCache
addr_range=0:18446744073709551615
assoc=1
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_access=false
prefetch_cache_check_push=true
@ -187,17 +191,55 @@ clock=1000
responder_set=true
width=64
default=system.tsunami.pciconfig.pio
port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
[system.iocache]
type=BaseCache
addr_range=0:18446744073709551615
assoc=8
block_size=64
cpu_side_filter_ranges=549755813888:18446744073709551615
hash_delay=1
latency=50000
lifo=false
max_miss_count=0
mem_side_filter_ranges=0:18446744073709551615
mshrs=20
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=500000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
repl=Null
size=1024
split=false
split_size=0
subblock_size=0
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.port[28]
mem_side=system.membus.port[2]
[system.l2c]
type=BaseCache
addr_range=0:18446744073709551615
assoc=8
block_size=64
cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
mem_side_filter_ranges=
mshrs=92
prefetch_access=false
prefetch_cache_check_push=true
@ -221,7 +263,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.port[0]
mem_side=system.membus.port[2]
mem_side=system.membus.port[3]
[system.membus]
type=Bus
@ -232,7 +274,7 @@ clock=1000
responder_set=false
width=64
default=system.membus.responder.pio
port=system.bridge.side_b system.physmem.port[0] system.l2c.mem_side
port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
[system.membus.responder]
type=IsaFake
@ -366,8 +408,8 @@ system=system
tx_delay=1000000
tx_fifo_size=524288
tx_thread=false
config=system.iobus.port[28]
dma=system.iobus.port[29]
config=system.iobus.port[29]
dma=system.iobus.port[30]
pio=system.iobus.port[27]
[system.tsunami.ethernet.configdata]
@ -732,8 +774,8 @@ pci_func=0
pio_latency=1000
platform=system.tsunami
system=system
config=system.iobus.port[30]
dma=system.iobus.port[31]
config=system.iobus.port[31]
dma=system.iobus.port[32]
pio=system.iobus.port[26]
[system.tsunami.ide.configdata]

7
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console
View file

@ -72,7 +72,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
hdb: M5 IDE Disk, ATA DISK drive
ide0 at 0x8410-0x8417,0x8422 on irq 31
hda: max request size: 128KiB
hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33)
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33)
hda: cache flushes not supported
hda: hda1
hdb: max request size: 128KiB
@ -99,6 +99,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
All bugs added by David S. Miller <davem@redhat.com>
VFS: Mounted root (ext2 filesystem) readonly.
Freeing unused kernel memory: 224k freed
init started: BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary
init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary
mounting filesystems...
loading script...
EXT2-fs warning: checktime reached, running e2fsck is recommended
loading script...

488
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt
View file

@ -1,92 +1,92 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 631972 # Simulator instruction rate (inst/s)
host_mem_usage 219140 # Number of bytes of host memory used
host_seconds 95.00 # Real time elapsed on the host
host_tick_rate 20109299069 # Simulator tick rate (ticks/s)
host_inst_rate 1028480 # Simulator instruction rate (inst/s)
host_mem_usage 285368 # Number of bytes of host memory used
host_seconds 58.37 # Real time elapsed on the host
host_tick_rate 32711130426 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 60034774 # Number of instructions simulated
sim_seconds 1.910310 # Number of seconds simulated
sim_ticks 1910309711000 # Number of ticks simulated
system.cpu.dcache.LoadLockedReq_accesses 200211 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_avg_miss_latency 13960.656682 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 12960.656682 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_hits 182851 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_latency 242357000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_rate 0.086709 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses 17360 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 224997000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.086709 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_misses 17360 # number of LoadLockedReq MSHR misses
system.cpu.dcache.ReadReq_accesses 9525872 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 13240.454388 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12240.427719 # average ReadReq mshr miss latency
sim_insts 60031203 # Number of instructions simulated
sim_seconds 1.909320 # Number of seconds simulated
sim_ticks 1909320028000 # Number of ticks simulated
system.cpu.dcache.LoadLockedReq_accesses 200196 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_avg_miss_latency 13961.565057 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 12961.565057 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_hits 182842 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_latency 242289000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_rate 0.086685 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses 17354 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 224935000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.086685 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_misses 17354 # number of LoadLockedReq MSHR misses
system.cpu.dcache.ReadReq_accesses 9525051 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 13247.769109 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12247.742435 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_hits 7801048 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 22837453500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.181067 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1724824 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 21112583500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.181067 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1724824 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_hits 7800516 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 22846241500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.181053 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1724535 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 21121660500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.181053 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1724535 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable_latency 830826000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.StoreCondReq_accesses 199189 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_avg_miss_latency 14000.798456 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 13000.798456 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_accesses 199174 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_avg_miss_latency 14002.263422 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 13002.263422 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_hits 169131 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_miss_latency 420836000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_rate 0.150902 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_misses 30058 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_mshr_miss_latency 390778000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.150902 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_misses 30058 # number of StoreCondReq MSHR misses
system.cpu.dcache.WriteReq_accesses 6151132 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 14000.947966 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000.947966 # average WriteReq mshr miss latency
system.cpu.dcache.StoreCondReq_miss_latency 420670000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_rate 0.150838 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_misses 30043 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_mshr_miss_latency 390627000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.150838 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_misses 30043 # number of StoreCondReq MSHR misses
system.cpu.dcache.WriteReq_accesses 6150630 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 14004.147760 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13004.147760 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_hits 5750801 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 5605013500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.065082 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 400331 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 5204682500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.065082 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 400331 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1164414500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_hits 5750414 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 5604684000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.065069 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 400216 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 5204468000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.065069 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 400216 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1164291500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 6.854770 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 6.855501 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 15677004 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 13383.714129 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 12383.692484 # average overall mshr miss latency
system.cpu.dcache.demand_hits 13551849 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 28442467000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.135559 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2125155 # number of demand (read+write) misses
system.cpu.dcache.demand_accesses 15675681 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 13390.239845 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 12390.218195 # average overall mshr miss latency
system.cpu.dcache.demand_hits 13550930 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 28450925500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.135544 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2124751 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 26317266000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.135559 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2125155 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 26326128500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.135544 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2124751 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 15677004 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 13383.714129 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 12383.692484 # average overall mshr miss latency
system.cpu.dcache.overall_accesses 15675681 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 13390.239845 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 12390.218195 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 13551849 # number of overall hits
system.cpu.dcache.overall_miss_latency 28442467000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.135559 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2125155 # number of overall misses
system.cpu.dcache.overall_hits 13550930 # number of overall hits
system.cpu.dcache.overall_miss_latency 28450925500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.135544 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2124751 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 26317266000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.135559 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2125155 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 1995240500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_miss_latency 26326128500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.135544 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2124751 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 1995117500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
@ -97,69 +97,69 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 2046194 # number of replacements
system.cpu.dcache.sampled_refs 2046706 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 2045831 # number of replacements
system.cpu.dcache.sampled_refs 2046343 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 511.987834 # Cycle average of tags in use
system.cpu.dcache.total_refs 14029698 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 511.987794 # Cycle average of tags in use
system.cpu.dcache.total_refs 14028706 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 58297000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 429991 # number of writebacks
system.cpu.dcache.writebacks 429859 # number of writebacks
system.cpu.dtb.accesses 1020787 # DTB accesses
system.cpu.dtb.acv 367 # DTB access violations
system.cpu.dtb.hits 16056951 # DTB hits
system.cpu.dtb.hits 16055629 # DTB hits
system.cpu.dtb.misses 11471 # DTB misses
system.cpu.dtb.read_accesses 728856 # DTB read accesses
system.cpu.dtb.read_acv 210 # DTB read access violations
system.cpu.dtb.read_hits 9706492 # DTB read hits
system.cpu.dtb.read_hits 9705676 # DTB read hits
system.cpu.dtb.read_misses 10329 # DTB read misses
system.cpu.dtb.write_accesses 291931 # DTB write accesses
system.cpu.dtb.write_acv 157 # DTB write access violations
system.cpu.dtb.write_hits 6350459 # DTB write hits
system.cpu.dtb.write_hits 6349953 # DTB write hits
system.cpu.dtb.write_misses 1142 # DTB write misses
system.cpu.icache.ReadReq_accesses 60034775 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 12033.060657 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11032.326155 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 59106935 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 11164755000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.015455 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 927840 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 10236233500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.015455 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 927840 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_accesses 60031204 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 12033.101057 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11032.368005 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 59103575 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 11162253500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.015452 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 927629 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 10233944500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.015452 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 927629 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 63.714789 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 63.725661 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 60034775 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 12033.060657 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11032.326155 # average overall mshr miss latency
system.cpu.icache.demand_hits 59106935 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 11164755000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.015455 # miss rate for demand accesses
system.cpu.icache.demand_misses 927840 # number of demand (read+write) misses
system.cpu.icache.demand_accesses 60031204 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 12033.101057 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11032.368005 # average overall mshr miss latency
system.cpu.icache.demand_hits 59103575 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 11162253500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.015452 # miss rate for demand accesses
system.cpu.icache.demand_misses 927629 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 10236233500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.015455 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 927840 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_miss_latency 10233944500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.015452 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 927629 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 60034775 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 12033.060657 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11032.326155 # average overall mshr miss latency
system.cpu.icache.overall_accesses 60031204 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 12033.101057 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11032.368005 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 59106935 # number of overall hits
system.cpu.icache.overall_miss_latency 11164755000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.015455 # miss rate for overall accesses
system.cpu.icache.overall_misses 927840 # number of overall misses
system.cpu.icache.overall_hits 59103575 # number of overall hits
system.cpu.icache.overall_miss_latency 11162253500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.015452 # miss rate for overall accesses
system.cpu.icache.overall_misses 927629 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 10236233500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.015455 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 927840 # number of overall MSHR misses
system.cpu.icache.overall_mshr_miss_latency 10233944500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.015452 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 927629 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -171,71 +171,71 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 927169 # number of replacements
system.cpu.icache.sampled_refs 927680 # Sample count of references to valid blocks.
system.cpu.icache.replacements 926958 # number of replacements
system.cpu.icache.sampled_refs 927469 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 508.749374 # Cycle average of tags in use
system.cpu.icache.total_refs 59106935 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 508.747859 # Cycle average of tags in use
system.cpu.icache.total_refs 59103575 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 35000367000 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0.939637 # Percentage of idle cycles
system.cpu.itb.accesses 4978395 # ITB accesses
system.cpu.idle_fraction 0.939605 # Percentage of idle cycles
system.cpu.itb.accesses 4978081 # ITB accesses
system.cpu.itb.acv 184 # ITB acv
system.cpu.itb.hits 4973389 # ITB hits
system.cpu.itb.hits 4973075 # ITB hits
system.cpu.itb.misses 5006 # ITB misses
system.cpu.kern.callpal 192813 # number of callpals executed
system.cpu.kern.callpal 192799 # number of callpals executed
system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal_swpctx 4176 2.17% 2.17% # number of callpals executed
system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed
system.cpu.kern.callpal_swpctx 4172 2.16% 2.17% # number of callpals executed
system.cpu.kern.callpal_tbi 54 0.03% 2.19% # number of callpals executed
system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed
system.cpu.kern.callpal_swpipl 175877 91.22% 93.42% # number of callpals executed
system.cpu.kern.callpal_rdps 6828 3.54% 96.96% # number of callpals executed
system.cpu.kern.callpal_swpipl 175869 91.22% 93.42% # number of callpals executed
system.cpu.kern.callpal_rdps 6827 3.54% 96.96% # number of callpals executed
system.cpu.kern.callpal_wrkgp 1 0.00% 96.96% # number of callpals executed
system.cpu.kern.callpal_wrusp 7 0.00% 96.96% # number of callpals executed
system.cpu.kern.callpal_rdusp 9 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal_whami 2 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal_rti 5152 2.67% 99.64% # number of callpals executed
system.cpu.kern.callpal_rti 5151 2.67% 99.64% # number of callpals executed
system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.hwrei 211901 # number of hwrei instructions executed
system.cpu.kern.inst.quiesce 6181 # number of quiesce instructions executed
system.cpu.kern.ipl_count 183088 # number of times we switched to this ipl
system.cpu.kern.ipl_count_0 74875 40.90% 40.90% # number of times we switched to this ipl
system.cpu.kern.inst.hwrei 211886 # number of hwrei instructions executed
system.cpu.kern.inst.quiesce 6177 # number of quiesce instructions executed
system.cpu.kern.ipl_count 183078 # number of times we switched to this ipl
system.cpu.kern.ipl_count_0 74873 40.90% 40.90% # number of times we switched to this ipl
system.cpu.kern.ipl_count_21 131 0.07% 40.97% # number of times we switched to this ipl
system.cpu.kern.ipl_count_22 1927 1.05% 42.02% # number of times we switched to this ipl
system.cpu.kern.ipl_count_31 106155 57.98% 100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_good 149074 # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good_0 73508 49.31% 49.31% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_count_22 1926 1.05% 42.02% # number of times we switched to this ipl
system.cpu.kern.ipl_count_31 106148 57.98% 100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_good 149069 # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good_0 73506 49.31% 49.31% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good_21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good_22 1927 1.29% 50.69% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good_31 73508 49.31% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks 1910308997000 # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_0 1853401678500 97.02% 97.02% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_21 78202500 0.00% 97.03% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_22 538133000 0.03% 97.05% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_31 56290983000 2.95% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_used_0 0.981743 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_good_22 1926 1.29% 50.69% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good_31 73506 49.31% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks 1909319316000 # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_0 1852420057000 97.02% 97.02% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_21 77949500 0.00% 97.02% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_22 537776500 0.03% 97.05% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_31 56283533000 2.95% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_used_0 0.981742 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used_31 0.692459 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.mode_good_kernel 1908
system.cpu.kern.mode_good_user 1738
system.cpu.kern.mode_good_idle 170
system.cpu.kern.mode_switch_kernel 5896 # number of protection mode switches
system.cpu.kern.mode_switch_user 1738 # number of protection mode switches
system.cpu.kern.mode_switch_idle 2098 # number of protection mode switches
system.cpu.kern.mode_switch_good 1.404639 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good_kernel 0.323609 # fraction of useful protection mode switches
system.cpu.kern.ipl_used_31 0.692486 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.mode_good_kernel 1907
system.cpu.kern.mode_good_user 1739
system.cpu.kern.mode_good_idle 168
system.cpu.kern.mode_switch_kernel 5895 # number of protection mode switches
system.cpu.kern.mode_switch_user 1739 # number of protection mode switches
system.cpu.kern.mode_switch_idle 2094 # number of protection mode switches
system.cpu.kern.mode_switch_good 1.403724 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good_kernel 0.323494 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good_idle 0.081030 # fraction of useful protection mode switches
system.cpu.kern.mode_ticks_kernel 43115749000 2.26% 2.26% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks_user 4716926000 0.25% 2.50% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks_idle 1862476320000 97.50% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
system.cpu.kern.mode_switch_good_idle 0.080229 # fraction of useful protection mode switches
system.cpu.kern.mode_ticks_kernel 43141321000 2.26% 2.26% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks_user 4716637000 0.25% 2.51% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks_idle 1861461356000 97.49% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4173 # number of times the context was actually changed
system.cpu.kern.syscall 326 # number of syscalls executed
system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed
@ -267,10 +267,10 @@ system.cpu.kern.syscall_98 2 0.61% 97.55% # nu
system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed
system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed
system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed
system.cpu.not_idle_fraction 0.060363 # Percentage of non-idle cycles
system.cpu.numCycles 1910309711000 # number of cpu cycles simulated
system.cpu.num_insts 60034774 # Number of instructions executed
system.cpu.num_refs 16305091 # Number of memory references
system.cpu.not_idle_fraction 0.060395 # Percentage of non-idle cycles
system.cpu.numCycles 1909320028000 # number of cpu cycles simulated
system.cpu.num_insts 60031203 # Number of instructions executed
system.cpu.num_refs 16303737 # Number of memory references
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
@ -283,78 +283,148 @@ system.disk2.dma_read_txs 0 # Nu
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.l2c.ReadExReq_accesses 304522 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_avg_miss_latency 12000.719160 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 11000.719160 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_miss_latency 3654483000 # number of ReadExReq miss cycles
system.iocache.ReadReq_accesses 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_avg_miss_latency 61832.358382 # average ReadReq miss latency
system.iocache.ReadReq_avg_mshr_miss_latency 60832.358382 # average ReadReq mshr miss latency
system.iocache.ReadReq_miss_latency 10696998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_misses 173 # number of ReadReq misses
system.iocache.ReadReq_mshr_miss_latency 10523998 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses
system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_avg_miss_latency 55508.947969 # average WriteReq miss latency
system.iocache.WriteReq_avg_mshr_miss_latency 54508.947969 # average WriteReq mshr miss latency
system.iocache.WriteReq_miss_latency 2306507806 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_misses 41552 # number of WriteReq misses
system.iocache.WriteReq_mshr_miss_latency 2264955806 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
system.iocache.avg_blocked_cycles_no_mshrs 4134.747706 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.blocked_no_mshrs 10464 # number of cycles access was blocked
system.iocache.blocked_no_targets 0 # number of cycles access was blocked
system.iocache.blocked_cycles_no_mshrs 43266000 # number of cycles access was blocked
system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.demand_accesses 41725 # number of demand (read+write) accesses
system.iocache.demand_avg_miss_latency 55535.166064 # average overall miss latency
system.iocache.demand_avg_mshr_miss_latency 54535.166064 # average overall mshr miss latency
system.iocache.demand_hits 0 # number of demand (read+write) hits
system.iocache.demand_miss_latency 2317204804 # number of demand (read+write) miss cycles
system.iocache.demand_miss_rate 1 # miss rate for demand accesses
system.iocache.demand_misses 41725 # number of demand (read+write) misses
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.iocache.demand_mshr_miss_latency 2275479804 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.overall_accesses 41725 # number of overall (read+write) accesses
system.iocache.overall_avg_miss_latency 55535.166064 # average overall miss latency
system.iocache.overall_avg_mshr_miss_latency 54535.166064 # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.iocache.overall_hits 0 # number of overall hits
system.iocache.overall_miss_latency 2317204804 # number of overall miss cycles
system.iocache.overall_miss_rate 1 # miss rate for overall accesses
system.iocache.overall_misses 41725 # number of overall misses
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
system.iocache.overall_mshr_miss_latency 2275479804 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.iocache.replacements 41685 # number of replacements
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.iocache.tagsinuse 1.326249 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.warmup_cycle 1746583798000 # Cycle when the warmup percentage was hit.
system.iocache.writebacks 41512 # number of writebacks
system.l2c.ReadExReq_accesses 304456 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_avg_miss_latency 12004.125391 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 11004.125391 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_miss_latency 3654728000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses 304522 # number of ReadExReq misses
system.l2c.ReadExReq_mshr_miss_latency 3349961000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_misses 304456 # number of ReadExReq misses
system.l2c.ReadExReq_mshr_miss_latency 3350272000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_misses 304522 # number of ReadExReq MSHR misses
system.l2c.ReadReq_accesses 2670005 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_avg_miss_latency 12000.233269 # average ReadReq miss latency
system.l2c.ReadReq_avg_mshr_miss_latency 11000.233269 # average ReadReq mshr miss latency
system.l2c.ReadExReq_mshr_misses 304456 # number of ReadExReq MSHR misses
system.l2c.ReadReq_accesses 2669499 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_avg_miss_latency 12011.481535 # average ReadReq miss latency
system.l2c.ReadReq_avg_mshr_miss_latency 11011.481535 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_hits 1568273 # number of ReadReq hits
system.l2c.ReadReq_miss_latency 13221041000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_rate 0.412633 # miss rate for ReadReq accesses
system.l2c.ReadReq_misses 1101732 # number of ReadReq misses
system.l2c.ReadReq_mshr_miss_latency 12119309000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate 0.412633 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_misses 1101732 # number of ReadReq MSHR misses
system.l2c.ReadReq_hits 1567817 # number of ReadReq hits
system.l2c.ReadReq_miss_latency 13232833000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_rate 0.412692 # miss rate for ReadReq accesses
system.l2c.ReadReq_misses 1101682 # number of ReadReq misses
system.l2c.ReadReq_mshr_miss_latency 12131151000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate 0.412692 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_misses 1101682 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_uncacheable_latency 750102000 # number of ReadReq MSHR uncacheable cycles
system.l2c.UpgradeReq_accesses 125867 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_avg_miss_latency 11999.892744 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 11000.750793 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_miss_latency 1510390500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_accesses 125803 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_avg_miss_latency 12002.178008 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 11003.036494 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_miss_latency 1509910000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_misses 125867 # number of UpgradeReq misses
system.l2c.UpgradeReq_mshr_miss_latency 1384631500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_misses 125803 # number of UpgradeReq misses
system.l2c.UpgradeReq_mshr_miss_latency 1384215000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_misses 125867 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses 125803 # number of UpgradeReq MSHR misses
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_mshr_uncacheable_latency 1051110500 # number of WriteReq MSHR uncacheable cycles
system.l2c.Writeback_accesses 429991 # number of Writeback accesses(hits+misses)
system.l2c.WriteReq_mshr_uncacheable_latency 1050999500 # number of WriteReq MSHR uncacheable cycles
system.l2c.Writeback_accesses 429859 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_miss_rate 1 # miss rate for Writeback accesses
system.l2c.Writeback_misses 429991 # number of Writeback misses
system.l2c.Writeback_misses 429859 # number of Writeback misses
system.l2c.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
system.l2c.Writeback_mshr_misses 429991 # number of Writeback MSHR misses
system.l2c.Writeback_mshr_misses 429859 # number of Writeback MSHR misses
system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.l2c.avg_refs 1.660842 # Average number of references to valid blocks.
system.l2c.avg_refs 1.660129 # Average number of references to valid blocks.
system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.demand_accesses 2974527 # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency 12000.338488 # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency 11000.338488 # average overall mshr miss latency
system.l2c.demand_hits 1568273 # number of demand (read+write) hits
system.l2c.demand_miss_latency 16875524000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate 0.472766 # miss rate for demand accesses
system.l2c.demand_misses 1406254 # number of demand (read+write) misses
system.l2c.demand_accesses 2973955 # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency 12009.888788 # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency 11009.888788 # average overall mshr miss latency
system.l2c.demand_hits 1567817 # number of demand (read+write) hits
system.l2c.demand_miss_latency 16887561000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate 0.472818 # miss rate for demand accesses
system.l2c.demand_misses 1406138 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency 15469270000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate 0.472766 # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses 1406254 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_miss_latency 15481423000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate 0.472818 # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses 1406138 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.overall_accesses 2974527 # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency 12000.338488 # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency 11000.338488 # average overall mshr miss latency
system.l2c.overall_accesses 2973955 # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency 12009.888788 # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency 11009.888788 # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
system.l2c.overall_hits 1568273 # number of overall hits
system.l2c.overall_miss_latency 16875524000 # number of overall miss cycles
system.l2c.overall_miss_rate 0.472766 # miss rate for overall accesses
system.l2c.overall_misses 1406254 # number of overall misses
system.l2c.overall_hits 1567817 # number of overall hits
system.l2c.overall_miss_latency 16887561000 # number of overall miss cycles
system.l2c.overall_miss_rate 0.472818 # miss rate for overall accesses
system.l2c.overall_misses 1406138 # number of overall misses
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency 15469270000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate 0.472766 # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses 1406254 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency 1801212500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_miss_latency 15481423000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate 0.472818 # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses 1406138 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency 1801101500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
@ -365,11 +435,11 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu
system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.l2c.replacements 947259 # number of replacements
system.l2c.sampled_refs 965538 # Sample count of references to valid blocks.
system.l2c.replacements 947227 # number of replacements
system.l2c.sampled_refs 965496 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.l2c.tagsinuse 15874.904757 # Cycle average of tags in use
system.l2c.total_refs 1603606 # Total number of references to valid blocks.
system.l2c.tagsinuse 15873.138648 # Cycle average of tags in use
system.l2c.total_refs 1602848 # Total number of references to valid blocks.
system.l2c.warmup_cycle 4106790000 # Cycle when the warmup percentage was hit.
system.l2c.writebacks 0 # number of writebacks
system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post

4
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr
View file

@ -1,3 +1,3 @@
Listening for system connection on port 3457
0: system.remote_gdb.listener: listening for remote gdb on port 7001
Listening for system connection on port 3456
0: system.remote_gdb.listener: listening for remote gdb on port 7000
warn: Entering event queue @ 0. Starting simulation...

8
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 3 2007 04:02:11
M5 started Fri Aug 3 04:23:34 2007
M5 executing on zizzer.eecs.umich.edu
M5 compiled Aug 10 2007 16:03:34
M5 started Fri Aug 10 16:04:35 2007
M5 executing on zeep
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 1910309711000 because m5_exit instruction encountered
Exiting @ tick 1909320028000 because m5_exit instruction encountered

12
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
View file

@ -14,7 +14,7 @@ kernel=/dist/m5/system/binaries/vmlinux
mem_mode=atomic
pal=/dist/m5/system/binaries/ts_osfpal
physmem=drivesys.physmem
readfile=/z/stever/hg/m5.stever/configs/boot/netperf-server.rcS
readfile=/z/saidi/work/m5.bb/configs/boot/netperf-server.rcS
symbolfile=
system_rev=1024
system_type=34
@ -22,8 +22,8 @@ system_type=34
[drivesys.bridge]
type=Bridge
delay=50000
fix_partial_write_a=false
fix_partial_write_b=true
filter_ranges_a=
filter_ranges_b=
nack_delay=4000
req_size_a=16
req_size_b=16
@ -708,7 +708,7 @@ kernel=/dist/m5/system/binaries/vmlinux
mem_mode=atomic
pal=/dist/m5/system/binaries/ts_osfpal
physmem=testsys.physmem
readfile=/z/stever/hg/m5.stever/configs/boot/netperf-stream-client.rcS
readfile=/z/saidi/work/m5.bb/configs/boot/netperf-stream-client.rcS
symbolfile=
system_rev=1024
system_type=34
@ -716,8 +716,8 @@ system_type=34
[testsys.bridge]
type=Bridge
delay=50000
fix_partial_write_a=false
fix_partial_write_b=true
filter_ranges_a=
filter_ranges_b=
nack_delay=4000
req_size_a=16
req_size_b=16

9
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console
View file

@ -58,7 +58,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
eth0: enabling optical transceiver
eth0: using 64 bit addressing.
eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:02 io=0x09000000 irq=30 f=h,sg
eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg
tun: Universal TUN/TAP device driver, 1.6
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
@ -72,7 +72,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
hdb: M5 IDE Disk, ATA DISK drive
ide0 at 0x8410-0x8417,0x8422 on irq 31
hda: max request size: 128KiB
hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33)
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33)
hda: cache flushes not supported
hda: hda1
hdb: max request size: 128KiB
@ -99,9 +99,10 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
All bugs added by David S. Miller <davem@redhat.com>
VFS: Mounted root (ext2 filesystem) readonly.
Freeing unused kernel memory: 224k freed
init started: BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary
init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary
mounting filesystems...
loading script...
EXT2-fs warning: checktime reached, running e2fsck is recommended
loading script...
setting up network...
eth0: link now 1000F mbps, full duplex and up.
running netserver...

7
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console
View file

@ -72,7 +72,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
hdb: M5 IDE Disk, ATA DISK drive
ide0 at 0x8410-0x8417,0x8422 on irq 31
hda: max request size: 128KiB
hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33)
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33)
hda: cache flushes not supported
hda: hda1
hdb: max request size: 128KiB
@ -99,9 +99,10 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
All bugs added by David S. Miller <davem@redhat.com>
VFS: Mounted root (ext2 filesystem) readonly.
Freeing unused kernel memory: 224k freed
init started: BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary
init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary
mounting filesystems...
loading script...
EXT2-fs warning: checktime reached, running e2fsck is recommended
loading script...
setting up network...
eth0: link now 1000F mbps, full duplex and up.
waiting for server...server ready

14
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt
View file

@ -139,10 +139,10 @@ drivesys.tsunami.ethernet.txPPS 25 # Pa
drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted
drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device
drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
host_inst_rate 51081325 # Simulator instruction rate (inst/s)
host_mem_usage 406704 # Number of bytes of host memory used
host_seconds 5.35 # Real time elapsed on the host
host_tick_rate 37372483621 # Simulator tick rate (ticks/s)
host_inst_rate 109126509 # Simulator instruction rate (inst/s)
host_mem_usage 477016 # Number of bytes of host memory used
host_seconds 2.51 # Real time elapsed on the host
host_tick_rate 79838467246 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 273348482 # Number of instructions simulated
sim_seconds 0.200001 # Number of seconds simulated
@ -381,10 +381,10 @@ drivesys.tsunami.ethernet.totalSwi 0 # to
drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
host_inst_rate 71036507796 # Simulator instruction rate (inst/s)
host_mem_usage 406704 # Number of bytes of host memory used
host_inst_rate 139108642239 # Simulator instruction rate (inst/s)
host_mem_usage 477016 # Number of bytes of host memory used
host_seconds 0.00 # Real time elapsed on the host
host_tick_rate 191282064 # Simulator tick rate (ticks/s)
host_tick_rate 375168496 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 273348482 # Number of instructions simulated
sim_seconds 0.000001 # Number of seconds simulated

8
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr
View file

@ -1,6 +1,6 @@
Listening for testsys connection on port 3457
Listening for drivesys connection on port 3458
0: testsys.remote_gdb.listener: listening for remote gdb on port 7001
0: drivesys.remote_gdb.listener: listening for remote gdb on port 7002
Listening for testsys connection on port 3456
Listening for drivesys connection on port 3457
0: testsys.remote_gdb.listener: listening for remote gdb on port 7000
0: drivesys.remote_gdb.listener: listening for remote gdb on port 7001
warn: Entering event queue @ 0. Starting simulation...
warn: Obsolete M5 instruction ivlb encountered.

6
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 3 2007 04:02:11
M5 started Fri Aug 3 04:26:58 2007
M5 executing on zizzer.eecs.umich.edu
M5 compiled Aug 10 2007 16:03:34
M5 started Fri Aug 10 16:06:35 2007
M5 executing on zeep
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 4300235844056 because checkpoint