ARM: Decode the VLDR instruction.
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4f130683e0
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943b77b9bb
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@ -153,7 +153,7 @@ def format ExtensionRegLoadStore() {{
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{
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{
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const uint32_t opcode = bits(machInst, 24, 20);
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const uint32_t opcode = bits(machInst, 24, 20);
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const uint32_t offset = bits(machInst, 7, 0);
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const uint32_t offset = bits(machInst, 7, 0);
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const bool single = bits(machInst, 22);
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const bool single = (bits(machInst, 8) == 0);
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const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
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const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
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RegIndex vd;
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RegIndex vd;
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if (single) {
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if (single) {
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@ -177,7 +177,7 @@ def format ExtensionRegLoadStore() {{
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(IntRegIndex)(uint32_t)bits(machInst, 19, 16);
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(IntRegIndex)(uint32_t)bits(machInst, 19, 16);
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const bool op = bits(machInst, 20);
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const bool op = bits(machInst, 20);
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uint32_t vm;
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uint32_t vm;
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if (bits(machInst, 8) == 0) {
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if (single) {
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vm = (bits(machInst, 3, 0) << 1) | bits(machInst, 5);
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vm = (bits(machInst, 3, 0) << 1) | bits(machInst, 5);
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} else {
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} else {
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vm = (bits(machInst, 3, 0) << 1) |
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vm = (bits(machInst, 3, 0) << 1) |
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@ -222,12 +222,38 @@ def format ExtensionRegLoadStore() {{
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if (bits(opcode, 1, 0) == 0x0) {
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if (bits(opcode, 1, 0) == 0x0) {
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return new WarnUnimplemented("vstr", machInst);
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return new WarnUnimplemented("vstr", machInst);
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} else if (bits(opcode, 1, 0) == 0x1) {
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} else if (bits(opcode, 1, 0) == 0x1) {
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return new WarnUnimplemented("vldr", machInst);
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const bool up = (bits(machInst, 23) == 1);
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const uint32_t imm = bits(machInst, 7, 0) << 2;
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RegIndex vd;
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if (single) {
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vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
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(bits(machInst, 22)));
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if (up) {
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return new %(vldr_us)s(machInst, vd, rn, up, imm);
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} else {
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return new %(vldr_s)s(machInst, vd, rn, up, imm);
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}
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} else {
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vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
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(bits(machInst, 22) << 5));
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if (up) {
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return new %(vldr_ud)s(machInst, vd, vd + 1,
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rn, up, imm);
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} else {
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return new %(vldr_d)s(machInst, vd, vd + 1,
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rn, up, imm);
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}
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}
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}
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}
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}
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}
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return new Unknown(machInst);
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return new Unknown(machInst);
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}
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}
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'''
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''' % {
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"vldr_us" : "VLDR_" + loadImmClassName(False, True, False),
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"vldr_s" : "VLDR_" + loadImmClassName(False, False, False),
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"vldr_ud" : "VLDR_" + loadDoubleImmClassName(False, True, False),
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"vldr_d" : "VLDR_" + loadDoubleImmClassName(False, False, False)
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}
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}};
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}};
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def format ShortFpTransfer() {{
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def format ShortFpTransfer() {{
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