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Be sure to delete packet and sender state if the cache is blocked.

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src/cpu/o3/lsq_unit.hh:
    Be sure to delete data if the cache is blocked.

--HG--
extra : convert_revision : fafbcfb8937e85555823942e69e798e557a600e5
This commit is contained in:
Kevin Lim 2006-10-09 19:14:14 -04:00
parent af7315c7dc
commit 92bf23bed6
1 changed files with 18 additions and 21 deletions
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39
src/cpu/o3/lsq_unit.hh
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@ -626,20 +626,27 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
++usedPorts;
PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
data_pkt->dataStatic(load_inst->memData);
LSQSenderState *state = new LSQSenderState;
state->isLoad = true;
state->idx = load_idx;
state->inst = load_inst;
data_pkt->senderState = state;
// if we the cache is not blocked, do cache access
if (!lsq->cacheBlocked()) {
PacketPtr data_pkt =
new Packet(req, Packet::ReadReq, Packet::Broadcast);
data_pkt->dataStatic(load_inst->memData);
LSQSenderState *state = new LSQSenderState;
state->isLoad = true;
state->idx = load_idx;
state->inst = load_inst;
data_pkt->senderState = state;
if (!dcachePort->sendTiming(data_pkt)) {
if (data_pkt->result == Packet::BadAddress) {
delete data_pkt;
Packet::Result result = data_pkt->result;
// Delete state and data packet because a load retry
// initiates a pipeline restart; it does not retry.
delete state;
delete data_pkt;
if (result == Packet::BadAddress) {
return TheISA::genMachineCheckFault();
}
@ -669,16 +676,6 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
return NoFault;
}
if (data_pkt->result != Packet::Success) {
DPRINTF(LSQUnit, "LSQUnit: D-cache miss!\n");
DPRINTF(Activity, "Activity: ld accessing mem miss [sn:%lli]\n",
load_inst->seqNum);
} else {
DPRINTF(LSQUnit, "LSQUnit: D-cache hit!\n");
DPRINTF(Activity, "Activity: ld accessing mem hit [sn:%lli]\n",
load_inst->seqNum);
}
return NoFault;
}