ARM: Even though writes to MVFR0/1 should be unpredictable, we need to make them to do nothing.
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@ -328,6 +328,12 @@ let {{
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case 1:
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specReg = MISCREG_FPSCR;
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break;
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case 6:
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specReg = MISCREG_MVFR1;
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break;
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case 7:
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specReg = MISCREG_MVFR0;
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break;
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case 8:
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specReg = MISCREG_FPEXC;
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break;
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