ARM: mark msr/mrs instructions as SerializeBefore/After
Since miscellaneous registers bypass wakeup logic, force serialization to resolve data dependencies through them * * * ARM: adding non-speculative/serialize flags for instructions change CPSR
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@ -63,7 +63,8 @@ let {{
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mrsCpsrCode = "Dest = (Cpsr | CondCodes) & 0xF8FF03DF"
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mrsCpsrCode = "Dest = (Cpsr | CondCodes) & 0xF8FF03DF"
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mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
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mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
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{ "code": mrsCpsrCode,
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{ "code": mrsCpsrCode,
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"predicate_test": condPredicateTest }, [])
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"predicate_test": condPredicateTest },
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["IsSerializeAfter"])
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header_output += MrsDeclare.subst(mrsCpsrIop)
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header_output += MrsDeclare.subst(mrsCpsrIop)
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decoder_output += MrsConstructor.subst(mrsCpsrIop)
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decoder_output += MrsConstructor.subst(mrsCpsrIop)
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exec_output += PredOpExecute.subst(mrsCpsrIop)
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exec_output += PredOpExecute.subst(mrsCpsrIop)
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@ -71,7 +72,8 @@ let {{
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mrsSpsrCode = "Dest = Spsr"
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mrsSpsrCode = "Dest = Spsr"
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mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
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mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
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{ "code": mrsSpsrCode,
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{ "code": mrsSpsrCode,
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"predicate_test": predicateTest }, [])
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"predicate_test": predicateTest },
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["IsSerializeAfter"])
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header_output += MrsDeclare.subst(mrsSpsrIop)
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header_output += MrsDeclare.subst(mrsSpsrIop)
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decoder_output += MrsConstructor.subst(mrsSpsrIop)
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decoder_output += MrsConstructor.subst(mrsSpsrIop)
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exec_output += PredOpExecute.subst(mrsSpsrIop)
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exec_output += PredOpExecute.subst(mrsSpsrIop)
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@ -85,7 +87,8 @@ let {{
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'''
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'''
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msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
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msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
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{ "code": msrCpsrRegCode,
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{ "code": msrCpsrRegCode,
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"predicate_test": condPredicateTest }, [])
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"predicate_test": condPredicateTest },
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["IsSerializeAfter","IsNonSpeculative"])
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header_output += MsrRegDeclare.subst(msrCpsrRegIop)
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header_output += MsrRegDeclare.subst(msrCpsrRegIop)
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decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
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decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
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exec_output += PredOpExecute.subst(msrCpsrRegIop)
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exec_output += PredOpExecute.subst(msrCpsrRegIop)
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@ -93,7 +96,8 @@ let {{
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msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
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msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
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msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
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msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
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{ "code": msrSpsrRegCode,
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{ "code": msrSpsrRegCode,
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"predicate_test": predicateTest }, [])
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"predicate_test": predicateTest },
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["IsSerializeAfter","IsNonSpeculative"])
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header_output += MsrRegDeclare.subst(msrSpsrRegIop)
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header_output += MsrRegDeclare.subst(msrSpsrRegIop)
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decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
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decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
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exec_output += PredOpExecute.subst(msrSpsrRegIop)
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exec_output += PredOpExecute.subst(msrSpsrRegIop)
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@ -107,7 +111,8 @@ let {{
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'''
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'''
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msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
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msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
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{ "code": msrCpsrImmCode,
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{ "code": msrCpsrImmCode,
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"predicate_test": condPredicateTest }, [])
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"predicate_test": condPredicateTest },
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["IsSerializeAfter","IsNonSpeculative"])
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header_output += MsrImmDeclare.subst(msrCpsrImmIop)
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header_output += MsrImmDeclare.subst(msrCpsrImmIop)
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decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
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decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
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exec_output += PredOpExecute.subst(msrCpsrImmIop)
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exec_output += PredOpExecute.subst(msrCpsrImmIop)
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@ -115,7 +120,8 @@ let {{
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msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
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msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
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msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
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msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
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{ "code": msrSpsrImmCode,
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{ "code": msrSpsrImmCode,
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"predicate_test": predicateTest }, [])
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"predicate_test": predicateTest },
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["IsSerializeAfter","IsNonSpeculative"])
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header_output += MsrImmDeclare.subst(msrSpsrImmIop)
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header_output += MsrImmDeclare.subst(msrSpsrImmIop)
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decoder_output += MsrImmConstructor.subst(msrSpsrImmIop)
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decoder_output += MsrImmConstructor.subst(msrSpsrImmIop)
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exec_output += PredOpExecute.subst(msrSpsrImmIop)
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exec_output += PredOpExecute.subst(msrSpsrImmIop)
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@ -609,7 +615,8 @@ let {{
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'''
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'''
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mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp",
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mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp",
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{ "code": mcr15code,
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{ "code": mcr15code,
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"predicate_test": predicateTest }, [])
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"predicate_test": predicateTest },
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["IsSerializeAfter","IsNonSpeculative"])
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header_output += RegRegOpDeclare.subst(mcr15Iop)
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header_output += RegRegOpDeclare.subst(mcr15Iop)
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decoder_output += RegRegOpConstructor.subst(mcr15Iop)
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decoder_output += RegRegOpConstructor.subst(mcr15Iop)
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exec_output += PredOpExecute.subst(mcr15Iop)
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exec_output += PredOpExecute.subst(mcr15Iop)
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@ -623,7 +630,8 @@ let {{
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mcr15UserIop = InstObjParams("mcr", "Mcr15User", "RegRegOp",
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mcr15UserIop = InstObjParams("mcr", "Mcr15User", "RegRegOp",
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{ "code": "MiscDest = Op1",
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{ "code": "MiscDest = Op1",
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"predicate_test": predicateTest }, [])
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"predicate_test": predicateTest },
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["IsSerializeAfter","IsNonSpeculative"])
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header_output += RegRegOpDeclare.subst(mcr15UserIop)
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header_output += RegRegOpDeclare.subst(mcr15UserIop)
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decoder_output += RegRegOpConstructor.subst(mcr15UserIop)
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decoder_output += RegRegOpConstructor.subst(mcr15UserIop)
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exec_output += PredOpExecute.subst(mcr15UserIop)
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exec_output += PredOpExecute.subst(mcr15UserIop)
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@ -687,7 +695,8 @@ let {{
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'''
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'''
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cpsIop = InstObjParams("cps", "Cps", "ImmOp",
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cpsIop = InstObjParams("cps", "Cps", "ImmOp",
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{ "code": cpsCode,
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{ "code": cpsCode,
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"predicate_test": predicateTest }, [])
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"predicate_test": predicateTest },
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["IsSerializeAfter","IsNonSpeculative"])
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header_output += ImmOpDeclare.subst(cpsIop)
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header_output += ImmOpDeclare.subst(cpsIop)
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decoder_output += ImmOpConstructor.subst(cpsIop)
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decoder_output += ImmOpConstructor.subst(cpsIop)
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exec_output += PredOpExecute.subst(cpsIop)
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exec_output += PredOpExecute.subst(cpsIop)
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@ -321,6 +321,8 @@ template <class Impl>
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void
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void
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BaseDynInst<Impl>::markSrcRegReady()
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BaseDynInst<Impl>::markSrcRegReady()
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{
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{
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DPRINTF(IQ, "[sn:%lli] has %d ready out of %d sources. RTI %d)\n",
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seqNum, readyRegs+1, numSrcRegs(), readyToIssue());
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if (++readyRegs == numSrcRegs()) {
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if (++readyRegs == numSrcRegs()) {
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setCanIssue();
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setCanIssue();
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}
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}
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@ -1192,6 +1192,7 @@ DefaultIEW<Impl>::executeInsts()
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}
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}
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// Uncomment this if you want to see all available instructions.
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// Uncomment this if you want to see all available instructions.
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// @todo This doesn't actually work anymore, we should fix it.
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// printAvailableInsts();
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// printAvailableInsts();
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// Execute/writeback any instructions that are available.
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// Execute/writeback any instructions that are available.
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@ -896,6 +896,8 @@ InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
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// handled by the IQ and thus have no dependency graph entry.
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// handled by the IQ and thus have no dependency graph entry.
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// @todo Figure out a cleaner way to handle this.
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// @todo Figure out a cleaner way to handle this.
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if (dest_reg >= numPhysRegs) {
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if (dest_reg >= numPhysRegs) {
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DPRINTF(IQ, "dest_reg :%d, numPhysRegs: %d\n", dest_reg,
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numPhysRegs);
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continue;
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continue;
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}
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}
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@ -907,8 +909,8 @@ InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
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DynInstPtr dep_inst = dependGraph.pop(dest_reg);
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DynInstPtr dep_inst = dependGraph.pop(dest_reg);
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while (dep_inst) {
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while (dep_inst) {
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DPRINTF(IQ, "Waking up a dependent instruction, PC%#x.\n",
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DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] "
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dep_inst->readPC());
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"PC%#x.\n", dep_inst->seqNum, dep_inst->readPC());
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// Might want to give more information to the instruction
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// Might want to give more information to the instruction
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// so that it knows which of its source registers is
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// so that it knows which of its source registers is
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