ruby: replace Address by Addr
This patch eliminates the type Address defined by the ruby memory system. This memory system would now use the type Addr that is in use by the rest of the system.
This commit is contained in:
Nilay Vaish
parent
9ea5d9cad9
commit
91a84c5b3c
106 changed files with 1122 additions and 1372 deletions
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@ -34,8 +34,8 @@
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typedef RubyTester::SenderState SenderState;
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Check::Check(const Address& address, const Address& pc,
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int _num_writers, int _num_readers, RubyTester* _tester)
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Check::Check(Addr address, Addr pc, int _num_writers, int _num_readers,
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RubyTester* _tester)
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: m_num_writers(_num_writers), m_num_readers(_num_readers),
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m_tester_ptr(_tester)
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{
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@ -103,8 +103,8 @@ Check::initiatePrefetch()
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}
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// Prefetches are assumed to be 0 sized
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Request *req = new Request(m_address.getAddress(), 0, flags,
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m_tester_ptr->masterId(), curTick(), m_pc.getAddress());
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Request *req = new Request(m_address, 0, flags,
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m_tester_ptr->masterId(), curTick(), m_pc);
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req->setThreadContext(index, 0);
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PacketPtr pkt = new Packet(req, cmd);
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@ -142,8 +142,8 @@ Check::initiateFlush()
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Request::Flags flags;
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Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags,
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m_tester_ptr->masterId(), curTick(), m_pc.getAddress());
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Request *req = new Request(m_address, CHECK_SIZE, flags,
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m_tester_ptr->masterId(), curTick(), m_pc);
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Packet::Command cmd;
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@ -172,12 +172,11 @@ Check::initiateAction()
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Request::Flags flags;
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// Create the particular address for the next byte to be written
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Address writeAddr(m_address.getAddress() + m_store_count);
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Addr writeAddr(m_address + m_store_count);
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// Stores are assumed to be 1 byte-sized
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Request *req = new Request(writeAddr.getAddress(), 1, flags,
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m_tester_ptr->masterId(), curTick(),
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m_pc.getAddress());
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Request *req = new Request(writeAddr, 1, flags, m_tester_ptr->masterId(),
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curTick(), m_pc);
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req->setThreadContext(index, 0);
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Packet::Command cmd;
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@ -238,8 +237,8 @@ Check::initiateCheck()
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}
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// Checks are sized depending on the number of bytes written
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Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags,
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m_tester_ptr->masterId(), curTick(), m_pc.getAddress());
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Request *req = new Request(m_address, CHECK_SIZE, flags,
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m_tester_ptr->masterId(), curTick(), m_pc);
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req->setThreadContext(index, 0);
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PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
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@ -273,12 +272,12 @@ Check::initiateCheck()
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void
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Check::performCallback(NodeID proc, SubBlock* data, Cycles curTime)
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{
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Address address = data->getAddress();
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Addr address = data->getAddress();
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// This isn't exactly right since we now have multi-byte checks
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// assert(getAddress() == address);
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assert(getAddress().getLineAddress() == address.getLineAddress());
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assert(makeLineAddress(m_address) == makeLineAddress(address));
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assert(data != NULL);
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DPRINTF(RubyTest, "RubyTester Callback\n");
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@ -325,13 +324,13 @@ Check::performCallback(NodeID proc, SubBlock* data, Cycles curTime)
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}
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DPRINTF(RubyTest, "proc: %d, Address: 0x%x\n", proc,
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getAddress().getLineAddress());
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makeLineAddress(m_address));
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DPRINTF(RubyTest, "Callback done\n");
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debugPrint();
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}
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void
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Check::changeAddress(const Address& address)
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Check::changeAddress(Addr address)
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{
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assert(m_status == TesterStatus_Idle || m_status == TesterStatus_Ready);
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m_status = TesterStatus_Idle;
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@ -375,7 +374,6 @@ Check::debugPrint()
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{
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DPRINTF(RubyTest,
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"[%#x, value: %d, status: %s, initiating node: %d, store_count: %d]\n",
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m_address.getAddress(), (int)m_value,
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TesterStatus_to_string(m_status).c_str(),
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m_address, (int)m_value, TesterStatus_to_string(m_status).c_str(),
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m_initiatingNode, m_store_count);
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}
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@ -45,13 +45,13 @@ const int CHECK_SIZE = (1 << CHECK_SIZE_BITS);
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class Check
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{
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public:
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Check(const Address& address, const Address& pc, int _num_writers,
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Check(Addr address, Addr pc, int _num_writers,
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int _num_readers, RubyTester* _tester);
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void initiate(); // Does Action or Check or nether
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void performCallback(NodeID proc, SubBlock* data, Cycles curTime);
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const Address& getAddress() { return m_address; }
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void changeAddress(const Address& address);
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Addr getAddress() const { return m_address; }
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void changeAddress(Addr address);
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void print(std::ostream& out) const;
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@ -70,8 +70,8 @@ class Check
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uint8_t m_value;
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int m_store_count;
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NodeID m_initiatingNode;
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Address m_address;
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Address m_pc;
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Addr m_address;
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Addr m_pc;
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RubyAccessMode m_access_mode;
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int m_num_writers;
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int m_num_readers;
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@ -37,8 +37,7 @@ CheckTable::CheckTable(int _num_writers, int _num_readers, RubyTester* _tester)
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: m_num_writers(_num_writers), m_num_readers(_num_readers),
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m_tester_ptr(_tester)
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{
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physical_address_t physical = 0;
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Address address;
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Addr physical = 0;
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const int size1 = 32;
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const int size2 = 100;
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@ -47,8 +46,7 @@ CheckTable::CheckTable(int _num_writers, int _num_readers, RubyTester* _tester)
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physical = 1000;
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for (int i = 0; i < size1; i++) {
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// Setup linear addresses
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address.setAddress(physical);
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addCheck(address);
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addCheck(physical);
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physical += CHECK_SIZE;
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}
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@ -57,16 +55,14 @@ CheckTable::CheckTable(int _num_writers, int _num_readers, RubyTester* _tester)
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physical = 1000;
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for (int i = 0; i < size2; i++) {
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// Setup linear addresses
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address.setAddress(physical);
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addCheck(address);
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addCheck(physical);
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physical += 256;
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}
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physical = 1000 + CHECK_SIZE;
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for (int i = 0; i < size2; i++) {
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// Setup linear addresses
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address.setAddress(physical);
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addCheck(address);
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addCheck(physical);
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physical += 256;
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}
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}
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@ -79,27 +75,27 @@ CheckTable::~CheckTable()
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}
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void
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CheckTable::addCheck(const Address& address)
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CheckTable::addCheck(Addr address)
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{
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if (floorLog2(CHECK_SIZE) != 0) {
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if (address.bitSelect(0, CHECK_SIZE_BITS - 1) != 0) {
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if (bitSelect(address, 0, CHECK_SIZE_BITS - 1) != 0) {
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panic("Check not aligned");
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}
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}
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for (int i = 0; i < CHECK_SIZE; i++) {
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if (m_lookup_map.count(Address(address.getAddress()+i))) {
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if (m_lookup_map.count(address+i)) {
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// A mapping for this byte already existed, discard the
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// entire check
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return;
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}
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}
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Check* check_ptr = new Check(address, Address(100 + m_check_vector.size()),
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Check* check_ptr = new Check(address, 100 + m_check_vector.size(),
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m_num_writers, m_num_readers, m_tester_ptr);
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for (int i = 0; i < CHECK_SIZE; i++) {
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// Insert it once per byte
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m_lookup_map[Address(address.getAddress() + i)] = check_ptr;
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m_lookup_map[address + i] = check_ptr;
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}
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m_check_vector.push_back(check_ptr);
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}
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@ -112,11 +108,11 @@ CheckTable::getRandomCheck()
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}
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Check*
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CheckTable::getCheck(const Address& address)
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CheckTable::getCheck(const Addr address)
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{
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DPRINTF(RubyTest, "Looking for check by address: %s", address);
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m5::hash_map<Address, Check*>::iterator i = m_lookup_map.find(address);
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m5::hash_map<Addr, Check*>::iterator i = m_lookup_map.find(address);
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if (i == m_lookup_map.end())
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return NULL;
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@ -46,7 +46,7 @@ class CheckTable
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~CheckTable();
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Check* getRandomCheck();
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Check* getCheck(const Address& address);
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Check* getCheck(Addr address);
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// bool isPresent(const Address& address) const;
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// void removeCheckFromTable(const Address& address);
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@ -56,14 +56,14 @@ class CheckTable
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void print(std::ostream& out) const;
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private:
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void addCheck(const Address& address);
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void addCheck(Addr address);
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// Private copy constructor and assignment operator
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CheckTable(const CheckTable& obj);
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CheckTable& operator=(const CheckTable& obj);
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std::vector<Check*> m_check_vector;
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m5::hash_map<Address, Check*> m_lookup_map;
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m5::hash_map<Addr, Check*> m_lookup_map;
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int m_num_writers;
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int m_num_readers;
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@ -82,7 +82,7 @@ class RubyTester : public MemObject
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{
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SubBlock subBlock;
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SenderState(Address addr, int size) : subBlock(addr, size) {}
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SenderState(Addr addr, int size) : subBlock(addr, size) {}
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};
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@ -119,7 +119,7 @@ machine(L0Cache, "MESI Directory L0 Cache")
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// TBE fields
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structure(TBE, desc="...") {
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Address addr, desc="Physical address for this TBE";
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Addr addr, desc="Physical address for this TBE";
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State TBEState, desc="Transient state";
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DataBlock DataBlk, desc="Buffer for the data block";
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bool Dirty, default="false", desc="data is dirty";
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@ -127,10 +127,10 @@ machine(L0Cache, "MESI Directory L0 Cache")
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}
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structure(TBETable, external="yes") {
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TBE lookup(Address);
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void allocate(Address);
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void deallocate(Address);
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bool isPresent(Address);
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TBE lookup(Addr);
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void allocate(Addr);
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void deallocate(Addr);
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bool isPresent(Addr);
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}
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TBETable TBEs, template="<L0Cache_TBE>", constructor="m_number_of_TBEs";
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@ -139,12 +139,12 @@ machine(L0Cache, "MESI Directory L0 Cache")
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void unset_cache_entry();
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void set_tbe(TBE a);
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void unset_tbe();
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void wakeUpBuffers(Address a);
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void wakeUpAllBuffers(Address a);
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void wakeUpBuffers(Addr a);
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void wakeUpAllBuffers(Addr a);
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void profileMsgDelay(int virtualNetworkType, Cycles c);
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// inclusive cache returns L0 entries only
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Entry getCacheEntry(Address addr), return_by_pointer="yes" {
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Entry getCacheEntry(Addr addr), return_by_pointer="yes" {
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Entry Dcache_entry := static_cast(Entry, "pointer", Dcache[addr]);
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if(is_valid(Dcache_entry)) {
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return Dcache_entry;
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@ -154,17 +154,17 @@ machine(L0Cache, "MESI Directory L0 Cache")
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return Icache_entry;
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}
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Entry getDCacheEntry(Address addr), return_by_pointer="yes" {
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Entry getDCacheEntry(Addr addr), return_by_pointer="yes" {
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Entry Dcache_entry := static_cast(Entry, "pointer", Dcache[addr]);
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return Dcache_entry;
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}
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Entry getICacheEntry(Address addr), return_by_pointer="yes" {
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Entry getICacheEntry(Addr addr), return_by_pointer="yes" {
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Entry Icache_entry := static_cast(Entry, "pointer", Icache[addr]);
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return Icache_entry;
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}
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State getState(TBE tbe, Entry cache_entry, Address addr) {
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State getState(TBE tbe, Entry cache_entry, Addr addr) {
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assert((Dcache.isTagPresent(addr) && Icache.isTagPresent(addr)) == false);
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if(is_valid(tbe)) {
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@ -175,7 +175,7 @@ machine(L0Cache, "MESI Directory L0 Cache")
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return State:I;
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}
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void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
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void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
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assert((Dcache.isTagPresent(addr) && Icache.isTagPresent(addr)) == false);
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// MUST CHANGE
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@ -188,7 +188,7 @@ machine(L0Cache, "MESI Directory L0 Cache")
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}
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}
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AccessPermission getAccessPermission(Address addr) {
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AccessPermission getAccessPermission(Addr addr) {
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TBE tbe := TBEs[addr];
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if(is_valid(tbe)) {
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DPRINTF(RubySlicc, "%s\n", L0Cache_State_to_permission(tbe.TBEState));
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@ -205,7 +205,7 @@ machine(L0Cache, "MESI Directory L0 Cache")
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return AccessPermission:NotPresent;
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}
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void functionalRead(Address addr, Packet *pkt) {
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void functionalRead(Addr addr, Packet *pkt) {
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TBE tbe := TBEs[addr];
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if(is_valid(tbe)) {
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testAndRead(addr, tbe.DataBlk, pkt);
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@ -214,7 +214,7 @@ machine(L0Cache, "MESI Directory L0 Cache")
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}
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}
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int functionalWrite(Address addr, Packet *pkt) {
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int functionalWrite(Addr addr, Packet *pkt) {
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int num_functional_writes := 0;
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TBE tbe := TBEs[addr];
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@ -229,7 +229,7 @@ machine(L0Cache, "MESI Directory L0 Cache")
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return num_functional_writes;
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}
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void setAccessPermission(Entry cache_entry, Address addr, State state) {
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void setAccessPermission(Entry cache_entry, Addr addr, State state) {
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if (is_valid(cache_entry)) {
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cache_entry.changePermission(L0Cache_State_to_permission(state));
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}
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@ -133,7 +133,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
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// TBE fields
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structure(TBE, desc="...") {
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Address addr, desc="Physical address for this TBE";
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Addr addr, desc="Physical address for this TBE";
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State TBEState, desc="Transient state";
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DataBlock DataBlk, desc="Buffer for the data block";
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bool Dirty, default="false", desc="data is dirty";
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@ -141,10 +141,10 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
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}
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structure(TBETable, external="yes") {
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TBE lookup(Address);
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void allocate(Address);
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void deallocate(Address);
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bool isPresent(Address);
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TBE lookup(Addr);
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void allocate(Addr);
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void deallocate(Addr);
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bool isPresent(Addr);
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}
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TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
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@ -155,17 +155,17 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
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void unset_cache_entry();
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void set_tbe(TBE a);
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void unset_tbe();
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void wakeUpBuffers(Address a);
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void wakeUpAllBuffers(Address a);
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void wakeUpBuffers(Addr a);
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void wakeUpAllBuffers(Addr a);
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void profileMsgDelay(int virtualNetworkType, Cycles c);
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// inclusive cache returns L1 entries only
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Entry getCacheEntry(Address addr), return_by_pointer="yes" {
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Entry getCacheEntry(Addr addr), return_by_pointer="yes" {
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Entry cache_entry := static_cast(Entry, "pointer", cache[addr]);
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return cache_entry;
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}
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State getState(TBE tbe, Entry cache_entry, Address addr) {
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State getState(TBE tbe, Entry cache_entry, Addr addr) {
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if(is_valid(tbe)) {
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return tbe.TBEState;
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} else if (is_valid(cache_entry)) {
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@ -174,7 +174,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
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return State:I;
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}
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void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
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void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
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// MUST CHANGE
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if(is_valid(tbe)) {
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tbe.TBEState := state;
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@ -185,7 +185,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
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}
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}
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AccessPermission getAccessPermission(Address addr) {
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AccessPermission getAccessPermission(Addr addr) {
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TBE tbe := TBEs[addr];
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if(is_valid(tbe)) {
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DPRINTF(RubySlicc, "%s\n", L1Cache_State_to_permission(tbe.TBEState));
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@ -202,7 +202,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
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return AccessPermission:NotPresent;
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}
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void functionalRead(Address addr, Packet *pkt) {
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void functionalRead(Addr addr, Packet *pkt) {
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TBE tbe := TBEs[addr];
|
||||
if(is_valid(tbe)) {
|
||||
testAndRead(addr, tbe.DataBlk, pkt);
|
||||
|
|
@ -211,7 +211,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
|
|||
}
|
||||
}
|
||||
|
||||
int functionalWrite(Address addr, Packet *pkt) {
|
||||
int functionalWrite(Addr addr, Packet *pkt) {
|
||||
int num_functional_writes := 0;
|
||||
|
||||
TBE tbe := TBEs[addr];
|
||||
|
|
@ -226,7 +226,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
|
|||
return num_functional_writes;
|
||||
}
|
||||
|
||||
void setAccessPermission(Entry cache_entry, Address addr, State state) {
|
||||
void setAccessPermission(Entry cache_entry, Addr addr, State state) {
|
||||
if (is_valid(cache_entry)) {
|
||||
cache_entry.changePermission(L1Cache_State_to_permission(state));
|
||||
}
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ enumeration(CoherenceClass, desc="...") {
|
|||
|
||||
// Class for messages sent between the L0 and the L1 controllers.
|
||||
structure(CoherenceMsg, desc="...", interface="Message") {
|
||||
Address addr, desc="Physical address of the cache block";
|
||||
Addr addr, desc="Physical address of the cache block";
|
||||
CoherenceClass Class, desc="Type of message (GetS, GetX, PutX, etc)";
|
||||
RubyAccessMode AccessMode, desc="user/supervisor access type";
|
||||
MachineID Sender, desc="What component sent this message";
|
||||
|
|
|
|||
|
|
@ -134,7 +134,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
|
|||
|
||||
// TBE fields
|
||||
structure(TBE, desc="...") {
|
||||
Address addr, desc="Physical address for this TBE";
|
||||
Addr addr, desc="Physical address for this TBE";
|
||||
State TBEState, desc="Transient state";
|
||||
DataBlock DataBlk, desc="Buffer for the data block";
|
||||
bool Dirty, default="false", desc="data is dirty";
|
||||
|
|
@ -143,10 +143,10 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
|
|||
}
|
||||
|
||||
structure(TBETable, external="yes") {
|
||||
TBE lookup(Address);
|
||||
void allocate(Address);
|
||||
void deallocate(Address);
|
||||
bool isPresent(Address);
|
||||
TBE lookup(Addr);
|
||||
void allocate(Addr);
|
||||
void deallocate(Addr);
|
||||
bool isPresent(Addr);
|
||||
}
|
||||
|
||||
TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
|
||||
|
|
@ -159,11 +159,11 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
|
|||
void unset_cache_entry();
|
||||
void set_tbe(TBE a);
|
||||
void unset_tbe();
|
||||
void wakeUpBuffers(Address a);
|
||||
void wakeUpBuffers(Addr a);
|
||||
void profileMsgDelay(int virtualNetworkType, Cycles c);
|
||||
|
||||
// inclusive cache returns L1 entries only
|
||||
Entry getCacheEntry(Address addr), return_by_pointer="yes" {
|
||||
Entry getCacheEntry(Addr addr), return_by_pointer="yes" {
|
||||
Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache[addr]);
|
||||
if(is_valid(L1Dcache_entry)) {
|
||||
return L1Dcache_entry;
|
||||
|
|
@ -173,17 +173,17 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
|
|||
return L1Icache_entry;
|
||||
}
|
||||
|
||||
Entry getL1DCacheEntry(Address addr), return_by_pointer="yes" {
|
||||
Entry getL1DCacheEntry(Addr addr), return_by_pointer="yes" {
|
||||
Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache[addr]);
|
||||
return L1Dcache_entry;
|
||||
}
|
||||
|
||||
Entry getL1ICacheEntry(Address addr), return_by_pointer="yes" {
|
||||
Entry getL1ICacheEntry(Addr addr), return_by_pointer="yes" {
|
||||
Entry L1Icache_entry := static_cast(Entry, "pointer", L1Icache[addr]);
|
||||
return L1Icache_entry;
|
||||
}
|
||||
|
||||
State getState(TBE tbe, Entry cache_entry, Address addr) {
|
||||
State getState(TBE tbe, Entry cache_entry, Addr addr) {
|
||||
assert((L1Dcache.isTagPresent(addr) && L1Icache.isTagPresent(addr)) == false);
|
||||
|
||||
if(is_valid(tbe)) {
|
||||
|
|
@ -194,7 +194,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
|
|||
return State:NP;
|
||||
}
|
||||
|
||||
void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
|
||||
void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
|
||||
assert((L1Dcache.isTagPresent(addr) && L1Icache.isTagPresent(addr)) == false);
|
||||
|
||||
// MUST CHANGE
|
||||
|
|
@ -207,7 +207,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
|
|||
}
|
||||
}
|
||||
|
||||
AccessPermission getAccessPermission(Address addr) {
|
||||
AccessPermission getAccessPermission(Addr addr) {
|
||||
TBE tbe := TBEs[addr];
|
||||
if(is_valid(tbe)) {
|
||||
DPRINTF(RubySlicc, "%s\n", L1Cache_State_to_permission(tbe.TBEState));
|
||||
|
|
@ -224,7 +224,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
|
|||
return AccessPermission:NotPresent;
|
||||
}
|
||||
|
||||
void functionalRead(Address addr, Packet *pkt) {
|
||||
void functionalRead(Addr addr, Packet *pkt) {
|
||||
TBE tbe := TBEs[addr];
|
||||
if(is_valid(tbe)) {
|
||||
testAndRead(addr, tbe.DataBlk, pkt);
|
||||
|
|
@ -233,7 +233,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
|
|||
}
|
||||
}
|
||||
|
||||
int functionalWrite(Address addr, Packet *pkt) {
|
||||
int functionalWrite(Addr addr, Packet *pkt) {
|
||||
int num_functional_writes := 0;
|
||||
|
||||
TBE tbe := TBEs[addr];
|
||||
|
|
@ -248,7 +248,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
|
|||
return num_functional_writes;
|
||||
}
|
||||
|
||||
void setAccessPermission(Entry cache_entry, Address addr, State state) {
|
||||
void setAccessPermission(Entry cache_entry, Addr addr, State state) {
|
||||
if (is_valid(cache_entry)) {
|
||||
cache_entry.changePermission(L1Cache_State_to_permission(state));
|
||||
}
|
||||
|
|
@ -508,7 +508,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
|
|||
}
|
||||
}
|
||||
|
||||
void enqueuePrefetch(Address address, RubyRequestType type) {
|
||||
void enqueuePrefetch(Addr address, RubyRequestType type) {
|
||||
enqueue(optionalQueue_out, RubyRequest, 1) {
|
||||
out_msg.LineAddress := address;
|
||||
out_msg.Type := type;
|
||||
|
|
|
|||
|
|
@ -129,7 +129,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
|
|||
|
||||
// TBE fields
|
||||
structure(TBE, desc="...") {
|
||||
Address addr, desc="Physical address for this TBE";
|
||||
Addr addr, desc="Physical address for this TBE";
|
||||
State TBEState, desc="Transient state";
|
||||
DataBlock DataBlk, desc="Buffer for the data block";
|
||||
bool Dirty, default="false", desc="Data is Dirty";
|
||||
|
|
@ -140,10 +140,10 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
|
|||
}
|
||||
|
||||
structure(TBETable, external="yes") {
|
||||
TBE lookup(Address);
|
||||
void allocate(Address);
|
||||
void deallocate(Address);
|
||||
bool isPresent(Address);
|
||||
TBE lookup(Addr);
|
||||
void allocate(Addr);
|
||||
void deallocate(Addr);
|
||||
bool isPresent(Addr);
|
||||
}
|
||||
|
||||
TBETable TBEs, template="<L2Cache_TBE>", constructor="m_number_of_TBEs";
|
||||
|
|
@ -152,15 +152,15 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
|
|||
void unset_cache_entry();
|
||||
void set_tbe(TBE a);
|
||||
void unset_tbe();
|
||||
void wakeUpBuffers(Address a);
|
||||
void wakeUpBuffers(Addr a);
|
||||
void profileMsgDelay(int virtualNetworkType, Cycles c);
|
||||
|
||||
// inclusive cache, returns L2 entries only
|
||||
Entry getCacheEntry(Address addr), return_by_pointer="yes" {
|
||||
Entry getCacheEntry(Addr addr), return_by_pointer="yes" {
|
||||
return static_cast(Entry, "pointer", L2cache[addr]);
|
||||
}
|
||||
|
||||
bool isSharer(Address addr, MachineID requestor, Entry cache_entry) {
|
||||
bool isSharer(Addr addr, MachineID requestor, Entry cache_entry) {
|
||||
if (is_valid(cache_entry)) {
|
||||
return cache_entry.Sharers.isElement(requestor);
|
||||
} else {
|
||||
|
|
@ -168,14 +168,14 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
|
|||
}
|
||||
}
|
||||
|
||||
void addSharer(Address addr, MachineID requestor, Entry cache_entry) {
|
||||
void addSharer(Addr addr, MachineID requestor, Entry cache_entry) {
|
||||
assert(is_valid(cache_entry));
|
||||
DPRINTF(RubySlicc, "machineID: %s, requestor: %s, address: %s\n",
|
||||
machineID, requestor, addr);
|
||||
cache_entry.Sharers.add(requestor);
|
||||
}
|
||||
|
||||
State getState(TBE tbe, Entry cache_entry, Address addr) {
|
||||
State getState(TBE tbe, Entry cache_entry, Addr addr) {
|
||||
if(is_valid(tbe)) {
|
||||
return tbe.TBEState;
|
||||
} else if (is_valid(cache_entry)) {
|
||||
|
|
@ -184,7 +184,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
|
|||
return State:NP;
|
||||
}
|
||||
|
||||
void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
|
||||
void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
|
||||
// MUST CHANGE
|
||||
if (is_valid(tbe)) {
|
||||
tbe.TBEState := state;
|
||||
|
|
@ -195,7 +195,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
|
|||
}
|
||||
}
|
||||
|
||||
AccessPermission getAccessPermission(Address addr) {
|
||||
AccessPermission getAccessPermission(Addr addr) {
|
||||
TBE tbe := TBEs[addr];
|
||||
if(is_valid(tbe)) {
|
||||
DPRINTF(RubySlicc, "%s\n", L2Cache_State_to_permission(tbe.TBEState));
|
||||
|
|
@ -212,7 +212,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
|
|||
return AccessPermission:NotPresent;
|
||||
}
|
||||
|
||||
void functionalRead(Address addr, Packet *pkt) {
|
||||
void functionalRead(Addr addr, Packet *pkt) {
|
||||
TBE tbe := TBEs[addr];
|
||||
if(is_valid(tbe)) {
|
||||
testAndRead(addr, tbe.DataBlk, pkt);
|
||||
|
|
@ -221,7 +221,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
|
|||
}
|
||||
}
|
||||
|
||||
int functionalWrite(Address addr, Packet *pkt) {
|
||||
int functionalWrite(Addr addr, Packet *pkt) {
|
||||
int num_functional_writes := 0;
|
||||
|
||||
TBE tbe := TBEs[addr];
|
||||
|
|
@ -236,13 +236,13 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
|
|||
return num_functional_writes;
|
||||
}
|
||||
|
||||
void setAccessPermission(Entry cache_entry, Address addr, State state) {
|
||||
void setAccessPermission(Entry cache_entry, Addr addr, State state) {
|
||||
if (is_valid(cache_entry)) {
|
||||
cache_entry.changePermission(L2Cache_State_to_permission(state));
|
||||
}
|
||||
}
|
||||
|
||||
Event L1Cache_request_type_to_event(CoherenceRequestType type, Address addr,
|
||||
Event L1Cache_request_type_to_event(CoherenceRequestType type, Addr addr,
|
||||
MachineID requestor, Entry cache_entry) {
|
||||
if(type == CoherenceRequestType:GETS) {
|
||||
return Event:L1_GETS;
|
||||
|
|
|
|||
|
|
@ -77,17 +77,17 @@ machine(Directory, "MESI Two Level directory protocol")
|
|||
|
||||
// TBE entries for DMA requests
|
||||
structure(TBE, desc="TBE entries for outstanding DMA requests") {
|
||||
Address PhysicalAddress, desc="physical address";
|
||||
Addr PhysicalAddress, desc="physical address";
|
||||
State TBEState, desc="Transient State";
|
||||
DataBlock DataBlk, desc="Data to be written (DMA write only)";
|
||||
int Len, desc="...";
|
||||
}
|
||||
|
||||
structure(TBETable, external="yes") {
|
||||
TBE lookup(Address);
|
||||
void allocate(Address);
|
||||
void deallocate(Address);
|
||||
bool isPresent(Address);
|
||||
TBE lookup(Addr);
|
||||
void allocate(Addr);
|
||||
void deallocate(Addr);
|
||||
bool isPresent(Addr);
|
||||
bool functionalRead(Packet *pkt);
|
||||
int functionalWrite(Packet *pkt);
|
||||
}
|
||||
|
|
@ -98,9 +98,9 @@ machine(Directory, "MESI Two Level directory protocol")
|
|||
|
||||
void set_tbe(TBE tbe);
|
||||
void unset_tbe();
|
||||
void wakeUpBuffers(Address a);
|
||||
void wakeUpBuffers(Addr a);
|
||||
|
||||
Entry getDirectoryEntry(Address addr), return_by_pointer="yes" {
|
||||
Entry getDirectoryEntry(Addr addr), return_by_pointer="yes" {
|
||||
Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
|
||||
|
||||
if (is_valid(dir_entry)) {
|
||||
|
|
@ -112,7 +112,7 @@ machine(Directory, "MESI Two Level directory protocol")
|
|||
return dir_entry;
|
||||
}
|
||||
|
||||
State getState(TBE tbe, Address addr) {
|
||||
State getState(TBE tbe, Addr addr) {
|
||||
if (is_valid(tbe)) {
|
||||
return tbe.TBEState;
|
||||
} else if (directory.isPresent(addr)) {
|
||||
|
|
@ -122,7 +122,7 @@ machine(Directory, "MESI Two Level directory protocol")
|
|||
}
|
||||
}
|
||||
|
||||
void setState(TBE tbe, Address addr, State state) {
|
||||
void setState(TBE tbe, Addr addr, State state) {
|
||||
if (is_valid(tbe)) {
|
||||
tbe.TBEState := state;
|
||||
}
|
||||
|
|
@ -132,7 +132,7 @@ machine(Directory, "MESI Two Level directory protocol")
|
|||
}
|
||||
}
|
||||
|
||||
AccessPermission getAccessPermission(Address addr) {
|
||||
AccessPermission getAccessPermission(Addr addr) {
|
||||
TBE tbe := TBEs[addr];
|
||||
if(is_valid(tbe)) {
|
||||
DPRINTF(RubySlicc, "%s\n", Directory_State_to_permission(tbe.TBEState));
|
||||
|
|
@ -148,7 +148,7 @@ machine(Directory, "MESI Two Level directory protocol")
|
|||
return AccessPermission:NotPresent;
|
||||
}
|
||||
|
||||
void functionalRead(Address addr, Packet *pkt) {
|
||||
void functionalRead(Addr addr, Packet *pkt) {
|
||||
TBE tbe := TBEs[addr];
|
||||
if(is_valid(tbe)) {
|
||||
testAndRead(addr, tbe.DataBlk, pkt);
|
||||
|
|
@ -157,7 +157,7 @@ machine(Directory, "MESI Two Level directory protocol")
|
|||
}
|
||||
}
|
||||
|
||||
int functionalWrite(Address addr, Packet *pkt) {
|
||||
int functionalWrite(Addr addr, Packet *pkt) {
|
||||
int num_functional_writes := 0;
|
||||
|
||||
TBE tbe := TBEs[addr];
|
||||
|
|
@ -170,7 +170,7 @@ machine(Directory, "MESI Two Level directory protocol")
|
|||
return num_functional_writes;
|
||||
}
|
||||
|
||||
void setAccessPermission(Address addr, State state) {
|
||||
void setAccessPermission(Addr addr, State state) {
|
||||
if (directory.isPresent(addr)) {
|
||||
getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state));
|
||||
}
|
||||
|
|
|
|||
|
|
@ -52,26 +52,26 @@ machine(DMA, "DMA Controller")
|
|||
MessageBuffer mandatoryQueue;
|
||||
State cur_state;
|
||||
|
||||
State getState(Address addr) {
|
||||
State getState(Addr addr) {
|
||||
return cur_state;
|
||||
}
|
||||
|
||||
void setState(Address addr, State state) {
|
||||
void setState(Addr addr, State state) {
|
||||
cur_state := state;
|
||||
}
|
||||
|
||||
AccessPermission getAccessPermission(Address addr) {
|
||||
AccessPermission getAccessPermission(Addr addr) {
|
||||
return AccessPermission:NotPresent;
|
||||
}
|
||||
|
||||
void setAccessPermission(Address addr, State state) {
|
||||
void setAccessPermission(Addr addr, State state) {
|
||||
}
|
||||
|
||||
void functionalRead(Address addr, Packet *pkt) {
|
||||
void functionalRead(Addr addr, Packet *pkt) {
|
||||
error("DMA does not support functional read.");
|
||||
}
|
||||
|
||||
int functionalWrite(Address addr, Packet *pkt) {
|
||||
int functionalWrite(Addr addr, Packet *pkt) {
|
||||
error("DMA does not support functional write.");
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -58,7 +58,7 @@ enumeration(CoherenceResponseType, desc="...") {
|
|||
|
||||
// RequestMsg
|
||||
structure(RequestMsg, desc="...", interface="Message") {
|
||||
Address addr, desc="Physical address for this request";
|
||||
Addr addr, desc="Physical address for this request";
|
||||
CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)";
|
||||
RubyAccessMode AccessMode, desc="user/supervisor access type";
|
||||
MachineID Requestor , desc="What component request";
|
||||
|
|
@ -87,7 +87,7 @@ structure(RequestMsg, desc="...", interface="Message") {
|
|||
|
||||
// ResponseMsg
|
||||
structure(ResponseMsg, desc="...", interface="Message") {
|
||||
Address addr, desc="Physical address for this request";
|
||||
Addr addr, desc="Physical address for this request";
|
||||
CoherenceResponseType Type, desc="Type of response (Ack, Data, etc)";
|
||||
MachineID Sender, desc="What component sent the data";
|
||||
NetDest Destination, desc="Node to whom the data is sent";
|
||||
|
|
|
|||
|
|
@ -93,10 +93,10 @@ machine(L1Cache, "MI Example L1 Cache")
|
|||
}
|
||||
|
||||
structure(TBETable, external="yes") {
|
||||
TBE lookup(Address);
|
||||
void allocate(Address);
|
||||
void deallocate(Address);
|
||||
bool isPresent(Address);
|
||||
TBE lookup(Addr);
|
||||
void allocate(Addr);
|
||||
void deallocate(Addr);
|
||||
bool isPresent(Addr);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -110,7 +110,7 @@ machine(L1Cache, "MI Example L1 Cache")
|
|||
void unset_tbe();
|
||||
void profileMsgDelay(int virtualNetworkType, Cycles b);
|
||||
|
||||
Entry getCacheEntry(Address address), return_by_pointer="yes" {
|
||||
Entry getCacheEntry(Addr address), return_by_pointer="yes" {
|
||||
return static_cast(Entry, "pointer", cacheMemory.lookup(address));
|
||||
}
|
||||
|
||||
|
|
@ -127,7 +127,7 @@ machine(L1Cache, "MI Example L1 Cache")
|
|||
}
|
||||
}
|
||||
|
||||
State getState(TBE tbe, Entry cache_entry, Address addr) {
|
||||
State getState(TBE tbe, Entry cache_entry, Addr addr) {
|
||||
|
||||
if (is_valid(tbe)) {
|
||||
return tbe.TBEState;
|
||||
|
|
@ -140,7 +140,7 @@ machine(L1Cache, "MI Example L1 Cache")
|
|||
}
|
||||
}
|
||||
|
||||
void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
|
||||
void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
|
||||
|
||||
if (is_valid(tbe)) {
|
||||
tbe.TBEState := state;
|
||||
|
|
@ -151,7 +151,7 @@ machine(L1Cache, "MI Example L1 Cache")
|
|||
}
|
||||
}
|
||||
|
||||
AccessPermission getAccessPermission(Address addr) {
|
||||
AccessPermission getAccessPermission(Addr addr) {
|
||||
TBE tbe := TBEs[addr];
|
||||
if(is_valid(tbe)) {
|
||||
return L1Cache_State_to_permission(tbe.TBEState);
|
||||
|
|
@ -165,13 +165,13 @@ machine(L1Cache, "MI Example L1 Cache")
|
|||
return AccessPermission:NotPresent;
|
||||
}
|
||||
|
||||
void setAccessPermission(Entry cache_entry, Address addr, State state) {
|
||||
void setAccessPermission(Entry cache_entry, Addr addr, State state) {
|
||||
if (is_valid(cache_entry)) {
|
||||
cache_entry.changePermission(L1Cache_State_to_permission(state));
|
||||
}
|
||||
}
|
||||
|
||||
void functionalRead(Address addr, Packet *pkt) {
|
||||
void functionalRead(Addr addr, Packet *pkt) {
|
||||
TBE tbe := TBEs[addr];
|
||||
if(is_valid(tbe)) {
|
||||
testAndRead(addr, tbe.DataBlk, pkt);
|
||||
|
|
@ -180,7 +180,7 @@ machine(L1Cache, "MI Example L1 Cache")
|
|||
}
|
||||
}
|
||||
|
||||
int functionalWrite(Address addr, Packet *pkt) {
|
||||
int functionalWrite(Addr addr, Packet *pkt) {
|
||||
int num_functional_writes := 0;
|
||||
|
||||
TBE tbe := TBEs[addr];
|
||||
|
|
|
|||
|
|
@ -90,7 +90,7 @@ machine(Directory, "Directory protocol")
|
|||
|
||||
// TBE entries for DMA requests
|
||||
structure(TBE, desc="TBE entries for outstanding DMA requests") {
|
||||
Address PhysicalAddress, desc="physical address";
|
||||
Addr PhysicalAddress, desc="physical address";
|
||||
State TBEState, desc="Transient State";
|
||||
DataBlock DataBlk, desc="Data to be written (DMA write only)";
|
||||
int Len, desc="...";
|
||||
|
|
@ -98,10 +98,10 @@ machine(Directory, "Directory protocol")
|
|||
}
|
||||
|
||||
structure(TBETable, external="yes") {
|
||||
TBE lookup(Address);
|
||||
void allocate(Address);
|
||||
void deallocate(Address);
|
||||
bool isPresent(Address);
|
||||
TBE lookup(Addr);
|
||||
void allocate(Addr);
|
||||
void deallocate(Addr);
|
||||
bool isPresent(Addr);
|
||||
}
|
||||
|
||||
// ** OBJECTS **
|
||||
|
|
@ -110,7 +110,7 @@ machine(Directory, "Directory protocol")
|
|||
void set_tbe(TBE b);
|
||||
void unset_tbe();
|
||||
|
||||
Entry getDirectoryEntry(Address addr), return_by_pointer="yes" {
|
||||
Entry getDirectoryEntry(Addr addr), return_by_pointer="yes" {
|
||||
Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
|
||||
|
||||
if (is_valid(dir_entry)) {
|
||||
|
|
@ -122,7 +122,7 @@ machine(Directory, "Directory protocol")
|
|||
return dir_entry;
|
||||
}
|
||||
|
||||
State getState(TBE tbe, Address addr) {
|
||||
State getState(TBE tbe, Addr addr) {
|
||||
if (is_valid(tbe)) {
|
||||
return tbe.TBEState;
|
||||
} else if (directory.isPresent(addr)) {
|
||||
|
|
@ -132,7 +132,7 @@ machine(Directory, "Directory protocol")
|
|||
}
|
||||
}
|
||||
|
||||
void setState(TBE tbe, Address addr, State state) {
|
||||
void setState(TBE tbe, Addr addr, State state) {
|
||||
|
||||
if (is_valid(tbe)) {
|
||||
tbe.TBEState := state;
|
||||
|
|
@ -154,7 +154,7 @@ machine(Directory, "Directory protocol")
|
|||
}
|
||||
}
|
||||
|
||||
AccessPermission getAccessPermission(Address addr) {
|
||||
AccessPermission getAccessPermission(Addr addr) {
|
||||
TBE tbe := TBEs[addr];
|
||||
if(is_valid(tbe)) {
|
||||
return Directory_State_to_permission(tbe.TBEState);
|
||||
|
|
@ -167,13 +167,13 @@ machine(Directory, "Directory protocol")
|
|||
return AccessPermission:NotPresent;
|
||||
}
|
||||
|
||||
void setAccessPermission(Address addr, State state) {
|
||||
void setAccessPermission(Addr addr, State state) {
|
||||
if (directory.isPresent(addr)) {
|
||||
getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state));
|
||||
}
|
||||
}
|
||||
|
||||
void functionalRead(Address addr, Packet *pkt) {
|
||||
void functionalRead(Addr addr, Packet *pkt) {
|
||||
TBE tbe := TBEs[addr];
|
||||
if(is_valid(tbe)) {
|
||||
testAndRead(addr, tbe.DataBlk, pkt);
|
||||
|
|
@ -182,7 +182,7 @@ machine(Directory, "Directory protocol")
|
|||
}
|
||||
}
|
||||
|
||||
int functionalWrite(Address addr, Packet *pkt) {
|
||||
int functionalWrite(Addr addr, Packet *pkt) {
|
||||
int num_functional_writes := 0;
|
||||
|
||||
TBE tbe := TBEs[addr];
|
||||
|
|
|
|||
|
|
@ -52,25 +52,25 @@ machine(DMA, "DMA Controller")
|
|||
MessageBuffer mandatoryQueue;
|
||||
State cur_state;
|
||||
|
||||
State getState(Address addr) {
|
||||
State getState(Addr addr) {
|
||||
return cur_state;
|
||||
}
|
||||
void setState(Address addr, State state) {
|
||||
void setState(Addr addr, State state) {
|
||||
cur_state := state;
|
||||
}
|
||||
|
||||
AccessPermission getAccessPermission(Address addr) {
|
||||
AccessPermission getAccessPermission(Addr addr) {
|
||||
return AccessPermission:NotPresent;
|
||||
}
|
||||
|
||||
void setAccessPermission(Address addr, State state) {
|
||||
void setAccessPermission(Addr addr, State state) {
|
||||
}
|
||||
|
||||
void functionalRead(Address addr, Packet *pkt) {
|
||||
void functionalRead(Addr addr, Packet *pkt) {
|
||||
error("DMA does not support functional read.");
|
||||
}
|
||||
|
||||
int functionalWrite(Address addr, Packet *pkt) {
|
||||
int functionalWrite(Addr addr, Packet *pkt) {
|
||||
error("DMA does not support functional write.");
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@ enumeration(CoherenceResponseType, desc="...") {
|
|||
|
||||
// RequestMsg (and also forwarded requests)
|
||||
structure(RequestMsg, desc="...", interface="Message") {
|
||||
Address addr, desc="Physical address for this request";
|
||||
Addr addr, desc="Physical address for this request";
|
||||
CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)";
|
||||
MachineID Requestor, desc="Node who initiated the request";
|
||||
NetDest Destination, desc="Multicast destination mask";
|
||||
|
|
@ -75,7 +75,7 @@ structure(RequestMsg, desc="...", interface="Message") {
|
|||
|
||||
// ResponseMsg (and also unblock requests)
|
||||
structure(ResponseMsg, desc="...", interface="Message") {
|
||||
Address addr, desc="Physical address for this request";
|
||||
Addr addr, desc="Physical address for this request";
|
||||
CoherenceResponseType Type, desc="Type of response (Ack, Data, etc)";
|
||||
MachineID Sender, desc="Node who sent the data";
|
||||
NetDest Destination, desc="Node to whom the data is sent";
|
||||
|
|
@ -110,8 +110,8 @@ enumeration(DMAResponseType, desc="...", default="DMAResponseType_NULL") {
|
|||
|
||||
structure(DMARequestMsg, desc="...", interface="Message") {
|
||||
DMARequestType Type, desc="Request type (read/write)";
|
||||
Address PhysicalAddress, desc="Physical address for this request";
|
||||
Address LineAddress, desc="Line address for this request";
|
||||
Addr PhysicalAddress, desc="Physical address for this request";
|
||||
Addr LineAddress, desc="Line address for this request";
|
||||
MachineID Requestor, desc="Node who initiated the request";
|
||||
NetDest Destination, desc="Destination";
|
||||
DataBlock DataBlk, desc="DataBlk attached to this request";
|
||||
|
|
@ -129,8 +129,8 @@ structure(DMARequestMsg, desc="...", interface="Message") {
|
|||
|
||||
structure(DMAResponseMsg, desc="...", interface="Message") {
|
||||
DMAResponseType Type, desc="Response type (DATA/ACK)";
|
||||
Address PhysicalAddress, desc="Physical address for this request";
|
||||
Address LineAddress, desc="Line address for this request";
|
||||
Addr PhysicalAddress, desc="Physical address for this request";
|
||||
Addr LineAddress, desc="Line address for this request";
|
||||
NetDest Destination, desc="Destination";
|
||||
DataBlock DataBlk, desc="DataBlk attached to this request";
|
||||
MessageSizeType MessageSize, desc="size category of the message";
|
||||
|
|
|
|||
|
|
@ -115,7 +115,7 @@ machine(L1Cache, "Directory protocol")
|
|||
|
||||
// TBE fields
|
||||
structure(TBE, desc="...") {
|
||||
Address addr, desc="Physical address for this TBE";
|
||||
Addr addr, desc="Physical address for this TBE";
|
||||
State TBEState, desc="Transient state";
|
||||
DataBlock DataBlk, desc="data for the block, required for concurrent writebacks";
|
||||
bool Dirty, desc="Is the data dirty (different than memory)?";
|
||||
|
|
@ -123,10 +123,10 @@ machine(L1Cache, "Directory protocol")
|
|||
}
|
||||
|
||||
structure(TBETable, external ="yes") {
|
||||
TBE lookup(Address);
|
||||
void allocate(Address);
|
||||
void deallocate(Address);
|
||||
bool isPresent(Address);
|
||||
TBE lookup(Addr);
|
||||
void allocate(Addr);
|
||||
void deallocate(Addr);
|
||||
bool isPresent(Addr);
|
||||
}
|
||||
|
||||
void set_cache_entry(AbstractCacheEntry b);
|
||||
|
|
@ -140,7 +140,7 @@ machine(L1Cache, "Directory protocol")
|
|||
TimerTable useTimerTable;
|
||||
int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
|
||||
|
||||
Entry getCacheEntry(Address addr), return_by_pointer="yes" {
|
||||
Entry getCacheEntry(Addr addr), return_by_pointer="yes" {
|
||||
Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache.lookup(addr));
|
||||
if(is_valid(L1Dcache_entry)) {
|
||||
return L1Dcache_entry;
|
||||
|
|
@ -150,15 +150,15 @@ machine(L1Cache, "Directory protocol")
|
|||
return L1Icache_entry;
|
||||
}
|
||||
|
||||
Entry getL1DCacheEntry(Address addr), return_by_pointer="yes" {
|
||||
Entry getL1DCacheEntry(Addr addr), return_by_pointer="yes" {
|
||||
return static_cast(Entry, "pointer", L1Dcache.lookup(addr));
|
||||
}
|
||||
|
||||
Entry getL1ICacheEntry(Address addr), return_by_pointer="yes" {
|
||||
Entry getL1ICacheEntry(Addr addr), return_by_pointer="yes" {
|
||||
return static_cast(Entry, "pointer", L1Icache.lookup(addr));
|
||||
}
|
||||
|
||||
State getState(TBE tbe, Entry cache_entry, Address addr) {
|
||||
State getState(TBE tbe, Entry cache_entry, Addr addr) {
|
||||
if(is_valid(tbe)) {
|
||||
return tbe.TBEState;
|
||||
} else if (is_valid(cache_entry)) {
|
||||
|
|
@ -167,7 +167,7 @@ machine(L1Cache, "Directory protocol")
|
|||
return State:I;
|
||||
}
|
||||
|
||||
void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
|
||||
void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
|
||||
assert((L1Dcache.isTagPresent(addr) && L1Icache.isTagPresent(addr)) == false);
|
||||
|
||||
if (is_valid(tbe)) {
|
||||
|
|
@ -189,7 +189,7 @@ machine(L1Cache, "Directory protocol")
|
|||
}
|
||||
}
|
||||
|
||||
AccessPermission getAccessPermission(Address addr) {
|
||||
AccessPermission getAccessPermission(Addr addr) {
|
||||
TBE tbe := TBEs[addr];
|
||||
if(is_valid(tbe)) {
|
||||
DPRINTF(RubySlicc, "%s\n", L1Cache_State_to_permission(tbe.TBEState));
|
||||
|
|
@ -206,13 +206,13 @@ machine(L1Cache, "Directory protocol")
|
|||
return AccessPermission:NotPresent;
|
||||
}
|
||||
|
||||
void setAccessPermission(Entry cache_entry, Address addr, State state) {
|
||||
void setAccessPermission(Entry cache_entry, Addr addr, State state) {
|
||||
if (is_valid(cache_entry)) {
|
||||
cache_entry.changePermission(L1Cache_State_to_permission(state));
|
||||
}
|
||||
}
|
||||
|
||||
void functionalRead(Address addr, Packet *pkt) {
|
||||
void functionalRead(Addr addr, Packet *pkt) {
|
||||
Entry cache_entry := getCacheEntry(addr);
|
||||
if(is_valid(cache_entry)) {
|
||||
testAndRead(addr, cache_entry.DataBlk, pkt);
|
||||
|
|
@ -226,7 +226,7 @@ machine(L1Cache, "Directory protocol")
|
|||
}
|
||||
}
|
||||
|
||||
int functionalWrite(Address addr, Packet *pkt) {
|
||||
int functionalWrite(Addr addr, Packet *pkt) {
|
||||
int num_functional_writes := 0;
|
||||
|
||||
Entry cache_entry := getCacheEntry(addr);
|
||||
|
|
@ -265,7 +265,7 @@ machine(L1Cache, "Directory protocol")
|
|||
// ** IN_PORTS **
|
||||
|
||||
// Use Timer
|
||||
in_port(useTimerTable_in, Address, useTimerTable) {
|
||||
in_port(useTimerTable_in, Addr, useTimerTable) {
|
||||
if (useTimerTable_in.isReady()) {
|
||||
trigger(Event:Use_Timeout, useTimerTable.readyAddress(),
|
||||
getCacheEntry(useTimerTable.readyAddress()),
|
||||
|
|
|
|||
|
|
@ -192,9 +192,9 @@ machine(L2Cache, "Token protocol")
|
|||
|
||||
// TBE fields
|
||||
structure(TBE, desc="...") {
|
||||
Address addr, desc="Physical address for this TBE";
|
||||
Addr addr, desc="Physical address for this TBE";
|
||||
State TBEState, desc="Transient state";
|
||||
Address PC, desc="Program counter of request";
|
||||
Addr PC, desc="Program counter of request";
|
||||
DataBlock DataBlk, desc="Buffer for the data block";
|
||||
bool Dirty, desc="Is the data dirty (different than memory)?";
|
||||
|
||||
|
|
@ -210,17 +210,17 @@ machine(L2Cache, "Token protocol")
|
|||
}
|
||||
|
||||
structure(TBETable, external = "yes") {
|
||||
TBE lookup(Address);
|
||||
void allocate(Address);
|
||||
void deallocate(Address);
|
||||
bool isPresent(Address);
|
||||
TBE lookup(Addr);
|
||||
void allocate(Addr);
|
||||
void deallocate(Addr);
|
||||
bool isPresent(Addr);
|
||||
}
|
||||
|
||||
structure(PerfectCacheMemory, external = "yes") {
|
||||
void allocate(Address);
|
||||
void deallocate(Address);
|
||||
DirEntry lookup(Address);
|
||||
bool isTagPresent(Address);
|
||||
void allocate(Addr);
|
||||
void deallocate(Addr);
|
||||
DirEntry lookup(Addr);
|
||||
bool isTagPresent(Addr);
|
||||
}
|
||||
|
||||
TBETable TBEs, template="<L2Cache_TBE>", constructor="m_number_of_TBEs";
|
||||
|
|
@ -231,19 +231,19 @@ machine(L2Cache, "Token protocol")
|
|||
void set_tbe(TBE b);
|
||||
void unset_tbe();
|
||||
|
||||
Entry getCacheEntry(Address address), return_by_pointer="yes" {
|
||||
Entry getCacheEntry(Addr address), return_by_pointer="yes" {
|
||||
return static_cast(Entry, "pointer", L2cache[address]);
|
||||
}
|
||||
|
||||
bool isDirTagPresent(Address addr) {
|
||||
bool isDirTagPresent(Addr addr) {
|
||||
return (localDirectory.isTagPresent(addr) );
|
||||
}
|
||||
|
||||
DirEntry getDirEntry(Address address), return_by_pointer="yes" {
|
||||
DirEntry getDirEntry(Addr address), return_by_pointer="yes" {
|
||||
return localDirectory.lookup(address);
|
||||
}
|
||||
|
||||
bool isOnlySharer(Entry cache_entry, Address addr, MachineID shar_id) {
|
||||
bool isOnlySharer(Entry cache_entry, Addr addr, MachineID shar_id) {
|
||||
if (is_valid(cache_entry)) {
|
||||
assert (localDirectory.isTagPresent(addr) == false);
|
||||
if (cache_entry.Sharers.count() > 1) {
|
||||
|
|
@ -285,7 +285,7 @@ machine(L2Cache, "Token protocol")
|
|||
}
|
||||
}
|
||||
|
||||
void copyCacheStateToDir(Entry cache_entry, Address addr) {
|
||||
void copyCacheStateToDir(Entry cache_entry, Addr addr) {
|
||||
assert(localDirectory.isTagPresent(addr) == false);
|
||||
assert(is_valid(cache_entry));
|
||||
localDirectory.allocate(addr);
|
||||
|
|
@ -297,7 +297,7 @@ machine(L2Cache, "Token protocol")
|
|||
|
||||
}
|
||||
|
||||
void copyDirToCache(Entry cache_entry, Address addr) {
|
||||
void copyDirToCache(Entry cache_entry, Addr addr) {
|
||||
assert(is_valid(cache_entry));
|
||||
DirEntry dir_entry := getDirEntry(addr);
|
||||
cache_entry.Sharers := dir_entry.Sharers;
|
||||
|
|
@ -306,7 +306,7 @@ machine(L2Cache, "Token protocol")
|
|||
}
|
||||
|
||||
|
||||
void recordLocalSharerInDir(Entry cache_entry, Address addr, MachineID shar_id) {
|
||||
void recordLocalSharerInDir(Entry cache_entry, Addr addr, MachineID shar_id) {
|
||||
if (is_valid(cache_entry)) {
|
||||
assert (localDirectory.isTagPresent(addr) == false);
|
||||
cache_entry.Sharers.add(shar_id);
|
||||
|
|
@ -323,7 +323,7 @@ machine(L2Cache, "Token protocol")
|
|||
}
|
||||
}
|
||||
|
||||
void recordNewLocalExclusiveInDir(Entry cache_entry, Address addr, MachineID exc_id) {
|
||||
void recordNewLocalExclusiveInDir(Entry cache_entry, Addr addr, MachineID exc_id) {
|
||||
|
||||
if (is_valid(cache_entry)) {
|
||||
assert (localDirectory.isTagPresent(addr) == false);
|
||||
|
|
@ -342,7 +342,7 @@ machine(L2Cache, "Token protocol")
|
|||
}
|
||||
}
|
||||
|
||||
void removeAllLocalSharersFromDir(Entry cache_entry, Address addr) {
|
||||
void removeAllLocalSharersFromDir(Entry cache_entry, Addr addr) {
|
||||
if (is_valid(cache_entry)) {
|
||||
assert (localDirectory.isTagPresent(addr) == false);
|
||||
cache_entry.Sharers.clear();
|
||||
|
|
@ -355,7 +355,7 @@ machine(L2Cache, "Token protocol")
|
|||
}
|
||||
}
|
||||
|
||||
void removeSharerFromDir(Entry cache_entry, Address addr, MachineID sender) {
|
||||
void removeSharerFromDir(Entry cache_entry, Addr addr, MachineID sender) {
|
||||
if (is_valid(cache_entry)) {
|
||||
assert (localDirectory.isTagPresent(addr) == false);
|
||||
cache_entry.Sharers.remove(sender);
|
||||
|
|
@ -366,7 +366,7 @@ machine(L2Cache, "Token protocol")
|
|||
}
|
||||
}
|
||||
|
||||
void removeOwnerFromDir(Entry cache_entry, Address addr, MachineID sender) {
|
||||
void removeOwnerFromDir(Entry cache_entry, Addr addr, MachineID sender) {
|
||||
if (is_valid(cache_entry)) {
|
||||
assert (localDirectory.isTagPresent(addr) == false);
|
||||
cache_entry.OwnerValid := false;
|
||||
|
|
@ -377,7 +377,7 @@ machine(L2Cache, "Token protocol")
|
|||
}
|
||||
}
|
||||
|
||||
bool isLocalSharer(Entry cache_entry, Address addr, MachineID shar_id) {
|
||||
bool isLocalSharer(Entry cache_entry, Addr addr, MachineID shar_id) {
|
||||
if (is_valid(cache_entry)) {
|
||||
assert (localDirectory.isTagPresent(addr) == false);
|
||||
return cache_entry.Sharers.isElement(shar_id);
|
||||
|
|
@ -388,7 +388,7 @@ machine(L2Cache, "Token protocol")
|
|||
}
|
||||
}
|
||||
|
||||
NetDest getLocalSharers(Entry cache_entry, Address addr) {
|
||||
NetDest getLocalSharers(Entry cache_entry, Addr addr) {
|
||||
if (is_valid(cache_entry)) {
|
||||
assert (localDirectory.isTagPresent(addr) == false);
|
||||
return cache_entry.Sharers;
|
||||
|
|
@ -399,7 +399,7 @@ machine(L2Cache, "Token protocol")
|
|||
}
|
||||
}
|
||||
|
||||
MachineID getLocalOwner(Entry cache_entry, Address addr) {
|
||||
MachineID getLocalOwner(Entry cache_entry, Addr addr) {
|
||||
if (is_valid(cache_entry)) {
|
||||
assert (localDirectory.isTagPresent(addr) == false);
|
||||
return cache_entry.Owner;
|
||||
|
|
@ -410,7 +410,7 @@ machine(L2Cache, "Token protocol")
|
|||
}
|
||||
}
|
||||
|
||||
int countLocalSharers(Entry cache_entry, Address addr) {
|
||||
int countLocalSharers(Entry cache_entry, Addr addr) {
|
||||
if (is_valid(cache_entry)) {
|
||||
assert (localDirectory.isTagPresent(addr) == false);
|
||||
return cache_entry.Sharers.count();
|
||||
|
|
@ -421,7 +421,7 @@ machine(L2Cache, "Token protocol")
|
|||
}
|
||||
}
|
||||
|
||||
bool isLocalOwnerValid(Entry cache_entry, Address addr) {
|
||||
bool isLocalOwnerValid(Entry cache_entry, Addr addr) {
|
||||
if (is_valid(cache_entry)) {
|
||||
assert (localDirectory.isTagPresent(addr) == false);
|
||||
return cache_entry.OwnerValid;
|
||||
|
|
@ -432,7 +432,7 @@ machine(L2Cache, "Token protocol")
|
|||
}
|
||||
}
|
||||
|
||||
int countLocalSharersExceptRequestor(Entry cache_entry, Address addr, MachineID requestor) {
|
||||
int countLocalSharersExceptRequestor(Entry cache_entry, Addr addr, MachineID requestor) {
|
||||
if (is_valid(cache_entry)) {
|
||||
assert (localDirectory.isTagPresent(addr) == false);
|
||||
if (cache_entry.Sharers.isElement(requestor)) {
|
||||
|
|
@ -453,7 +453,7 @@ machine(L2Cache, "Token protocol")
|
|||
}
|
||||
}
|
||||
|
||||
State getState(TBE tbe, Entry cache_entry, Address addr) {
|
||||
State getState(TBE tbe, Entry cache_entry, Addr addr) {
|
||||
|
||||
if (is_valid(tbe)) {
|
||||
return tbe.TBEState;
|
||||
|
|
@ -471,7 +471,7 @@ machine(L2Cache, "Token protocol")
|
|||
return CoherenceRequestType_to_string(type);
|
||||
}
|
||||
|
||||
void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
|
||||
void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
|
||||
assert((localDirectory.isTagPresent(addr) && L2cache.isTagPresent(addr)) == false);
|
||||
|
||||
if (is_valid(tbe)) {
|
||||
|
|
@ -518,7 +518,7 @@ machine(L2Cache, "Token protocol")
|
|||
}
|
||||
}
|
||||
|
||||
AccessPermission getAccessPermission(Address addr) {
|
||||
AccessPermission getAccessPermission(Addr addr) {
|
||||
TBE tbe := TBEs[addr];
|
||||
if(is_valid(tbe)) {
|
||||
DPRINTF(RubySlicc, "%s\n", L2Cache_State_to_permission(tbe.TBEState));
|
||||
|
|
@ -535,13 +535,13 @@ machine(L2Cache, "Token protocol")
|
|||
return AccessPermission:NotPresent;
|
||||
}
|
||||
|
||||
void setAccessPermission(Entry cache_entry, Address addr, State state) {
|
||||
void setAccessPermission(Entry cache_entry, Addr addr, State state) {
|
||||
if (is_valid(cache_entry)) {
|
||||
cache_entry.changePermission(L2Cache_State_to_permission(state));
|
||||
}
|
||||
}
|
||||
|
||||
void functionalRead(Address addr, Packet *pkt) {
|
||||
void functionalRead(Addr addr, Packet *pkt) {
|
||||
TBE tbe := TBEs[addr];
|
||||
if(is_valid(tbe)) {
|
||||
testAndRead(addr, tbe.DataBlk, pkt);
|
||||
|
|
@ -550,7 +550,7 @@ machine(L2Cache, "Token protocol")
|
|||
}
|
||||
}
|
||||
|
||||
int functionalWrite(Address addr, Packet *pkt) {
|
||||
int functionalWrite(Addr addr, Packet *pkt) {
|
||||
int num_functional_writes := 0;
|
||||
|
||||
TBE tbe := TBEs[addr];
|
||||
|
|
|
|||
|
|
@ -102,17 +102,17 @@ machine(Directory, "Directory protocol")
|
|||
}
|
||||
|
||||
structure(TBE, desc="...") {
|
||||
Address PhysicalAddress, desc="Physical address for this entry";
|
||||
Addr PhysicalAddress, desc="Physical address for this entry";
|
||||
int Len, desc="Length of request";
|
||||
DataBlock DataBlk, desc="DataBlk";
|
||||
MachineID Requestor, desc="original requestor";
|
||||
}
|
||||
|
||||
structure(TBETable, external = "yes") {
|
||||
TBE lookup(Address);
|
||||
void allocate(Address);
|
||||
void deallocate(Address);
|
||||
bool isPresent(Address);
|
||||
TBE lookup(Addr);
|
||||
void allocate(Addr);
|
||||
void deallocate(Addr);
|
||||
bool isPresent(Addr);
|
||||
}
|
||||
|
||||
// ** OBJECTS **
|
||||
|
|
@ -121,7 +121,7 @@ machine(Directory, "Directory protocol")
|
|||
void set_tbe(TBE b);
|
||||
void unset_tbe();
|
||||
|
||||
Entry getDirectoryEntry(Address addr), return_by_pointer="yes" {
|
||||
Entry getDirectoryEntry(Addr addr), return_by_pointer="yes" {
|
||||
Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
|
||||
|
||||
if (is_valid(dir_entry)) {
|
||||
|
|
@ -133,11 +133,11 @@ machine(Directory, "Directory protocol")
|
|||
return dir_entry;
|
||||
}
|
||||
|
||||
State getState(TBE tbe, Address addr) {
|
||||
State getState(TBE tbe, Addr addr) {
|
||||
return getDirectoryEntry(addr).DirectoryState;
|
||||
}
|
||||
|
||||
void setState(TBE tbe, Address addr, State state) {
|
||||
void setState(TBE tbe, Addr addr, State state) {
|
||||
if (directory.isPresent(addr)) {
|
||||
|
||||
if (state == State:I) {
|
||||
|
|
@ -174,7 +174,7 @@ machine(Directory, "Directory protocol")
|
|||
}
|
||||
}
|
||||
|
||||
AccessPermission getAccessPermission(Address addr) {
|
||||
AccessPermission getAccessPermission(Addr addr) {
|
||||
if (directory.isPresent(addr)) {
|
||||
DPRINTF(RubySlicc, "%s\n", Directory_State_to_permission(getDirectoryEntry(addr).DirectoryState));
|
||||
return Directory_State_to_permission(getDirectoryEntry(addr).DirectoryState);
|
||||
|
|
@ -184,17 +184,17 @@ machine(Directory, "Directory protocol")
|
|||
return AccessPermission:NotPresent;
|
||||
}
|
||||
|
||||
void setAccessPermission(Address addr, State state) {
|
||||
void setAccessPermission(Addr addr, State state) {
|
||||
if (directory.isPresent(addr)) {
|
||||
getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state));
|
||||
}
|
||||
}
|
||||
|
||||
void functionalRead(Address addr, Packet *pkt) {
|
||||
void functionalRead(Addr addr, Packet *pkt) {
|
||||
functionalMemoryRead(pkt);
|
||||
}
|
||||
|
||||
int functionalWrite(Address addr, Packet *pkt) {
|
||||
int functionalWrite(Addr addr, Packet *pkt) {
|
||||
int num_functional_writes := 0;
|
||||
num_functional_writes := num_functional_writes + functionalMemoryWrite(pkt);
|
||||
return num_functional_writes;
|
||||
|
|
@ -202,7 +202,7 @@ machine(Directory, "Directory protocol")
|
|||
|
||||
// if no sharers, then directory can be considered
|
||||
// both a sharer and exclusive w.r.t. coherence checking
|
||||
bool isBlockShared(Address addr) {
|
||||
bool isBlockShared(Addr addr) {
|
||||
if (directory.isPresent(addr)) {
|
||||
if (getDirectoryEntry(addr).DirectoryState == State:I) {
|
||||
return true;
|
||||
|
|
@ -211,7 +211,7 @@ machine(Directory, "Directory protocol")
|
|||
return false;
|
||||
}
|
||||
|
||||
bool isBlockExclusive(Address addr) {
|
||||
bool isBlockExclusive(Addr addr) {
|
||||
if (directory.isPresent(addr)) {
|
||||
if (getDirectoryEntry(addr).DirectoryState == State:I) {
|
||||
return true;
|
||||
|
|
@ -487,7 +487,7 @@ machine(Directory, "Directory protocol")
|
|||
desc="Queue off-chip writeback request") {
|
||||
peek(unblockNetwork_in, ResponseMsg) {
|
||||
DataBlock DataBlk := in_msg.DataBlk;
|
||||
DataBlk.copyPartial(tbe.DataBlk, addressOffset(tbe.PhysicalAddress),
|
||||
DataBlk.copyPartial(tbe.DataBlk, getOffset(tbe.PhysicalAddress),
|
||||
tbe.Len);
|
||||
queueMemoryWrite(tbe.Requestor, address, to_memory_controller_latency,
|
||||
DataBlk);
|
||||
|
|
|
|||
|
|
@ -57,16 +57,16 @@ machine(DMA, "DMA Controller")
|
|||
}
|
||||
|
||||
structure(TBE, desc="...") {
|
||||
Address address, desc="Physical address";
|
||||
Addr address, desc="Physical address";
|
||||
int NumAcks, default="0", desc="Number of Acks pending";
|
||||
DataBlock DataBlk, desc="Data";
|
||||
}
|
||||
|
||||
structure(TBETable, external = "yes") {
|
||||
TBE lookup(Address);
|
||||
void allocate(Address);
|
||||
void deallocate(Address);
|
||||
bool isPresent(Address);
|
||||
TBE lookup(Addr);
|
||||
void allocate(Addr);
|
||||
void deallocate(Addr);
|
||||
bool isPresent(Addr);
|
||||
}
|
||||
|
||||
MessageBuffer mandatoryQueue;
|
||||
|
|
@ -77,25 +77,25 @@ machine(DMA, "DMA Controller")
|
|||
void set_tbe(TBE b);
|
||||
void unset_tbe();
|
||||
|
||||
State getState(TBE tbe, Address addr) {
|
||||
State getState(TBE tbe, Addr addr) {
|
||||
return cur_state;
|
||||
}
|
||||
void setState(TBE tbe, Address addr, State state) {
|
||||
void setState(TBE tbe, Addr addr, State state) {
|
||||
cur_state := state;
|
||||
}
|
||||
|
||||
AccessPermission getAccessPermission(Address addr) {
|
||||
AccessPermission getAccessPermission(Addr addr) {
|
||||
return AccessPermission:NotPresent;
|
||||
}
|
||||
|
||||
void setAccessPermission(Address addr, State state) {
|
||||
void setAccessPermission(Addr addr, State state) {
|
||||
}
|
||||
|
||||
void functionalRead(Address addr, Packet *pkt) {
|
||||
void functionalRead(Addr addr, Packet *pkt) {
|
||||
error("DMA does not support functional read.");
|
||||
}
|
||||
|
||||
int functionalWrite(Address addr, Packet *pkt) {
|
||||
int functionalWrite(Addr addr, Packet *pkt) {
|
||||
error("DMA does not support functional write.");
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -69,7 +69,7 @@ enumeration(TriggerType, desc="...") {
|
|||
|
||||
// TriggerMsg
|
||||
structure(TriggerMsg, desc="...", interface="Message") {
|
||||
Address addr, desc="Physical address for this request";
|
||||
Addr addr, desc="Physical address for this request";
|
||||
TriggerType Type, desc="Type of trigger";
|
||||
|
||||
bool functionalRead(Packet *pkt) {
|
||||
|
|
@ -85,7 +85,7 @@ structure(TriggerMsg, desc="...", interface="Message") {
|
|||
|
||||
// RequestMsg (and also forwarded requests)
|
||||
structure(RequestMsg, desc="...", interface="Message") {
|
||||
Address addr, desc="Physical address for this request";
|
||||
Addr addr, desc="Physical address for this request";
|
||||
int Len, desc="Length of Request";
|
||||
CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)";
|
||||
MachineID Requestor, desc="Node who initiated the request";
|
||||
|
|
@ -114,7 +114,7 @@ structure(RequestMsg, desc="...", interface="Message") {
|
|||
|
||||
// ResponseMsg (and also unblock requests)
|
||||
structure(ResponseMsg, desc="...", interface="Message") {
|
||||
Address addr, desc="Physical address for this request";
|
||||
Addr addr, desc="Physical address for this request";
|
||||
CoherenceResponseType Type, desc="Type of response (Ack, Data, etc)";
|
||||
MachineID Sender, desc="Node who sent the data";
|
||||
MachineType SenderMachine, desc="type of component sending msg";
|
||||
|
|
|
|||
|
|
@ -150,10 +150,10 @@ machine(L1Cache, "Token protocol")
|
|||
|
||||
// TBE fields
|
||||
structure(TBE, desc="...") {
|
||||
Address addr, desc="Physical address for this TBE";
|
||||
Addr addr, desc="Physical address for this TBE";
|
||||
State TBEState, desc="Transient state";
|
||||
int IssueCount, default="0", desc="The number of times we've issued a request for this line.";
|
||||
Address PC, desc="Program counter of request";
|
||||
Addr PC, desc="Program counter of request";
|
||||
|
||||
bool WentPersistent, default="false", desc="Request went persistent";
|
||||
bool ExternalResponse, default="false", desc="Response came from an external controller";
|
||||
|
|
@ -166,22 +166,22 @@ machine(L1Cache, "Token protocol")
|
|||
}
|
||||
|
||||
structure(TBETable, external="yes") {
|
||||
TBE lookup(Address);
|
||||
void allocate(Address);
|
||||
void deallocate(Address);
|
||||
bool isPresent(Address);
|
||||
TBE lookup(Addr);
|
||||
void allocate(Addr);
|
||||
void deallocate(Addr);
|
||||
bool isPresent(Addr);
|
||||
}
|
||||
|
||||
structure(PersistentTable, external="yes") {
|
||||
void persistentRequestLock(Address, MachineID, AccessType);
|
||||
void persistentRequestUnlock(Address, MachineID);
|
||||
bool okToIssueStarving(Address, MachineID);
|
||||
MachineID findSmallest(Address);
|
||||
AccessType typeOfSmallest(Address);
|
||||
void markEntries(Address);
|
||||
bool isLocked(Address);
|
||||
int countStarvingForAddress(Address);
|
||||
int countReadStarvingForAddress(Address);
|
||||
void persistentRequestLock(Addr, MachineID, AccessType);
|
||||
void persistentRequestUnlock(Addr, MachineID);
|
||||
bool okToIssueStarving(Addr, MachineID);
|
||||
MachineID findSmallest(Addr);
|
||||
AccessType typeOfSmallest(Addr);
|
||||
void markEntries(Addr);
|
||||
bool isLocked(Addr);
|
||||
int countStarvingForAddress(Addr);
|
||||
int countReadStarvingForAddress(Addr);
|
||||
}
|
||||
|
||||
void set_cache_entry(AbstractCacheEntry b);
|
||||
|
|
@ -189,7 +189,7 @@ machine(L1Cache, "Token protocol")
|
|||
void set_tbe(TBE b);
|
||||
void unset_tbe();
|
||||
void wakeUpAllBuffers();
|
||||
void wakeUpBuffers(Address a);
|
||||
void wakeUpBuffers(Addr a);
|
||||
Cycles curCycle();
|
||||
|
||||
TBETable L1_TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
|
||||
|
|
@ -230,7 +230,7 @@ machine(L1Cache, "Token protocol")
|
|||
averageLatencyCounter := averageLatencyCounter - averageLatencyEstimate() + latency;
|
||||
}
|
||||
|
||||
Entry getCacheEntry(Address addr), return_by_pointer="yes" {
|
||||
Entry getCacheEntry(Addr addr), return_by_pointer="yes" {
|
||||
Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache.lookup(addr));
|
||||
if(is_valid(L1Dcache_entry)) {
|
||||
return L1Dcache_entry;
|
||||
|
|
@ -240,23 +240,23 @@ machine(L1Cache, "Token protocol")
|
|||
return L1Icache_entry;
|
||||
}
|
||||
|
||||
void functionalRead(Address addr, Packet *pkt) {
|
||||
void functionalRead(Addr addr, Packet *pkt) {
|
||||
testAndRead(addr, getCacheEntry(addr).DataBlk, pkt);
|
||||
}
|
||||
|
||||
int functionalWrite(Address addr, Packet *pkt) {
|
||||
int functionalWrite(Addr addr, Packet *pkt) {
|
||||
int num_functional_writes := 0;
|
||||
num_functional_writes := num_functional_writes +
|
||||
testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt);
|
||||
return num_functional_writes;
|
||||
}
|
||||
|
||||
Entry getL1DCacheEntry(Address addr), return_by_pointer="yes" {
|
||||
Entry getL1DCacheEntry(Addr addr), return_by_pointer="yes" {
|
||||
Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache.lookup(addr));
|
||||
return L1Dcache_entry;
|
||||
}
|
||||
|
||||
Entry getL1ICacheEntry(Address addr), return_by_pointer="yes" {
|
||||
Entry getL1ICacheEntry(Addr addr), return_by_pointer="yes" {
|
||||
Entry L1Icache_entry := static_cast(Entry, "pointer", L1Icache.lookup(addr));
|
||||
return L1Icache_entry;
|
||||
}
|
||||
|
|
@ -268,7 +268,7 @@ machine(L1Cache, "Token protocol")
|
|||
return 0;
|
||||
}
|
||||
|
||||
State getState(TBE tbe, Entry cache_entry, Address addr) {
|
||||
State getState(TBE tbe, Entry cache_entry, Addr addr) {
|
||||
|
||||
if (is_valid(tbe)) {
|
||||
return tbe.TBEState;
|
||||
|
|
@ -284,7 +284,7 @@ machine(L1Cache, "Token protocol")
|
|||
}
|
||||
}
|
||||
|
||||
void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
|
||||
void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
|
||||
assert((L1Dcache.isTagPresent(addr) && L1Icache.isTagPresent(addr)) == false);
|
||||
|
||||
if (is_valid(tbe)) {
|
||||
|
|
@ -365,7 +365,7 @@ machine(L1Cache, "Token protocol")
|
|||
}
|
||||
}
|
||||
|
||||
AccessPermission getAccessPermission(Address addr) {
|
||||
AccessPermission getAccessPermission(Addr addr) {
|
||||
TBE tbe := L1_TBEs[addr];
|
||||
if(is_valid(tbe)) {
|
||||
return L1Cache_State_to_permission(tbe.TBEState);
|
||||
|
|
@ -379,7 +379,7 @@ machine(L1Cache, "Token protocol")
|
|||
return AccessPermission:NotPresent;
|
||||
}
|
||||
|
||||
void setAccessPermission(Entry cache_entry, Address addr, State state) {
|
||||
void setAccessPermission(Entry cache_entry, Addr addr, State state) {
|
||||
if (is_valid(cache_entry)) {
|
||||
cache_entry.changePermission(L1Cache_State_to_permission(state));
|
||||
}
|
||||
|
|
@ -414,7 +414,7 @@ machine(L1Cache, "Token protocol")
|
|||
}
|
||||
|
||||
// NOTE: direct local hits should not call this function
|
||||
bool isExternalHit(Address addr, MachineID sender) {
|
||||
bool isExternalHit(Addr addr, MachineID sender) {
|
||||
if (machineIDToMachineType(sender) == MachineType:L1Cache) {
|
||||
return true;
|
||||
} else if (machineIDToMachineType(sender) == MachineType:L2Cache) {
|
||||
|
|
@ -430,11 +430,11 @@ machine(L1Cache, "Token protocol")
|
|||
return true;
|
||||
}
|
||||
|
||||
bool okToIssueStarving(Address addr, MachineID machineID) {
|
||||
bool okToIssueStarving(Addr addr, MachineID machineID) {
|
||||
return persistentTable.okToIssueStarving(addr, machineID);
|
||||
}
|
||||
|
||||
void markPersistentEntries(Address addr) {
|
||||
void markPersistentEntries(Addr addr) {
|
||||
persistentTable.markEntries(addr);
|
||||
}
|
||||
|
||||
|
|
@ -457,7 +457,7 @@ machine(L1Cache, "Token protocol")
|
|||
// ** IN_PORTS **
|
||||
|
||||
// Use Timer
|
||||
in_port(useTimerTable_in, Address, useTimerTable, rank=5) {
|
||||
in_port(useTimerTable_in, Addr, useTimerTable, rank=5) {
|
||||
if (useTimerTable_in.isReady()) {
|
||||
TBE tbe := L1_TBEs[useTimerTable.readyAddress()];
|
||||
|
||||
|
|
@ -483,7 +483,7 @@ machine(L1Cache, "Token protocol")
|
|||
}
|
||||
|
||||
// Reissue Timer
|
||||
in_port(reissueTimerTable_in, Address, reissueTimerTable, rank=4) {
|
||||
in_port(reissueTimerTable_in, Addr, reissueTimerTable, rank=4) {
|
||||
if (reissueTimerTable_in.isReady()) {
|
||||
trigger(Event:Request_Timeout, reissueTimerTable.readyAddress(),
|
||||
getCacheEntry(reissueTimerTable.readyAddress()),
|
||||
|
|
|
|||
|
|
@ -129,21 +129,21 @@ machine(L2Cache, "Token protocol")
|
|||
}
|
||||
|
||||
structure(PerfectCacheMemory, external="yes") {
|
||||
void allocate(Address);
|
||||
void deallocate(Address);
|
||||
DirEntry lookup(Address);
|
||||
bool isTagPresent(Address);
|
||||
void allocate(Addr);
|
||||
void deallocate(Addr);
|
||||
DirEntry lookup(Addr);
|
||||
bool isTagPresent(Addr);
|
||||
}
|
||||
|
||||
structure(PersistentTable, external="yes") {
|
||||
void persistentRequestLock(Address, MachineID, AccessType);
|
||||
void persistentRequestUnlock(Address, MachineID);
|
||||
MachineID findSmallest(Address);
|
||||
AccessType typeOfSmallest(Address);
|
||||
void markEntries(Address);
|
||||
bool isLocked(Address);
|
||||
int countStarvingForAddress(Address);
|
||||
int countReadStarvingForAddress(Address);
|
||||
void persistentRequestLock(Addr, MachineID, AccessType);
|
||||
void persistentRequestUnlock(Addr, MachineID);
|
||||
MachineID findSmallest(Addr);
|
||||
AccessType typeOfSmallest(Addr);
|
||||
void markEntries(Addr);
|
||||
bool isLocked(Addr);
|
||||
int countStarvingForAddress(Addr);
|
||||
int countReadStarvingForAddress(Addr);
|
||||
}
|
||||
|
||||
PersistentTable persistentTable;
|
||||
|
|
@ -152,20 +152,20 @@ machine(L2Cache, "Token protocol")
|
|||
void set_cache_entry(AbstractCacheEntry b);
|
||||
void unset_cache_entry();
|
||||
|
||||
Entry getCacheEntry(Address address), return_by_pointer="yes" {
|
||||
Entry getCacheEntry(Addr address), return_by_pointer="yes" {
|
||||
Entry cache_entry := static_cast(Entry, "pointer", L2cache.lookup(address));
|
||||
return cache_entry;
|
||||
}
|
||||
|
||||
DirEntry getDirEntry(Address address), return_by_pointer="yes" {
|
||||
DirEntry getDirEntry(Addr address), return_by_pointer="yes" {
|
||||
return localDirectory.lookup(address);
|
||||
}
|
||||
|
||||
void functionalRead(Address addr, Packet *pkt) {
|
||||
void functionalRead(Addr addr, Packet *pkt) {
|
||||
testAndRead(addr, getCacheEntry(addr).DataBlk, pkt);
|
||||
}
|
||||
|
||||
int functionalWrite(Address addr, Packet *pkt) {
|
||||
int functionalWrite(Addr addr, Packet *pkt) {
|
||||
int num_functional_writes := 0;
|
||||
num_functional_writes := num_functional_writes +
|
||||
testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt);
|
||||
|
|
@ -180,7 +180,7 @@ machine(L2Cache, "Token protocol")
|
|||
}
|
||||
}
|
||||
|
||||
State getState(Entry cache_entry, Address addr) {
|
||||
State getState(Entry cache_entry, Addr addr) {
|
||||
if (is_valid(cache_entry)) {
|
||||
return cache_entry.CacheState;
|
||||
} else if (persistentTable.isLocked(addr)) {
|
||||
|
|
@ -190,7 +190,7 @@ machine(L2Cache, "Token protocol")
|
|||
}
|
||||
}
|
||||
|
||||
void setState(Entry cache_entry, Address addr, State state) {
|
||||
void setState(Entry cache_entry, Addr addr, State state) {
|
||||
|
||||
if (is_valid(cache_entry)) {
|
||||
// Make sure the token count is in range
|
||||
|
|
@ -227,7 +227,7 @@ machine(L2Cache, "Token protocol")
|
|||
}
|
||||
}
|
||||
|
||||
AccessPermission getAccessPermission(Address addr) {
|
||||
AccessPermission getAccessPermission(Addr addr) {
|
||||
Entry cache_entry := getCacheEntry(addr);
|
||||
if(is_valid(cache_entry)) {
|
||||
return L2Cache_State_to_permission(cache_entry.CacheState);
|
||||
|
|
@ -236,13 +236,13 @@ machine(L2Cache, "Token protocol")
|
|||
return AccessPermission:NotPresent;
|
||||
}
|
||||
|
||||
void setAccessPermission(Entry cache_entry, Address addr, State state) {
|
||||
void setAccessPermission(Entry cache_entry, Addr addr, State state) {
|
||||
if (is_valid(cache_entry)) {
|
||||
cache_entry.changePermission(L2Cache_State_to_permission(state));
|
||||
}
|
||||
}
|
||||
|
||||
void removeSharer(Address addr, NodeID id) {
|
||||
void removeSharer(Addr addr, NodeID id) {
|
||||
|
||||
if (localDirectory.isTagPresent(addr)) {
|
||||
DirEntry dir_entry := getDirEntry(addr);
|
||||
|
|
@ -253,7 +253,7 @@ machine(L2Cache, "Token protocol")
|
|||
}
|
||||
}
|
||||
|
||||
bool sharersExist(Address addr) {
|
||||
bool sharersExist(Addr addr) {
|
||||
if (localDirectory.isTagPresent(addr)) {
|
||||
DirEntry dir_entry := getDirEntry(addr);
|
||||
if (dir_entry.Sharers.count() > 0) {
|
||||
|
|
@ -268,7 +268,7 @@ machine(L2Cache, "Token protocol")
|
|||
}
|
||||
}
|
||||
|
||||
bool exclusiveExists(Address addr) {
|
||||
bool exclusiveExists(Addr addr) {
|
||||
if (localDirectory.isTagPresent(addr)) {
|
||||
DirEntry dir_entry := getDirEntry(addr);
|
||||
if (dir_entry.exclusive) {
|
||||
|
|
@ -284,12 +284,12 @@ machine(L2Cache, "Token protocol")
|
|||
}
|
||||
|
||||
// assumes that caller will check to make sure tag is present
|
||||
Set getSharers(Address addr) {
|
||||
Set getSharers(Addr addr) {
|
||||
DirEntry dir_entry := getDirEntry(addr);
|
||||
return dir_entry.Sharers;
|
||||
}
|
||||
|
||||
void setNewWriter(Address addr, NodeID id) {
|
||||
void setNewWriter(Addr addr, NodeID id) {
|
||||
if (localDirectory.isTagPresent(addr) == false) {
|
||||
localDirectory.allocate(addr);
|
||||
}
|
||||
|
|
@ -299,7 +299,7 @@ machine(L2Cache, "Token protocol")
|
|||
dir_entry.exclusive := true;
|
||||
}
|
||||
|
||||
void addNewSharer(Address addr, NodeID id) {
|
||||
void addNewSharer(Addr addr, NodeID id) {
|
||||
if (localDirectory.isTagPresent(addr) == false) {
|
||||
localDirectory.allocate(addr);
|
||||
}
|
||||
|
|
@ -308,7 +308,7 @@ machine(L2Cache, "Token protocol")
|
|||
// dir_entry.exclusive := false;
|
||||
}
|
||||
|
||||
void clearExclusiveBitIfExists(Address addr) {
|
||||
void clearExclusiveBitIfExists(Addr addr) {
|
||||
if (localDirectory.isTagPresent(addr)) {
|
||||
DirEntry dir_entry := getDirEntry(addr);
|
||||
dir_entry.exclusive := false;
|
||||
|
|
|
|||
|
|
@ -133,20 +133,20 @@ machine(Directory, "Token protocol")
|
|||
}
|
||||
|
||||
structure(PersistentTable, external="yes") {
|
||||
void persistentRequestLock(Address, MachineID, AccessType);
|
||||
void persistentRequestUnlock(Address, MachineID);
|
||||
bool okToIssueStarving(Address, MachineID);
|
||||
MachineID findSmallest(Address);
|
||||
AccessType typeOfSmallest(Address);
|
||||
void markEntries(Address);
|
||||
bool isLocked(Address);
|
||||
int countStarvingForAddress(Address);
|
||||
int countReadStarvingForAddress(Address);
|
||||
void persistentRequestLock(Addr, MachineID, AccessType);
|
||||
void persistentRequestUnlock(Addr, MachineID);
|
||||
bool okToIssueStarving(Addr, MachineID);
|
||||
MachineID findSmallest(Addr);
|
||||
AccessType typeOfSmallest(Addr);
|
||||
void markEntries(Addr);
|
||||
bool isLocked(Addr);
|
||||
int countStarvingForAddress(Addr);
|
||||
int countReadStarvingForAddress(Addr);
|
||||
}
|
||||
|
||||
// TBE entries for DMA requests
|
||||
structure(TBE, desc="TBE entries for outstanding DMA requests") {
|
||||
Address PhysicalAddress, desc="physical address";
|
||||
Addr PhysicalAddress, desc="physical address";
|
||||
State TBEState, desc="Transient State";
|
||||
DataBlock DataBlk, desc="Current view of the associated address range";
|
||||
int Len, desc="...";
|
||||
|
|
@ -155,10 +155,10 @@ machine(Directory, "Token protocol")
|
|||
}
|
||||
|
||||
structure(TBETable, external="yes") {
|
||||
TBE lookup(Address);
|
||||
void allocate(Address);
|
||||
void deallocate(Address);
|
||||
bool isPresent(Address);
|
||||
TBE lookup(Addr);
|
||||
void allocate(Addr);
|
||||
void deallocate(Addr);
|
||||
bool isPresent(Addr);
|
||||
}
|
||||
|
||||
// ** OBJECTS **
|
||||
|
|
@ -174,7 +174,7 @@ machine(Directory, "Token protocol")
|
|||
void set_tbe(TBE b);
|
||||
void unset_tbe();
|
||||
|
||||
Entry getDirectoryEntry(Address addr), return_by_pointer="yes" {
|
||||
Entry getDirectoryEntry(Addr addr), return_by_pointer="yes" {
|
||||
Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
|
||||
|
||||
if (is_valid(dir_entry)) {
|
||||
|
|
@ -186,7 +186,7 @@ machine(Directory, "Token protocol")
|
|||
return dir_entry;
|
||||
}
|
||||
|
||||
State getState(TBE tbe, Address addr) {
|
||||
State getState(TBE tbe, Addr addr) {
|
||||
if (is_valid(tbe)) {
|
||||
return tbe.TBEState;
|
||||
} else {
|
||||
|
|
@ -194,7 +194,7 @@ machine(Directory, "Token protocol")
|
|||
}
|
||||
}
|
||||
|
||||
void setState(TBE tbe, Address addr, State state) {
|
||||
void setState(TBE tbe, Addr addr, State state) {
|
||||
if (is_valid(tbe)) {
|
||||
tbe.TBEState := state;
|
||||
}
|
||||
|
|
@ -217,7 +217,7 @@ machine(Directory, "Token protocol")
|
|||
}
|
||||
}
|
||||
|
||||
AccessPermission getAccessPermission(Address addr) {
|
||||
AccessPermission getAccessPermission(Addr addr) {
|
||||
TBE tbe := TBEs[addr];
|
||||
if(is_valid(tbe)) {
|
||||
return Directory_State_to_permission(tbe.TBEState);
|
||||
|
|
@ -232,19 +232,19 @@ machine(Directory, "Token protocol")
|
|||
return AccessPermission:NotPresent;
|
||||
}
|
||||
|
||||
void setAccessPermission(Address addr, State state) {
|
||||
void setAccessPermission(Addr addr, State state) {
|
||||
getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state));
|
||||
}
|
||||
|
||||
bool okToIssueStarving(Address addr, MachineID machinID) {
|
||||
bool okToIssueStarving(Addr addr, MachineID machinID) {
|
||||
return persistentTable.okToIssueStarving(addr, machineID);
|
||||
}
|
||||
|
||||
void markPersistentEntries(Address addr) {
|
||||
void markPersistentEntries(Addr addr) {
|
||||
persistentTable.markEntries(addr);
|
||||
}
|
||||
|
||||
void functionalRead(Address addr, Packet *pkt) {
|
||||
void functionalRead(Addr addr, Packet *pkt) {
|
||||
TBE tbe := TBEs[addr];
|
||||
if(is_valid(tbe)) {
|
||||
testAndRead(addr, tbe.DataBlk, pkt);
|
||||
|
|
@ -253,7 +253,7 @@ machine(Directory, "Token protocol")
|
|||
}
|
||||
}
|
||||
|
||||
int functionalWrite(Address addr, Packet *pkt) {
|
||||
int functionalWrite(Addr addr, Packet *pkt) {
|
||||
int num_functional_writes := 0;
|
||||
|
||||
TBE tbe := TBEs[addr];
|
||||
|
|
@ -292,7 +292,7 @@ machine(Directory, "Token protocol")
|
|||
}
|
||||
|
||||
// Reissue Timer
|
||||
in_port(reissueTimerTable_in, Address, reissueTimerTable) {
|
||||
in_port(reissueTimerTable_in, Addr, reissueTimerTable) {
|
||||
if (reissueTimerTable_in.isReady()) {
|
||||
trigger(Event:Request_Timeout, reissueTimerTable.readyAddress(),
|
||||
TBEs[reissueTimerTable.readyAddress()]);
|
||||
|
|
@ -736,7 +736,7 @@ machine(Directory, "Token protocol")
|
|||
peek(responseNetwork_in, ResponseMsg) {
|
||||
DataBlock DataBlk := tbe.DataBlk;
|
||||
tbe.DataBlk := in_msg.DataBlk;
|
||||
tbe.DataBlk.copyPartial(DataBlk, addressOffset(tbe.PhysicalAddress),
|
||||
tbe.DataBlk.copyPartial(DataBlk, getOffset(tbe.PhysicalAddress),
|
||||
tbe.Len);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -54,25 +54,25 @@ machine(DMA, "DMA Controller")
|
|||
MessageBuffer mandatoryQueue;
|
||||
State cur_state;
|
||||
|
||||
State getState(Address addr) {
|
||||
State getState(Addr addr) {
|
||||
return cur_state;
|
||||
}
|
||||
void setState(Address addr, State state) {
|
||||
void setState(Addr addr, State state) {
|
||||
cur_state := state;
|
||||
}
|
||||
|
||||
AccessPermission getAccessPermission(Address addr) {
|
||||
AccessPermission getAccessPermission(Addr addr) {
|
||||
return AccessPermission:NotPresent;
|
||||
}
|
||||
|
||||
void setAccessPermission(Address addr, State state) {
|
||||
void setAccessPermission(Addr addr, State state) {
|
||||
}
|
||||
|
||||
void functionalRead(Address addr, Packet *pkt) {
|
||||
void functionalRead(Addr addr, Packet *pkt) {
|
||||
error("DMA does not support functional read.");
|
||||
}
|
||||
|
||||
int functionalWrite(Address addr, Packet *pkt) {
|
||||
int functionalWrite(Addr addr, Packet *pkt) {
|
||||
error("DMA does not support functional write.");
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -58,7 +58,7 @@ enumeration(CoherenceResponseType, desc="...") {
|
|||
|
||||
// PersistentMsg
|
||||
structure(PersistentMsg, desc="...", interface="Message") {
|
||||
Address addr, desc="Physical address for this request";
|
||||
Addr addr, desc="Physical address for this request";
|
||||
PersistentRequestType Type, desc="Type of starvation request";
|
||||
MachineID Requestor, desc="Node who initiated the request";
|
||||
NetDest Destination, desc="Destination set";
|
||||
|
|
@ -79,7 +79,7 @@ structure(PersistentMsg, desc="...", interface="Message") {
|
|||
|
||||
// RequestMsg
|
||||
structure(RequestMsg, desc="...", interface="Message") {
|
||||
Address addr, desc="Physical address for this request";
|
||||
Addr addr, desc="Physical address for this request";
|
||||
CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)";
|
||||
MachineID Requestor, desc="Node who initiated the request";
|
||||
NetDest Destination, desc="Multicast destination mask";
|
||||
|
|
@ -102,7 +102,7 @@ structure(RequestMsg, desc="...", interface="Message") {
|
|||
|
||||
// ResponseMsg
|
||||
structure(ResponseMsg, desc="...", interface="Message") {
|
||||
Address addr, desc="Physical address for this request";
|
||||
Addr addr, desc="Physical address for this request";
|
||||
CoherenceResponseType Type, desc="Type of response (Ack, Data, etc)";
|
||||
MachineID Sender, desc="Node who sent the data";
|
||||
NetDest Destination, desc="Node to whom the data is sent";
|
||||
|
|
@ -136,8 +136,8 @@ enumeration(DMAResponseType, desc="...", default="DMAResponseType_NULL") {
|
|||
|
||||
structure(DMARequestMsg, desc="...", interface="Message") {
|
||||
DMARequestType Type, desc="Request type (read/write)";
|
||||
Address PhysicalAddress, desc="Physical address for this request";
|
||||
Address LineAddress, desc="Line address for this request";
|
||||
Addr PhysicalAddress, desc="Physical address for this request";
|
||||
Addr LineAddress, desc="Line address for this request";
|
||||
MachineID Requestor, desc="Node who initiated the request";
|
||||
NetDest Destination, desc="Destination";
|
||||
DataBlock DataBlk, desc="DataBlk attached to this request";
|
||||
|
|
@ -155,8 +155,8 @@ structure(DMARequestMsg, desc="...", interface="Message") {
|
|||
|
||||
structure(DMAResponseMsg, desc="...", interface="Message") {
|
||||
DMAResponseType Type, desc="Response type (DATA/ACK)";
|
||||
Address PhysicalAddress, desc="Physical address for this request";
|
||||
Address LineAddress, desc="Line address for this request";
|
||||
Addr PhysicalAddress, desc="Physical address for this request";
|
||||
Addr LineAddress, desc="Line address for this request";
|
||||
NetDest Destination, desc="Destination";
|
||||
DataBlock DataBlk, desc="DataBlk attached to this request";
|
||||
MessageSizeType MessageSize, desc="size category of the message";
|
||||
|
|
|
|||
|
|
@ -174,10 +174,10 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
|
|||
}
|
||||
|
||||
structure(TBETable, external="yes") {
|
||||
TBE lookup(Address);
|
||||
void allocate(Address);
|
||||
void deallocate(Address);
|
||||
bool isPresent(Address);
|
||||
TBE lookup(Addr);
|
||||
void allocate(Addr);
|
||||
void deallocate(Addr);
|
||||
bool isPresent(Addr);
|
||||
}
|
||||
|
||||
TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
|
||||
|
|
@ -187,10 +187,10 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
|
|||
void set_tbe(TBE b);
|
||||
void unset_tbe();
|
||||
void wakeUpAllBuffers();
|
||||
void wakeUpBuffers(Address a);
|
||||
void wakeUpBuffers(Addr a);
|
||||
Cycles curCycle();
|
||||
|
||||
Entry getCacheEntry(Address address), return_by_pointer="yes" {
|
||||
Entry getCacheEntry(Addr address), return_by_pointer="yes" {
|
||||
Entry L2cache_entry := static_cast(Entry, "pointer", L2cache.lookup(address));
|
||||
if(is_valid(L2cache_entry)) {
|
||||
return L2cache_entry;
|
||||
|
|
@ -205,7 +205,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
|
|||
return L1Icache_entry;
|
||||
}
|
||||
|
||||
void functionalRead(Address addr, Packet *pkt) {
|
||||
void functionalRead(Addr addr, Packet *pkt) {
|
||||
Entry cache_entry := getCacheEntry(addr);
|
||||
if(is_valid(cache_entry)) {
|
||||
testAndRead(addr, cache_entry.DataBlk, pkt);
|
||||
|
|
@ -219,7 +219,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
|
|||
}
|
||||
}
|
||||
|
||||
int functionalWrite(Address addr, Packet *pkt) {
|
||||
int functionalWrite(Addr addr, Packet *pkt) {
|
||||
int num_functional_writes := 0;
|
||||
|
||||
Entry cache_entry := getCacheEntry(addr);
|
||||
|
|
@ -235,22 +235,22 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
|
|||
return num_functional_writes;
|
||||
}
|
||||
|
||||
Entry getL2CacheEntry(Address address), return_by_pointer="yes" {
|
||||
Entry getL2CacheEntry(Addr address), return_by_pointer="yes" {
|
||||
Entry L2cache_entry := static_cast(Entry, "pointer", L2cache.lookup(address));
|
||||
return L2cache_entry;
|
||||
}
|
||||
|
||||
Entry getL1DCacheEntry(Address address), return_by_pointer="yes" {
|
||||
Entry getL1DCacheEntry(Addr address), return_by_pointer="yes" {
|
||||
Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache.lookup(address));
|
||||
return L1Dcache_entry;
|
||||
}
|
||||
|
||||
Entry getL1ICacheEntry(Address address), return_by_pointer="yes" {
|
||||
Entry getL1ICacheEntry(Addr address), return_by_pointer="yes" {
|
||||
Entry L1Icache_entry := static_cast(Entry, "pointer", L1Icache.lookup(address));
|
||||
return L1Icache_entry;
|
||||
}
|
||||
|
||||
State getState(TBE tbe, Entry cache_entry, Address addr) {
|
||||
State getState(TBE tbe, Entry cache_entry, Addr addr) {
|
||||
if(is_valid(tbe)) {
|
||||
return tbe.TBEState;
|
||||
} else if (is_valid(cache_entry)) {
|
||||
|
|
@ -259,7 +259,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
|
|||
return State:I;
|
||||
}
|
||||
|
||||
void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
|
||||
void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
|
||||
assert((L1Dcache.isTagPresent(addr) && L1Icache.isTagPresent(addr)) == false);
|
||||
assert((L1Icache.isTagPresent(addr) && L2cache.isTagPresent(addr)) == false);
|
||||
assert((L1Dcache.isTagPresent(addr) && L2cache.isTagPresent(addr)) == false);
|
||||
|
|
@ -273,7 +273,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
|
|||
}
|
||||
}
|
||||
|
||||
AccessPermission getAccessPermission(Address addr) {
|
||||
AccessPermission getAccessPermission(Addr addr) {
|
||||
TBE tbe := TBEs[addr];
|
||||
if(is_valid(tbe)) {
|
||||
return L1Cache_State_to_permission(tbe.TBEState);
|
||||
|
|
@ -287,7 +287,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
|
|||
return AccessPermission:NotPresent;
|
||||
}
|
||||
|
||||
void setAccessPermission(Entry cache_entry, Address addr, State state) {
|
||||
void setAccessPermission(Entry cache_entry, Addr addr, State state) {
|
||||
if (is_valid(cache_entry)) {
|
||||
cache_entry.changePermission(L1Cache_State_to_permission(state));
|
||||
}
|
||||
|
|
@ -448,7 +448,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
|
|||
if (L2cache.cacheAvail(in_msg.LineAddress)) {
|
||||
trigger(Event:L1_to_L2, in_msg.LineAddress, L1Dcache_entry, tbe);
|
||||
} else {
|
||||
Address l2_victim_addr := L2cache.cacheProbe(in_msg.LineAddress);
|
||||
Addr l2_victim_addr := L2cache.cacheProbe(in_msg.LineAddress);
|
||||
trigger(Event:L2_Replacement,
|
||||
l2_victim_addr,
|
||||
getL2CacheEntry(l2_victim_addr),
|
||||
|
|
@ -471,7 +471,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
|
|||
}
|
||||
} else {
|
||||
// No room in the L1, so we need to make room
|
||||
Address l1i_victim_addr := L1Icache.cacheProbe(in_msg.LineAddress);
|
||||
Addr l1i_victim_addr := L1Icache.cacheProbe(in_msg.LineAddress);
|
||||
if (L2cache.cacheAvail(l1i_victim_addr)) {
|
||||
// The L2 has room, so we move the line from the L1 to the L2
|
||||
trigger(Event:L1_to_L2,
|
||||
|
|
@ -479,7 +479,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
|
|||
getL1ICacheEntry(l1i_victim_addr),
|
||||
TBEs[l1i_victim_addr]);
|
||||
} else {
|
||||
Address l2_victim_addr := L2cache.cacheProbe(l1i_victim_addr);
|
||||
Addr l2_victim_addr := L2cache.cacheProbe(l1i_victim_addr);
|
||||
// The L2 does not have room, so we replace a line from the L2
|
||||
trigger(Event:L2_Replacement,
|
||||
l2_victim_addr,
|
||||
|
|
@ -506,7 +506,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
|
|||
if (L2cache.cacheAvail(in_msg.LineAddress)) {
|
||||
trigger(Event:L1_to_L2, in_msg.LineAddress, L1Icache_entry, tbe);
|
||||
} else {
|
||||
Address l2_victim_addr := L2cache.cacheProbe(in_msg.LineAddress);
|
||||
Addr l2_victim_addr := L2cache.cacheProbe(in_msg.LineAddress);
|
||||
trigger(Event:L2_Replacement,
|
||||
l2_victim_addr,
|
||||
getL2CacheEntry(l2_victim_addr),
|
||||
|
|
@ -528,7 +528,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
|
|||
}
|
||||
} else {
|
||||
// No room in the L1, so we need to make room
|
||||
Address l1d_victim_addr := L1Dcache.cacheProbe(in_msg.LineAddress);
|
||||
Addr l1d_victim_addr := L1Dcache.cacheProbe(in_msg.LineAddress);
|
||||
if (L2cache.cacheAvail(l1d_victim_addr)) {
|
||||
// The L2 has room, so we move the line from the L1 to the L2
|
||||
trigger(Event:L1_to_L2,
|
||||
|
|
@ -536,7 +536,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
|
|||
getL1DCacheEntry(l1d_victim_addr),
|
||||
TBEs[l1d_victim_addr]);
|
||||
} else {
|
||||
Address l2_victim_addr := L2cache.cacheProbe(l1d_victim_addr);
|
||||
Addr l2_victim_addr := L2cache.cacheProbe(l1d_victim_addr);
|
||||
// The L2 does not have room, so we replace a line from the L2
|
||||
trigger(Event:L2_Replacement,
|
||||
l2_victim_addr,
|
||||
|
|
|
|||
|
|
@ -158,7 +158,7 @@ machine(Directory, "AMD Hammer-like protocol")
|
|||
|
||||
// TBE entries for DMA requests
|
||||
structure(TBE, desc="TBE entries for outstanding DMA requests") {
|
||||
Address PhysicalAddress, desc="physical address";
|
||||
Addr PhysicalAddress, desc="physical address";
|
||||
State TBEState, desc="Transient State";
|
||||
CoherenceResponseType ResponseType, desc="The type for the subsequent response message";
|
||||
int Acks, default="0", desc="The number of acks that the waiting response represents";
|
||||
|
|
@ -175,17 +175,17 @@ machine(Directory, "AMD Hammer-like protocol")
|
|||
}
|
||||
|
||||
structure(TBETable, external="yes") {
|
||||
TBE lookup(Address);
|
||||
void allocate(Address);
|
||||
void deallocate(Address);
|
||||
bool isPresent(Address);
|
||||
TBE lookup(Addr);
|
||||
void allocate(Addr);
|
||||
void deallocate(Addr);
|
||||
bool isPresent(Addr);
|
||||
}
|
||||
|
||||
void set_cache_entry(AbstractCacheEntry b);
|
||||
void unset_cache_entry();
|
||||
void set_tbe(TBE a);
|
||||
void unset_tbe();
|
||||
void wakeUpBuffers(Address a);
|
||||
void wakeUpBuffers(Addr a);
|
||||
Cycles curCycle();
|
||||
|
||||
// ** OBJECTS **
|
||||
|
|
@ -194,7 +194,7 @@ machine(Directory, "AMD Hammer-like protocol")
|
|||
|
||||
TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
|
||||
|
||||
Entry getDirectoryEntry(Address addr), return_by_pointer="yes" {
|
||||
Entry getDirectoryEntry(Addr addr), return_by_pointer="yes" {
|
||||
Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
|
||||
|
||||
if (is_valid(dir_entry)) {
|
||||
|
|
@ -206,7 +206,7 @@ machine(Directory, "AMD Hammer-like protocol")
|
|||
return dir_entry;
|
||||
}
|
||||
|
||||
PfEntry getProbeFilterEntry(Address addr), return_by_pointer="yes" {
|
||||
PfEntry getProbeFilterEntry(Addr addr), return_by_pointer="yes" {
|
||||
if (probe_filter_enabled || full_bit_dir_enabled) {
|
||||
PfEntry pfEntry := static_cast(PfEntry, "pointer", probeFilter.lookup(addr));
|
||||
return pfEntry;
|
||||
|
|
@ -214,7 +214,7 @@ machine(Directory, "AMD Hammer-like protocol")
|
|||
return OOD;
|
||||
}
|
||||
|
||||
State getState(TBE tbe, PfEntry pf_entry, Address addr) {
|
||||
State getState(TBE tbe, PfEntry pf_entry, Addr addr) {
|
||||
if (is_valid(tbe)) {
|
||||
return tbe.TBEState;
|
||||
} else {
|
||||
|
|
@ -227,7 +227,7 @@ machine(Directory, "AMD Hammer-like protocol")
|
|||
}
|
||||
}
|
||||
|
||||
void setState(TBE tbe, PfEntry pf_entry, Address addr, State state) {
|
||||
void setState(TBE tbe, PfEntry pf_entry, Addr addr, State state) {
|
||||
if (is_valid(tbe)) {
|
||||
tbe.TBEState := state;
|
||||
}
|
||||
|
|
@ -249,7 +249,7 @@ machine(Directory, "AMD Hammer-like protocol")
|
|||
getDirectoryEntry(addr).DirectoryState := state;
|
||||
}
|
||||
|
||||
AccessPermission getAccessPermission(Address addr) {
|
||||
AccessPermission getAccessPermission(Addr addr) {
|
||||
TBE tbe := TBEs[addr];
|
||||
if(is_valid(tbe)) {
|
||||
return Directory_State_to_permission(tbe.TBEState);
|
||||
|
|
@ -262,11 +262,11 @@ machine(Directory, "AMD Hammer-like protocol")
|
|||
return AccessPermission:NotPresent;
|
||||
}
|
||||
|
||||
void setAccessPermission(PfEntry pf_entry, Address addr, State state) {
|
||||
void setAccessPermission(PfEntry pf_entry, Addr addr, State state) {
|
||||
getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state));
|
||||
}
|
||||
|
||||
void functionalRead(Address addr, Packet *pkt) {
|
||||
void functionalRead(Addr addr, Packet *pkt) {
|
||||
TBE tbe := TBEs[addr];
|
||||
if(is_valid(tbe)) {
|
||||
testAndRead(addr, tbe.DataBlk, pkt);
|
||||
|
|
@ -275,7 +275,7 @@ machine(Directory, "AMD Hammer-like protocol")
|
|||
}
|
||||
}
|
||||
|
||||
int functionalWrite(Address addr, Packet *pkt) {
|
||||
int functionalWrite(Addr addr, Packet *pkt) {
|
||||
int num_functional_writes := 0;
|
||||
|
||||
TBE tbe := TBEs[addr];
|
||||
|
|
|
|||
|
|
@ -52,25 +52,25 @@ machine(DMA, "DMA Controller")
|
|||
MessageBuffer mandatoryQueue;
|
||||
State cur_state;
|
||||
|
||||
State getState(Address addr) {
|
||||
State getState(Addr addr) {
|
||||
return cur_state;
|
||||
}
|
||||
void setState(Address addr, State state) {
|
||||
void setState(Addr addr, State state) {
|
||||
cur_state := state;
|
||||
}
|
||||
|
||||
AccessPermission getAccessPermission(Address addr) {
|
||||
AccessPermission getAccessPermission(Addr addr) {
|
||||
return AccessPermission:NotPresent;
|
||||
}
|
||||
|
||||
void setAccessPermission(Address addr, State state) {
|
||||
void setAccessPermission(Addr addr, State state) {
|
||||
}
|
||||
|
||||
void functionalRead(Address addr, Packet *pkt) {
|
||||
void functionalRead(Addr addr, Packet *pkt) {
|
||||
error("DMA does not support functional read.");
|
||||
}
|
||||
|
||||
int functionalWrite(Address addr, Packet *pkt) {
|
||||
int functionalWrite(Addr addr, Packet *pkt) {
|
||||
error("DMA does not support functional write.");
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -71,7 +71,7 @@ enumeration(TriggerType, desc="...") {
|
|||
|
||||
// TriggerMsg
|
||||
structure(TriggerMsg, desc="...", interface="Message") {
|
||||
Address addr, desc="Physical address for this request";
|
||||
Addr addr, desc="Physical address for this request";
|
||||
TriggerType Type, desc="Type of trigger";
|
||||
|
||||
bool functionalRead(Packet *pkt) {
|
||||
|
|
@ -87,7 +87,7 @@ structure(TriggerMsg, desc="...", interface="Message") {
|
|||
|
||||
// RequestMsg (and also forwarded requests)
|
||||
structure(RequestMsg, desc="...", interface="Message") {
|
||||
Address addr, desc="Physical address for this request";
|
||||
Addr addr, desc="Physical address for this request";
|
||||
CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)";
|
||||
MachineID Requestor, desc="Node who initiated the request";
|
||||
NetDest MergedRequestors, desc="Merge set of read requestors";
|
||||
|
|
@ -114,7 +114,7 @@ structure(RequestMsg, desc="...", interface="Message") {
|
|||
|
||||
// ResponseMsg (and also unblock requests)
|
||||
structure(ResponseMsg, desc="...", interface="Message") {
|
||||
Address addr, desc="Physical address for this request";
|
||||
Addr addr, desc="Physical address for this request";
|
||||
CoherenceResponseType Type, desc="Type of response (Ack, Data, etc)";
|
||||
MachineID Sender, desc="Node who sent the data";
|
||||
MachineID CurOwner, desc="current owner of the block, used for UnblockS responses";
|
||||
|
|
@ -166,8 +166,8 @@ enumeration(DMAResponseType, desc="...", default="DMAResponseType_NULL") {
|
|||
|
||||
structure(DMARequestMsg, desc="...", interface="Message") {
|
||||
DMARequestType Type, desc="Request type (read/write)";
|
||||
Address PhysicalAddress, desc="Physical address for this request";
|
||||
Address LineAddress, desc="Line address for this request";
|
||||
Addr PhysicalAddress, desc="Physical address for this request";
|
||||
Addr LineAddress, desc="Line address for this request";
|
||||
MachineID Requestor, desc="Node who initiated the request";
|
||||
NetDest Destination, desc="Destination";
|
||||
DataBlock DataBlk, desc="DataBlk attached to this request";
|
||||
|
|
@ -185,8 +185,8 @@ structure(DMARequestMsg, desc="...", interface="Message") {
|
|||
|
||||
structure(DMAResponseMsg, desc="...", interface="Message") {
|
||||
DMAResponseType Type, desc="Response type (DATA/ACK)";
|
||||
Address PhysicalAddress, desc="Physical address for this request";
|
||||
Address LineAddress, desc="Line address for this request";
|
||||
Addr PhysicalAddress, desc="Physical address for this request";
|
||||
Addr LineAddress, desc="Line address for this request";
|
||||
NetDest Destination, desc="Destination";
|
||||
DataBlock DataBlk, desc="DataBlk attached to this request";
|
||||
MessageSizeType MessageSize, desc="size category of the message";
|
||||
|
|
|
|||
|
|
@ -95,30 +95,30 @@ machine(L1Cache, "Network_test L1 Cache")
|
|||
}
|
||||
|
||||
|
||||
State getState(Entry cache_entry, Address addr) {
|
||||
State getState(Entry cache_entry, Addr addr) {
|
||||
return State:I;
|
||||
}
|
||||
|
||||
void setState(Entry cache_entry, Address addr, State state) {
|
||||
void setState(Entry cache_entry, Addr addr, State state) {
|
||||
|
||||
}
|
||||
|
||||
AccessPermission getAccessPermission(Address addr) {
|
||||
AccessPermission getAccessPermission(Addr addr) {
|
||||
return AccessPermission:NotPresent;
|
||||
}
|
||||
|
||||
void setAccessPermission(Entry cache_entry, Address addr, State state) {
|
||||
void setAccessPermission(Entry cache_entry, Addr addr, State state) {
|
||||
}
|
||||
|
||||
Entry getCacheEntry(Address address), return_by_pointer="yes" {
|
||||
Entry getCacheEntry(Addr address), return_by_pointer="yes" {
|
||||
return OOD;
|
||||
}
|
||||
|
||||
void functionalRead(Address addr, Packet *pkt) {
|
||||
void functionalRead(Addr addr, Packet *pkt) {
|
||||
error("Network test does not support functional read.");
|
||||
}
|
||||
|
||||
int functionalWrite(Address addr, Packet *pkt) {
|
||||
int functionalWrite(Addr addr, Packet *pkt) {
|
||||
error("Network test does not support functional write.");
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -61,26 +61,26 @@ machine(Directory, "Network_test Directory")
|
|||
}
|
||||
|
||||
// ** OBJECTS **
|
||||
State getState(Address addr) {
|
||||
State getState(Addr addr) {
|
||||
return State:I;
|
||||
}
|
||||
|
||||
void setState(Address addr, State state) {
|
||||
void setState(Addr addr, State state) {
|
||||
|
||||
}
|
||||
|
||||
AccessPermission getAccessPermission(Address addr) {
|
||||
AccessPermission getAccessPermission(Addr addr) {
|
||||
return AccessPermission:NotPresent;
|
||||
}
|
||||
|
||||
void setAccessPermission(Address addr, State state) {
|
||||
void setAccessPermission(Addr addr, State state) {
|
||||
}
|
||||
|
||||
void functionalRead(Address addr, Packet *pkt) {
|
||||
void functionalRead(Addr addr, Packet *pkt) {
|
||||
error("Network test does not support functional read.");
|
||||
}
|
||||
|
||||
int functionalWrite(Address addr, Packet *pkt) {
|
||||
int functionalWrite(Addr addr, Packet *pkt) {
|
||||
error("Network test does not support functional write.");
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ enumeration(CoherenceRequestType, desc="...") {
|
|||
|
||||
// RequestMsg (and also forwarded requests)
|
||||
structure(RequestMsg, desc="...", interface="Message") {
|
||||
Address addr, desc="Physical address for this request";
|
||||
Addr addr, desc="Physical address for this request";
|
||||
CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)";
|
||||
MachineID Requestor, desc="Node who initiated the request";
|
||||
NetDest Destination, desc="Multicast destination mask";
|
||||
|
|
|
|||
|
|
@ -30,14 +30,14 @@
|
|||
// Mapping functions
|
||||
|
||||
int machineCount(MachineType machType);
|
||||
MachineID mapAddressToRange(Address addr, MachineType type,
|
||||
MachineID mapAddressToRange(Addr addr, MachineType type,
|
||||
int low, int high);
|
||||
MachineID mapAddressToRange(Address addr, MachineType type,
|
||||
MachineID mapAddressToRange(Addr addr, MachineType type,
|
||||
int low, int high, NodeID n);
|
||||
NetDest broadcast(MachineType type);
|
||||
MachineID map_Address_to_DMA(Address addr);
|
||||
MachineID map_Address_to_Directory(Address addr);
|
||||
NodeID map_Address_to_DirectoryNode(Address addr);
|
||||
MachineID map_Address_to_DMA(Addr addr);
|
||||
MachineID map_Address_to_Directory(Addr addr);
|
||||
NodeID map_Address_to_DirectoryNode(Addr addr);
|
||||
NodeID machineIDToNodeID(MachineID machID);
|
||||
NodeID machineIDToVersion(MachineID machID);
|
||||
MachineType machineIDToMachineType(MachineID machID);
|
||||
|
|
|
|||
|
|
@ -35,10 +35,10 @@ NodeID clusterID;
|
|||
// Functions implemented in the AbstractController class for
|
||||
// making timing access to the memory maintained by the
|
||||
// memory controllers.
|
||||
void queueMemoryRead(MachineID id, Address addr, Cycles latency);
|
||||
void queueMemoryWrite(MachineID id, Address addr, Cycles latency,
|
||||
void queueMemoryRead(MachineID id, Addr addr, Cycles latency);
|
||||
void queueMemoryWrite(MachineID id, Addr addr, Cycles latency,
|
||||
DataBlock block);
|
||||
void queueMemoryWritePartial(MachineID id, Address addr, Cycles latency,
|
||||
void queueMemoryWritePartial(MachineID id, Addr addr, Cycles latency,
|
||||
DataBlock block, int size);
|
||||
|
||||
// Functions implemented in the AbstractController class for
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ external_type(uint32_t, primitive="yes");
|
|||
external_type(uint64, primitive="yes");
|
||||
external_type(PacketPtr, primitive="yes");
|
||||
external_type(Packet, primitive="yes");
|
||||
external_type(Address);
|
||||
external_type(Addr, primitive="yes");
|
||||
external_type(Cycles, primitive="yes", default="Cycles(0)");
|
||||
|
||||
structure(DataBlock, external = "yes", desc="..."){
|
||||
|
|
@ -43,8 +43,8 @@ structure(DataBlock, external = "yes", desc="..."){
|
|||
void copyPartial(DataBlock, int, int);
|
||||
}
|
||||
|
||||
bool testAndRead(Address addr, DataBlock datablk, Packet *pkt);
|
||||
bool testAndWrite(Address addr, DataBlock datablk, Packet *pkt);
|
||||
bool testAndRead(Addr addr, DataBlock datablk, Packet *pkt);
|
||||
bool testAndWrite(Addr addr, DataBlock datablk, Packet *pkt);
|
||||
|
||||
// AccessPermission
|
||||
// The following five states define the access permission of all memory blocks.
|
||||
|
|
@ -215,10 +215,10 @@ enumeration(PrefetchBit, default="PrefetchBit_No", desc="...") {
|
|||
|
||||
// CacheMsg
|
||||
structure(SequencerMsg, desc="...", interface="Message") {
|
||||
Address LineAddress, desc="Line address for this request";
|
||||
Address PhysicalAddress, desc="Physical address for this request";
|
||||
Addr LineAddress, desc="Line address for this request";
|
||||
Addr PhysicalAddress, desc="Physical address for this request";
|
||||
SequencerRequestType Type, desc="Type of request (LD, ST, etc)";
|
||||
Address ProgramCounter, desc="Program counter of the instruction that caused the miss";
|
||||
Addr ProgramCounter, desc="Program counter of the instruction that caused the miss";
|
||||
RubyAccessMode AccessMode, desc="user/supervisor access type";
|
||||
DataBlock DataBlk, desc="Data";
|
||||
int Len, desc="size in bytes of access";
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@ enumeration(MemoryRequestType, desc="...") {
|
|||
// Message to and from Memory Control
|
||||
|
||||
structure(MemoryMsg, desc="...", interface="Message") {
|
||||
Address addr, desc="Physical address for this request";
|
||||
Addr addr, desc="Physical address for this request";
|
||||
MemoryRequestType Type, desc="Type of memory request (MEMORY_READ or MEMORY_WB)";
|
||||
MachineID Sender, desc="What component sent the data";
|
||||
MachineID OriginalRequestorMachId, desc="What component originally requested";
|
||||
|
|
|
|||
|
|
@ -98,30 +98,30 @@ structure (NetDest, external = "yes", non_obj="yes") {
|
|||
}
|
||||
|
||||
structure (Sequencer, external = "yes") {
|
||||
void readCallback(Address, DataBlock);
|
||||
void readCallback(Address, DataBlock, bool);
|
||||
void readCallback(Address, DataBlock, bool, MachineType);
|
||||
void readCallback(Address, DataBlock, bool, MachineType,
|
||||
void readCallback(Addr, DataBlock);
|
||||
void readCallback(Addr, DataBlock, bool);
|
||||
void readCallback(Addr, DataBlock, bool, MachineType);
|
||||
void readCallback(Addr, DataBlock, bool, MachineType,
|
||||
Cycles, Cycles, Cycles);
|
||||
|
||||
void writeCallback(Address, DataBlock);
|
||||
void writeCallback(Address, DataBlock, bool);
|
||||
void writeCallback(Address, DataBlock, bool, MachineType);
|
||||
void writeCallback(Address, DataBlock, bool, MachineType,
|
||||
void writeCallback(Addr, DataBlock);
|
||||
void writeCallback(Addr, DataBlock, bool);
|
||||
void writeCallback(Addr, DataBlock, bool, MachineType);
|
||||
void writeCallback(Addr, DataBlock, bool, MachineType,
|
||||
Cycles, Cycles, Cycles);
|
||||
|
||||
void checkCoherence(Address);
|
||||
void evictionCallback(Address);
|
||||
void checkCoherence(Addr);
|
||||
void evictionCallback(Addr);
|
||||
void recordRequestType(SequencerRequestType);
|
||||
bool checkResourceAvailable(CacheResourceType, Address);
|
||||
void invalidateSC(Address);
|
||||
bool checkResourceAvailable(CacheResourceType, Addr);
|
||||
void invalidateSC(Addr);
|
||||
}
|
||||
|
||||
structure(RubyRequest, desc="...", interface="Message", external="yes") {
|
||||
Address LineAddress, desc="Line address for this request";
|
||||
Address PhysicalAddress, desc="Physical address for this request";
|
||||
Addr LineAddress, desc="Line address for this request";
|
||||
Addr PhysicalAddress, desc="Physical address for this request";
|
||||
RubyRequestType Type, desc="Type of request (LD, ST, etc)";
|
||||
Address ProgramCounter, desc="Program counter of the instruction that caused the miss";
|
||||
Addr ProgramCounter, desc="Program counter of the instruction that caused the miss";
|
||||
RubyAccessMode AccessMode, desc="user/supervisor access type";
|
||||
int Size, desc="size in bytes of access";
|
||||
PrefetchBit Prefetch, desc="Is this a prefetch request";
|
||||
|
|
@ -133,10 +133,10 @@ structure(AbstractEntry, primitive="yes", external = "yes") {
|
|||
}
|
||||
|
||||
structure (DirectoryMemory, external = "yes") {
|
||||
AbstractEntry allocate(Address, AbstractEntry);
|
||||
AbstractEntry lookup(Address);
|
||||
bool isPresent(Address);
|
||||
void invalidateBlock(Address);
|
||||
AbstractEntry allocate(Addr, AbstractEntry);
|
||||
AbstractEntry lookup(Addr);
|
||||
bool isPresent(Addr);
|
||||
void invalidateBlock(Addr);
|
||||
void recordRequestType(DirectoryRequestType);
|
||||
}
|
||||
|
||||
|
|
@ -145,23 +145,23 @@ structure(AbstractCacheEntry, primitive="yes", external = "yes") {
|
|||
}
|
||||
|
||||
structure (CacheMemory, external = "yes") {
|
||||
bool cacheAvail(Address);
|
||||
Address cacheProbe(Address);
|
||||
AbstractCacheEntry allocate(Address, AbstractCacheEntry);
|
||||
AbstractCacheEntry allocate(Address, AbstractCacheEntry, bool);
|
||||
void allocateVoid(Address, AbstractCacheEntry);
|
||||
void deallocate(Address);
|
||||
AbstractCacheEntry lookup(Address);
|
||||
bool isTagPresent(Address);
|
||||
bool cacheAvail(Addr);
|
||||
Addr cacheProbe(Addr);
|
||||
AbstractCacheEntry allocate(Addr, AbstractCacheEntry);
|
||||
AbstractCacheEntry allocate(Addr, AbstractCacheEntry, bool);
|
||||
void allocateVoid(Addr, AbstractCacheEntry);
|
||||
void deallocate(Addr);
|
||||
AbstractCacheEntry lookup(Addr);
|
||||
bool isTagPresent(Addr);
|
||||
Cycles getTagLatency();
|
||||
Cycles getDataLatency();
|
||||
void setMRU(Address);
|
||||
void recordRequestType(CacheRequestType, Address);
|
||||
bool checkResourceAvailable(CacheResourceType, Address);
|
||||
void setMRU(Addr);
|
||||
void recordRequestType(CacheRequestType, Addr);
|
||||
bool checkResourceAvailable(CacheResourceType, Addr);
|
||||
|
||||
int getCacheSize();
|
||||
int getNumBlocks();
|
||||
Address getAddressAtIdx(int);
|
||||
Addr getAddressAtIdx(int);
|
||||
|
||||
Scalar demand_misses;
|
||||
Scalar demand_hits;
|
||||
|
|
@ -179,25 +179,25 @@ structure (DMASequencer, external = "yes") {
|
|||
|
||||
structure (TimerTable, inport="yes", external = "yes") {
|
||||
bool isReady();
|
||||
Address readyAddress();
|
||||
void set(Address, Cycles);
|
||||
void unset(Address);
|
||||
bool isSet(Address);
|
||||
Addr readyAddress();
|
||||
void set(Addr, Cycles);
|
||||
void unset(Addr);
|
||||
bool isSet(Addr);
|
||||
}
|
||||
|
||||
structure (GenericBloomFilter, external = "yes") {
|
||||
void clear(int);
|
||||
void increment(Address, int);
|
||||
void decrement(Address, int);
|
||||
void set(Address, int);
|
||||
void unset(Address, int);
|
||||
void increment(Addr, int);
|
||||
void decrement(Addr, int);
|
||||
void set(Addr, int);
|
||||
void unset(Addr, int);
|
||||
|
||||
bool isSet(Address, int);
|
||||
int getCount(Address, int);
|
||||
bool isSet(Addr, int);
|
||||
int getCount(Addr, int);
|
||||
}
|
||||
|
||||
structure (Prefetcher, external = "yes") {
|
||||
void observeMiss(Address, RubyRequestType);
|
||||
void observePfHit(Address);
|
||||
void observePfMiss(Address);
|
||||
void observeMiss(Addr, RubyRequestType);
|
||||
void observePfHit(Addr);
|
||||
void observePfMiss(Addr);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -35,11 +35,11 @@ int random(int number);
|
|||
Cycles zero_time();
|
||||
NodeID intToID(int nodenum);
|
||||
int IDToInt(NodeID id);
|
||||
int addressToInt(Address addr);
|
||||
int addressToInt(Addr addr);
|
||||
void procProfileCoherenceRequest(NodeID node, bool needCLB);
|
||||
void dirProfileCoherenceRequest(NodeID node, bool needCLB);
|
||||
int max_tokens();
|
||||
Address setOffset(Address addr, int offset);
|
||||
Address makeLineAddress(Address addr);
|
||||
int addressOffset(Address addr);
|
||||
Addr setOffset(Addr addr, int offset);
|
||||
Addr makeLineAddress(Addr addr);
|
||||
int getOffset(Addr addr);
|
||||
int mod(int val, int mod);
|
||||
|
|
|
|||
|
|
@ -29,115 +29,94 @@
|
|||
#include "mem/ruby/common/Address.hh"
|
||||
#include "mem/ruby/system/System.hh"
|
||||
|
||||
physical_address_t
|
||||
Address::getLineAddress() const
|
||||
Addr
|
||||
bitSelect(Addr addr, unsigned int small, unsigned int big)
|
||||
{
|
||||
return bitSelect(RubySystem::getBlockSizeBits(), ADDRESS_WIDTH);
|
||||
assert(big >= small);
|
||||
|
||||
if (big >= ADDRESS_WIDTH - 1) {
|
||||
return (addr >> small);
|
||||
} else {
|
||||
Addr mask = ~((Addr)~0 << (big + 1));
|
||||
// FIXME - this is slow to manipulate a 64-bit number using 32-bits
|
||||
Addr partial = (addr & mask);
|
||||
return (partial >> small);
|
||||
}
|
||||
}
|
||||
|
||||
physical_address_t
|
||||
Address::getOffset() const
|
||||
Addr
|
||||
bitRemove(Addr addr, unsigned int small, unsigned int big)
|
||||
{
|
||||
return bitSelect(0, RubySystem::getBlockSizeBits() - 1);
|
||||
assert(big >= small);
|
||||
|
||||
if (small >= ADDRESS_WIDTH - 1) {
|
||||
return addr;
|
||||
} else if (big >= ADDRESS_WIDTH - 1) {
|
||||
Addr mask = (Addr)~0 >> small;
|
||||
return (addr & mask);
|
||||
} else if (small == 0) {
|
||||
Addr mask = (Addr)~0 << big;
|
||||
return (addr & mask);
|
||||
} else {
|
||||
Addr mask = ~((Addr)~0 << small);
|
||||
Addr lower_bits = addr & mask;
|
||||
mask = (Addr)~0 << (big + 1);
|
||||
Addr higher_bits = addr & mask;
|
||||
|
||||
// Shift the valid high bits over the removed section
|
||||
higher_bits = higher_bits >> (big - small + 1);
|
||||
return (higher_bits | lower_bits);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
Address::makeLineAddress()
|
||||
Addr
|
||||
maskLowOrderBits(Addr addr, unsigned int number)
|
||||
{
|
||||
m_address = maskLowOrderBits(RubySystem::getBlockSizeBits());
|
||||
Addr mask;
|
||||
|
||||
if (number >= ADDRESS_WIDTH - 1) {
|
||||
mask = ~0;
|
||||
} else {
|
||||
mask = (Addr)~0 << number;
|
||||
}
|
||||
return (addr & mask);
|
||||
}
|
||||
|
||||
Addr
|
||||
maskHighOrderBits(Addr addr, unsigned int number)
|
||||
{
|
||||
Addr mask;
|
||||
|
||||
if (number >= ADDRESS_WIDTH - 1) {
|
||||
mask = ~0;
|
||||
} else {
|
||||
mask = (Addr)~0 >> number;
|
||||
}
|
||||
return (addr & mask);
|
||||
}
|
||||
|
||||
Addr
|
||||
shiftLowOrderBits(Addr addr, unsigned int number)
|
||||
{
|
||||
return (addr >> number);
|
||||
}
|
||||
|
||||
Addr
|
||||
getOffset(Addr addr)
|
||||
{
|
||||
return bitSelect(addr, 0, RubySystem::getBlockSizeBits() - 1);
|
||||
}
|
||||
|
||||
Addr
|
||||
makeLineAddress(Addr addr)
|
||||
{
|
||||
return maskLowOrderBits(addr, RubySystem::getBlockSizeBits());
|
||||
}
|
||||
|
||||
// returns the next stride address based on line address
|
||||
void
|
||||
Address::makeNextStrideAddress(int stride)
|
||||
Addr
|
||||
makeNextStrideAddress(Addr addr, int stride)
|
||||
{
|
||||
m_address = maskLowOrderBits(RubySystem::getBlockSizeBits())
|
||||
+ RubySystem::getBlockSizeBytes()*stride;
|
||||
}
|
||||
|
||||
int64
|
||||
Address::memoryModuleIndex() const
|
||||
{
|
||||
int64 index =
|
||||
bitSelect(RubySystem::getBlockSizeBits() +
|
||||
RubySystem::getMemorySizeBits(), ADDRESS_WIDTH);
|
||||
assert (index >= 0);
|
||||
return index;
|
||||
|
||||
// int64 indexHighPortion =
|
||||
// address.bitSelect(MEMORY_SIZE_BITS - 1,
|
||||
// PAGE_SIZE_BITS + NUMBER_OF_MEMORY_MODULE_BITS);
|
||||
// int64 indexLowPortion =
|
||||
// address.bitSelect(DATA_BLOCK_BITS, PAGE_SIZE_BITS - 1);
|
||||
//
|
||||
// int64 index = indexLowPortion |
|
||||
// (indexHighPortion << (PAGE_SIZE_BITS - DATA_BLOCK_BITS));
|
||||
|
||||
/*
|
||||
Round-robin mapping of addresses, at page size granularity
|
||||
|
||||
ADDRESS_WIDTH MEMORY_SIZE_BITS PAGE_SIZE_BITS DATA_BLOCK_BITS
|
||||
| | | |
|
||||
\ / \ / \ / \ / 0
|
||||
-----------------------------------------------------------------------
|
||||
| unused |xxxxxxxxxxxxxxx| |xxxxxxxxxxxxxxx| |
|
||||
| |xxxxxxxxxxxxxxx| |xxxxxxxxxxxxxxx| |
|
||||
-----------------------------------------------------------------------
|
||||
indexHighPortion indexLowPortion
|
||||
<------->
|
||||
NUMBER_OF_MEMORY_MODULE_BITS
|
||||
*/
|
||||
}
|
||||
|
||||
void
|
||||
Address::print(std::ostream& out) const
|
||||
{
|
||||
using namespace std;
|
||||
out << "[" << hex << "0x" << m_address << "," << " line 0x"
|
||||
<< maskLowOrderBits(RubySystem::getBlockSizeBits()) << dec << "]"
|
||||
<< flush;
|
||||
}
|
||||
|
||||
void
|
||||
Address::output(std::ostream& out) const
|
||||
{
|
||||
// Note: this outputs addresses in the form "ffff", not "0xffff".
|
||||
// This code should always be able to write out addresses in a
|
||||
// format that can be read in by the below input() method. Please
|
||||
// don't change this without talking to Milo first.
|
||||
out << std::hex << m_address << std::dec;
|
||||
}
|
||||
|
||||
void
|
||||
Address::input(std::istream& in)
|
||||
{
|
||||
// Note: this only works with addresses in the form "ffff", not
|
||||
// "0xffff". This code should always be able to read in addresses
|
||||
// written out by the above output() method. Please don't change
|
||||
// this without talking to Milo first.
|
||||
in >> std::hex >> m_address >> std::dec;
|
||||
}
|
||||
|
||||
Address::Address(const Address& obj)
|
||||
{
|
||||
m_address = obj.m_address;
|
||||
}
|
||||
|
||||
Address&
|
||||
Address::operator=(const Address& obj)
|
||||
{
|
||||
if (this == &obj) {
|
||||
// assert(false);
|
||||
} else {
|
||||
m_address = obj.m_address;
|
||||
}
|
||||
return *this;
|
||||
}
|
||||
|
||||
Address
|
||||
next_stride_address(const Address& addr, int stride)
|
||||
{
|
||||
Address temp = addr;
|
||||
temp.makeNextStrideAddress(stride);
|
||||
return temp;
|
||||
return maskLowOrderBits(addr, RubySystem::getBlockSizeBits())
|
||||
+ RubySystem::getBlockSizeBytes() * stride;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -34,193 +34,18 @@
|
|||
#include <iostream>
|
||||
|
||||
#include "base/hashmap.hh"
|
||||
#include "mem/ruby/common/TypeDefines.hh"
|
||||
#include "base/types.hh"
|
||||
|
||||
const uint32_t ADDRESS_WIDTH = 64; // address width in bytes
|
||||
|
||||
class Address;
|
||||
typedef Address PhysAddress;
|
||||
typedef Address VirtAddress;
|
||||
|
||||
class Address
|
||||
{
|
||||
public:
|
||||
Address()
|
||||
: m_address(0)
|
||||
{ }
|
||||
|
||||
explicit
|
||||
Address(physical_address_t address)
|
||||
: m_address(address)
|
||||
{ }
|
||||
|
||||
Address(const Address& obj);
|
||||
Address& operator=(const Address& obj);
|
||||
|
||||
void setAddress(physical_address_t address) { m_address = address; }
|
||||
physical_address_t getAddress() const {return m_address;}
|
||||
// selects bits inclusive
|
||||
physical_address_t bitSelect(unsigned int small, unsigned int big) const;
|
||||
physical_address_t bitRemove(unsigned int small, unsigned int big) const;
|
||||
physical_address_t maskLowOrderBits(unsigned int number) const;
|
||||
physical_address_t maskHighOrderBits(unsigned int number) const;
|
||||
physical_address_t shiftLowOrderBits(unsigned int number) const;
|
||||
|
||||
physical_address_t getLineAddress() const;
|
||||
physical_address_t getOffset() const;
|
||||
void makeLineAddress();
|
||||
void makeNextStrideAddress(int stride);
|
||||
|
||||
int64 memoryModuleIndex() const;
|
||||
|
||||
void print(std::ostream& out) const;
|
||||
void output(std::ostream& out) const;
|
||||
void input(std::istream& in);
|
||||
|
||||
void
|
||||
setOffset(int offset)
|
||||
{
|
||||
// first, zero out the offset bits
|
||||
makeLineAddress();
|
||||
m_address |= (physical_address_t) offset;
|
||||
}
|
||||
|
||||
private:
|
||||
physical_address_t m_address;
|
||||
};
|
||||
|
||||
inline Address
|
||||
line_address(const Address& addr)
|
||||
{
|
||||
Address temp(addr);
|
||||
temp.makeLineAddress();
|
||||
return temp;
|
||||
}
|
||||
|
||||
inline bool
|
||||
operator<(const Address& obj1, const Address& obj2)
|
||||
{
|
||||
return obj1.getAddress() < obj2.getAddress();
|
||||
}
|
||||
|
||||
inline std::ostream&
|
||||
operator<<(std::ostream& out, const Address& obj)
|
||||
{
|
||||
obj.print(out);
|
||||
out << std::flush;
|
||||
return out;
|
||||
}
|
||||
|
||||
inline bool
|
||||
operator==(const Address& obj1, const Address& obj2)
|
||||
{
|
||||
return (obj1.getAddress() == obj2.getAddress());
|
||||
}
|
||||
|
||||
inline bool
|
||||
operator!=(const Address& obj1, const Address& obj2)
|
||||
{
|
||||
return (obj1.getAddress() != obj2.getAddress());
|
||||
}
|
||||
|
||||
// rips bits inclusive
|
||||
inline physical_address_t
|
||||
Address::bitSelect(unsigned int small, unsigned int big) const
|
||||
{
|
||||
physical_address_t mask;
|
||||
assert(big >= small);
|
||||
|
||||
if (big >= ADDRESS_WIDTH - 1) {
|
||||
return (m_address >> small);
|
||||
} else {
|
||||
mask = ~((physical_address_t)~0 << (big + 1));
|
||||
// FIXME - this is slow to manipulate a 64-bit number using 32-bits
|
||||
physical_address_t partial = (m_address & mask);
|
||||
return (partial >> small);
|
||||
}
|
||||
}
|
||||
|
||||
// removes bits inclusive
|
||||
inline physical_address_t
|
||||
Address::bitRemove(unsigned int small, unsigned int big) const
|
||||
{
|
||||
physical_address_t mask;
|
||||
assert(big >= small);
|
||||
|
||||
if (small >= ADDRESS_WIDTH - 1) {
|
||||
return m_address;
|
||||
} else if (big >= ADDRESS_WIDTH - 1) {
|
||||
mask = (physical_address_t)~0 >> small;
|
||||
return (m_address & mask);
|
||||
} else if (small == 0) {
|
||||
mask = (physical_address_t)~0 << big;
|
||||
return (m_address & mask);
|
||||
} else {
|
||||
mask = ~((physical_address_t)~0 << small);
|
||||
physical_address_t lower_bits = m_address & mask;
|
||||
mask = (physical_address_t)~0 << (big + 1);
|
||||
physical_address_t higher_bits = m_address & mask;
|
||||
|
||||
// Shift the valid high bits over the removed section
|
||||
higher_bits = higher_bits >> (big - small + 1);
|
||||
return (higher_bits | lower_bits);
|
||||
}
|
||||
}
|
||||
|
||||
inline physical_address_t
|
||||
Address::maskLowOrderBits(unsigned int number) const
|
||||
{
|
||||
physical_address_t mask;
|
||||
|
||||
if (number >= ADDRESS_WIDTH - 1) {
|
||||
mask = ~0;
|
||||
} else {
|
||||
mask = (physical_address_t)~0 << number;
|
||||
}
|
||||
return (m_address & mask);
|
||||
}
|
||||
|
||||
inline physical_address_t
|
||||
Address::maskHighOrderBits(unsigned int number) const
|
||||
{
|
||||
physical_address_t mask;
|
||||
|
||||
if (number >= ADDRESS_WIDTH - 1) {
|
||||
mask = ~0;
|
||||
} else {
|
||||
mask = (physical_address_t)~0 >> number;
|
||||
}
|
||||
return (m_address & mask);
|
||||
}
|
||||
|
||||
inline physical_address_t
|
||||
Address::shiftLowOrderBits(unsigned int number) const
|
||||
{
|
||||
return (m_address >> number);
|
||||
}
|
||||
|
||||
Address next_stride_address(const Address& addr, int stride);
|
||||
|
||||
__hash_namespace_begin
|
||||
template <> struct hash<Address>
|
||||
{
|
||||
size_t
|
||||
operator()(const Address &s) const
|
||||
{
|
||||
return (size_t)s.getAddress();
|
||||
}
|
||||
};
|
||||
__hash_namespace_end
|
||||
|
||||
namespace std {
|
||||
template <> struct equal_to<Address>
|
||||
{
|
||||
bool
|
||||
operator()(const Address& s1, const Address& s2) const
|
||||
{
|
||||
return s1 == s2;
|
||||
}
|
||||
};
|
||||
} // namespace std
|
||||
// selects bits inclusive
|
||||
Addr bitSelect(Addr addr, unsigned int small, unsigned int big);
|
||||
Addr bitRemove(Addr addr, unsigned int small, unsigned int big);
|
||||
Addr maskLowOrderBits(Addr addr, unsigned int number);
|
||||
Addr maskHighOrderBits(Addr addr, unsigned int number);
|
||||
Addr shiftLowOrderBits(Addr addr, unsigned int number);
|
||||
Addr getOffset(Addr addr);
|
||||
Addr makeLineAddress(Addr addr);
|
||||
Addr makeNextStrideAddress(Addr addr, int stride);
|
||||
|
||||
#endif // __MEM_RUBY_COMMON_ADDRESS_HH__
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@
|
|||
|
||||
using m5::stl_helpers::operator<<;
|
||||
|
||||
SubBlock::SubBlock(const Address& addr, int size)
|
||||
SubBlock::SubBlock(Addr addr, int size)
|
||||
{
|
||||
m_address = addr;
|
||||
resize(size);
|
||||
|
|
@ -45,7 +45,7 @@ SubBlock::internalMergeFrom(const DataBlock& data)
|
|||
{
|
||||
int size = getSize();
|
||||
assert(size > 0);
|
||||
int offset = m_address.getOffset();
|
||||
int offset = getOffset(m_address);
|
||||
for (int i = 0; i < size; i++) {
|
||||
this->setByte(i, data.getByte(offset + i));
|
||||
}
|
||||
|
|
@ -56,7 +56,7 @@ SubBlock::internalMergeTo(DataBlock& data) const
|
|||
{
|
||||
int size = getSize();
|
||||
assert(size > 0);
|
||||
int offset = m_address.getOffset();
|
||||
int offset = getOffset(m_address);
|
||||
for (int i = 0; i < size; i++) {
|
||||
// This will detect crossing a cache line boundary
|
||||
data.setByte(offset + i, this->getByte(i));
|
||||
|
|
|
|||
|
|
@ -39,11 +39,11 @@ class SubBlock
|
|||
{
|
||||
public:
|
||||
SubBlock() { }
|
||||
SubBlock(const Address& addr, int size);
|
||||
SubBlock(Addr addr, int size);
|
||||
~SubBlock() { }
|
||||
|
||||
const Address& getAddress() const { return m_address; }
|
||||
void setAddress(const Address& addr) { m_address = addr; }
|
||||
Addr getAddress() const { return m_address; }
|
||||
void setAddress(Addr addr) { m_address = addr; }
|
||||
|
||||
int getSize() const { return m_data.size(); }
|
||||
void resize(int size) { m_data.resize(size); }
|
||||
|
|
@ -66,7 +66,7 @@ class SubBlock
|
|||
void internalMergeFrom(const DataBlock& data);
|
||||
|
||||
// Data Members (m_ prefix)
|
||||
Address m_address;
|
||||
Addr m_address;
|
||||
std::vector<uint8_t> m_data;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -33,8 +33,6 @@
|
|||
typedef unsigned long long uint64;
|
||||
typedef long long int64;
|
||||
|
||||
typedef uint64 physical_address_t;
|
||||
|
||||
typedef unsigned int LinkID;
|
||||
typedef unsigned int NodeID;
|
||||
typedef unsigned int SwitchID;
|
||||
|
|
|
|||
|
|
@ -38,19 +38,19 @@ class AbstractBloomFilter
|
|||
public:
|
||||
virtual ~AbstractBloomFilter() {};
|
||||
virtual void clear() = 0;
|
||||
virtual void increment(const Address& addr) = 0;
|
||||
virtual void decrement(const Address& addr) = 0;
|
||||
virtual void increment(Addr addr) = 0;
|
||||
virtual void decrement(Addr addr) = 0;
|
||||
virtual void merge(AbstractBloomFilter * other_filter) = 0;
|
||||
virtual void set(const Address& addr) = 0;
|
||||
virtual void unset(const Address& addr) = 0;
|
||||
virtual void set(Addr addr) = 0;
|
||||
virtual void unset(Addr addr) = 0;
|
||||
|
||||
virtual bool isSet(const Address& addr) = 0;
|
||||
virtual int getCount(const Address& addr) = 0;
|
||||
virtual bool isSet(Addr addr) = 0;
|
||||
virtual int getCount(Addr addr) = 0;
|
||||
virtual int getTotalCount() = 0;
|
||||
|
||||
virtual void print(std::ostream& out) const = 0;
|
||||
|
||||
virtual int getIndex(const Address& addr) = 0;
|
||||
virtual int getIndex(Addr addr) = 0;
|
||||
virtual int readBit(const int index) = 0;
|
||||
virtual void writeBit(const int index, const int value) = 0;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -65,13 +65,13 @@ BlockBloomFilter::clear()
|
|||
}
|
||||
|
||||
void
|
||||
BlockBloomFilter::increment(const Address& addr)
|
||||
BlockBloomFilter::increment(Addr addr)
|
||||
{
|
||||
// Not used
|
||||
}
|
||||
|
||||
void
|
||||
BlockBloomFilter::decrement(const Address& addr)
|
||||
BlockBloomFilter::decrement(Addr addr)
|
||||
{
|
||||
// Not used
|
||||
}
|
||||
|
|
@ -83,28 +83,28 @@ BlockBloomFilter::merge(AbstractBloomFilter * other_filter)
|
|||
}
|
||||
|
||||
void
|
||||
BlockBloomFilter::set(const Address& addr)
|
||||
BlockBloomFilter::set(Addr addr)
|
||||
{
|
||||
int i = get_index(addr);
|
||||
m_filter[i] = 1;
|
||||
}
|
||||
|
||||
void
|
||||
BlockBloomFilter::unset(const Address& addr)
|
||||
BlockBloomFilter::unset(Addr addr)
|
||||
{
|
||||
int i = get_index(addr);
|
||||
m_filter[i] = 0;
|
||||
}
|
||||
|
||||
bool
|
||||
BlockBloomFilter::isSet(const Address& addr)
|
||||
BlockBloomFilter::isSet(Addr addr)
|
||||
{
|
||||
int i = get_index(addr);
|
||||
return (m_filter[i]);
|
||||
}
|
||||
|
||||
int
|
||||
BlockBloomFilter::getCount(const Address& addr)
|
||||
BlockBloomFilter::getCount(Addr addr)
|
||||
{
|
||||
return m_filter[get_index(addr)];
|
||||
}
|
||||
|
|
@ -123,7 +123,7 @@ BlockBloomFilter::getTotalCount()
|
|||
}
|
||||
|
||||
int
|
||||
BlockBloomFilter::getIndex(const Address& addr)
|
||||
BlockBloomFilter::getIndex(Addr addr)
|
||||
{
|
||||
return get_index(addr);
|
||||
}
|
||||
|
|
@ -146,17 +146,16 @@ BlockBloomFilter::writeBit(const int index, const int value)
|
|||
}
|
||||
|
||||
int
|
||||
BlockBloomFilter::get_index(const Address& addr)
|
||||
BlockBloomFilter::get_index(Addr addr)
|
||||
{
|
||||
// Pull out some bit field ==> B1
|
||||
// Pull out additional bits, not the same as B1 ==> B2
|
||||
// XOR B1 and B2 to get hash index
|
||||
physical_address_t block_bits =
|
||||
addr.bitSelect(RubySystem::getBlockSizeBits(),
|
||||
Addr block_bits = bitSelect(addr, RubySystem::getBlockSizeBits(),
|
||||
2 * RubySystem::getBlockSizeBits() - 1);
|
||||
int offset = 5;
|
||||
physical_address_t other_bits =
|
||||
addr.bitSelect(2 * RubySystem::getBlockSizeBits() + offset,
|
||||
Addr other_bits = bitSelect(addr,
|
||||
2 * RubySystem::getBlockSizeBits() + offset,
|
||||
2 * RubySystem::getBlockSizeBits() + offset +
|
||||
m_filter_size_bits - 1);
|
||||
int index = block_bits ^ other_bits;
|
||||
|
|
|
|||
|
|
@ -43,23 +43,23 @@ class BlockBloomFilter : public AbstractBloomFilter
|
|||
~BlockBloomFilter();
|
||||
|
||||
void clear();
|
||||
void increment(const Address& addr);
|
||||
void decrement(const Address& addr);
|
||||
void increment(Addr addr);
|
||||
void decrement(Addr addr);
|
||||
void merge(AbstractBloomFilter * other_filter);
|
||||
void set(const Address& addr);
|
||||
void unset(const Address& addr);
|
||||
void set(Addr addr);
|
||||
void unset(Addr addr);
|
||||
|
||||
bool isSet(const Address& addr);
|
||||
int getCount(const Address& addr);
|
||||
bool isSet(Addr addr);
|
||||
int getCount(Addr addr);
|
||||
int getTotalCount();
|
||||
int getIndex(const Address& addr);
|
||||
int getIndex(Addr addr);
|
||||
int readBit(const int index);
|
||||
void writeBit(const int index, const int value);
|
||||
|
||||
void print(std::ostream& out) const;
|
||||
|
||||
private:
|
||||
int get_index(const Address& addr);
|
||||
int get_index(Addr addr);
|
||||
|
||||
std::vector<int> m_filter;
|
||||
int m_filter_size;
|
||||
|
|
|
|||
|
|
@ -73,13 +73,13 @@ BulkBloomFilter::clear()
|
|||
}
|
||||
|
||||
void
|
||||
BulkBloomFilter::increment(const Address& addr)
|
||||
BulkBloomFilter::increment(Addr addr)
|
||||
{
|
||||
// Not used
|
||||
}
|
||||
|
||||
void
|
||||
BulkBloomFilter::decrement(const Address& addr)
|
||||
BulkBloomFilter::decrement(Addr addr)
|
||||
{
|
||||
// Not used
|
||||
}
|
||||
|
|
@ -91,16 +91,16 @@ BulkBloomFilter::merge(AbstractBloomFilter * other_filter)
|
|||
}
|
||||
|
||||
void
|
||||
BulkBloomFilter::set(const Address& addr)
|
||||
BulkBloomFilter::set(Addr addr)
|
||||
{
|
||||
// c0 contains the cache index bits
|
||||
int set_bits = m_sector_bits;
|
||||
int block_bits = RubySystem::getBlockSizeBits();
|
||||
int c0 = addr.bitSelect( block_bits, block_bits + set_bits - 1);
|
||||
int c0 = bitSelect(addr, block_bits, block_bits + set_bits - 1);
|
||||
// c1 contains the lower m_sector_bits permuted bits
|
||||
//Address permuted_bits = permute(addr);
|
||||
//int c1 = permuted_bits.bitSelect(0, set_bits-1);
|
||||
int c1 = addr.bitSelect( block_bits+set_bits, (block_bits+2*set_bits) - 1);
|
||||
int c1 = bitSelect(addr, block_bits+set_bits, (block_bits+2*set_bits) - 1);
|
||||
//assert(c0 < (m_filter_size/2));
|
||||
//assert(c0 + (m_filter_size/2) < m_filter_size);
|
||||
//assert(c1 < (m_filter_size/2));
|
||||
|
|
@ -111,22 +111,22 @@ BulkBloomFilter::set(const Address& addr)
|
|||
}
|
||||
|
||||
void
|
||||
BulkBloomFilter::unset(const Address& addr)
|
||||
BulkBloomFilter::unset(Addr addr)
|
||||
{
|
||||
// not used
|
||||
}
|
||||
|
||||
bool
|
||||
BulkBloomFilter::isSet(const Address& addr)
|
||||
BulkBloomFilter::isSet(Addr addr)
|
||||
{
|
||||
// c0 contains the cache index bits
|
||||
int set_bits = m_sector_bits;
|
||||
int block_bits = RubySystem::getBlockSizeBits();
|
||||
int c0 = addr.bitSelect( block_bits, block_bits + set_bits - 1);
|
||||
int c0 = bitSelect(addr, block_bits, block_bits + set_bits - 1);
|
||||
// c1 contains the lower 10 permuted bits
|
||||
//Address permuted_bits = permute(addr);
|
||||
//int c1 = permuted_bits.bitSelect(0, set_bits-1);
|
||||
int c1 = addr.bitSelect( block_bits+set_bits, (block_bits+2*set_bits) - 1);
|
||||
int c1 = bitSelect(addr, block_bits+set_bits, (block_bits+2*set_bits) - 1);
|
||||
//assert(c0 < (m_filter_size/2));
|
||||
//assert(c0 + (m_filter_size/2) < m_filter_size);
|
||||
//assert(c1 < (m_filter_size/2));
|
||||
|
|
@ -173,7 +173,7 @@ BulkBloomFilter::isSet(const Address& addr)
|
|||
}
|
||||
|
||||
int
|
||||
BulkBloomFilter::getCount(const Address& addr)
|
||||
BulkBloomFilter::getCount(Addr addr)
|
||||
{
|
||||
// not used
|
||||
return 0;
|
||||
|
|
@ -192,7 +192,7 @@ BulkBloomFilter::getTotalCount()
|
|||
}
|
||||
|
||||
int
|
||||
BulkBloomFilter::getIndex(const Address& addr)
|
||||
BulkBloomFilter::getIndex(Addr addr)
|
||||
{
|
||||
return get_index(addr);
|
||||
}
|
||||
|
|
@ -216,40 +216,40 @@ BulkBloomFilter::print(ostream& out) const
|
|||
}
|
||||
|
||||
int
|
||||
BulkBloomFilter::get_index(const Address& addr)
|
||||
BulkBloomFilter::get_index(Addr addr)
|
||||
{
|
||||
return addr.bitSelect(RubySystem::getBlockSizeBits(),
|
||||
return bitSelect(addr, RubySystem::getBlockSizeBits(),
|
||||
RubySystem::getBlockSizeBits() +
|
||||
m_filter_size_bits - 1);
|
||||
}
|
||||
|
||||
Address
|
||||
BulkBloomFilter::permute(const Address & addr)
|
||||
Addr
|
||||
BulkBloomFilter::permute(Addr addr)
|
||||
{
|
||||
// permutes the original address bits according to Table 5
|
||||
int block_offset = RubySystem::getBlockSizeBits();
|
||||
physical_address_t part1 = addr.bitSelect(block_offset, block_offset + 6),
|
||||
part2 = addr.bitSelect(block_offset + 9, block_offset + 9),
|
||||
part3 = addr.bitSelect(block_offset + 11, block_offset + 11),
|
||||
part4 = addr.bitSelect(block_offset + 17, block_offset + 17),
|
||||
part5 = addr.bitSelect(block_offset + 7, block_offset + 8),
|
||||
part6 = addr.bitSelect(block_offset + 10, block_offset + 10),
|
||||
part7 = addr.bitSelect(block_offset + 12, block_offset + 12),
|
||||
part8 = addr.bitSelect(block_offset + 13, block_offset + 13),
|
||||
part9 = addr.bitSelect(block_offset + 15, block_offset + 16),
|
||||
part10 = addr.bitSelect(block_offset + 18, block_offset + 20),
|
||||
part11 = addr.bitSelect(block_offset + 14, block_offset + 14);
|
||||
Addr part1 = bitSelect(addr, block_offset, block_offset + 6),
|
||||
part2 = bitSelect(addr, block_offset + 9, block_offset + 9),
|
||||
part3 = bitSelect(addr, block_offset + 11, block_offset + 11),
|
||||
part4 = bitSelect(addr, block_offset + 17, block_offset + 17),
|
||||
part5 = bitSelect(addr, block_offset + 7, block_offset + 8),
|
||||
part6 = bitSelect(addr, block_offset + 10, block_offset + 10),
|
||||
part7 = bitSelect(addr, block_offset + 12, block_offset + 12),
|
||||
part8 = bitSelect(addr, block_offset + 13, block_offset + 13),
|
||||
part9 = bitSelect(addr, block_offset + 15, block_offset + 16),
|
||||
part10 = bitSelect(addr, block_offset + 18, block_offset + 20),
|
||||
part11 = bitSelect(addr, block_offset + 14, block_offset + 14);
|
||||
|
||||
physical_address_t result =
|
||||
Addr result =
|
||||
(part1 << 14) | (part2 << 13) | (part3 << 12) | (part4 << 11) |
|
||||
(part5 << 9) | (part6 << 8) | (part7 << 7) | (part8 << 6) |
|
||||
(part9 << 4) | (part10 << 1) | (part11);
|
||||
|
||||
// assume 32 bit addresses (both virtual and physical)
|
||||
// select the remaining high-order 11 bits
|
||||
physical_address_t remaining_bits =
|
||||
addr.bitSelect(block_offset + 21, 31) << 21;
|
||||
Addr remaining_bits =
|
||||
bitSelect(addr, block_offset + 21, 31) << 21;
|
||||
result = result | remaining_bits;
|
||||
|
||||
return Address(result);
|
||||
return result;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -43,24 +43,24 @@ class BulkBloomFilter : public AbstractBloomFilter
|
|||
~BulkBloomFilter();
|
||||
|
||||
void clear();
|
||||
void increment(const Address& addr);
|
||||
void decrement(const Address& addr);
|
||||
void increment(Addr addr);
|
||||
void decrement(Addr addr);
|
||||
void merge(AbstractBloomFilter * other_filter);
|
||||
void set(const Address& addr);
|
||||
void unset(const Address& addr);
|
||||
void set(Addr addr);
|
||||
void unset(Addr addr);
|
||||
|
||||
bool isSet(const Address& addr);
|
||||
int getCount(const Address& addr);
|
||||
bool isSet(Addr addr);
|
||||
int getCount(Addr addr);
|
||||
int getTotalCount();
|
||||
int getIndex(const Address& addr);
|
||||
int getIndex(Addr addr);
|
||||
int readBit(const int index);
|
||||
void writeBit(const int index, const int value);
|
||||
|
||||
void print(std::ostream& out) const;
|
||||
|
||||
private:
|
||||
int get_index(const Address& addr);
|
||||
Address permute(const Address & addr);
|
||||
int get_index(Addr addr);
|
||||
Addr permute(Addr addr);
|
||||
|
||||
std::vector<int> m_filter;
|
||||
std::vector<int> m_temp_filter;
|
||||
|
|
|
|||
|
|
@ -79,13 +79,13 @@ GenericBloomFilter::clear()
|
|||
}
|
||||
|
||||
void
|
||||
GenericBloomFilter::increment(const Address& addr)
|
||||
GenericBloomFilter::increment(Addr addr)
|
||||
{
|
||||
m_filter->increment(addr);
|
||||
}
|
||||
|
||||
void
|
||||
GenericBloomFilter::decrement(const Address& addr)
|
||||
GenericBloomFilter::decrement(Addr addr)
|
||||
{
|
||||
m_filter->decrement(addr);
|
||||
}
|
||||
|
|
@ -97,25 +97,25 @@ GenericBloomFilter::merge(GenericBloomFilter * other_filter)
|
|||
}
|
||||
|
||||
void
|
||||
GenericBloomFilter::set(const Address& addr)
|
||||
GenericBloomFilter::set(Addr addr)
|
||||
{
|
||||
m_filter->set(addr);
|
||||
}
|
||||
|
||||
void
|
||||
GenericBloomFilter::unset(const Address& addr)
|
||||
GenericBloomFilter::unset(Addr addr)
|
||||
{
|
||||
m_filter->unset(addr);
|
||||
}
|
||||
|
||||
bool
|
||||
GenericBloomFilter::isSet(const Address& addr)
|
||||
GenericBloomFilter::isSet(Addr addr)
|
||||
{
|
||||
return m_filter->isSet(addr);
|
||||
}
|
||||
|
||||
int
|
||||
GenericBloomFilter::getCount(const Address& addr)
|
||||
GenericBloomFilter::getCount(Addr addr)
|
||||
{
|
||||
return m_filter->getCount(addr);
|
||||
}
|
||||
|
|
@ -127,7 +127,7 @@ GenericBloomFilter::getTotalCount()
|
|||
}
|
||||
|
||||
int
|
||||
GenericBloomFilter::getIndex(const Address& addr)
|
||||
GenericBloomFilter::getIndex(Addr addr)
|
||||
{
|
||||
return m_filter->getIndex(addr);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -42,24 +42,24 @@ class GenericBloomFilter
|
|||
~GenericBloomFilter();
|
||||
|
||||
void clear();
|
||||
void increment(const Address& addr);
|
||||
void decrement(const Address& addr);
|
||||
void increment(Addr addr);
|
||||
void decrement(Addr addr);
|
||||
void merge(GenericBloomFilter * other_filter);
|
||||
void set(const Address& addr);
|
||||
void unset(const Address& addr);
|
||||
void set(Addr addr);
|
||||
void unset(Addr addr);
|
||||
AbstractBloomFilter *
|
||||
getFilter()
|
||||
{
|
||||
return m_filter;
|
||||
}
|
||||
|
||||
bool isSet(const Address& addr);
|
||||
bool isSet(Addr addr);
|
||||
|
||||
int getCount(const Address& addr);
|
||||
int getCount(Addr addr);
|
||||
|
||||
int getTotalCount();
|
||||
|
||||
int getIndex(const Address& addr);
|
||||
int getIndex(Addr addr);
|
||||
int readBit(const int index);
|
||||
void writeBit(const int index, const int value);
|
||||
|
||||
|
|
|
|||
|
|
@ -416,13 +416,13 @@ H3BloomFilter::clear()
|
|||
}
|
||||
|
||||
void
|
||||
H3BloomFilter::increment(const Address& addr)
|
||||
H3BloomFilter::increment(Addr addr)
|
||||
{
|
||||
// Not used
|
||||
}
|
||||
|
||||
void
|
||||
H3BloomFilter::decrement(const Address& addr)
|
||||
H3BloomFilter::decrement(Addr addr)
|
||||
{
|
||||
// Not used
|
||||
}
|
||||
|
|
@ -438,7 +438,7 @@ H3BloomFilter::merge(AbstractBloomFilter *other_filter)
|
|||
}
|
||||
|
||||
void
|
||||
H3BloomFilter::set(const Address& addr)
|
||||
H3BloomFilter::set(Addr addr)
|
||||
{
|
||||
for (int i = 0; i < m_num_hashes; i++) {
|
||||
int idx = get_index(addr, i);
|
||||
|
|
@ -447,14 +447,14 @@ H3BloomFilter::set(const Address& addr)
|
|||
}
|
||||
|
||||
void
|
||||
H3BloomFilter::unset(const Address& addr)
|
||||
H3BloomFilter::unset(Addr addr)
|
||||
{
|
||||
cout << "ERROR: Unset should never be called in a Bloom filter";
|
||||
assert(0);
|
||||
}
|
||||
|
||||
bool
|
||||
H3BloomFilter::isSet(const Address& addr)
|
||||
H3BloomFilter::isSet(Addr addr)
|
||||
{
|
||||
bool res = true;
|
||||
|
||||
|
|
@ -466,13 +466,13 @@ H3BloomFilter::isSet(const Address& addr)
|
|||
}
|
||||
|
||||
int
|
||||
H3BloomFilter::getCount(const Address& addr)
|
||||
H3BloomFilter::getCount(Addr addr)
|
||||
{
|
||||
return isSet(addr)? 1: 0;
|
||||
}
|
||||
|
||||
int
|
||||
H3BloomFilter::getIndex(const Address& addr)
|
||||
H3BloomFilter::getIndex(Addr addr)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -505,9 +505,9 @@ H3BloomFilter::print(ostream& out) const
|
|||
}
|
||||
|
||||
int
|
||||
H3BloomFilter::get_index(const Address& addr, int i)
|
||||
H3BloomFilter::get_index(Addr addr, int i)
|
||||
{
|
||||
uint64 x = addr.getLineAddress();
|
||||
uint64 x = makeLineAddress(addr);
|
||||
// uint64 y = (x*mults_list[i] + adds_list[i]) % primes_list[i];
|
||||
int y = hash_H3(x,i);
|
||||
|
||||
|
|
|
|||
|
|
@ -34,6 +34,7 @@
|
|||
#include <vector>
|
||||
|
||||
#include "mem/ruby/common/Address.hh"
|
||||
#include "mem/ruby/common/TypeDefines.hh"
|
||||
#include "mem/ruby/filters/AbstractBloomFilter.hh"
|
||||
|
||||
class H3BloomFilter : public AbstractBloomFilter
|
||||
|
|
@ -43,18 +44,18 @@ class H3BloomFilter : public AbstractBloomFilter
|
|||
~H3BloomFilter();
|
||||
|
||||
void clear();
|
||||
void increment(const Address& addr);
|
||||
void decrement(const Address& addr);
|
||||
void increment(Addr addr);
|
||||
void decrement(Addr addr);
|
||||
void merge(AbstractBloomFilter * other_filter);
|
||||
void set(const Address& addr);
|
||||
void unset(const Address& addr);
|
||||
void set(Addr addr);
|
||||
void unset(Addr addr);
|
||||
|
||||
bool isSet(const Address& addr);
|
||||
int getCount(const Address& addr);
|
||||
bool isSet(Addr addr);
|
||||
int getCount(Addr addr);
|
||||
int getTotalCount();
|
||||
void print(std::ostream& out) const;
|
||||
|
||||
int getIndex(const Address& addr);
|
||||
int getIndex(Addr addr);
|
||||
int readBit(const int index);
|
||||
void writeBit(const int index, const int value);
|
||||
|
||||
|
|
@ -65,7 +66,7 @@ class H3BloomFilter : public AbstractBloomFilter
|
|||
}
|
||||
|
||||
private:
|
||||
int get_index(const Address& addr, int hashNumber);
|
||||
int get_index(Addr addr, int hashNumber);
|
||||
|
||||
int hash_H3(uint64 value, int index);
|
||||
|
||||
|
|
|
|||
|
|
@ -65,7 +65,7 @@ LSB_CountingBloomFilter::clear()
|
|||
}
|
||||
|
||||
void
|
||||
LSB_CountingBloomFilter::increment(const Address& addr)
|
||||
LSB_CountingBloomFilter::increment(Addr addr)
|
||||
{
|
||||
int i = get_index(addr);
|
||||
if (m_filter[i] < m_count)
|
||||
|
|
@ -74,7 +74,7 @@ LSB_CountingBloomFilter::increment(const Address& addr)
|
|||
|
||||
|
||||
void
|
||||
LSB_CountingBloomFilter::decrement(const Address& addr)
|
||||
LSB_CountingBloomFilter::decrement(Addr addr)
|
||||
{
|
||||
int i = get_index(addr);
|
||||
if (m_filter[i] > 0)
|
||||
|
|
@ -88,26 +88,26 @@ LSB_CountingBloomFilter::merge(AbstractBloomFilter * other_filter)
|
|||
}
|
||||
|
||||
void
|
||||
LSB_CountingBloomFilter::set(const Address& addr)
|
||||
LSB_CountingBloomFilter::set(Addr addr)
|
||||
{
|
||||
// TODO
|
||||
}
|
||||
|
||||
void
|
||||
LSB_CountingBloomFilter::unset(const Address& addr)
|
||||
LSB_CountingBloomFilter::unset(Addr addr)
|
||||
{
|
||||
// TODO
|
||||
}
|
||||
|
||||
bool
|
||||
LSB_CountingBloomFilter::isSet(const Address& addr)
|
||||
LSB_CountingBloomFilter::isSet(Addr addr)
|
||||
{
|
||||
// TODO
|
||||
return false;
|
||||
}
|
||||
|
||||
int
|
||||
LSB_CountingBloomFilter::getCount(const Address& addr)
|
||||
LSB_CountingBloomFilter::getCount(Addr addr)
|
||||
{
|
||||
return m_filter[get_index(addr)];
|
||||
}
|
||||
|
|
@ -124,7 +124,7 @@ LSB_CountingBloomFilter::getTotalCount()
|
|||
}
|
||||
|
||||
int
|
||||
LSB_CountingBloomFilter::getIndex(const Address& addr)
|
||||
LSB_CountingBloomFilter::getIndex(Addr addr)
|
||||
{
|
||||
return get_index(addr);
|
||||
}
|
||||
|
|
@ -148,9 +148,9 @@ LSB_CountingBloomFilter::writeBit(const int index, const int value)
|
|||
}
|
||||
|
||||
int
|
||||
LSB_CountingBloomFilter::get_index(const Address& addr)
|
||||
LSB_CountingBloomFilter::get_index(Addr addr)
|
||||
{
|
||||
return addr.bitSelect(RubySystem::getBlockSizeBits(),
|
||||
return bitSelect(addr, RubySystem::getBlockSizeBits(),
|
||||
RubySystem::getBlockSizeBits() +
|
||||
m_filter_size_bits - 1);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -43,23 +43,23 @@ class LSB_CountingBloomFilter : public AbstractBloomFilter
|
|||
~LSB_CountingBloomFilter();
|
||||
|
||||
void clear();
|
||||
void increment(const Address& addr);
|
||||
void decrement(const Address& addr);
|
||||
void increment(Addr addr);
|
||||
void decrement(Addr addr);
|
||||
void merge(AbstractBloomFilter * other_filter);
|
||||
void set(const Address& addr);
|
||||
void unset(const Address& addr);
|
||||
void set(Addr addr);
|
||||
void unset(Addr addr);
|
||||
|
||||
bool isSet(const Address& addr);
|
||||
int getCount(const Address& addr);
|
||||
bool isSet(Addr addr);
|
||||
int getCount(Addr addr);
|
||||
int getTotalCount();
|
||||
int getIndex(const Address& addr);
|
||||
int getIndex(Addr addr);
|
||||
int readBit(const int index);
|
||||
void writeBit(const int index, const int value);
|
||||
|
||||
void print(std::ostream& out) const;
|
||||
|
||||
private:
|
||||
int get_index(const Address& addr);
|
||||
int get_index(Addr addr);
|
||||
|
||||
std::vector<int> m_filter;
|
||||
int m_filter_size;
|
||||
|
|
|
|||
|
|
@ -76,14 +76,14 @@ MultiBitSelBloomFilter::clear()
|
|||
}
|
||||
|
||||
void
|
||||
MultiBitSelBloomFilter::increment(const Address& addr)
|
||||
MultiBitSelBloomFilter::increment(Addr addr)
|
||||
{
|
||||
// Not used
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
MultiBitSelBloomFilter::decrement(const Address& addr)
|
||||
MultiBitSelBloomFilter::decrement(Addr addr)
|
||||
{
|
||||
// Not used
|
||||
}
|
||||
|
|
@ -99,7 +99,7 @@ MultiBitSelBloomFilter::merge(AbstractBloomFilter *other_filter)
|
|||
}
|
||||
|
||||
void
|
||||
MultiBitSelBloomFilter::set(const Address& addr)
|
||||
MultiBitSelBloomFilter::set(Addr addr)
|
||||
{
|
||||
for (int i = 0; i < m_num_hashes; i++) {
|
||||
int idx = get_index(addr, i);
|
||||
|
|
@ -108,14 +108,14 @@ MultiBitSelBloomFilter::set(const Address& addr)
|
|||
}
|
||||
|
||||
void
|
||||
MultiBitSelBloomFilter::unset(const Address& addr)
|
||||
MultiBitSelBloomFilter::unset(Addr addr)
|
||||
{
|
||||
cout << "ERROR: Unset should never be called in a Bloom filter";
|
||||
assert(0);
|
||||
}
|
||||
|
||||
bool
|
||||
MultiBitSelBloomFilter::isSet(const Address& addr)
|
||||
MultiBitSelBloomFilter::isSet(Addr addr)
|
||||
{
|
||||
bool res = true;
|
||||
|
||||
|
|
@ -127,13 +127,13 @@ MultiBitSelBloomFilter::isSet(const Address& addr)
|
|||
}
|
||||
|
||||
int
|
||||
MultiBitSelBloomFilter::getCount(const Address& addr)
|
||||
MultiBitSelBloomFilter::getCount(Addr addr)
|
||||
{
|
||||
return isSet(addr)? 1: 0;
|
||||
}
|
||||
|
||||
int
|
||||
MultiBitSelBloomFilter::getIndex(const Address& addr)
|
||||
MultiBitSelBloomFilter::getIndex(Addr addr)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -166,12 +166,12 @@ MultiBitSelBloomFilter::print(ostream& out) const
|
|||
}
|
||||
|
||||
int
|
||||
MultiBitSelBloomFilter::get_index(const Address& addr, int i)
|
||||
MultiBitSelBloomFilter::get_index(Addr addr, int i)
|
||||
{
|
||||
// m_skip_bits is used to perform BitSelect after skipping some
|
||||
// bits. Used to simulate BitSel hashing on larger than cache-line
|
||||
// granularities
|
||||
uint64 x = (addr.getLineAddress()) >> m_skip_bits;
|
||||
uint64 x = (makeLineAddress(addr) >> m_skip_bits);
|
||||
int y = hash_bitsel(x, i, m_num_hashes, 30, m_filter_size_bits);
|
||||
//36-bit addresses, 6-bit cache lines
|
||||
|
||||
|
|
|
|||
|
|
@ -34,6 +34,7 @@
|
|||
#include <vector>
|
||||
|
||||
#include "mem/ruby/common/Address.hh"
|
||||
#include "mem/ruby/common/TypeDefines.hh"
|
||||
#include "mem/ruby/filters/AbstractBloomFilter.hh"
|
||||
|
||||
class MultiBitSelBloomFilter : public AbstractBloomFilter
|
||||
|
|
@ -43,18 +44,18 @@ class MultiBitSelBloomFilter : public AbstractBloomFilter
|
|||
~MultiBitSelBloomFilter();
|
||||
|
||||
void clear();
|
||||
void increment(const Address& addr);
|
||||
void decrement(const Address& addr);
|
||||
void increment(Addr addr);
|
||||
void decrement(Addr addr);
|
||||
void merge(AbstractBloomFilter * other_filter);
|
||||
void set(const Address& addr);
|
||||
void unset(const Address& addr);
|
||||
void set(Addr addr);
|
||||
void unset(Addr addr);
|
||||
|
||||
bool isSet(const Address& addr);
|
||||
int getCount(const Address& addr);
|
||||
bool isSet(Addr addr);
|
||||
int getCount(Addr addr);
|
||||
int getTotalCount();
|
||||
void print(std::ostream& out) const;
|
||||
|
||||
int getIndex(const Address& addr);
|
||||
int getIndex(Addr addr);
|
||||
int readBit(const int index);
|
||||
void writeBit(const int index, const int value);
|
||||
|
||||
|
|
@ -65,7 +66,7 @@ class MultiBitSelBloomFilter : public AbstractBloomFilter
|
|||
}
|
||||
|
||||
private:
|
||||
int get_index(const Address& addr, int hashNumber);
|
||||
int get_index(Addr addr, int hashNumber);
|
||||
|
||||
int hash_bitsel(uint64 value, int index, int jump, int maxBits,
|
||||
int numBits);
|
||||
|
|
|
|||
|
|
@ -72,14 +72,14 @@ MultiGrainBloomFilter::clear()
|
|||
}
|
||||
|
||||
void
|
||||
MultiGrainBloomFilter::increment(const Address& addr)
|
||||
MultiGrainBloomFilter::increment(Addr addr)
|
||||
{
|
||||
// Not used
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
MultiGrainBloomFilter::decrement(const Address& addr)
|
||||
MultiGrainBloomFilter::decrement(Addr addr)
|
||||
{
|
||||
// Not used
|
||||
}
|
||||
|
|
@ -91,7 +91,7 @@ MultiGrainBloomFilter::merge(AbstractBloomFilter *other_filter)
|
|||
}
|
||||
|
||||
void
|
||||
MultiGrainBloomFilter::set(const Address& addr)
|
||||
MultiGrainBloomFilter::set(Addr addr)
|
||||
{
|
||||
int i = get_block_index(addr);
|
||||
assert(i < m_filter_size);
|
||||
|
|
@ -102,13 +102,13 @@ MultiGrainBloomFilter::set(const Address& addr)
|
|||
}
|
||||
|
||||
void
|
||||
MultiGrainBloomFilter::unset(const Address& addr)
|
||||
MultiGrainBloomFilter::unset(Addr addr)
|
||||
{
|
||||
// not used
|
||||
}
|
||||
|
||||
bool
|
||||
MultiGrainBloomFilter::isSet(const Address& addr)
|
||||
MultiGrainBloomFilter::isSet(Addr addr)
|
||||
{
|
||||
int i = get_block_index(addr);
|
||||
assert(i < m_filter_size);
|
||||
|
|
@ -118,7 +118,7 @@ MultiGrainBloomFilter::isSet(const Address& addr)
|
|||
}
|
||||
|
||||
int
|
||||
MultiGrainBloomFilter::getCount(const Address& addr)
|
||||
MultiGrainBloomFilter::getCount(Addr addr)
|
||||
{
|
||||
// not used
|
||||
return 0;
|
||||
|
|
@ -141,7 +141,7 @@ MultiGrainBloomFilter::getTotalCount()
|
|||
}
|
||||
|
||||
int
|
||||
MultiGrainBloomFilter::getIndex(const Address& addr)
|
||||
MultiGrainBloomFilter::getIndex(Addr addr)
|
||||
{
|
||||
return 0;
|
||||
// TODO
|
||||
|
|
@ -166,21 +166,21 @@ MultiGrainBloomFilter::print(ostream& out) const
|
|||
}
|
||||
|
||||
int
|
||||
MultiGrainBloomFilter::get_block_index(const Address& addr)
|
||||
MultiGrainBloomFilter::get_block_index(Addr addr)
|
||||
{
|
||||
// grap a chunk of bits after byte offset
|
||||
return addr.bitSelect(RubySystem::getBlockSizeBits(),
|
||||
return bitSelect(addr, RubySystem::getBlockSizeBits(),
|
||||
RubySystem::getBlockSizeBits() +
|
||||
m_filter_size_bits - 1);
|
||||
}
|
||||
|
||||
int
|
||||
MultiGrainBloomFilter::get_page_index(const Address & addr)
|
||||
MultiGrainBloomFilter::get_page_index(Addr addr)
|
||||
{
|
||||
int bits = RubySystem::getBlockSizeBits() + m_filter_size_bits - 1;
|
||||
|
||||
// grap a chunk of bits after first chunk
|
||||
return addr.bitSelect(bits, bits + m_page_filter_size_bits - 1);
|
||||
return bitSelect(addr, bits, bits + m_page_filter_size_bits - 1);
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -43,24 +43,24 @@ class MultiGrainBloomFilter : public AbstractBloomFilter
|
|||
~MultiGrainBloomFilter();
|
||||
|
||||
void clear();
|
||||
void increment(const Address& addr);
|
||||
void decrement(const Address& addr);
|
||||
void increment(Addr addr);
|
||||
void decrement(Addr addr);
|
||||
void merge(AbstractBloomFilter * other_filter);
|
||||
void set(const Address& addr);
|
||||
void unset(const Address& addr);
|
||||
void set(Addr addr);
|
||||
void unset(Addr addr);
|
||||
|
||||
bool isSet(const Address& addr);
|
||||
int getCount(const Address& addr);
|
||||
bool isSet(Addr addr);
|
||||
int getCount(Addr addr);
|
||||
int getTotalCount();
|
||||
int getIndex(const Address& addr);
|
||||
int getIndex(Addr addr);
|
||||
int readBit(const int index);
|
||||
void writeBit(const int index, const int value);
|
||||
|
||||
void print(std::ostream& out) const;
|
||||
|
||||
private:
|
||||
int get_block_index(const Address& addr);
|
||||
int get_page_index(const Address & addr);
|
||||
int get_block_index(Addr addr);
|
||||
int get_page_index(Addr addr);
|
||||
|
||||
// The block filter
|
||||
std::vector<int> m_filter;
|
||||
|
|
|
|||
|
|
@ -64,13 +64,13 @@ NonCountingBloomFilter::clear()
|
|||
}
|
||||
|
||||
void
|
||||
NonCountingBloomFilter::increment(const Address& addr)
|
||||
NonCountingBloomFilter::increment(Addr addr)
|
||||
{
|
||||
// Not used
|
||||
}
|
||||
|
||||
void
|
||||
NonCountingBloomFilter::decrement(const Address& addr)
|
||||
NonCountingBloomFilter::decrement(Addr addr)
|
||||
{
|
||||
// Not used
|
||||
}
|
||||
|
|
@ -86,21 +86,21 @@ NonCountingBloomFilter::merge(AbstractBloomFilter *other_filter)
|
|||
}
|
||||
|
||||
void
|
||||
NonCountingBloomFilter::set(const Address& addr)
|
||||
NonCountingBloomFilter::set(Addr addr)
|
||||
{
|
||||
int i = get_index(addr);
|
||||
m_filter[i] = 1;
|
||||
}
|
||||
|
||||
void
|
||||
NonCountingBloomFilter::unset(const Address& addr)
|
||||
NonCountingBloomFilter::unset(Addr addr)
|
||||
{
|
||||
int i = get_index(addr);
|
||||
m_filter[i] = 0;
|
||||
}
|
||||
|
||||
bool
|
||||
NonCountingBloomFilter::isSet(const Address& addr)
|
||||
NonCountingBloomFilter::isSet(Addr addr)
|
||||
{
|
||||
int i = get_index(addr);
|
||||
return (m_filter[i]);
|
||||
|
|
@ -108,7 +108,7 @@ NonCountingBloomFilter::isSet(const Address& addr)
|
|||
|
||||
|
||||
int
|
||||
NonCountingBloomFilter::getCount(const Address& addr)
|
||||
NonCountingBloomFilter::getCount(Addr addr)
|
||||
{
|
||||
return m_filter[get_index(addr)];
|
||||
}
|
||||
|
|
@ -130,7 +130,7 @@ NonCountingBloomFilter::print(ostream& out) const
|
|||
}
|
||||
|
||||
int
|
||||
NonCountingBloomFilter::getIndex(const Address& addr)
|
||||
NonCountingBloomFilter::getIndex(Addr addr)
|
||||
{
|
||||
return get_index(addr);
|
||||
}
|
||||
|
|
@ -148,9 +148,9 @@ NonCountingBloomFilter::writeBit(const int index, const int value)
|
|||
}
|
||||
|
||||
int
|
||||
NonCountingBloomFilter::get_index(const Address& addr)
|
||||
NonCountingBloomFilter::get_index(Addr addr)
|
||||
{
|
||||
return addr.bitSelect(RubySystem::getBlockSizeBits() + m_offset,
|
||||
return bitSelect(addr, RubySystem::getBlockSizeBits() + m_offset,
|
||||
RubySystem::getBlockSizeBits() + m_offset +
|
||||
m_filter_size_bits - 1);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -43,17 +43,17 @@ class NonCountingBloomFilter : public AbstractBloomFilter
|
|||
~NonCountingBloomFilter();
|
||||
|
||||
void clear();
|
||||
void increment(const Address& addr);
|
||||
void decrement(const Address& addr);
|
||||
void increment(Addr addr);
|
||||
void decrement(Addr addr);
|
||||
void merge(AbstractBloomFilter * other_filter);
|
||||
void set(const Address& addr);
|
||||
void unset(const Address& addr);
|
||||
void set(Addr addr);
|
||||
void unset(Addr addr);
|
||||
|
||||
bool isSet(const Address& addr);
|
||||
int getCount(const Address& addr);
|
||||
bool isSet(Addr addr);
|
||||
int getCount(Addr addr);
|
||||
int getTotalCount();
|
||||
|
||||
int getIndex(const Address& addr);
|
||||
int getIndex(Addr addr);
|
||||
int readBit(const int index);
|
||||
void writeBit(const int index, const int value);
|
||||
|
||||
|
|
@ -66,7 +66,7 @@ class NonCountingBloomFilter : public AbstractBloomFilter
|
|||
}
|
||||
|
||||
private:
|
||||
int get_index(const Address& addr);
|
||||
int get_index(Addr addr);
|
||||
|
||||
std::vector<int> m_filter;
|
||||
int m_filter_size;
|
||||
|
|
|
|||
|
|
@ -289,7 +289,7 @@ MessageBuffer::reanalyzeList(list<MsgPtr> <, Tick schdTick)
|
|||
}
|
||||
|
||||
void
|
||||
MessageBuffer::reanalyzeMessages(const Address& addr)
|
||||
MessageBuffer::reanalyzeMessages(Addr addr)
|
||||
{
|
||||
DPRINTF(RubyQueue, "ReanalyzeMessages %s\n", addr);
|
||||
assert(m_stall_msg_map.count(addr) > 0);
|
||||
|
|
@ -325,11 +325,11 @@ MessageBuffer::reanalyzeAllMessages()
|
|||
}
|
||||
|
||||
void
|
||||
MessageBuffer::stallMessage(const Address& addr)
|
||||
MessageBuffer::stallMessage(Addr addr)
|
||||
{
|
||||
DPRINTF(RubyQueue, "Stalling due to %s\n", addr);
|
||||
assert(isReady());
|
||||
assert(addr.getOffset() == 0);
|
||||
assert(getOffset(addr) == 0);
|
||||
MsgPtr message = m_prio_heap.front();
|
||||
|
||||
dequeue();
|
||||
|
|
|
|||
|
|
@ -55,9 +55,9 @@ class MessageBuffer : public SimObject
|
|||
typedef MessageBufferParams Params;
|
||||
MessageBuffer(const Params *p);
|
||||
|
||||
void reanalyzeMessages(const Address& addr);
|
||||
void reanalyzeMessages(Addr addr);
|
||||
void reanalyzeAllMessages();
|
||||
void stallMessage(const Address& addr);
|
||||
void stallMessage(Addr addr);
|
||||
|
||||
// TRUE if head of queue timestamp <= SystemTime
|
||||
bool isReady() const;
|
||||
|
|
@ -165,7 +165,7 @@ class MessageBuffer : public SimObject
|
|||
|
||||
// use a std::map for the stalled messages as this container is
|
||||
// sorted and ensures a well-defined iteration order
|
||||
typedef std::map< Address, std::list<MsgPtr> > StallMsgMapType;
|
||||
typedef std::map<Addr, std::list<MsgPtr> > StallMsgMapType;
|
||||
|
||||
StallMsgMapType m_stall_msg_map;
|
||||
|
||||
|
|
|
|||
|
|
@ -47,13 +47,13 @@ class AccessTraceForAddress
|
|||
{ }
|
||||
~AccessTraceForAddress();
|
||||
|
||||
void setAddress(const Address& addr) { m_addr = addr; }
|
||||
void setAddress(Addr addr) { m_addr = addr; }
|
||||
void update(RubyRequestType type, RubyAccessMode access_mode, NodeID cpu,
|
||||
bool sharing_miss);
|
||||
int getTotal() const;
|
||||
int getSharing() const { return m_sharing; }
|
||||
int getTouchedBy() const { return m_touched_by.count(); }
|
||||
const Address& getAddress() const { return m_addr; }
|
||||
Addr getAddress() const { return m_addr; }
|
||||
void addSample(int value);
|
||||
|
||||
void print(std::ostream& out) const;
|
||||
|
|
@ -66,7 +66,7 @@ class AccessTraceForAddress
|
|||
}
|
||||
|
||||
private:
|
||||
Address m_addr;
|
||||
Addr m_addr;
|
||||
uint64 m_loads;
|
||||
uint64 m_stores;
|
||||
uint64 m_atomics;
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@ using m5::stl_helpers::operator<<;
|
|||
|
||||
// Helper functions
|
||||
AccessTraceForAddress&
|
||||
lookupTraceForAddress(const Address& addr, AddressMap& record_map)
|
||||
lookupTraceForAddress(Addr addr, AddressMap& record_map)
|
||||
{
|
||||
// we create a static default object here that is used to insert
|
||||
// since the insertion will create a copy of the object in the
|
||||
|
|
@ -244,7 +244,7 @@ AddressProfiler::clearStats()
|
|||
}
|
||||
|
||||
void
|
||||
AddressProfiler::profileGetX(const Address& datablock, const Address& PC,
|
||||
AddressProfiler::profileGetX(Addr datablock, Addr PC,
|
||||
const Set& owner, const Set& sharers,
|
||||
NodeID requestor)
|
||||
{
|
||||
|
|
@ -262,7 +262,7 @@ AddressProfiler::profileGetX(const Address& datablock, const Address& PC,
|
|||
}
|
||||
|
||||
void
|
||||
AddressProfiler::profileGetS(const Address& datablock, const Address& PC,
|
||||
AddressProfiler::profileGetS(Addr datablock, Addr PC,
|
||||
const Set& owner, const Set& sharers,
|
||||
NodeID requestor)
|
||||
{
|
||||
|
|
@ -279,7 +279,7 @@ AddressProfiler::profileGetS(const Address& datablock, const Address& PC,
|
|||
}
|
||||
|
||||
void
|
||||
AddressProfiler::addTraceSample(Address data_addr, Address pc_addr,
|
||||
AddressProfiler::addTraceSample(Addr data_addr, Addr pc_addr,
|
||||
RubyRequestType type,
|
||||
RubyAccessMode access_mode, NodeID id,
|
||||
bool sharing_miss)
|
||||
|
|
@ -290,14 +290,14 @@ AddressProfiler::addTraceSample(Address data_addr, Address pc_addr,
|
|||
}
|
||||
|
||||
// record data address trace info
|
||||
data_addr.makeLineAddress();
|
||||
data_addr = makeLineAddress(data_addr);
|
||||
lookupTraceForAddress(data_addr, m_dataAccessTrace).
|
||||
update(type, access_mode, id, sharing_miss);
|
||||
|
||||
// record macro data address trace info
|
||||
|
||||
// 6 for datablock, 4 to make it 16x more coarse
|
||||
Address macro_addr(data_addr.maskLowOrderBits(10));
|
||||
Addr macro_addr = maskLowOrderBits(data_addr, 10);
|
||||
lookupTraceForAddress(macro_addr, m_macroBlockAccessTrace).
|
||||
update(type, access_mode, id, sharing_miss);
|
||||
|
||||
|
|
@ -316,8 +316,7 @@ AddressProfiler::addTraceSample(Address data_addr, Address pc_addr,
|
|||
}
|
||||
|
||||
void
|
||||
AddressProfiler::profileRetry(const Address& data_addr, AccessType type,
|
||||
int count)
|
||||
AddressProfiler::profileRetry(Addr data_addr, AccessType type, int count)
|
||||
{
|
||||
m_retryProfileHisto.add(count);
|
||||
if (type == AccessType_Read) {
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@ class Set;
|
|||
class AddressProfiler
|
||||
{
|
||||
public:
|
||||
typedef m5::hash_map<Address, AccessTraceForAddress> AddressMap;
|
||||
typedef m5::hash_map<Addr, AccessTraceForAddress> AddressMap;
|
||||
|
||||
public:
|
||||
AddressProfiler(int num_of_sequencers, Profiler *profiler);
|
||||
|
|
@ -53,13 +53,13 @@ class AddressProfiler
|
|||
void printStats(std::ostream& out) const;
|
||||
void clearStats();
|
||||
|
||||
void addTraceSample(Address data_addr, Address pc_addr,
|
||||
void addTraceSample(Addr data_addr, Addr pc_addr,
|
||||
RubyRequestType type, RubyAccessMode access_mode,
|
||||
NodeID id, bool sharing_miss);
|
||||
void profileRetry(const Address& data_addr, AccessType type, int count);
|
||||
void profileGetX(const Address& datablock, const Address& PC,
|
||||
void profileRetry(Addr data_addr, AccessType type, int count);
|
||||
void profileGetX(Addr datablock, Addr PC,
|
||||
const Set& owner, const Set& sharers, NodeID requestor);
|
||||
void profileGetS(const Address& datablock, const Address& PC,
|
||||
void profileGetS(Addr datablock, Addr PC,
|
||||
const Set& owner, const Set& sharers, NodeID requestor);
|
||||
|
||||
void print(std::ostream& out) const;
|
||||
|
|
@ -96,7 +96,7 @@ class AddressProfiler
|
|||
int m_num_of_sequencers;
|
||||
};
|
||||
|
||||
AccessTraceForAddress& lookupTraceForAddress(const Address& addr,
|
||||
AccessTraceForAddress& lookupTraceForAddress(Addr addr,
|
||||
AddressProfiler::AddressMap&
|
||||
record_map);
|
||||
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@ Histogram* StoreTrace::s_store_first_to_stolen_ptr = NULL;
|
|||
Histogram* StoreTrace::s_store_last_to_stolen_ptr = NULL;
|
||||
Histogram* StoreTrace::s_store_first_to_last_ptr = NULL;
|
||||
|
||||
StoreTrace::StoreTrace(const Address& addr)
|
||||
StoreTrace::StoreTrace(Addr addr)
|
||||
: m_store_count(-1), m_store_first_to_stolen(-1),
|
||||
m_store_last_to_stolen(-1), m_store_first_to_last(-1)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@ class StoreTrace
|
|||
{
|
||||
public:
|
||||
StoreTrace() { }
|
||||
explicit StoreTrace(const Address& addr);
|
||||
explicit StoreTrace(Addr addr);
|
||||
~StoreTrace();
|
||||
|
||||
void store(NodeID node);
|
||||
|
|
@ -60,7 +60,7 @@ class StoreTrace
|
|||
static Histogram* s_store_last_to_stolen_ptr;
|
||||
static Histogram* s_store_first_to_last_ptr;
|
||||
|
||||
Address m_addr;
|
||||
Addr m_addr;
|
||||
NodeID m_last_writer;
|
||||
Tick m_first_store;
|
||||
Tick m_last_store;
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@
|
|||
AbstractCacheEntry::AbstractCacheEntry()
|
||||
{
|
||||
m_Permission = AccessPermission_NotPresent;
|
||||
m_Address.setAddress(0);
|
||||
m_Address = 0;
|
||||
m_locked = -1;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -57,7 +57,7 @@ class AbstractCacheEntry : public AbstractEntry
|
|||
{ panic("getDataBlk() not implemented!"); }
|
||||
|
||||
|
||||
Address m_Address; // Address of this block, required by CacheMemory
|
||||
Addr m_Address; // Address of this block, required by CacheMemory
|
||||
int m_locked; // Holds info whether the address is locked,
|
||||
// required for implementing LL/SC
|
||||
};
|
||||
|
|
|
|||
|
|
@ -93,7 +93,7 @@ AbstractController::profileMsgDelay(uint32_t virtualNetwork, Cycles delay)
|
|||
}
|
||||
|
||||
void
|
||||
AbstractController::stallBuffer(MessageBuffer* buf, Address addr)
|
||||
AbstractController::stallBuffer(MessageBuffer* buf, Addr addr)
|
||||
{
|
||||
if (m_waiting_buffers.count(addr) == 0) {
|
||||
MsgVecType* msgVec = new MsgVecType;
|
||||
|
|
@ -107,7 +107,7 @@ AbstractController::stallBuffer(MessageBuffer* buf, Address addr)
|
|||
}
|
||||
|
||||
void
|
||||
AbstractController::wakeUpBuffers(Address addr)
|
||||
AbstractController::wakeUpBuffers(Addr addr)
|
||||
{
|
||||
if (m_waiting_buffers.count(addr) > 0) {
|
||||
//
|
||||
|
|
@ -127,7 +127,7 @@ AbstractController::wakeUpBuffers(Address addr)
|
|||
}
|
||||
|
||||
void
|
||||
AbstractController::wakeUpAllBuffers(Address addr)
|
||||
AbstractController::wakeUpAllBuffers(Addr addr)
|
||||
{
|
||||
if (m_waiting_buffers.count(addr) > 0) {
|
||||
//
|
||||
|
|
@ -186,14 +186,14 @@ AbstractController::wakeUpAllBuffers()
|
|||
}
|
||||
|
||||
void
|
||||
AbstractController::blockOnQueue(Address addr, MessageBuffer* port)
|
||||
AbstractController::blockOnQueue(Addr addr, MessageBuffer* port)
|
||||
{
|
||||
m_is_blocking = true;
|
||||
m_block_map[addr] = port;
|
||||
}
|
||||
|
||||
void
|
||||
AbstractController::unblock(Address addr)
|
||||
AbstractController::unblock(Addr addr)
|
||||
{
|
||||
m_block_map.erase(addr);
|
||||
if (m_block_map.size() == 0) {
|
||||
|
|
@ -209,11 +209,10 @@ AbstractController::getMasterPort(const std::string &if_name,
|
|||
}
|
||||
|
||||
void
|
||||
AbstractController::queueMemoryRead(const MachineID &id, Address addr,
|
||||
AbstractController::queueMemoryRead(const MachineID &id, Addr addr,
|
||||
Cycles latency)
|
||||
{
|
||||
RequestPtr req = new Request(addr.getAddress(),
|
||||
RubySystem::getBlockSizeBytes(), 0,
|
||||
RequestPtr req = new Request(addr, RubySystem::getBlockSizeBytes(), 0,
|
||||
m_masterId);
|
||||
|
||||
PacketPtr pkt = Packet::createRead(req);
|
||||
|
|
@ -234,11 +233,10 @@ AbstractController::queueMemoryRead(const MachineID &id, Address addr,
|
|||
}
|
||||
|
||||
void
|
||||
AbstractController::queueMemoryWrite(const MachineID &id, Address addr,
|
||||
AbstractController::queueMemoryWrite(const MachineID &id, Addr addr,
|
||||
Cycles latency, const DataBlock &block)
|
||||
{
|
||||
RequestPtr req = new Request(addr.getAddress(),
|
||||
RubySystem::getBlockSizeBytes(), 0,
|
||||
RequestPtr req = new Request(addr, RubySystem::getBlockSizeBytes(), 0,
|
||||
m_masterId);
|
||||
|
||||
PacketPtr pkt = Packet::createWrite(req);
|
||||
|
|
@ -262,18 +260,17 @@ AbstractController::queueMemoryWrite(const MachineID &id, Address addr,
|
|||
}
|
||||
|
||||
void
|
||||
AbstractController::queueMemoryWritePartial(const MachineID &id, Address addr,
|
||||
AbstractController::queueMemoryWritePartial(const MachineID &id, Addr addr,
|
||||
Cycles latency,
|
||||
const DataBlock &block, int size)
|
||||
{
|
||||
RequestPtr req = new Request(addr.getAddress(),
|
||||
RubySystem::getBlockSizeBytes(), 0,
|
||||
RequestPtr req = new Request(addr, RubySystem::getBlockSizeBytes(), 0,
|
||||
m_masterId);
|
||||
|
||||
PacketPtr pkt = Packet::createWrite(req);
|
||||
uint8_t *newData = new uint8_t[size];
|
||||
pkt->dataDynamic(newData);
|
||||
memcpy(newData, block.getData(addr.getOffset(), size), size);
|
||||
memcpy(newData, block.getData(getOffset(addr), size), size);
|
||||
|
||||
SenderState *s = new SenderState(id);
|
||||
pkt->pushSenderState(s);
|
||||
|
|
@ -310,7 +307,7 @@ AbstractController::recvTimingResp(PacketPtr pkt)
|
|||
assert(pkt->isResponse());
|
||||
|
||||
std::shared_ptr<MemoryMsg> msg = std::make_shared<MemoryMsg>(clockEdge());
|
||||
(*msg).m_addr.setAddress(pkt->getAddr());
|
||||
(*msg).m_addr = pkt->getAddr();
|
||||
(*msg).m_Sender = m_machineID;
|
||||
|
||||
SenderState *s = dynamic_cast<SenderState *>(pkt->senderState);
|
||||
|
|
|
|||
|
|
@ -71,12 +71,12 @@ class AbstractController : public MemObject, public Consumer
|
|||
void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; }
|
||||
|
||||
// return instance name
|
||||
void blockOnQueue(Address, MessageBuffer*);
|
||||
void unblock(Address);
|
||||
void blockOnQueue(Addr, MessageBuffer*);
|
||||
void unblock(Addr);
|
||||
|
||||
virtual MessageBuffer* getMandatoryQueue() const = 0;
|
||||
virtual MessageBuffer* getMemoryQueue() const = 0;
|
||||
virtual AccessPermission getAccessPermission(const Address& addr) = 0;
|
||||
virtual AccessPermission getAccessPermission(const Addr &addr) = 0;
|
||||
|
||||
virtual void print(std::ostream & out) const = 0;
|
||||
virtual void wakeup() = 0;
|
||||
|
|
@ -88,16 +88,16 @@ class AbstractController : public MemObject, public Consumer
|
|||
|
||||
//! These functions are used by ruby system to read/write the data blocks
|
||||
//! that exist with in the controller.
|
||||
virtual void functionalRead(const Address &addr, PacketPtr) = 0;
|
||||
virtual void functionalRead(const Addr &addr, PacketPtr) = 0;
|
||||
void functionalMemoryRead(PacketPtr);
|
||||
//! The return value indicates the number of messages written with the
|
||||
//! data from the packet.
|
||||
virtual int functionalWriteBuffers(PacketPtr&) = 0;
|
||||
virtual int functionalWrite(const Address &addr, PacketPtr) = 0;
|
||||
virtual int functionalWrite(const Addr &addr, PacketPtr) = 0;
|
||||
int functionalMemoryWrite(PacketPtr);
|
||||
|
||||
//! Function for enqueuing a prefetch request
|
||||
virtual void enqueuePrefetch(const Address&, const RubyRequestType&)
|
||||
virtual void enqueuePrefetch(const Addr &, const RubyRequestType&)
|
||||
{ fatal("Prefetches not implemented!");}
|
||||
|
||||
//! Function for collating statistics from all the controllers of this
|
||||
|
|
@ -113,10 +113,10 @@ class AbstractController : public MemObject, public Consumer
|
|||
BaseMasterPort& getMasterPort(const std::string& if_name,
|
||||
PortID idx = InvalidPortID);
|
||||
|
||||
void queueMemoryRead(const MachineID &id, Address addr, Cycles latency);
|
||||
void queueMemoryWrite(const MachineID &id, Address addr, Cycles latency,
|
||||
void queueMemoryRead(const MachineID &id, Addr addr, Cycles latency);
|
||||
void queueMemoryWrite(const MachineID &id, Addr addr, Cycles latency,
|
||||
const DataBlock &block);
|
||||
void queueMemoryWritePartial(const MachineID &id, Address addr, Cycles latency,
|
||||
void queueMemoryWritePartial(const MachineID &id, Addr addr, Cycles latency,
|
||||
const DataBlock &block, int size);
|
||||
void recvTimingResp(PacketPtr pkt);
|
||||
|
||||
|
|
@ -133,9 +133,9 @@ class AbstractController : public MemObject, public Consumer
|
|||
//! Profiles the delay associated with messages.
|
||||
void profileMsgDelay(uint32_t virtualNetwork, Cycles delay);
|
||||
|
||||
void stallBuffer(MessageBuffer* buf, Address addr);
|
||||
void wakeUpBuffers(Address addr);
|
||||
void wakeUpAllBuffers(Address addr);
|
||||
void stallBuffer(MessageBuffer* buf, Addr addr);
|
||||
void wakeUpBuffers(Addr addr);
|
||||
void wakeUpAllBuffers(Addr addr);
|
||||
void wakeUpAllBuffers();
|
||||
|
||||
protected:
|
||||
|
|
@ -148,11 +148,11 @@ class AbstractController : public MemObject, public Consumer
|
|||
|
||||
Network* m_net_ptr;
|
||||
bool m_is_blocking;
|
||||
std::map<Address, MessageBuffer*> m_block_map;
|
||||
std::map<Addr, MessageBuffer*> m_block_map;
|
||||
|
||||
typedef std::vector<MessageBuffer*> MsgVecType;
|
||||
typedef std::set<MessageBuffer*> MsgBufType;
|
||||
typedef std::map< Address, MsgVecType* > WaitingBufType;
|
||||
typedef std::map<Addr, MsgVecType* > WaitingBufType;
|
||||
WaitingBufType m_waiting_buffers;
|
||||
|
||||
unsigned int m_in_ports;
|
||||
|
|
|
|||
|
|
@ -69,7 +69,7 @@ RubyRequest::functionalWrite(Packet *pkt)
|
|||
|
||||
Addr wBase = pkt->getAddr();
|
||||
Addr wTail = wBase + pkt->getSize();
|
||||
Addr mBase = m_PhysicalAddress.getAddress();
|
||||
Addr mBase = m_PhysicalAddress;
|
||||
Addr mTail = mBase + m_Size;
|
||||
|
||||
const uint8_t * pktData = pkt->getConstPtr<uint8_t>();
|
||||
|
|
|
|||
|
|
@ -40,10 +40,10 @@
|
|||
class RubyRequest : public Message
|
||||
{
|
||||
public:
|
||||
Address m_PhysicalAddress;
|
||||
Address m_LineAddress;
|
||||
Addr m_PhysicalAddress;
|
||||
Addr m_LineAddress;
|
||||
RubyRequestType m_Type;
|
||||
Address m_ProgramCounter;
|
||||
Addr m_ProgramCounter;
|
||||
RubyAccessMode m_AccessMode;
|
||||
int m_Size;
|
||||
PrefetchBit m_Prefetch;
|
||||
|
|
@ -66,18 +66,17 @@ class RubyRequest : public Message
|
|||
pkt(_pkt),
|
||||
m_contextId(_proc_id)
|
||||
{
|
||||
m_LineAddress = m_PhysicalAddress;
|
||||
m_LineAddress.makeLineAddress();
|
||||
m_LineAddress = makeLineAddress(m_PhysicalAddress);
|
||||
}
|
||||
|
||||
RubyRequest(Tick curTime) : Message(curTime) {}
|
||||
MsgPtr clone() const
|
||||
{ return std::shared_ptr<Message>(new RubyRequest(*this)); }
|
||||
|
||||
const Address& getLineAddress() const { return m_LineAddress; }
|
||||
const Address& getPhysicalAddress() const { return m_PhysicalAddress; }
|
||||
Addr getLineAddress() const { return m_LineAddress; }
|
||||
Addr getPhysicalAddress() const { return m_PhysicalAddress; }
|
||||
const RubyRequestType& getType() const { return m_Type; }
|
||||
const Address& getProgramCounter() const { return m_ProgramCounter; }
|
||||
Addr getProgramCounter() const { return m_ProgramCounter; }
|
||||
const RubyAccessMode& getAccessMode() const { return m_AccessMode; }
|
||||
const int& getSize() const { return m_Size; }
|
||||
const PrefetchBit& getPrefetch() const { return m_Prefetch; }
|
||||
|
|
@ -95,4 +94,4 @@ operator<<(std::ostream& out, const RubyRequest& obj)
|
|||
return out;
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif // __MEM_RUBY_SLICC_INTERFACE_RUBY_REQUEST_HH__
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@
|
|||
// used to determine the home directory
|
||||
// returns a value between 0 and total_directories_within_the_system
|
||||
inline NodeID
|
||||
map_Address_to_DirectoryNode(const Address& addr)
|
||||
map_Address_to_DirectoryNode(Addr addr)
|
||||
{
|
||||
return DirectoryMemory::mapAddressToDirectoryVersion(addr);
|
||||
}
|
||||
|
|
@ -46,7 +46,7 @@ map_Address_to_DirectoryNode(const Address& addr)
|
|||
// used to determine the home directory
|
||||
// returns a value between 0 and total_directories_within_the_system
|
||||
inline MachineID
|
||||
map_Address_to_Directory(const Address &addr)
|
||||
map_Address_to_Directory(Addr addr)
|
||||
{
|
||||
MachineID mach =
|
||||
{MachineType_Directory, map_Address_to_DirectoryNode(addr)};
|
||||
|
|
@ -65,14 +65,14 @@ broadcast(MachineType type)
|
|||
}
|
||||
|
||||
inline MachineID
|
||||
mapAddressToRange(const Address & addr, MachineType type, int low_bit,
|
||||
mapAddressToRange(Addr addr, MachineType type, int low_bit,
|
||||
int num_bits, int cluster_id = 0)
|
||||
{
|
||||
MachineID mach = {type, 0};
|
||||
if (num_bits == 0)
|
||||
mach.num = cluster_id;
|
||||
else
|
||||
mach.num = addr.bitSelect(low_bit, low_bit + num_bits - 1)
|
||||
mach.num = bitSelect(addr, low_bit, low_bit + num_bits - 1)
|
||||
+ (1 << num_bits) * cluster_id;
|
||||
return mach;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -36,9 +36,10 @@
|
|||
#include <cassert>
|
||||
|
||||
#include "debug/RubySlicc.hh"
|
||||
#include "mem/packet.hh"
|
||||
#include "mem/ruby/common/Address.hh"
|
||||
#include "mem/ruby/common/DataBlock.hh"
|
||||
#include "mem/packet.hh"
|
||||
#include "mem/ruby/common/TypeDefines.hh"
|
||||
|
||||
inline Cycles zero_time() { return Cycles(0); }
|
||||
|
||||
|
|
@ -57,35 +58,10 @@ IDToInt(NodeID id)
|
|||
}
|
||||
|
||||
inline int
|
||||
addressToInt(Address addr)
|
||||
addressToInt(Addr addr)
|
||||
{
|
||||
assert(!(addr.getAddress() & 0xffffffff00000000));
|
||||
|
||||
return (int)addr.getAddress();
|
||||
}
|
||||
|
||||
// Appends an offset to an address
|
||||
inline Address
|
||||
setOffset(Address addr, int offset)
|
||||
{
|
||||
Address result = addr;
|
||||
result.setOffset(offset);
|
||||
return result;
|
||||
}
|
||||
|
||||
// Makes an address into a line address
|
||||
inline Address
|
||||
makeLineAddress(Address addr)
|
||||
{
|
||||
Address result = addr;
|
||||
result.makeLineAddress();
|
||||
return result;
|
||||
}
|
||||
|
||||
inline int
|
||||
addressOffset(Address addr)
|
||||
{
|
||||
return addr.getOffset();
|
||||
assert(!(addr & 0xffffffff00000000));
|
||||
return addr;
|
||||
}
|
||||
|
||||
inline int
|
||||
|
|
@ -106,18 +82,15 @@ inline int max_tokens()
|
|||
* returned if the data block was read, otherwise false is returned.
|
||||
*/
|
||||
inline bool
|
||||
testAndRead(Address addr, DataBlock& blk, Packet *pkt)
|
||||
testAndRead(Addr addr, DataBlock& blk, Packet *pkt)
|
||||
{
|
||||
Address pktLineAddr(pkt->getAddr());
|
||||
pktLineAddr.makeLineAddress();
|
||||
|
||||
Address lineAddr = addr;
|
||||
lineAddr.makeLineAddress();
|
||||
Addr pktLineAddr = makeLineAddress(pkt->getAddr());
|
||||
Addr lineAddr = makeLineAddress(addr);
|
||||
|
||||
if (pktLineAddr == lineAddr) {
|
||||
uint8_t *data = pkt->getPtr<uint8_t>();
|
||||
unsigned int size_in_bytes = pkt->getSize();
|
||||
unsigned startByte = pkt->getAddr() - lineAddr.getAddress();
|
||||
unsigned startByte = pkt->getAddr() - lineAddr;
|
||||
|
||||
for (unsigned i = 0; i < size_in_bytes; ++i) {
|
||||
data[i] = blk.getByte(i + startByte);
|
||||
|
|
@ -134,18 +107,15 @@ testAndRead(Address addr, DataBlock& blk, Packet *pkt)
|
|||
* returned if the data block was written, otherwise false is returned.
|
||||
*/
|
||||
inline bool
|
||||
testAndWrite(Address addr, DataBlock& blk, Packet *pkt)
|
||||
testAndWrite(Addr addr, DataBlock& blk, Packet *pkt)
|
||||
{
|
||||
Address pktLineAddr(pkt->getAddr());
|
||||
pktLineAddr.makeLineAddress();
|
||||
|
||||
Address lineAddr = addr;
|
||||
lineAddr.makeLineAddress();
|
||||
Addr pktLineAddr = makeLineAddress(pkt->getAddr());
|
||||
Addr lineAddr = makeLineAddress(addr);
|
||||
|
||||
if (pktLineAddr == lineAddr) {
|
||||
const uint8_t *data = pkt->getConstPtr<uint8_t>();
|
||||
unsigned int size_in_bytes = pkt->getSize();
|
||||
unsigned startByte = pkt->getAddr() - lineAddr.getAddress();
|
||||
unsigned startByte = pkt->getAddr() - lineAddr;
|
||||
|
||||
for (unsigned i = 0; i < size_in_bytes; ++i) {
|
||||
blk.setByte(i + startByte, data[i]);
|
||||
|
|
|
|||
|
|
@ -99,21 +99,21 @@ CacheMemory::~CacheMemory()
|
|||
|
||||
// convert a Address to its location in the cache
|
||||
int64
|
||||
CacheMemory::addressToCacheSet(const Address& address) const
|
||||
CacheMemory::addressToCacheSet(Addr address) const
|
||||
{
|
||||
assert(address == line_address(address));
|
||||
return address.bitSelect(m_start_index_bit,
|
||||
assert(address == makeLineAddress(address));
|
||||
return bitSelect(address, m_start_index_bit,
|
||||
m_start_index_bit + m_cache_num_set_bits - 1);
|
||||
}
|
||||
|
||||
// Given a cache index: returns the index of the tag in a set.
|
||||
// returns -1 if the tag is not found.
|
||||
int
|
||||
CacheMemory::findTagInSet(int64 cacheSet, const Address& tag) const
|
||||
CacheMemory::findTagInSet(int64 cacheSet, Addr tag) const
|
||||
{
|
||||
assert(tag == line_address(tag));
|
||||
assert(tag == makeLineAddress(tag));
|
||||
// search the set for the tags
|
||||
m5::hash_map<Address, int>::const_iterator it = m_tag_index.find(tag);
|
||||
m5::hash_map<Addr, int>::const_iterator it = m_tag_index.find(tag);
|
||||
if (it != m_tag_index.end())
|
||||
if (m_cache[cacheSet][it->second]->m_Permission !=
|
||||
AccessPermission_NotPresent)
|
||||
|
|
@ -125,11 +125,11 @@ CacheMemory::findTagInSet(int64 cacheSet, const Address& tag) const
|
|||
// returns -1 if the tag is not found.
|
||||
int
|
||||
CacheMemory::findTagInSetIgnorePermissions(int64 cacheSet,
|
||||
const Address& tag) const
|
||||
Addr tag) const
|
||||
{
|
||||
assert(tag == line_address(tag));
|
||||
assert(tag == makeLineAddress(tag));
|
||||
// search the set for the tags
|
||||
m5::hash_map<Address, int>::const_iterator it = m_tag_index.find(tag);
|
||||
m5::hash_map<Addr, int>::const_iterator it = m_tag_index.find(tag);
|
||||
if (it != m_tag_index.end())
|
||||
return it->second;
|
||||
return -1; // Not found
|
||||
|
|
@ -138,10 +138,10 @@ CacheMemory::findTagInSetIgnorePermissions(int64 cacheSet,
|
|||
// Given an unique cache block identifier (idx): return the valid address
|
||||
// stored by the cache block. If the block is invalid/notpresent, the
|
||||
// function returns the 0 address
|
||||
Address
|
||||
Addr
|
||||
CacheMemory::getAddressAtIdx(int idx) const
|
||||
{
|
||||
Address tmp(0);
|
||||
Addr tmp(0);
|
||||
|
||||
int set = idx / m_cache_assoc;
|
||||
assert(set < m_cache_num_sets);
|
||||
|
|
@ -159,10 +159,10 @@ CacheMemory::getAddressAtIdx(int idx) const
|
|||
}
|
||||
|
||||
bool
|
||||
CacheMemory::tryCacheAccess(const Address& address, RubyRequestType type,
|
||||
CacheMemory::tryCacheAccess(Addr address, RubyRequestType type,
|
||||
DataBlock*& data_ptr)
|
||||
{
|
||||
assert(address == line_address(address));
|
||||
assert(address == makeLineAddress(address));
|
||||
DPRINTF(RubyCache, "address: %s\n", address);
|
||||
int64 cacheSet = addressToCacheSet(address);
|
||||
int loc = findTagInSet(cacheSet, address);
|
||||
|
|
@ -186,10 +186,10 @@ CacheMemory::tryCacheAccess(const Address& address, RubyRequestType type,
|
|||
}
|
||||
|
||||
bool
|
||||
CacheMemory::testCacheAccess(const Address& address, RubyRequestType type,
|
||||
CacheMemory::testCacheAccess(Addr address, RubyRequestType type,
|
||||
DataBlock*& data_ptr)
|
||||
{
|
||||
assert(address == line_address(address));
|
||||
assert(address == makeLineAddress(address));
|
||||
DPRINTF(RubyCache, "address: %s\n", address);
|
||||
int64 cacheSet = addressToCacheSet(address);
|
||||
int loc = findTagInSet(cacheSet, address);
|
||||
|
|
@ -210,9 +210,9 @@ CacheMemory::testCacheAccess(const Address& address, RubyRequestType type,
|
|||
|
||||
// tests to see if an address is present in the cache
|
||||
bool
|
||||
CacheMemory::isTagPresent(const Address& address) const
|
||||
CacheMemory::isTagPresent(Addr address) const
|
||||
{
|
||||
assert(address == line_address(address));
|
||||
assert(address == makeLineAddress(address));
|
||||
int64 cacheSet = addressToCacheSet(address);
|
||||
int loc = findTagInSet(cacheSet, address);
|
||||
|
||||
|
|
@ -229,9 +229,9 @@ CacheMemory::isTagPresent(const Address& address) const
|
|||
// a) a tag match on this address or there is
|
||||
// b) an unused line in the same cache "way"
|
||||
bool
|
||||
CacheMemory::cacheAvail(const Address& address) const
|
||||
CacheMemory::cacheAvail(Addr address) const
|
||||
{
|
||||
assert(address == line_address(address));
|
||||
assert(address == makeLineAddress(address));
|
||||
|
||||
int64 cacheSet = addressToCacheSet(address);
|
||||
|
||||
|
|
@ -251,9 +251,9 @@ CacheMemory::cacheAvail(const Address& address) const
|
|||
}
|
||||
|
||||
AbstractCacheEntry*
|
||||
CacheMemory::allocate(const Address& address, AbstractCacheEntry* entry, bool touch)
|
||||
CacheMemory::allocate(Addr address, AbstractCacheEntry* entry, bool touch)
|
||||
{
|
||||
assert(address == line_address(address));
|
||||
assert(address == makeLineAddress(address));
|
||||
assert(!isTagPresent(address));
|
||||
assert(cacheAvail(address));
|
||||
DPRINTF(RubyCache, "address: %s\n", address);
|
||||
|
|
@ -282,9 +282,9 @@ CacheMemory::allocate(const Address& address, AbstractCacheEntry* entry, bool to
|
|||
}
|
||||
|
||||
void
|
||||
CacheMemory::deallocate(const Address& address)
|
||||
CacheMemory::deallocate(Addr address)
|
||||
{
|
||||
assert(address == line_address(address));
|
||||
assert(address == makeLineAddress(address));
|
||||
assert(isTagPresent(address));
|
||||
DPRINTF(RubyCache, "address: %s\n", address);
|
||||
int64 cacheSet = addressToCacheSet(address);
|
||||
|
|
@ -297,10 +297,10 @@ CacheMemory::deallocate(const Address& address)
|
|||
}
|
||||
|
||||
// Returns with the physical address of the conflicting cache line
|
||||
Address
|
||||
CacheMemory::cacheProbe(const Address& address) const
|
||||
Addr
|
||||
CacheMemory::cacheProbe(Addr address) const
|
||||
{
|
||||
assert(address == line_address(address));
|
||||
assert(address == makeLineAddress(address));
|
||||
assert(!cacheAvail(address));
|
||||
|
||||
int64 cacheSet = addressToCacheSet(address);
|
||||
|
|
@ -310,9 +310,9 @@ CacheMemory::cacheProbe(const Address& address) const
|
|||
|
||||
// looks an address up in the cache
|
||||
AbstractCacheEntry*
|
||||
CacheMemory::lookup(const Address& address)
|
||||
CacheMemory::lookup(Addr address)
|
||||
{
|
||||
assert(address == line_address(address));
|
||||
assert(address == makeLineAddress(address));
|
||||
int64 cacheSet = addressToCacheSet(address);
|
||||
int loc = findTagInSet(cacheSet, address);
|
||||
if(loc == -1) return NULL;
|
||||
|
|
@ -321,9 +321,9 @@ CacheMemory::lookup(const Address& address)
|
|||
|
||||
// looks an address up in the cache
|
||||
const AbstractCacheEntry*
|
||||
CacheMemory::lookup(const Address& address) const
|
||||
CacheMemory::lookup(Addr address) const
|
||||
{
|
||||
assert(address == line_address(address));
|
||||
assert(address == makeLineAddress(address));
|
||||
int64 cacheSet = addressToCacheSet(address);
|
||||
int loc = findTagInSet(cacheSet, address);
|
||||
if(loc == -1) return NULL;
|
||||
|
|
@ -332,7 +332,7 @@ CacheMemory::lookup(const Address& address) const
|
|||
|
||||
// Sets the most recently used bit for a cache block
|
||||
void
|
||||
CacheMemory::setMRU(const Address& address)
|
||||
CacheMemory::setMRU(Addr address)
|
||||
{
|
||||
int64 cacheSet = addressToCacheSet(address);
|
||||
int loc = findTagInSet(cacheSet, address);
|
||||
|
|
@ -364,7 +364,7 @@ CacheMemory::recordCacheContents(int cntrl, CacheRecorder* tr) const
|
|||
}
|
||||
|
||||
if (request_type != RubyRequestType_NULL) {
|
||||
tr->addRecord(cntrl, m_cache[i][j]->m_Address.getAddress(),
|
||||
tr->addRecord(cntrl, m_cache[i][j]->m_Address,
|
||||
0, request_type,
|
||||
m_replacementPolicy_ptr->getLastAccess(i, j),
|
||||
m_cache[i][j]->getDataBlk());
|
||||
|
|
@ -406,10 +406,10 @@ CacheMemory::printData(ostream& out) const
|
|||
}
|
||||
|
||||
void
|
||||
CacheMemory::setLocked(const Address& address, int context)
|
||||
CacheMemory::setLocked(Addr address, int context)
|
||||
{
|
||||
DPRINTF(RubyCache, "Setting Lock for addr: %x to %d\n", address, context);
|
||||
assert(address == line_address(address));
|
||||
assert(address == makeLineAddress(address));
|
||||
int64 cacheSet = addressToCacheSet(address);
|
||||
int loc = findTagInSet(cacheSet, address);
|
||||
assert(loc != -1);
|
||||
|
|
@ -417,10 +417,10 @@ CacheMemory::setLocked(const Address& address, int context)
|
|||
}
|
||||
|
||||
void
|
||||
CacheMemory::clearLocked(const Address& address)
|
||||
CacheMemory::clearLocked(Addr address)
|
||||
{
|
||||
DPRINTF(RubyCache, "Clear Lock for addr: %x\n", address);
|
||||
assert(address == line_address(address));
|
||||
assert(address == makeLineAddress(address));
|
||||
int64 cacheSet = addressToCacheSet(address);
|
||||
int loc = findTagInSet(cacheSet, address);
|
||||
assert(loc != -1);
|
||||
|
|
@ -428,9 +428,9 @@ CacheMemory::clearLocked(const Address& address)
|
|||
}
|
||||
|
||||
bool
|
||||
CacheMemory::isLocked(const Address& address, int context)
|
||||
CacheMemory::isLocked(Addr address, int context)
|
||||
{
|
||||
assert(address == line_address(address));
|
||||
assert(address == makeLineAddress(address));
|
||||
int64 cacheSet = addressToCacheSet(address);
|
||||
int loc = findTagInSet(cacheSet, address);
|
||||
assert(loc != -1);
|
||||
|
|
@ -531,7 +531,7 @@ CacheMemory::regStats()
|
|||
// assumption: SLICC generated files will only call this function
|
||||
// once **all** resources are granted
|
||||
void
|
||||
CacheMemory::recordRequestType(CacheRequestType requestType, Address addr)
|
||||
CacheMemory::recordRequestType(CacheRequestType requestType, Addr addr)
|
||||
{
|
||||
DPRINTF(RubyStats, "Recorded statistic: %s\n",
|
||||
CacheRequestType_to_string(requestType));
|
||||
|
|
@ -563,7 +563,7 @@ CacheMemory::recordRequestType(CacheRequestType requestType, Address addr)
|
|||
}
|
||||
|
||||
bool
|
||||
CacheMemory::checkResourceAvailable(CacheResourceType res, Address addr)
|
||||
CacheMemory::checkResourceAvailable(CacheResourceType res, Addr addr)
|
||||
{
|
||||
if (!m_resource_stalls) {
|
||||
return true;
|
||||
|
|
|
|||
|
|
@ -58,43 +58,42 @@ class CacheMemory : public SimObject
|
|||
|
||||
// Public Methods
|
||||
// perform a cache access and see if we hit or not. Return true on a hit.
|
||||
bool tryCacheAccess(const Address& address, RubyRequestType type,
|
||||
bool tryCacheAccess(Addr address, RubyRequestType type,
|
||||
DataBlock*& data_ptr);
|
||||
|
||||
// similar to above, but doesn't require full access check
|
||||
bool testCacheAccess(const Address& address, RubyRequestType type,
|
||||
bool testCacheAccess(Addr address, RubyRequestType type,
|
||||
DataBlock*& data_ptr);
|
||||
|
||||
// tests to see if an address is present in the cache
|
||||
bool isTagPresent(const Address& address) const;
|
||||
bool isTagPresent(Addr address) const;
|
||||
|
||||
// Returns true if there is:
|
||||
// a) a tag match on this address or there is
|
||||
// b) an unused line in the same cache "way"
|
||||
bool cacheAvail(const Address& address) const;
|
||||
bool cacheAvail(Addr address) const;
|
||||
|
||||
// find an unused entry and sets the tag appropriate for the address
|
||||
AbstractCacheEntry* allocate(const Address& address,
|
||||
AbstractCacheEntry* allocate(Addr address,
|
||||
AbstractCacheEntry* new_entry, bool touch);
|
||||
AbstractCacheEntry* allocate(const Address& address,
|
||||
AbstractCacheEntry* new_entry)
|
||||
AbstractCacheEntry* allocate(Addr address, AbstractCacheEntry* new_entry)
|
||||
{
|
||||
return allocate(address, new_entry, true);
|
||||
}
|
||||
void allocateVoid(const Address& address, AbstractCacheEntry* new_entry)
|
||||
void allocateVoid(Addr address, AbstractCacheEntry* new_entry)
|
||||
{
|
||||
allocate(address, new_entry, true);
|
||||
}
|
||||
|
||||
// Explicitly free up this address
|
||||
void deallocate(const Address& address);
|
||||
void deallocate(Addr address);
|
||||
|
||||
// Returns with the physical address of the conflicting cache line
|
||||
Address cacheProbe(const Address& address) const;
|
||||
Addr cacheProbe(Addr address) const;
|
||||
|
||||
// looks an address up in the cache
|
||||
AbstractCacheEntry* lookup(const Address& address);
|
||||
const AbstractCacheEntry* lookup(const Address& address) const;
|
||||
AbstractCacheEntry* lookup(Addr address);
|
||||
const AbstractCacheEntry* lookup(Addr address) const;
|
||||
|
||||
Cycles getTagLatency() const { return tagArray.getLatency(); }
|
||||
Cycles getDataLatency() const { return dataArray.getLatency(); }
|
||||
|
|
@ -106,19 +105,19 @@ class CacheMemory : public SimObject
|
|||
void recordCacheContents(int cntrl, CacheRecorder* tr) const;
|
||||
|
||||
// Set this address to most recently used
|
||||
void setMRU(const Address& address);
|
||||
void setMRU(Addr address);
|
||||
|
||||
void setLocked (const Address& addr, int context);
|
||||
void clearLocked (const Address& addr);
|
||||
bool isLocked (const Address& addr, int context);
|
||||
void setLocked (Addr addr, int context);
|
||||
void clearLocked (Addr addr);
|
||||
bool isLocked (Addr addr, int context);
|
||||
|
||||
// Print cache contents
|
||||
void print(std::ostream& out) const;
|
||||
void printData(std::ostream& out) const;
|
||||
|
||||
void regStats();
|
||||
bool checkResourceAvailable(CacheResourceType res, Address addr);
|
||||
void recordRequestType(CacheRequestType requestType, Address addr);
|
||||
bool checkResourceAvailable(CacheResourceType res, Addr addr);
|
||||
void recordRequestType(CacheRequestType requestType, Addr addr);
|
||||
|
||||
public:
|
||||
Stats::Scalar m_demand_hits;
|
||||
|
|
@ -141,17 +140,16 @@ class CacheMemory : public SimObject
|
|||
|
||||
int getCacheSize() const { return m_cache_size; }
|
||||
int getNumBlocks() const { return m_cache_num_sets * m_cache_assoc; }
|
||||
Address getAddressAtIdx(int idx) const;
|
||||
Addr getAddressAtIdx(int idx) const;
|
||||
|
||||
private:
|
||||
// convert a Address to its location in the cache
|
||||
int64 addressToCacheSet(const Address& address) const;
|
||||
int64 addressToCacheSet(Addr address) const;
|
||||
|
||||
// Given a cache tag: returns the index of the tag in a set.
|
||||
// returns -1 if the tag is not found.
|
||||
int findTagInSet(int64 line, const Address& tag) const;
|
||||
int findTagInSetIgnorePermissions(int64 cacheSet,
|
||||
const Address& tag) const;
|
||||
int findTagInSet(int64 line, Addr tag) const;
|
||||
int findTagInSetIgnorePermissions(int64 cacheSet, Addr tag) const;
|
||||
|
||||
// Private copy constructor and assignment operator
|
||||
CacheMemory(const CacheMemory& obj);
|
||||
|
|
@ -163,7 +161,7 @@ class CacheMemory : public SimObject
|
|||
|
||||
// The first index is the # of cache lines.
|
||||
// The second index is the the amount associativity.
|
||||
m5::hash_map<Address, int> m_tag_index;
|
||||
m5::hash_map<Addr, int> m_tag_index;
|
||||
std::vector<std::vector<AbstractCacheEntry*> > m_cache;
|
||||
|
||||
AbstractReplacementPolicy *m_replacementPolicy_ptr;
|
||||
|
|
|
|||
|
|
@ -71,7 +71,7 @@ DirectoryMemory::init()
|
|||
DirectoryMemory::~DirectoryMemory()
|
||||
{
|
||||
// free up all the directory entries
|
||||
for (uint64 i = 0; i < m_num_entries; i++) {
|
||||
for (uint64_t i = 0; i < m_num_entries; i++) {
|
||||
if (m_entries[i] != NULL) {
|
||||
delete m_entries[i];
|
||||
}
|
||||
|
|
@ -79,40 +79,41 @@ DirectoryMemory::~DirectoryMemory()
|
|||
delete [] m_entries;
|
||||
}
|
||||
|
||||
uint64
|
||||
DirectoryMemory::mapAddressToDirectoryVersion(PhysAddress address)
|
||||
uint64_t
|
||||
DirectoryMemory::mapAddressToDirectoryVersion(Addr address)
|
||||
{
|
||||
if (m_num_directories_bits == 0)
|
||||
return 0;
|
||||
|
||||
uint64 ret = address.bitSelect(m_numa_high_bit - m_num_directories_bits + 1,
|
||||
uint64_t ret = bitSelect(address,
|
||||
m_numa_high_bit - m_num_directories_bits + 1,
|
||||
m_numa_high_bit);
|
||||
return ret;
|
||||
}
|
||||
|
||||
bool
|
||||
DirectoryMemory::isPresent(PhysAddress address)
|
||||
DirectoryMemory::isPresent(Addr address)
|
||||
{
|
||||
bool ret = (mapAddressToDirectoryVersion(address) == m_version);
|
||||
return ret;
|
||||
}
|
||||
|
||||
uint64
|
||||
DirectoryMemory::mapAddressToLocalIdx(PhysAddress address)
|
||||
uint64_t
|
||||
DirectoryMemory::mapAddressToLocalIdx(Addr address)
|
||||
{
|
||||
uint64 ret;
|
||||
uint64_t ret;
|
||||
if (m_num_directories_bits > 0) {
|
||||
ret = address.bitRemove(m_numa_high_bit - m_num_directories_bits + 1,
|
||||
ret = bitRemove(address, m_numa_high_bit - m_num_directories_bits + 1,
|
||||
m_numa_high_bit);
|
||||
} else {
|
||||
ret = address.getAddress();
|
||||
ret = address;
|
||||
}
|
||||
|
||||
return ret >> (RubySystem::getBlockSizeBits());
|
||||
}
|
||||
|
||||
AbstractEntry*
|
||||
DirectoryMemory::lookup(PhysAddress address)
|
||||
DirectoryMemory::lookup(Addr address)
|
||||
{
|
||||
assert(isPresent(address));
|
||||
DPRINTF(RubyCache, "Looking up address: %s\n", address);
|
||||
|
|
@ -123,10 +124,10 @@ DirectoryMemory::lookup(PhysAddress address)
|
|||
}
|
||||
|
||||
AbstractEntry*
|
||||
DirectoryMemory::allocate(const PhysAddress& address, AbstractEntry* entry)
|
||||
DirectoryMemory::allocate(Addr address, AbstractEntry *entry)
|
||||
{
|
||||
assert(isPresent(address));
|
||||
uint64 idx;
|
||||
uint64_t idx;
|
||||
DPRINTF(RubyCache, "Looking up address: %s\n", address);
|
||||
|
||||
idx = mapAddressToLocalIdx(address);
|
||||
|
|
|
|||
|
|
@ -47,15 +47,14 @@ class DirectoryMemory : public SimObject
|
|||
|
||||
void init();
|
||||
|
||||
uint64 mapAddressToLocalIdx(PhysAddress address);
|
||||
static uint64 mapAddressToDirectoryVersion(PhysAddress address);
|
||||
uint64_t mapAddressToLocalIdx(Addr address);
|
||||
static uint64_t mapAddressToDirectoryVersion(Addr address);
|
||||
|
||||
uint64 getSize() { return m_size_bytes; }
|
||||
uint64_t getSize() { return m_size_bytes; }
|
||||
|
||||
bool isPresent(PhysAddress address);
|
||||
AbstractEntry* lookup(PhysAddress address);
|
||||
AbstractEntry* allocate(const PhysAddress& address,
|
||||
AbstractEntry* new_entry);
|
||||
bool isPresent(Addr address);
|
||||
AbstractEntry *lookup(Addr address);
|
||||
AbstractEntry *allocate(Addr address, AbstractEntry* new_entry);
|
||||
|
||||
void print(std::ostream& out) const;
|
||||
void recordRequestType(DirectoryRequestType requestType);
|
||||
|
|
@ -70,9 +69,9 @@ class DirectoryMemory : public SimObject
|
|||
AbstractEntry **m_entries;
|
||||
// int m_size; // # of memory module blocks this directory is
|
||||
// responsible for
|
||||
uint64 m_size_bytes;
|
||||
uint64 m_size_bits;
|
||||
uint64 m_num_entries;
|
||||
uint64_t m_size_bytes;
|
||||
uint64_t m_size_bits;
|
||||
uint64_t m_num_entries;
|
||||
int m_version;
|
||||
|
||||
static int m_num_directories;
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ class MemoryNode
|
|||
public:
|
||||
// old constructor
|
||||
MemoryNode(const Cycles& time, int counter, const PacketPtr p,
|
||||
const physical_address_t addr, const bool is_mem_read)
|
||||
Addr addr, const bool is_mem_read)
|
||||
: m_time(time), pkt(p)
|
||||
{
|
||||
m_msg_counter = counter;
|
||||
|
|
@ -59,7 +59,7 @@ class MemoryNode
|
|||
|
||||
// new constructor
|
||||
MemoryNode(const Cycles& time, const PacketPtr p,
|
||||
const physical_address_t addr, const bool is_mem_read,
|
||||
Addr addr, const bool is_mem_read,
|
||||
const bool is_dirty_wb)
|
||||
: m_time(time), pkt(p)
|
||||
{
|
||||
|
|
@ -74,7 +74,7 @@ class MemoryNode
|
|||
Cycles m_time;
|
||||
int m_msg_counter;
|
||||
PacketPtr pkt;
|
||||
physical_address_t m_addr;
|
||||
Addr m_addr;
|
||||
bool m_is_mem_read;
|
||||
bool m_is_dirty_wb;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -55,28 +55,28 @@ class PerfectCacheMemory
|
|||
PerfectCacheMemory();
|
||||
|
||||
// tests to see if an address is present in the cache
|
||||
bool isTagPresent(const Address& address) const;
|
||||
bool isTagPresent(Addr address) const;
|
||||
|
||||
// Returns true if there is:
|
||||
// a) a tag match on this address or there is
|
||||
// b) an Invalid line in the same cache "way"
|
||||
bool cacheAvail(const Address& address) const;
|
||||
bool cacheAvail(Addr address) const;
|
||||
|
||||
// find an Invalid entry and sets the tag appropriate for the address
|
||||
void allocate(const Address& address);
|
||||
void allocate(Addr address);
|
||||
|
||||
void deallocate(const Address& address);
|
||||
void deallocate(Addr address);
|
||||
|
||||
// Returns with the physical address of the conflicting cache line
|
||||
Address cacheProbe(const Address& newAddress) const;
|
||||
Addr cacheProbe(Addr newAddress) const;
|
||||
|
||||
// looks an address up in the cache
|
||||
ENTRY* lookup(const Address& address);
|
||||
const ENTRY* lookup(const Address& address) const;
|
||||
ENTRY* lookup(Addr address);
|
||||
const ENTRY* lookup(Addr address) const;
|
||||
|
||||
// Get/Set permission of cache block
|
||||
AccessPermission getPermission(const Address& address) const;
|
||||
void changePermission(const Address& address, AccessPermission new_perm);
|
||||
AccessPermission getPermission(Addr address) const;
|
||||
void changePermission(Addr address, AccessPermission new_perm);
|
||||
|
||||
// Print cache contents
|
||||
void print(std::ostream& out) const;
|
||||
|
|
@ -87,7 +87,7 @@ class PerfectCacheMemory
|
|||
PerfectCacheMemory& operator=(const PerfectCacheMemory& obj);
|
||||
|
||||
// Data Members (m_prefix)
|
||||
m5::hash_map<Address, PerfectCacheLineState<ENTRY> > m_map;
|
||||
m5::hash_map<Addr, PerfectCacheLineState<ENTRY> > m_map;
|
||||
};
|
||||
|
||||
template<class ENTRY>
|
||||
|
|
@ -108,14 +108,14 @@ PerfectCacheMemory<ENTRY>::PerfectCacheMemory()
|
|||
// tests to see if an address is present in the cache
|
||||
template<class ENTRY>
|
||||
inline bool
|
||||
PerfectCacheMemory<ENTRY>::isTagPresent(const Address& address) const
|
||||
PerfectCacheMemory<ENTRY>::isTagPresent(Addr address) const
|
||||
{
|
||||
return m_map.count(line_address(address)) > 0;
|
||||
return m_map.count(makeLineAddress(address)) > 0;
|
||||
}
|
||||
|
||||
template<class ENTRY>
|
||||
inline bool
|
||||
PerfectCacheMemory<ENTRY>::cacheAvail(const Address& address) const
|
||||
PerfectCacheMemory<ENTRY>::cacheAvail(Addr address) const
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
|
@ -124,26 +124,26 @@ PerfectCacheMemory<ENTRY>::cacheAvail(const Address& address) const
|
|||
// appropriate for the address
|
||||
template<class ENTRY>
|
||||
inline void
|
||||
PerfectCacheMemory<ENTRY>::allocate(const Address& address)
|
||||
PerfectCacheMemory<ENTRY>::allocate(Addr address)
|
||||
{
|
||||
PerfectCacheLineState<ENTRY> line_state;
|
||||
line_state.m_permission = AccessPermission_Invalid;
|
||||
line_state.m_entry = ENTRY();
|
||||
m_map[line_address(address)] = line_state;
|
||||
m_map[makeLineAddress(address)] = line_state;
|
||||
}
|
||||
|
||||
// deallocate entry
|
||||
template<class ENTRY>
|
||||
inline void
|
||||
PerfectCacheMemory<ENTRY>::deallocate(const Address& address)
|
||||
PerfectCacheMemory<ENTRY>::deallocate(Addr address)
|
||||
{
|
||||
m_map.erase(line_address(address));
|
||||
m_map.erase(makeLineAddress(address));
|
||||
}
|
||||
|
||||
// Returns with the physical address of the conflicting cache line
|
||||
template<class ENTRY>
|
||||
inline Address
|
||||
PerfectCacheMemory<ENTRY>::cacheProbe(const Address& newAddress) const
|
||||
inline Addr
|
||||
PerfectCacheMemory<ENTRY>::cacheProbe(Addr newAddress) const
|
||||
{
|
||||
panic("cacheProbe called in perfect cache");
|
||||
return newAddress;
|
||||
|
|
@ -152,33 +152,32 @@ PerfectCacheMemory<ENTRY>::cacheProbe(const Address& newAddress) const
|
|||
// looks an address up in the cache
|
||||
template<class ENTRY>
|
||||
inline ENTRY*
|
||||
PerfectCacheMemory<ENTRY>::lookup(const Address& address)
|
||||
PerfectCacheMemory<ENTRY>::lookup(Addr address)
|
||||
{
|
||||
return &m_map[line_address(address)].m_entry;
|
||||
return &m_map[makeLineAddress(address)].m_entry;
|
||||
}
|
||||
|
||||
// looks an address up in the cache
|
||||
template<class ENTRY>
|
||||
inline const ENTRY*
|
||||
PerfectCacheMemory<ENTRY>::lookup(const Address& address) const
|
||||
PerfectCacheMemory<ENTRY>::lookup(Addr address) const
|
||||
{
|
||||
return &m_map[line_address(address)].m_entry;
|
||||
return &m_map[makeLineAddress(address)].m_entry;
|
||||
}
|
||||
|
||||
template<class ENTRY>
|
||||
inline AccessPermission
|
||||
PerfectCacheMemory<ENTRY>::getPermission(const Address& address) const
|
||||
PerfectCacheMemory<ENTRY>::getPermission(Addr address) const
|
||||
{
|
||||
return m_map[line_address(address)].m_permission;
|
||||
return m_map[makeLineAddress(address)].m_permission;
|
||||
}
|
||||
|
||||
template<class ENTRY>
|
||||
inline void
|
||||
PerfectCacheMemory<ENTRY>::changePermission(const Address& address,
|
||||
PerfectCacheMemory<ENTRY>::changePermission(Addr address,
|
||||
AccessPermission new_perm)
|
||||
{
|
||||
Address line_address = address;
|
||||
line_address.makeLineAddress();
|
||||
Addr line_address = makeLineAddress(address);
|
||||
PerfectCacheLineState<ENTRY>& line_state = m_map[line_address];
|
||||
line_state.m_permission = new_perm;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ PersistentTable::~PersistentTable()
|
|||
}
|
||||
|
||||
void
|
||||
PersistentTable::persistentRequestLock(const Address& address,
|
||||
PersistentTable::persistentRequestLock(Addr address,
|
||||
MachineID locker,
|
||||
AccessType type)
|
||||
{
|
||||
|
|
@ -59,7 +59,7 @@ PersistentTable::persistentRequestLock(const Address& address,
|
|||
MachineID locker = (MachineID) persistent_randomize[llocker];
|
||||
#endif
|
||||
|
||||
assert(address == line_address(address));
|
||||
assert(address == makeLineAddress(address));
|
||||
|
||||
static const PersistentTableEntry dflt;
|
||||
pair<AddressMap::iterator, bool> r =
|
||||
|
|
@ -82,7 +82,7 @@ PersistentTable::persistentRequestLock(const Address& address,
|
|||
}
|
||||
|
||||
void
|
||||
PersistentTable::persistentRequestUnlock(const Address& address,
|
||||
PersistentTable::persistentRequestUnlock(Addr address,
|
||||
MachineID unlocker)
|
||||
{
|
||||
#if 0
|
||||
|
|
@ -93,7 +93,7 @@ PersistentTable::persistentRequestUnlock(const Address& address,
|
|||
MachineID unlocker = (MachineID) persistent_randomize[uunlocker];
|
||||
#endif
|
||||
|
||||
assert(address == line_address(address));
|
||||
assert(address == makeLineAddress(address));
|
||||
assert(m_map.count(address));
|
||||
PersistentTableEntry& entry = m_map[address];
|
||||
|
||||
|
|
@ -115,10 +115,10 @@ PersistentTable::persistentRequestUnlock(const Address& address,
|
|||
}
|
||||
|
||||
bool
|
||||
PersistentTable::okToIssueStarving(const Address& address,
|
||||
PersistentTable::okToIssueStarving(Addr address,
|
||||
MachineID machId) const
|
||||
{
|
||||
assert(address == line_address(address));
|
||||
assert(address == makeLineAddress(address));
|
||||
|
||||
AddressMap::const_iterator i = m_map.find(address);
|
||||
if (i == m_map.end()) {
|
||||
|
|
@ -138,9 +138,9 @@ PersistentTable::okToIssueStarving(const Address& address,
|
|||
}
|
||||
|
||||
MachineID
|
||||
PersistentTable::findSmallest(const Address& address) const
|
||||
PersistentTable::findSmallest(Addr address) const
|
||||
{
|
||||
assert(address == line_address(address));
|
||||
assert(address == makeLineAddress(address));
|
||||
AddressMap::const_iterator i = m_map.find(address);
|
||||
assert(i != m_map.end());
|
||||
const PersistentTableEntry& entry = i->second;
|
||||
|
|
@ -148,9 +148,9 @@ PersistentTable::findSmallest(const Address& address) const
|
|||
}
|
||||
|
||||
AccessType
|
||||
PersistentTable::typeOfSmallest(const Address& address) const
|
||||
PersistentTable::typeOfSmallest(Addr address) const
|
||||
{
|
||||
assert(address == line_address(address));
|
||||
assert(address == makeLineAddress(address));
|
||||
AddressMap::const_iterator i = m_map.find(address);
|
||||
assert(i != m_map.end());
|
||||
const PersistentTableEntry& entry = i->second;
|
||||
|
|
@ -163,9 +163,9 @@ PersistentTable::typeOfSmallest(const Address& address) const
|
|||
}
|
||||
|
||||
void
|
||||
PersistentTable::markEntries(const Address& address)
|
||||
PersistentTable::markEntries(Addr address)
|
||||
{
|
||||
assert(address == line_address(address));
|
||||
assert(address == makeLineAddress(address));
|
||||
AddressMap::iterator i = m_map.find(address);
|
||||
if (i == m_map.end())
|
||||
return;
|
||||
|
|
@ -180,18 +180,18 @@ PersistentTable::markEntries(const Address& address)
|
|||
}
|
||||
|
||||
bool
|
||||
PersistentTable::isLocked(const Address& address) const
|
||||
PersistentTable::isLocked(Addr address) const
|
||||
{
|
||||
assert(address == line_address(address));
|
||||
assert(address == makeLineAddress(address));
|
||||
|
||||
// If an entry is present, it must be locked
|
||||
return m_map.count(address) > 0;
|
||||
}
|
||||
|
||||
int
|
||||
PersistentTable::countStarvingForAddress(const Address& address) const
|
||||
PersistentTable::countStarvingForAddress(Addr address) const
|
||||
{
|
||||
assert(address == line_address(address));
|
||||
assert(address == makeLineAddress(address));
|
||||
AddressMap::const_iterator i = m_map.find(address);
|
||||
if (i == m_map.end())
|
||||
return 0;
|
||||
|
|
@ -201,9 +201,9 @@ PersistentTable::countStarvingForAddress(const Address& address) const
|
|||
}
|
||||
|
||||
int
|
||||
PersistentTable::countReadStarvingForAddress(const Address& address) const
|
||||
PersistentTable::countReadStarvingForAddress(Addr address) const
|
||||
{
|
||||
assert(address == line_address(address));
|
||||
assert(address == makeLineAddress(address));
|
||||
AddressMap::const_iterator i = m_map.find(address);
|
||||
if (i == m_map.end())
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -58,16 +58,16 @@ class PersistentTable
|
|||
~PersistentTable();
|
||||
|
||||
// Public Methods
|
||||
void persistentRequestLock(const Address& address, MachineID locker,
|
||||
void persistentRequestLock(Addr address, MachineID locker,
|
||||
AccessType type);
|
||||
void persistentRequestUnlock(const Address& address, MachineID unlocker);
|
||||
bool okToIssueStarving(const Address& address, MachineID machID) const;
|
||||
MachineID findSmallest(const Address& address) const;
|
||||
AccessType typeOfSmallest(const Address& address) const;
|
||||
void markEntries(const Address& address);
|
||||
bool isLocked(const Address& addr) const;
|
||||
int countStarvingForAddress(const Address& addr) const;
|
||||
int countReadStarvingForAddress(const Address& addr) const;
|
||||
void persistentRequestUnlock(Addr address, MachineID unlocker);
|
||||
bool okToIssueStarving(Addr address, MachineID machID) const;
|
||||
MachineID findSmallest(Addr address) const;
|
||||
AccessType typeOfSmallest(Addr address) const;
|
||||
void markEntries(Addr address);
|
||||
bool isLocked(Addr addr) const;
|
||||
int countStarvingForAddress(Addr addr) const;
|
||||
int countReadStarvingForAddress(Addr addr) const;
|
||||
|
||||
void print(std::ostream& out) const;
|
||||
|
||||
|
|
@ -77,7 +77,7 @@ class PersistentTable
|
|||
PersistentTable& operator=(const PersistentTable& obj);
|
||||
|
||||
// Data Members (m_prefix)
|
||||
typedef m5::hash_map<Address, PersistentTableEntry> AddressMap;
|
||||
typedef m5::hash_map<Addr, PersistentTableEntry> AddressMap;
|
||||
AddressMap m_map;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -42,9 +42,9 @@ Prefetcher::Prefetcher(const Params *p)
|
|||
m_array(p->num_streams), m_train_misses(p->train_misses),
|
||||
m_num_startup_pfs(p->num_startup_pfs), m_num_unit_filters(p->unit_filter),
|
||||
m_num_nonunit_filters(p->nonunit_filter),
|
||||
m_unit_filter(p->unit_filter, Address(0)),
|
||||
m_negative_filter(p->unit_filter, Address(0)),
|
||||
m_nonunit_filter(p->nonunit_filter, Address(0)),
|
||||
m_unit_filter(p->unit_filter, 0),
|
||||
m_negative_filter(p->unit_filter, 0),
|
||||
m_nonunit_filter(p->nonunit_filter, 0),
|
||||
m_prefetch_cross_pages(p->cross_page),
|
||||
m_page_shift(p->sys->getPageShift())
|
||||
{
|
||||
|
|
@ -133,10 +133,10 @@ Prefetcher::regStats()
|
|||
}
|
||||
|
||||
void
|
||||
Prefetcher::observeMiss(const Address& address, const RubyRequestType& type)
|
||||
Prefetcher::observeMiss(Addr address, const RubyRequestType& type)
|
||||
{
|
||||
DPRINTF(RubyPrefetcher, "Observed miss for %s\n", address);
|
||||
Address line_addr = line_address(address);
|
||||
Addr line_addr = makeLineAddress(address);
|
||||
numMissObserved++;
|
||||
|
||||
// check to see if we have already issued a prefetch for this block
|
||||
|
|
@ -201,7 +201,7 @@ Prefetcher::observeMiss(const Address& address, const RubyRequestType& type)
|
|||
}
|
||||
|
||||
void
|
||||
Prefetcher::observePfMiss(const Address& address)
|
||||
Prefetcher::observePfMiss(Addr address)
|
||||
{
|
||||
numPartialHits++;
|
||||
DPRINTF(RubyPrefetcher, "Observed partial hit for %s\n", address);
|
||||
|
|
@ -209,7 +209,7 @@ Prefetcher::observePfMiss(const Address& address)
|
|||
}
|
||||
|
||||
void
|
||||
Prefetcher::observePfHit(const Address& address)
|
||||
Prefetcher::observePfHit(Addr address)
|
||||
{
|
||||
numHits++;
|
||||
DPRINTF(RubyPrefetcher, "Observed hit for %s\n", address);
|
||||
|
|
@ -217,7 +217,7 @@ Prefetcher::observePfHit(const Address& address)
|
|||
}
|
||||
|
||||
void
|
||||
Prefetcher::issueNextPrefetch(const Address &address, PrefetchEntry *stream)
|
||||
Prefetcher::issueNextPrefetch(Addr address, PrefetchEntry *stream)
|
||||
{
|
||||
// get our corresponding stream fetcher
|
||||
if (stream == NULL) {
|
||||
|
|
@ -232,8 +232,8 @@ Prefetcher::issueNextPrefetch(const Address &address, PrefetchEntry *stream)
|
|||
}
|
||||
|
||||
// extend this prefetching stream by 1 (or more)
|
||||
Address page_addr = pageAddress(stream->m_address);
|
||||
Address line_addr = next_stride_address(stream->m_address,
|
||||
Addr page_addr = pageAddress(stream->m_address);
|
||||
Addr line_addr = makeNextStrideAddress(stream->m_address,
|
||||
stream->m_stride);
|
||||
|
||||
// possibly stop prefetching at page boundaries
|
||||
|
|
@ -276,33 +276,32 @@ Prefetcher::getLRUindex(void)
|
|||
void
|
||||
Prefetcher::clearNonunitEntry(uint32_t index)
|
||||
{
|
||||
m_nonunit_filter[index].setAddress(0);
|
||||
m_nonunit_filter[index] = 0;
|
||||
m_nonunit_stride[index] = 0;
|
||||
m_nonunit_hit[index] = 0;
|
||||
}
|
||||
|
||||
void
|
||||
Prefetcher::initializeStream(const Address& address, int stride,
|
||||
Prefetcher::initializeStream(Addr address, int stride,
|
||||
uint32_t index, const RubyRequestType& type)
|
||||
{
|
||||
numAllocatedStreams++;
|
||||
|
||||
// initialize the stream prefetcher
|
||||
PrefetchEntry *mystream = &(m_array[index]);
|
||||
mystream->m_address = line_address(address);
|
||||
mystream->m_address = makeLineAddress(address);
|
||||
mystream->m_stride = stride;
|
||||
mystream->m_use_time = m_controller->curCycle();
|
||||
mystream->m_is_valid = true;
|
||||
mystream->m_type = type;
|
||||
|
||||
// create a number of initial prefetches for this stream
|
||||
Address page_addr = pageAddress(mystream->m_address);
|
||||
Address line_addr = line_address(mystream->m_address);
|
||||
Address prev_addr = line_addr;
|
||||
Addr page_addr = pageAddress(mystream->m_address);
|
||||
Addr line_addr = makeLineAddress(mystream->m_address);
|
||||
|
||||
// insert a number of prefetches into the prefetch table
|
||||
for (int k = 0; k < m_num_startup_pfs; k++) {
|
||||
line_addr = next_stride_address(line_addr, stride);
|
||||
line_addr = makeNextStrideAddress(line_addr, stride);
|
||||
// possibly stop prefetching at page boundaries
|
||||
if (page_addr != pageAddress(line_addr)) {
|
||||
numPagesCrossed++;
|
||||
|
|
@ -317,7 +316,6 @@ Prefetcher::initializeStream(const Address& address, int stride,
|
|||
numPrefetchRequested++;
|
||||
DPRINTF(RubyPrefetcher, "Requesting prefetch for %s\n", line_addr);
|
||||
m_controller->enqueuePrefetch(line_addr, m_array[index].m_type);
|
||||
prev_addr = line_addr;
|
||||
}
|
||||
|
||||
// update the address to be the last address prefetched
|
||||
|
|
@ -325,14 +323,14 @@ Prefetcher::initializeStream(const Address& address, int stride,
|
|||
}
|
||||
|
||||
PrefetchEntry *
|
||||
Prefetcher::getPrefetchEntry(const Address &address, uint32_t &index)
|
||||
Prefetcher::getPrefetchEntry(Addr address, uint32_t &index)
|
||||
{
|
||||
// search all streams for a match
|
||||
for (int i = 0; i < m_num_streams; i++) {
|
||||
// search all the outstanding prefetches for this stream
|
||||
if (m_array[i].m_is_valid) {
|
||||
for (int j = 0; j < m_num_startup_pfs; j++) {
|
||||
if (next_stride_address(m_array[i].m_address,
|
||||
if (makeNextStrideAddress(m_array[i].m_address,
|
||||
-(m_array[i].m_stride*j)) == address) {
|
||||
return &(m_array[i]);
|
||||
}
|
||||
|
|
@ -343,17 +341,17 @@ Prefetcher::getPrefetchEntry(const Address &address, uint32_t &index)
|
|||
}
|
||||
|
||||
bool
|
||||
Prefetcher::accessUnitFilter(std::vector<Address>& filter_table,
|
||||
uint32_t *filter_hit, uint32_t &index, const Address &address,
|
||||
Prefetcher::accessUnitFilter(std::vector<Addr>& filter_table,
|
||||
uint32_t *filter_hit, uint32_t &index, Addr address,
|
||||
int stride, bool &alloc)
|
||||
{
|
||||
//reset the alloc flag
|
||||
alloc = false;
|
||||
|
||||
Address line_addr = line_address(address);
|
||||
Addr line_addr = makeLineAddress(address);
|
||||
for (int i = 0; i < m_num_unit_filters; i++) {
|
||||
if (filter_table[i] == line_addr) {
|
||||
filter_table[i] = next_stride_address(filter_table[i], stride);
|
||||
filter_table[i] = makeNextStrideAddress(filter_table[i], stride);
|
||||
filter_hit[i]++;
|
||||
if (filter_hit[i] >= m_train_misses) {
|
||||
alloc = true;
|
||||
|
|
@ -364,7 +362,7 @@ Prefetcher::accessUnitFilter(std::vector<Address>& filter_table,
|
|||
|
||||
// enter this address in the table
|
||||
int local_index = index;
|
||||
filter_table[local_index] = next_stride_address(line_addr, stride);
|
||||
filter_table[local_index] = makeNextStrideAddress(line_addr, stride);
|
||||
filter_hit[local_index] = 0;
|
||||
local_index = local_index + 1;
|
||||
if (local_index >= m_num_unit_filters) {
|
||||
|
|
@ -376,21 +374,21 @@ Prefetcher::accessUnitFilter(std::vector<Address>& filter_table,
|
|||
}
|
||||
|
||||
bool
|
||||
Prefetcher::accessNonunitFilter(const Address& address, int *stride,
|
||||
Prefetcher::accessNonunitFilter(Addr address, int *stride,
|
||||
bool &alloc)
|
||||
{
|
||||
//reset the alloc flag
|
||||
alloc = false;
|
||||
|
||||
/// look for non-unit strides based on a (user-defined) page size
|
||||
Address page_addr = pageAddress(address);
|
||||
Address line_addr = line_address(address);
|
||||
Addr page_addr = pageAddress(address);
|
||||
Addr line_addr = makeLineAddress(address);
|
||||
|
||||
for (uint32_t i = 0; i < m_num_nonunit_filters; i++) {
|
||||
if (pageAddress(m_nonunit_filter[i]) == page_addr) {
|
||||
// hit in the non-unit filter
|
||||
// compute the actual stride (for this reference)
|
||||
int delta = line_addr.getAddress() - m_nonunit_filter[i].getAddress();
|
||||
int delta = line_addr - m_nonunit_filter[i];
|
||||
|
||||
if (delta != 0) {
|
||||
// no zero stride prefetches
|
||||
|
|
@ -400,17 +398,19 @@ Prefetcher::accessNonunitFilter(const Address& address, int *stride,
|
|||
// increment count (if > 2) allocate stream
|
||||
m_nonunit_hit[i]++;
|
||||
if (m_nonunit_hit[i] > m_train_misses) {
|
||||
//This stride HAS to be the multiplicative constant of
|
||||
//dataBlockBytes (bc next_stride_address is calculated based
|
||||
//on this multiplicative constant!)
|
||||
*stride = m_nonunit_stride[i]/RubySystem::getBlockSizeBytes();
|
||||
// This stride HAS to be the multiplicative constant of
|
||||
// dataBlockBytes (bc makeNextStrideAddress is
|
||||
// calculated based on this multiplicative constant!)
|
||||
*stride = m_nonunit_stride[i] /
|
||||
RubySystem::getBlockSizeBytes();
|
||||
|
||||
// clear this filter entry
|
||||
clearNonunitEntry(i);
|
||||
alloc = true;
|
||||
}
|
||||
} else {
|
||||
// delta didn't match ... reset m_nonunit_hit count for this entry
|
||||
// delta didn't match ... reset m_nonunit_hit count for
|
||||
// this entry
|
||||
m_nonunit_hit[i] = 0;
|
||||
}
|
||||
|
||||
|
|
@ -469,10 +469,8 @@ Prefetcher::print(std::ostream& out) const
|
|||
}
|
||||
}
|
||||
|
||||
Address
|
||||
Prefetcher::pageAddress(const Address& addr) const
|
||||
Addr
|
||||
Prefetcher::pageAddress(Addr addr) const
|
||||
{
|
||||
Address temp = addr;
|
||||
temp.maskLowOrderBits(m_page_shift);
|
||||
return temp;
|
||||
return maskLowOrderBits(addr, m_page_shift);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -26,8 +26,8 @@
|
|||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef PREFETCHER_H
|
||||
#define PREFETCHER_H
|
||||
#ifndef __MEM_RUBY_STRUCTURES_PREFETCHER_HH__
|
||||
#define __MEM_RUBY_STRUCTURES_PREFETCHER_HH__
|
||||
|
||||
// Implements Power 4 like prefetching
|
||||
|
||||
|
|
@ -58,7 +58,7 @@ class PrefetchEntry
|
|||
}
|
||||
|
||||
//! The base address for the stream prefetch
|
||||
Address m_address;
|
||||
Addr m_address;
|
||||
|
||||
//! stride distance to get next address from
|
||||
int m_stride;
|
||||
|
|
@ -85,22 +85,22 @@ class Prefetcher : public SimObject
|
|||
Prefetcher(const Params *p);
|
||||
~Prefetcher();
|
||||
|
||||
void issueNextPrefetch(const Address &address, PrefetchEntry *stream);
|
||||
void issueNextPrefetch(Addr address, PrefetchEntry *stream);
|
||||
/**
|
||||
* Implement the prefetch hit(miss) callback interface.
|
||||
* These functions are called by the cache when it hits(misses)
|
||||
* on a line with the line's prefetch bit set. If this address
|
||||
* hits in m_array we will continue prefetching the stream.
|
||||
*/
|
||||
void observePfHit(const Address& address);
|
||||
void observePfMiss(const Address& address);
|
||||
void observePfHit(Addr address);
|
||||
void observePfMiss(Addr address);
|
||||
|
||||
/**
|
||||
* Observe a memory miss from the cache.
|
||||
*
|
||||
* @param address The physical address that missed out of the cache.
|
||||
*/
|
||||
void observeMiss(const Address& address, const RubyRequestType& type);
|
||||
void observeMiss(Addr address, const RubyRequestType& type);
|
||||
|
||||
/**
|
||||
* Print out some statistics
|
||||
|
|
@ -123,25 +123,25 @@ class Prefetcher : public SimObject
|
|||
void clearNonunitEntry(uint32_t index);
|
||||
|
||||
//! allocate a new stream buffer at a specific index
|
||||
void initializeStream(const Address& address, int stride,
|
||||
void initializeStream(Addr address, int stride,
|
||||
uint32_t index, const RubyRequestType& type);
|
||||
|
||||
//! get pointer to the matching stream entry, returns NULL if not found
|
||||
//! index holds the multiple of the stride this address is.
|
||||
PrefetchEntry* getPrefetchEntry(const Address &address,
|
||||
PrefetchEntry* getPrefetchEntry(Addr address,
|
||||
uint32_t &index);
|
||||
|
||||
/// access a unit stride filter to determine if there is a hit
|
||||
bool accessUnitFilter(std::vector<Address>& filter_table,
|
||||
uint32_t *hit_table, uint32_t &index, const Address &address,
|
||||
bool accessUnitFilter(std::vector<Addr>& filter_table,
|
||||
uint32_t *hit_table, uint32_t &index, Addr address,
|
||||
int stride, bool &alloc);
|
||||
|
||||
/// access a unit stride filter to determine if there is a hit
|
||||
bool accessNonunitFilter(const Address& address, int *stride,
|
||||
bool accessNonunitFilter(Addr address, int *stride,
|
||||
bool &alloc);
|
||||
|
||||
/// determine the page aligned address
|
||||
Address pageAddress(const Address& addr) const;
|
||||
Addr pageAddress(Addr addr) const;
|
||||
|
||||
//! number of prefetch streams available
|
||||
uint32_t m_num_streams;
|
||||
|
|
@ -159,7 +159,7 @@ class Prefetcher : public SimObject
|
|||
|
||||
/// a unit stride filter array: helps reduce BW requirement of
|
||||
/// prefetching
|
||||
std::vector<Address> m_unit_filter;
|
||||
std::vector<Addr> m_unit_filter;
|
||||
/// a round robin pointer into the unit filter group
|
||||
uint32_t m_unit_filter_index;
|
||||
//! An array used to count the of times particular filter entries
|
||||
|
|
@ -168,7 +168,7 @@ class Prefetcher : public SimObject
|
|||
|
||||
//! a negative nit stride filter array: helps reduce BW requirement
|
||||
//! of prefetching
|
||||
std::vector<Address> m_negative_filter;
|
||||
std::vector<Addr> m_negative_filter;
|
||||
/// a round robin pointer into the negative filter group
|
||||
uint32_t m_negative_filter_index;
|
||||
/// An array used to count the of times particular filter entries
|
||||
|
|
@ -177,7 +177,7 @@ class Prefetcher : public SimObject
|
|||
|
||||
/// a non-unit stride filter array: helps reduce BW requirement of
|
||||
/// prefetching
|
||||
std::vector<Address> m_nonunit_filter;
|
||||
std::vector<Addr> m_nonunit_filter;
|
||||
/// An array of strides (in # of cache lines) for the filter entries
|
||||
int *m_nonunit_stride;
|
||||
/// An array used to count the of times particular filter entries
|
||||
|
|
@ -213,4 +213,4 @@ class Prefetcher : public SimObject
|
|||
Stats::Scalar numMissedPrefetchedBlocks;
|
||||
};
|
||||
|
||||
#endif // PREFETCHER_H
|
||||
#endif // __MEM_RUBY_STRUCTURES_PREFETCHER_HH__
|
||||
|
|
|
|||
|
|
@ -289,7 +289,7 @@ bool
|
|||
RubyMemoryControl::recvTimingReq(PacketPtr pkt)
|
||||
{
|
||||
Cycles arrival_time = curCycle();
|
||||
physical_address_t addr = pkt->getAddr();
|
||||
Addr addr = pkt->getAddr();
|
||||
bool is_mem_read = pkt->isRead();
|
||||
|
||||
access(pkt);
|
||||
|
|
@ -306,7 +306,7 @@ RubyMemoryControl::enqueueMemRef(MemoryNode *memRef)
|
|||
{
|
||||
m_msg_counter++;
|
||||
memRef->m_msg_counter = m_msg_counter;
|
||||
physical_address_t addr = memRef->m_addr;
|
||||
Addr addr = memRef->m_addr;
|
||||
int bank = getBank(addr);
|
||||
|
||||
m_profiler_ptr->profileMemReq(bank);
|
||||
|
|
@ -343,7 +343,7 @@ RubyMemoryControl::enqueueToDirectory(MemoryNode *req, Cycles latency)
|
|||
// getBank returns an integer that is unique for each
|
||||
// bank across this memory controller.
|
||||
const int
|
||||
RubyMemoryControl::getBank(const physical_address_t addr) const
|
||||
RubyMemoryControl::getBank(const Addr addr) const
|
||||
{
|
||||
int dimm = (addr >> m_dimm_bit_0) & (m_dimms_per_channel - 1);
|
||||
int rank = (addr >> m_rank_bit_0) & (m_ranks_per_dimm - 1);
|
||||
|
|
@ -354,7 +354,7 @@ RubyMemoryControl::getBank(const physical_address_t addr) const
|
|||
}
|
||||
|
||||
const int
|
||||
RubyMemoryControl::getRank(const physical_address_t addr) const
|
||||
RubyMemoryControl::getRank(const Addr addr) const
|
||||
{
|
||||
int bank = getBank(addr);
|
||||
int rank = (bank / m_banks_per_rank);
|
||||
|
|
@ -374,7 +374,7 @@ RubyMemoryControl::getRank(int bank) const
|
|||
|
||||
// Not used!
|
||||
const int
|
||||
RubyMemoryControl::getChannel(const physical_address_t addr) const
|
||||
RubyMemoryControl::getChannel(const Addr addr) const
|
||||
{
|
||||
assert(false);
|
||||
return -1;
|
||||
|
|
@ -382,7 +382,7 @@ RubyMemoryControl::getChannel(const physical_address_t addr) const
|
|||
|
||||
// Not used!
|
||||
const int
|
||||
RubyMemoryControl::getRow(const physical_address_t addr) const
|
||||
RubyMemoryControl::getRow(const Addr addr) const
|
||||
{
|
||||
assert(false);
|
||||
return -1;
|
||||
|
|
|
|||
|
|
@ -75,12 +75,12 @@ class RubyMemoryControl : public AbstractMemory, public Consumer
|
|||
void print(std::ostream& out) const;
|
||||
void regStats();
|
||||
|
||||
const int getBank(const physical_address_t addr) const;
|
||||
const int getRank(const physical_address_t addr) const;
|
||||
const int getBank(const Addr addr) const;
|
||||
const int getRank(const Addr addr) const;
|
||||
|
||||
// not used in Ruby memory controller
|
||||
const int getChannel(const physical_address_t addr) const;
|
||||
const int getRow(const physical_address_t addr) const;
|
||||
const int getChannel(const Addr addr) const;
|
||||
const int getRow(const Addr addr) const;
|
||||
|
||||
//added by SS
|
||||
int getBanksPerRank() { return m_banks_per_rank; };
|
||||
|
|
|
|||
|
|
@ -43,16 +43,16 @@ class TBETable
|
|||
{
|
||||
}
|
||||
|
||||
bool isPresent(const Address& address) const;
|
||||
void allocate(const Address& address);
|
||||
void deallocate(const Address& address);
|
||||
bool isPresent(Addr address) const;
|
||||
void allocate(Addr address);
|
||||
void deallocate(Addr address);
|
||||
bool
|
||||
areNSlotsAvailable(int n) const
|
||||
{
|
||||
return (m_number_of_TBEs - m_map.size()) >= n;
|
||||
}
|
||||
|
||||
ENTRY* lookup(const Address& address);
|
||||
ENTRY* lookup(Addr address);
|
||||
|
||||
// Print cache contents
|
||||
void print(std::ostream& out) const;
|
||||
|
|
@ -63,7 +63,7 @@ class TBETable
|
|||
TBETable& operator=(const TBETable& obj);
|
||||
|
||||
// Data Members (m_prefix)
|
||||
m5::hash_map<Address, ENTRY> m_map;
|
||||
m5::hash_map<Addr, ENTRY> m_map;
|
||||
|
||||
private:
|
||||
int m_number_of_TBEs;
|
||||
|
|
@ -80,16 +80,16 @@ operator<<(std::ostream& out, const TBETable<ENTRY>& obj)
|
|||
|
||||
template<class ENTRY>
|
||||
inline bool
|
||||
TBETable<ENTRY>::isPresent(const Address& address) const
|
||||
TBETable<ENTRY>::isPresent(Addr address) const
|
||||
{
|
||||
assert(address == line_address(address));
|
||||
assert(address == makeLineAddress(address));
|
||||
assert(m_map.size() <= m_number_of_TBEs);
|
||||
return !!m_map.count(address);
|
||||
}
|
||||
|
||||
template<class ENTRY>
|
||||
inline void
|
||||
TBETable<ENTRY>::allocate(const Address& address)
|
||||
TBETable<ENTRY>::allocate(Addr address)
|
||||
{
|
||||
assert(!isPresent(address));
|
||||
assert(m_map.size() < m_number_of_TBEs);
|
||||
|
|
@ -98,7 +98,7 @@ TBETable<ENTRY>::allocate(const Address& address)
|
|||
|
||||
template<class ENTRY>
|
||||
inline void
|
||||
TBETable<ENTRY>::deallocate(const Address& address)
|
||||
TBETable<ENTRY>::deallocate(Addr address)
|
||||
{
|
||||
assert(isPresent(address));
|
||||
assert(m_map.size() > 0);
|
||||
|
|
@ -108,7 +108,7 @@ TBETable<ENTRY>::deallocate(const Address& address)
|
|||
// looks an address up in the cache
|
||||
template<class ENTRY>
|
||||
inline ENTRY*
|
||||
TBETable<ENTRY>::lookup(const Address& address)
|
||||
TBETable<ENTRY>::lookup(Addr address)
|
||||
{
|
||||
if(m_map.find(address) != m_map.end()) return &(m_map.find(address)->second);
|
||||
return NULL;
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@ TimerTable::TimerTable()
|
|||
m_clockobj_ptr = NULL;
|
||||
|
||||
m_next_valid = false;
|
||||
m_next_address = Address(0);
|
||||
m_next_address = 0;
|
||||
}
|
||||
|
||||
bool
|
||||
|
|
@ -52,7 +52,7 @@ TimerTable::isReady() const
|
|||
return (m_clockobj_ptr->curCycle() >= m_next_time);
|
||||
}
|
||||
|
||||
const Address&
|
||||
Addr
|
||||
TimerTable::readyAddress() const
|
||||
{
|
||||
assert(isReady());
|
||||
|
|
@ -65,9 +65,9 @@ TimerTable::readyAddress() const
|
|||
}
|
||||
|
||||
void
|
||||
TimerTable::set(const Address& address, Cycles relative_latency)
|
||||
TimerTable::set(Addr address, Cycles relative_latency)
|
||||
{
|
||||
assert(address == line_address(address));
|
||||
assert(address == makeLineAddress(address));
|
||||
assert(relative_latency > 0);
|
||||
assert(!m_map.count(address));
|
||||
|
||||
|
|
@ -85,9 +85,9 @@ TimerTable::set(const Address& address, Cycles relative_latency)
|
|||
}
|
||||
|
||||
void
|
||||
TimerTable::unset(const Address& address)
|
||||
TimerTable::unset(Addr address)
|
||||
{
|
||||
assert(address == line_address(address));
|
||||
assert(address == makeLineAddress(address));
|
||||
assert(m_map.count(address));
|
||||
m_map.erase(address);
|
||||
|
||||
|
|
|
|||
|
|
@ -62,13 +62,13 @@ class TimerTable
|
|||
}
|
||||
|
||||
bool isReady() const;
|
||||
const Address& readyAddress() const;
|
||||
bool isSet(const Address& address) const { return !!m_map.count(address); }
|
||||
void set(const Address& address, Cycles relative_latency);
|
||||
void set(const Address& address, uint64_t relative_latency)
|
||||
Addr readyAddress() const;
|
||||
bool isSet(Addr address) const { return !!m_map.count(address); }
|
||||
void set(Addr address, Cycles relative_latency);
|
||||
void set(Addr address, uint64_t relative_latency)
|
||||
{ set(address, Cycles(relative_latency)); }
|
||||
|
||||
void unset(const Address& address);
|
||||
void unset(Addr address);
|
||||
void print(std::ostream& out) const;
|
||||
|
||||
private:
|
||||
|
|
@ -82,11 +82,11 @@ class TimerTable
|
|||
|
||||
// use a std::map for the address map as this container is sorted
|
||||
// and ensures a well-defined iteration order
|
||||
typedef std::map<Address, Cycles> AddressMap;
|
||||
typedef std::map<Addr, Cycles> AddressMap;
|
||||
AddressMap m_map;
|
||||
mutable bool m_next_valid;
|
||||
mutable Cycles m_next_time; // Only valid if m_next_valid is true
|
||||
mutable Address m_next_address; // Only valid if m_next_valid is true
|
||||
mutable Addr m_next_address; // Only valid if m_next_valid is true
|
||||
|
||||
//! Object used for querying time.
|
||||
ClockedObject* m_clockobj_ptr;
|
||||
|
|
|
|||
|
|
@ -145,8 +145,7 @@ CacheRecorder::enqueueNextFetchRequest()
|
|||
}
|
||||
|
||||
void
|
||||
CacheRecorder::addRecord(int cntrl, const physical_address_t data_addr,
|
||||
const physical_address_t pc_addr,
|
||||
CacheRecorder::addRecord(int cntrl, Addr data_addr, Addr pc_addr,
|
||||
RubyRequestType type, Tick time, DataBlock& data)
|
||||
{
|
||||
TraceRecord* rec = (TraceRecord*)malloc(sizeof(TraceRecord) +
|
||||
|
|
|
|||
|
|
@ -56,8 +56,8 @@ class TraceRecord {
|
|||
public:
|
||||
int m_cntrl_id;
|
||||
Tick m_time;
|
||||
physical_address_t m_data_address;
|
||||
physical_address_t m_pc_address;
|
||||
Addr m_data_address;
|
||||
Addr m_pc_address;
|
||||
RubyRequestType m_type;
|
||||
uint8_t m_data[0];
|
||||
|
||||
|
|
@ -74,9 +74,8 @@ class CacheRecorder
|
|||
uint64_t uncompressed_trace_size,
|
||||
std::vector<Sequencer*>& SequencerMap,
|
||||
uint64_t block_size_bytes);
|
||||
void addRecord(int cntrl, const physical_address_t data_addr,
|
||||
const physical_address_t pc_addr, RubyRequestType type,
|
||||
Tick time, DataBlock& data);
|
||||
void addRecord(int cntrl, Addr data_addr, Addr pc_addr,
|
||||
RubyRequestType type, Tick time, DataBlock& data);
|
||||
|
||||
uint64 aggregateRecords(uint8_t** data, uint64 size);
|
||||
|
||||
|
|
|
|||
|
|
@ -94,7 +94,7 @@ DMASequencer::MemSlavePort::recvTimingReq(PacketPtr pkt)
|
|||
panic("DMASequencer should never see an inhibited request\n");
|
||||
|
||||
assert(isPhysMemAddress(pkt->getAddr()));
|
||||
assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <=
|
||||
assert(getOffset(pkt->getAddr()) + pkt->getSize() <=
|
||||
RubySystem::getBlockSizeBytes());
|
||||
|
||||
// Submit the ruby request
|
||||
|
|
@ -223,7 +223,7 @@ DMASequencer::makeRequest(PacketPtr pkt)
|
|||
return RequestStatus_BufferFull;
|
||||
}
|
||||
|
||||
uint64_t paddr = pkt->getAddr();
|
||||
Addr paddr = pkt->getAddr();
|
||||
uint8_t* data = pkt->getPtr<uint8_t>();
|
||||
int len = pkt->getSize();
|
||||
bool write = pkt->isWrite();
|
||||
|
|
@ -241,8 +241,8 @@ DMASequencer::makeRequest(PacketPtr pkt)
|
|||
|
||||
std::shared_ptr<SequencerMsg> msg =
|
||||
std::make_shared<SequencerMsg>(clockEdge());
|
||||
msg->getPhysicalAddress() = Address(paddr);
|
||||
msg->getLineAddress() = line_address(msg->getPhysicalAddress());
|
||||
msg->getPhysicalAddress() = paddr;
|
||||
msg->getLineAddress() = makeLineAddress(msg->getPhysicalAddress());
|
||||
msg->getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD;
|
||||
int offset = paddr & m_data_block_mask;
|
||||
|
||||
|
|
@ -280,11 +280,11 @@ DMASequencer::issueNext()
|
|||
|
||||
std::shared_ptr<SequencerMsg> msg =
|
||||
std::make_shared<SequencerMsg>(clockEdge());
|
||||
msg->getPhysicalAddress() = Address(active_request.start_paddr +
|
||||
active_request.bytes_completed);
|
||||
msg->getPhysicalAddress() = active_request.start_paddr +
|
||||
active_request.bytes_completed;
|
||||
|
||||
assert((msg->getPhysicalAddress().getAddress() & m_data_block_mask) == 0);
|
||||
msg->getLineAddress() = line_address(msg->getPhysicalAddress());
|
||||
assert((msg->getPhysicalAddress() & m_data_block_mask) == 0);
|
||||
msg->getLineAddress() = makeLineAddress(msg->getPhysicalAddress());
|
||||
|
||||
msg->getType() = (active_request.write ? SequencerRequestType_ST :
|
||||
SequencerRequestType_LD);
|
||||
|
|
|
|||
|
|
@ -76,7 +76,7 @@ class DMASequencer : public MemObject
|
|||
PortID id, RubySystem *_ruby_system,
|
||||
bool _access_backing_store);
|
||||
void hitCallback(PacketPtr pkt);
|
||||
void evictionCallback(const Address& address);
|
||||
void evictionCallback(Addr address);
|
||||
|
||||
protected:
|
||||
bool recvTimingReq(PacketPtr pkt);
|
||||
|
|
|
|||
|
|
@ -249,7 +249,7 @@ RubyPort::MemSlavePort::recvTimingReq(PacketPtr pkt)
|
|||
return true;
|
||||
}
|
||||
|
||||
assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <=
|
||||
assert(getOffset(pkt->getAddr()) + pkt->getSize() <=
|
||||
RubySystem::getBlockSizeBytes());
|
||||
|
||||
// Submit the ruby request
|
||||
|
|
@ -299,8 +299,7 @@ RubyPort::MemSlavePort::recvFunctional(PacketPtr pkt)
|
|||
}
|
||||
|
||||
assert(pkt->getAddr() + pkt->getSize() <=
|
||||
line_address(Address(pkt->getAddr())).getAddress() +
|
||||
RubySystem::getBlockSizeBytes());
|
||||
makeLineAddress(pkt->getAddr()) + RubySystem::getBlockSizeBytes());
|
||||
|
||||
if (access_backing_store) {
|
||||
// The attached physmem contains the official version of data.
|
||||
|
|
@ -504,14 +503,13 @@ RubyPort::MemSlavePort::isPhysMemAddress(Addr addr) const
|
|||
}
|
||||
|
||||
void
|
||||
RubyPort::ruby_eviction_callback(const Address& address)
|
||||
RubyPort::ruby_eviction_callback(Addr address)
|
||||
{
|
||||
DPRINTF(RubyPort, "Sending invalidations.\n");
|
||||
// This request is deleted in the stack-allocated packet destructor
|
||||
// when this function exits
|
||||
// TODO: should this really be using funcMasterId?
|
||||
RequestPtr req =
|
||||
new Request(address.getAddress(), 0, 0, Request::funcMasterId);
|
||||
RequestPtr req = new Request(address, 0, 0, Request::funcMasterId);
|
||||
// Use a single packet to signal all snooping ports of the invalidation.
|
||||
// This assumes that snooping ports do NOT modify the packet/request
|
||||
Packet pkt(req, MemCmd::InvalidateReq);
|
||||
|
|
|
|||
|
|
@ -81,7 +81,7 @@ class RubyPort : public MemObject
|
|||
MemSlavePort(const std::string &_name, RubyPort *_port,
|
||||
bool _access_backing_store, PortID id);
|
||||
void hitCallback(PacketPtr pkt);
|
||||
void evictionCallback(const Address& address);
|
||||
void evictionCallback(Addr address);
|
||||
|
||||
protected:
|
||||
bool recvTimingReq(PacketPtr pkt);
|
||||
|
|
@ -166,7 +166,7 @@ class RubyPort : public MemObject
|
|||
protected:
|
||||
void ruby_hit_callback(PacketPtr pkt);
|
||||
void testDrainComplete();
|
||||
void ruby_eviction_callback(const Address& address);
|
||||
void ruby_eviction_callback(Addr address);
|
||||
|
||||
/**
|
||||
* Called by the PIO port when receiving a timing response.
|
||||
|
|
|
|||
|
|
@ -98,7 +98,7 @@ Sequencer::wakeup()
|
|||
panic("Possible Deadlock detected. Aborting!\n"
|
||||
"version: %d request.paddr: 0x%x m_readRequestTable: %d "
|
||||
"current time: %u issue_time: %d difference: %d\n", m_version,
|
||||
Address(request->pkt->getAddr()), m_readRequestTable.size(),
|
||||
request->pkt->getAddr(), m_readRequestTable.size(),
|
||||
current_time * clockPeriod(), request->issue_time * clockPeriod(),
|
||||
(current_time * clockPeriod()) - (request->issue_time * clockPeriod()));
|
||||
}
|
||||
|
|
@ -113,7 +113,7 @@ Sequencer::wakeup()
|
|||
panic("Possible Deadlock detected. Aborting!\n"
|
||||
"version: %d request.paddr: 0x%x m_writeRequestTable: %d "
|
||||
"current time: %u issue_time: %d difference: %d\n", m_version,
|
||||
Address(request->pkt->getAddr()), m_writeRequestTable.size(),
|
||||
request->pkt->getAddr(), m_writeRequestTable.size(),
|
||||
current_time * clockPeriod(), request->issue_time * clockPeriod(),
|
||||
(current_time * clockPeriod()) - (request->issue_time * clockPeriod()));
|
||||
}
|
||||
|
|
@ -222,8 +222,7 @@ Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type)
|
|||
schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold));
|
||||
}
|
||||
|
||||
Address line_addr(pkt->getAddr());
|
||||
line_addr.makeLineAddress();
|
||||
Addr line_addr = makeLineAddress(pkt->getAddr());
|
||||
// Create a default entry, mapping the address to NULL, the cast is
|
||||
// there to make gcc 4.4 happy
|
||||
RequestTable::value_type default_entry(line_addr,
|
||||
|
|
@ -299,8 +298,7 @@ Sequencer::removeRequest(SequencerRequest* srequest)
|
|||
assert(m_outstanding_count ==
|
||||
m_writeRequestTable.size() + m_readRequestTable.size());
|
||||
|
||||
Address line_addr(srequest->pkt->getAddr());
|
||||
line_addr.makeLineAddress();
|
||||
Addr line_addr = makeLineAddress(srequest->pkt->getAddr());
|
||||
if ((srequest->m_type == RubyRequestType_ST) ||
|
||||
(srequest->m_type == RubyRequestType_RMW_Read) ||
|
||||
(srequest->m_type == RubyRequestType_RMW_Write) ||
|
||||
|
|
@ -317,7 +315,7 @@ Sequencer::removeRequest(SequencerRequest* srequest)
|
|||
}
|
||||
|
||||
void
|
||||
Sequencer::invalidateSC(const Address& address)
|
||||
Sequencer::invalidateSC(Addr address)
|
||||
{
|
||||
RequestTable::iterator i = m_writeRequestTable.find(address);
|
||||
if (i != m_writeRequestTable.end()) {
|
||||
|
|
@ -331,7 +329,7 @@ Sequencer::invalidateSC(const Address& address)
|
|||
}
|
||||
|
||||
bool
|
||||
Sequencer::handleLlsc(const Address& address, SequencerRequest* request)
|
||||
Sequencer::handleLlsc(Addr address, SequencerRequest* request)
|
||||
{
|
||||
//
|
||||
// The success flag indicates whether the LLSC operation was successful.
|
||||
|
|
@ -422,14 +420,14 @@ Sequencer::recordMissLatency(const Cycles cycles, const RubyRequestType type,
|
|||
}
|
||||
|
||||
void
|
||||
Sequencer::writeCallback(const Address& address, DataBlock& data,
|
||||
Sequencer::writeCallback(Addr address, DataBlock& data,
|
||||
const bool externalHit, const MachineType mach,
|
||||
const Cycles initialRequestTime,
|
||||
const Cycles forwardRequestTime,
|
||||
const Cycles firstResponseTime)
|
||||
{
|
||||
assert(address == line_address(address));
|
||||
assert(m_writeRequestTable.count(line_address(address)));
|
||||
assert(address == makeLineAddress(address));
|
||||
assert(m_writeRequestTable.count(makeLineAddress(address)));
|
||||
|
||||
RequestTable::iterator i = m_writeRequestTable.find(address);
|
||||
assert(i != m_writeRequestTable.end());
|
||||
|
|
@ -469,14 +467,14 @@ Sequencer::writeCallback(const Address& address, DataBlock& data,
|
|||
}
|
||||
|
||||
void
|
||||
Sequencer::readCallback(const Address& address, DataBlock& data,
|
||||
Sequencer::readCallback(Addr address, DataBlock& data,
|
||||
bool externalHit, const MachineType mach,
|
||||
Cycles initialRequestTime,
|
||||
Cycles forwardRequestTime,
|
||||
Cycles firstResponseTime)
|
||||
{
|
||||
assert(address == line_address(address));
|
||||
assert(m_readRequestTable.count(line_address(address)));
|
||||
assert(address == makeLineAddress(address));
|
||||
assert(m_readRequestTable.count(makeLineAddress(address)));
|
||||
|
||||
RequestTable::iterator i = m_readRequestTable.find(address);
|
||||
assert(i != m_readRequestTable.end());
|
||||
|
|
@ -501,9 +499,8 @@ Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data,
|
|||
const Cycles firstResponseTime)
|
||||
{
|
||||
PacketPtr pkt = srequest->pkt;
|
||||
Address request_address(pkt->getAddr());
|
||||
Address request_line_address(pkt->getAddr());
|
||||
request_line_address.makeLineAddress();
|
||||
Addr request_address(pkt->getAddr());
|
||||
Addr request_line_address = makeLineAddress(pkt->getAddr());
|
||||
RubyRequestType type = srequest->m_type;
|
||||
Cycles issued_time = srequest->issue_time;
|
||||
|
||||
|
|
@ -522,7 +519,7 @@ Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data,
|
|||
initialRequestTime, forwardRequestTime,
|
||||
firstResponseTime, curCycle());
|
||||
|
||||
DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %d cycles\n",
|
||||
DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %d cycles\n",
|
||||
curTick(), m_version, "Seq",
|
||||
llscSuccess ? "Done" : "SC_Failed", "", "",
|
||||
request_address, total_latency);
|
||||
|
|
@ -530,7 +527,7 @@ Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data,
|
|||
// update the data unless it is a non-data-carrying flush
|
||||
if (RubySystem::getWarmupEnabled()) {
|
||||
data.setData(pkt->getConstPtr<uint8_t>(),
|
||||
request_address.getOffset(), pkt->getSize());
|
||||
getOffset(request_address), pkt->getSize());
|
||||
} else if (!pkt->isFlush()) {
|
||||
if ((type == RubyRequestType_LD) ||
|
||||
(type == RubyRequestType_IFETCH) ||
|
||||
|
|
@ -538,12 +535,12 @@ Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data,
|
|||
(type == RubyRequestType_Locked_RMW_Read) ||
|
||||
(type == RubyRequestType_Load_Linked)) {
|
||||
memcpy(pkt->getPtr<uint8_t>(),
|
||||
data.getData(request_address.getOffset(), pkt->getSize()),
|
||||
data.getData(getOffset(request_address), pkt->getSize()),
|
||||
pkt->getSize());
|
||||
DPRINTF(RubySequencer, "read data %s\n", data);
|
||||
} else {
|
||||
data.setData(pkt->getConstPtr<uint8_t>(),
|
||||
request_address.getOffset(), pkt->getSize());
|
||||
getOffset(request_address), pkt->getSize());
|
||||
DPRINTF(RubySequencer, "set data %s\n", data);
|
||||
}
|
||||
}
|
||||
|
|
@ -690,7 +687,7 @@ Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type)
|
|||
RubyAccessMode_Supervisor, pkt,
|
||||
PrefetchBit_No, proc_id);
|
||||
|
||||
DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %s\n",
|
||||
DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %s\n",
|
||||
curTick(), m_version, "Seq", "Begin", "", "",
|
||||
msg->getPhysicalAddress(),
|
||||
RubyRequestType_to_string(secondary_type));
|
||||
|
|
@ -743,7 +740,7 @@ Sequencer::print(ostream& out) const
|
|||
// upgraded when invoked, coherence violations will be checked for the
|
||||
// given block
|
||||
void
|
||||
Sequencer::checkCoherence(const Address& addr)
|
||||
Sequencer::checkCoherence(Addr addr)
|
||||
{
|
||||
#ifdef CHECK_COHERENCE
|
||||
m_ruby_system->checkGlobalCoherenceInvariant(addr);
|
||||
|
|
@ -758,7 +755,7 @@ Sequencer::recordRequestType(SequencerRequestType requestType) {
|
|||
|
||||
|
||||
void
|
||||
Sequencer::evictionCallback(const Address& address)
|
||||
Sequencer::evictionCallback(Addr address)
|
||||
{
|
||||
ruby_eviction_callback(address);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -68,7 +68,7 @@ class Sequencer : public RubyPort
|
|||
void collateStats();
|
||||
void regStats();
|
||||
|
||||
void writeCallback(const Address& address,
|
||||
void writeCallback(Addr address,
|
||||
DataBlock& data,
|
||||
const bool externalHit = false,
|
||||
const MachineType mach = MachineType_NUM,
|
||||
|
|
@ -76,7 +76,7 @@ class Sequencer : public RubyPort
|
|||
const Cycles forwardRequestTime = Cycles(0),
|
||||
const Cycles firstResponseTime = Cycles(0));
|
||||
|
||||
void readCallback(const Address& address,
|
||||
void readCallback(Addr address,
|
||||
DataBlock& data,
|
||||
const bool externalHit = false,
|
||||
const MachineType mach = MachineType_NUM,
|
||||
|
|
@ -95,12 +95,12 @@ class Sequencer : public RubyPort
|
|||
{ deschedule(deadlockCheckEvent); }
|
||||
|
||||
void print(std::ostream& out) const;
|
||||
void checkCoherence(const Address& address);
|
||||
void checkCoherence(Addr address);
|
||||
|
||||
void markRemoved();
|
||||
void removeRequest(SequencerRequest* request);
|
||||
void evictionCallback(const Address& address);
|
||||
void invalidateSC(const Address& address);
|
||||
void evictionCallback(Addr address);
|
||||
void invalidateSC(Addr address);
|
||||
|
||||
void recordRequestType(SequencerRequestType requestType);
|
||||
Stats::Histogram& getOutstandReqHist() { return m_outstandReqHist; }
|
||||
|
|
@ -167,7 +167,7 @@ class Sequencer : public RubyPort
|
|||
Cycles completionTime);
|
||||
|
||||
RequestStatus insertRequest(PacketPtr pkt, RubyRequestType request_type);
|
||||
bool handleLlsc(const Address& address, SequencerRequest* request);
|
||||
bool handleLlsc(Addr address, SequencerRequest* request);
|
||||
|
||||
// Private copy constructor and assignment operator
|
||||
Sequencer(const Sequencer& obj);
|
||||
|
|
@ -187,7 +187,7 @@ class Sequencer : public RubyPort
|
|||
Cycles m_data_cache_hit_latency;
|
||||
Cycles m_inst_cache_hit_latency;
|
||||
|
||||
typedef m5::hash_map<Address, SequencerRequest*> RequestTable;
|
||||
typedef m5::hash_map<Addr, SequencerRequest*> RequestTable;
|
||||
RequestTable m_writeRequestTable;
|
||||
RequestTable m_readRequestTable;
|
||||
// Global outstanding request count, across all request tables
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue