Devices: Clean up the IDE controller.
This commit is contained in:
Gabe Black
parent
993b7be4bb
commit
9192b7f1ef
4 changed files with 530 additions and 772 deletions
File diff suppressed because it is too large
Load diff
|
|
@ -37,61 +37,13 @@
|
|||
#ifndef __IDE_CTRL_HH__
|
||||
#define __IDE_CTRL_HH__
|
||||
|
||||
#include "base/bitunion.hh"
|
||||
#include "dev/pcidev.hh"
|
||||
#include "dev/pcireg.h"
|
||||
#include "dev/io_device.hh"
|
||||
#include "params/IdeController.hh"
|
||||
|
||||
#define BMIC0 0x0 // Bus master IDE command register
|
||||
#define BMIS0 0x2 // Bus master IDE status register
|
||||
#define BMIDTP0 0x4 // Bus master IDE descriptor table pointer register
|
||||
#define BMIC1 0x8 // Bus master IDE command register
|
||||
#define BMIS1 0xa // Bus master IDE status register
|
||||
#define BMIDTP1 0xc // Bus master IDE descriptor table pointer register
|
||||
|
||||
// Bus master IDE command register bit fields
|
||||
#define RWCON 0x08 // Bus master read/write control
|
||||
#define SSBM 0x01 // Start/stop bus master
|
||||
|
||||
// Bus master IDE status register bit fields
|
||||
#define DMA1CAP 0x40 // Drive 1 DMA capable
|
||||
#define DMA0CAP 0x20 // Drive 0 DMA capable
|
||||
#define IDEINTS 0x04 // IDE Interrupt Status
|
||||
#define IDEDMAE 0x02 // IDE DMA error
|
||||
#define BMIDEA 0x01 // Bus master IDE active
|
||||
|
||||
// IDE Command byte fields
|
||||
#define IDE_SELECT_OFFSET (6)
|
||||
#define IDE_SELECT_DEV_BIT 0x10
|
||||
|
||||
#define IDE_FEATURE_OFFSET IDE_ERROR_OFFSET
|
||||
#define IDE_COMMAND_OFFSET IDE_STATUS_OFFSET
|
||||
|
||||
// IDE Timing Register bit fields
|
||||
#define IDETIM_DECODE_EN 0x8000
|
||||
|
||||
// PCI device specific register byte offsets
|
||||
#define IDE_CTRL_CONF_START 0x40
|
||||
#define IDE_CTRL_CONF_END ((IDE_CTRL_CONF_START) + sizeof(config_regs))
|
||||
|
||||
#define IDE_CTRL_CONF_PRIM_TIMING 0x40
|
||||
#define IDE_CTRL_CONF_SEC_TIMING 0x42
|
||||
#define IDE_CTRL_CONF_DEV_TIMING 0x44
|
||||
#define IDE_CTRL_CONF_UDMA_CNTRL 0x48
|
||||
#define IDE_CTRL_CONF_UDMA_TIMING 0x4A
|
||||
#define IDE_CTRL_CONF_IDE_CONFIG 0x54
|
||||
|
||||
|
||||
enum IdeRegType {
|
||||
COMMAND_BLOCK,
|
||||
CONTROL_BLOCK,
|
||||
BMI_BLOCK
|
||||
};
|
||||
|
||||
class IdeDisk;
|
||||
class IntrControl;
|
||||
class PciConfigAll;
|
||||
class Platform;
|
||||
|
||||
/**
|
||||
* Device model for an Intel PIIX4 IDE controller
|
||||
|
|
@ -99,137 +51,106 @@ class Platform;
|
|||
|
||||
class IdeController : public PciDev
|
||||
{
|
||||
friend class IdeDisk;
|
||||
|
||||
enum IdeChannel {
|
||||
PRIMARY = 0,
|
||||
SECONDARY = 1
|
||||
};
|
||||
|
||||
private:
|
||||
/** Primary command block registers */
|
||||
Addr pri_cmd_addr;
|
||||
Addr pri_cmd_size;
|
||||
/** Primary control block registers */
|
||||
Addr pri_ctrl_addr;
|
||||
Addr pri_ctrl_size;
|
||||
/** Secondary command block registers */
|
||||
Addr sec_cmd_addr;
|
||||
Addr sec_cmd_size;
|
||||
/** Secondary control block registers */
|
||||
Addr sec_ctrl_addr;
|
||||
Addr sec_ctrl_size;
|
||||
/** Bus master interface (BMI) registers */
|
||||
Addr bmi_addr;
|
||||
Addr bmi_size;
|
||||
// Bus master IDE status register bit fields
|
||||
BitUnion8(BMIStatusReg)
|
||||
Bitfield<6> dmaCap0;
|
||||
Bitfield<5> dmaCap1;
|
||||
Bitfield<2> intStatus;
|
||||
Bitfield<1> dmaError;
|
||||
Bitfield<0> active;
|
||||
EndBitUnion(BMIStatusReg)
|
||||
|
||||
BitUnion8(BMICommandReg)
|
||||
Bitfield<3> rw;
|
||||
Bitfield<0> startStop;
|
||||
EndBitUnion(BMICommandReg)
|
||||
|
||||
struct Channel
|
||||
{
|
||||
std::string _name;
|
||||
|
||||
const std::string
|
||||
name()
|
||||
{
|
||||
return _name;
|
||||
}
|
||||
|
||||
/** Command and control block registers */
|
||||
Addr cmdAddr, cmdSize, ctrlAddr, ctrlSize;
|
||||
|
||||
private:
|
||||
/** Registers used for bus master interface */
|
||||
union {
|
||||
uint8_t data[16];
|
||||
|
||||
struct {
|
||||
uint8_t bmic0;
|
||||
uint8_t reserved_0;
|
||||
uint8_t bmis0;
|
||||
uint8_t reserved_1;
|
||||
uint32_t bmidtp0;
|
||||
uint8_t bmic1;
|
||||
uint8_t reserved_2;
|
||||
uint8_t bmis1;
|
||||
uint8_t reserved_3;
|
||||
uint32_t bmidtp1;
|
||||
};
|
||||
|
||||
struct {
|
||||
uint8_t bmic;
|
||||
uint8_t reserved_4;
|
||||
uint8_t bmis;
|
||||
uint8_t reserved_5;
|
||||
struct BMIRegs
|
||||
{
|
||||
BMICommandReg command;
|
||||
uint8_t reserved0;
|
||||
BMIStatusReg status;
|
||||
uint8_t reserved1;
|
||||
uint32_t bmidtp;
|
||||
} chan[2];
|
||||
} bmiRegs;
|
||||
|
||||
/** IDE disks connected to this controller */
|
||||
IdeDisk *master, *slave;
|
||||
|
||||
/** Currently selected disk */
|
||||
IdeDisk *selected;
|
||||
|
||||
bool selectBit;
|
||||
|
||||
void
|
||||
select(bool selSlave)
|
||||
{
|
||||
selectBit = selSlave;
|
||||
selected = selectBit ? slave : master;
|
||||
}
|
||||
|
||||
void accessCommand(Addr offset, int size, uint8_t *data, bool read);
|
||||
void accessControl(Addr offset, int size, uint8_t *data, bool read);
|
||||
void accessBMI(Addr offset, int size, uint8_t *data, bool read);
|
||||
|
||||
Channel(std::string newName, Addr _cmdSize, Addr _ctrlSize);
|
||||
~Channel();
|
||||
|
||||
void serialize(std::ostream &os);
|
||||
void unserialize(Checkpoint *cp, const std::string §ion);
|
||||
|
||||
} primary, secondary;
|
||||
|
||||
/** Bus master interface (BMI) registers */
|
||||
Addr bmiAddr, bmiSize;
|
||||
|
||||
} bmi_regs;
|
||||
/** Shadows of the device select bit */
|
||||
uint8_t dev[2];
|
||||
/** Registers used in device specific PCI configuration */
|
||||
union {
|
||||
uint8_t data[22];
|
||||
|
||||
struct {
|
||||
uint16_t idetim0;
|
||||
uint16_t idetim1;
|
||||
uint8_t sidetim;
|
||||
uint8_t reserved_0[3];
|
||||
uint8_t udmactl;
|
||||
uint8_t reserved_1;
|
||||
uint16_t udmatim;
|
||||
uint8_t reserved_2[8];
|
||||
uint16_t ideconfig;
|
||||
};
|
||||
} config_regs;
|
||||
uint16_t primaryTiming, secondaryTiming;
|
||||
uint8_t deviceTiming;
|
||||
uint8_t udmaControl;
|
||||
uint16_t udmaTiming;
|
||||
uint16_t ideConfig;
|
||||
|
||||
// Internal management variables
|
||||
bool io_enabled;
|
||||
bool bm_enabled;
|
||||
bool cmd_in_progress[4];
|
||||
bool ioEnabled;
|
||||
bool bmEnabled;
|
||||
|
||||
private:
|
||||
/** IDE disks connected to controller */
|
||||
IdeDisk *disks[4];
|
||||
|
||||
private:
|
||||
/** Parse the access address to pass on to device */
|
||||
void parseAddr(const Addr &addr, Addr &offset, IdeChannel &channel,
|
||||
IdeRegType ®_type);
|
||||
|
||||
/** Select the disk based on the channel and device bit */
|
||||
int getDisk(IdeChannel channel);
|
||||
|
||||
/** Select the disk based on a pointer */
|
||||
int getDisk(IdeDisk *diskPtr);
|
||||
|
||||
public:
|
||||
/** See if a disk is selected based on its pointer */
|
||||
bool isDiskSelected(IdeDisk *diskPtr);
|
||||
void dispatchAccess(PacketPtr pkt, bool read);
|
||||
|
||||
public:
|
||||
typedef IdeControllerParams Params;
|
||||
const Params *params() const { return (const Params *)_params; }
|
||||
IdeController(Params *p);
|
||||
~IdeController();
|
||||
|
||||
virtual Tick writeConfig(PacketPtr pkt);
|
||||
virtual Tick readConfig(PacketPtr pkt);
|
||||
/** See if a disk is selected based on its pointer */
|
||||
bool isDiskSelected(IdeDisk *diskPtr);
|
||||
|
||||
void intrPost();
|
||||
|
||||
Tick writeConfig(PacketPtr pkt);
|
||||
Tick readConfig(PacketPtr pkt);
|
||||
|
||||
void setDmaComplete(IdeDisk *disk);
|
||||
|
||||
/**
|
||||
* Read a done field for a given target.
|
||||
* @param pkt Packet describing what is to be read
|
||||
* @return The amount of time to complete this request
|
||||
*/
|
||||
virtual Tick read(PacketPtr pkt);
|
||||
|
||||
/**
|
||||
* Write a done field for a given target.
|
||||
* @param pkt Packet describing what is to be written
|
||||
* @return The amount of time to complete this request
|
||||
*/
|
||||
virtual Tick write(PacketPtr pkt);
|
||||
|
||||
/**
|
||||
* Serialize this object to the given output stream.
|
||||
* @param os The stream to serialize to.
|
||||
*/
|
||||
virtual void serialize(std::ostream &os);
|
||||
|
||||
/**
|
||||
* Reconstruct the state of this object from a checkpoint.
|
||||
* @param cp The checkpoint use.
|
||||
* @param section The section name of this object
|
||||
*/
|
||||
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
||||
Tick read(PacketPtr pkt);
|
||||
Tick write(PacketPtr pkt);
|
||||
|
||||
void serialize(std::ostream &os);
|
||||
void unserialize(Checkpoint *cp, const std::string §ion);
|
||||
};
|
||||
#endif // __IDE_CTRL_HH_
|
||||
|
|
|
|||
|
|
@ -177,7 +177,7 @@ Addr
|
|||
IdeDisk::pciToDma(Addr pciAddr)
|
||||
{
|
||||
if (ctrl)
|
||||
return ctrl->plat->pciToDma(pciAddr);
|
||||
return ctrl->pciToDma(pciAddr);
|
||||
else
|
||||
panic("Access to unset controller!\n");
|
||||
}
|
||||
|
|
@ -187,18 +187,23 @@ IdeDisk::pciToDma(Addr pciAddr)
|
|||
////
|
||||
|
||||
void
|
||||
IdeDisk::read(const Addr &offset, IdeRegType reg_type, uint8_t *data)
|
||||
IdeDisk::readCommand(const Addr offset, int size, uint8_t *data)
|
||||
{
|
||||
DevAction_t action = ACT_NONE;
|
||||
|
||||
switch (reg_type) {
|
||||
case COMMAND_BLOCK:
|
||||
if (offset == DATA_OFFSET) {
|
||||
if (size == sizeof(uint16_t)) {
|
||||
*(uint16_t *)data = cmdReg.data;
|
||||
} else if (size == sizeof(uint32_t)) {
|
||||
*(uint16_t *)data = cmdReg.data;
|
||||
updateState(ACT_DATA_READ_SHORT);
|
||||
*((uint16_t *)data + 1) = cmdReg.data;
|
||||
} else {
|
||||
panic("Data read of unsupported size %d.\n", size);
|
||||
}
|
||||
updateState(ACT_DATA_READ_SHORT);
|
||||
return;
|
||||
}
|
||||
assert(size == sizeof(uint8_t));
|
||||
switch (offset) {
|
||||
// Data transfers occur two bytes at a time
|
||||
case DATA_OFFSET:
|
||||
*(uint16_t*)data = cmdReg.data;
|
||||
action = ACT_DATA_READ_SHORT;
|
||||
break;
|
||||
case ERROR_OFFSET:
|
||||
*data = cmdReg.error;
|
||||
break;
|
||||
|
|
@ -219,40 +224,43 @@ IdeDisk::read(const Addr &offset, IdeRegType reg_type, uint8_t *data)
|
|||
break;
|
||||
case STATUS_OFFSET:
|
||||
*data = status;
|
||||
action = ACT_STAT_READ;
|
||||
updateState(ACT_STAT_READ);
|
||||
break;
|
||||
default:
|
||||
panic("Invalid IDE command register offset: %#x\n", offset);
|
||||
}
|
||||
break;
|
||||
case CONTROL_BLOCK:
|
||||
if (offset == ALTSTAT_OFFSET)
|
||||
*data = status;
|
||||
else
|
||||
panic("Invalid IDE control register offset: %#x\n", offset);
|
||||
break;
|
||||
default:
|
||||
panic("Unknown register block!\n");
|
||||
}
|
||||
DPRINTF(IdeDisk, "Read to disk at offset: %#x data %#x\n", offset,
|
||||
(uint32_t)*data);
|
||||
|
||||
if (action != ACT_NONE)
|
||||
updateState(action);
|
||||
DPRINTF(IdeDisk, "Read to disk at offset: %#x data %#x\n", offset, *data);
|
||||
}
|
||||
|
||||
void
|
||||
IdeDisk::write(const Addr &offset, IdeRegType reg_type, const uint8_t *data)
|
||||
IdeDisk::readControl(const Addr offset, int size, uint8_t *data)
|
||||
{
|
||||
DevAction_t action = ACT_NONE;
|
||||
assert(size == sizeof(uint8_t));
|
||||
*data = status;
|
||||
if (offset != ALTSTAT_OFFSET)
|
||||
panic("Invalid IDE control register offset: %#x\n", offset);
|
||||
DPRINTF(IdeDisk, "Read to disk at offset: %#x data %#x\n", offset, *data);
|
||||
}
|
||||
|
||||
switch (reg_type) {
|
||||
case COMMAND_BLOCK:
|
||||
void
|
||||
IdeDisk::writeCommand(const Addr offset, int size, const uint8_t *data)
|
||||
{
|
||||
if (offset == DATA_OFFSET) {
|
||||
if (size == sizeof(uint16_t)) {
|
||||
cmdReg.data = *(const uint16_t *)data;
|
||||
} else if (size == sizeof(uint32_t)) {
|
||||
cmdReg.data = *(const uint16_t *)data;
|
||||
updateState(ACT_DATA_WRITE_SHORT);
|
||||
cmdReg.data = *((const uint16_t *)data + 1);
|
||||
} else {
|
||||
panic("Data write of unsupported size %d.\n", size);
|
||||
}
|
||||
updateState(ACT_DATA_WRITE_SHORT);
|
||||
return;
|
||||
}
|
||||
|
||||
assert(size == sizeof(uint8_t));
|
||||
switch (offset) {
|
||||
case DATA_OFFSET:
|
||||
cmdReg.data = *(uint16_t*)data;
|
||||
action = ACT_DATA_WRITE_SHORT;
|
||||
break;
|
||||
case FEATURES_OFFSET:
|
||||
break;
|
||||
case NSECTOR_OFFSET:
|
||||
|
|
@ -269,38 +277,37 @@ IdeDisk::write(const Addr &offset, IdeRegType reg_type, const uint8_t *data)
|
|||
break;
|
||||
case DRIVE_OFFSET:
|
||||
cmdReg.drive = *data;
|
||||
action = ACT_SELECT_WRITE;
|
||||
updateState(ACT_SELECT_WRITE);
|
||||
break;
|
||||
case COMMAND_OFFSET:
|
||||
cmdReg.command = *data;
|
||||
action = ACT_CMD_WRITE;
|
||||
updateState(ACT_CMD_WRITE);
|
||||
break;
|
||||
default:
|
||||
panic("Invalid IDE command register offset: %#x\n", offset);
|
||||
}
|
||||
break;
|
||||
case CONTROL_BLOCK:
|
||||
if (offset == CONTROL_OFFSET) {
|
||||
DPRINTF(IdeDisk, "Write to disk at offset: %#x data %#x\n", offset,
|
||||
(uint32_t)*data);
|
||||
}
|
||||
|
||||
void
|
||||
IdeDisk::writeControl(const Addr offset, int size, const uint8_t *data)
|
||||
{
|
||||
if (offset != CONTROL_OFFSET)
|
||||
panic("Invalid IDE control register offset: %#x\n", offset);
|
||||
|
||||
if (*data & CONTROL_RST_BIT) {
|
||||
// force the device into the reset state
|
||||
devState = Device_Srst;
|
||||
action = ACT_SRST_SET;
|
||||
} else if (devState == Device_Srst && !(*data & CONTROL_RST_BIT))
|
||||
action = ACT_SRST_CLEAR;
|
||||
updateState(ACT_SRST_SET);
|
||||
} else if (devState == Device_Srst && !(*data & CONTROL_RST_BIT)) {
|
||||
updateState(ACT_SRST_CLEAR);
|
||||
}
|
||||
|
||||
nIENBit = (*data & CONTROL_IEN_BIT) ? true : false;
|
||||
}
|
||||
else
|
||||
panic("Invalid IDE control register offset: %#x\n", offset);
|
||||
break;
|
||||
default:
|
||||
panic("Unknown register block!\n");
|
||||
}
|
||||
nIENBit = *data & CONTROL_IEN_BIT;
|
||||
|
||||
DPRINTF(IdeDisk, "Write to disk at offset: %#x data %#x\n", offset,
|
||||
(uint32_t)*data);
|
||||
if (action != ACT_NONE)
|
||||
updateState(action);
|
||||
}
|
||||
|
||||
////
|
||||
|
|
@ -683,7 +690,6 @@ IdeDisk::intrPost()
|
|||
|
||||
// talk to controller to set interrupt
|
||||
if (ctrl) {
|
||||
ctrl->bmi_regs.bmis0 |= IDEINTS;
|
||||
ctrl->intrPost();
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -278,8 +278,10 @@ class IdeDisk : public SimObject
|
|||
}
|
||||
|
||||
// Device register read/write
|
||||
void read(const Addr &offset, IdeRegType regtype, uint8_t *data);
|
||||
void write(const Addr &offset, IdeRegType regtype, const uint8_t *data);
|
||||
void readCommand(const Addr offset, int size, uint8_t *data);
|
||||
void readControl(const Addr offset, int size, uint8_t *data);
|
||||
void writeCommand(const Addr offset, int size, const uint8_t *data);
|
||||
void writeControl(const Addr offset, int size, const uint8_t *data);
|
||||
|
||||
// Start/abort functions
|
||||
void startDma(const uint32_t &prdTableBase);
|
||||
|
|
|
|||
Loading…
Reference in a new issue