Devices: Clean up the IDE controller.
This commit is contained in:
Gabe Black
parent
993b7be4bb
commit
9192b7f1ef
4 changed files with 530 additions and 772 deletions
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@ -37,61 +37,13 @@
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#ifndef __IDE_CTRL_HH__
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#define __IDE_CTRL_HH__
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#include "base/bitunion.hh"
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#include "dev/pcidev.hh"
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#include "dev/pcireg.h"
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#include "dev/io_device.hh"
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#include "params/IdeController.hh"
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#define BMIC0 0x0 // Bus master IDE command register
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#define BMIS0 0x2 // Bus master IDE status register
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#define BMIDTP0 0x4 // Bus master IDE descriptor table pointer register
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#define BMIC1 0x8 // Bus master IDE command register
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#define BMIS1 0xa // Bus master IDE status register
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#define BMIDTP1 0xc // Bus master IDE descriptor table pointer register
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// Bus master IDE command register bit fields
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#define RWCON 0x08 // Bus master read/write control
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#define SSBM 0x01 // Start/stop bus master
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// Bus master IDE status register bit fields
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#define DMA1CAP 0x40 // Drive 1 DMA capable
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#define DMA0CAP 0x20 // Drive 0 DMA capable
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#define IDEINTS 0x04 // IDE Interrupt Status
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#define IDEDMAE 0x02 // IDE DMA error
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#define BMIDEA 0x01 // Bus master IDE active
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// IDE Command byte fields
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#define IDE_SELECT_OFFSET (6)
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#define IDE_SELECT_DEV_BIT 0x10
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#define IDE_FEATURE_OFFSET IDE_ERROR_OFFSET
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#define IDE_COMMAND_OFFSET IDE_STATUS_OFFSET
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// IDE Timing Register bit fields
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#define IDETIM_DECODE_EN 0x8000
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// PCI device specific register byte offsets
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#define IDE_CTRL_CONF_START 0x40
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#define IDE_CTRL_CONF_END ((IDE_CTRL_CONF_START) + sizeof(config_regs))
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#define IDE_CTRL_CONF_PRIM_TIMING 0x40
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#define IDE_CTRL_CONF_SEC_TIMING 0x42
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#define IDE_CTRL_CONF_DEV_TIMING 0x44
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#define IDE_CTRL_CONF_UDMA_CNTRL 0x48
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#define IDE_CTRL_CONF_UDMA_TIMING 0x4A
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#define IDE_CTRL_CONF_IDE_CONFIG 0x54
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enum IdeRegType {
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COMMAND_BLOCK,
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CONTROL_BLOCK,
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BMI_BLOCK
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};
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class IdeDisk;
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class IntrControl;
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class PciConfigAll;
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class Platform;
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/**
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* Device model for an Intel PIIX4 IDE controller
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@ -99,137 +51,106 @@ class Platform;
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class IdeController : public PciDev
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{
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friend class IdeDisk;
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enum IdeChannel {
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PRIMARY = 0,
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SECONDARY = 1
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};
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private:
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/** Primary command block registers */
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Addr pri_cmd_addr;
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Addr pri_cmd_size;
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/** Primary control block registers */
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Addr pri_ctrl_addr;
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Addr pri_ctrl_size;
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/** Secondary command block registers */
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Addr sec_cmd_addr;
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Addr sec_cmd_size;
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/** Secondary control block registers */
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Addr sec_ctrl_addr;
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Addr sec_ctrl_size;
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/** Bus master interface (BMI) registers */
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Addr bmi_addr;
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Addr bmi_size;
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// Bus master IDE status register bit fields
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BitUnion8(BMIStatusReg)
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Bitfield<6> dmaCap0;
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Bitfield<5> dmaCap1;
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Bitfield<2> intStatus;
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Bitfield<1> dmaError;
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Bitfield<0> active;
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EndBitUnion(BMIStatusReg)
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BitUnion8(BMICommandReg)
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Bitfield<3> rw;
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Bitfield<0> startStop;
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EndBitUnion(BMICommandReg)
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struct Channel
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{
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std::string _name;
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const std::string
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name()
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{
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return _name;
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}
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/** Command and control block registers */
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Addr cmdAddr, cmdSize, ctrlAddr, ctrlSize;
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private:
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/** Registers used for bus master interface */
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union {
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uint8_t data[16];
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struct {
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uint8_t bmic0;
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uint8_t reserved_0;
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uint8_t bmis0;
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uint8_t reserved_1;
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uint32_t bmidtp0;
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uint8_t bmic1;
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uint8_t reserved_2;
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uint8_t bmis1;
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uint8_t reserved_3;
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uint32_t bmidtp1;
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};
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struct {
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uint8_t bmic;
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uint8_t reserved_4;
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uint8_t bmis;
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uint8_t reserved_5;
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struct BMIRegs
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{
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BMICommandReg command;
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uint8_t reserved0;
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BMIStatusReg status;
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uint8_t reserved1;
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uint32_t bmidtp;
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} chan[2];
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} bmiRegs;
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/** IDE disks connected to this controller */
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IdeDisk *master, *slave;
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/** Currently selected disk */
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IdeDisk *selected;
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bool selectBit;
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void
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select(bool selSlave)
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{
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selectBit = selSlave;
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selected = selectBit ? slave : master;
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}
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void accessCommand(Addr offset, int size, uint8_t *data, bool read);
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void accessControl(Addr offset, int size, uint8_t *data, bool read);
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void accessBMI(Addr offset, int size, uint8_t *data, bool read);
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Channel(std::string newName, Addr _cmdSize, Addr _ctrlSize);
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~Channel();
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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} primary, secondary;
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/** Bus master interface (BMI) registers */
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Addr bmiAddr, bmiSize;
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} bmi_regs;
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/** Shadows of the device select bit */
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uint8_t dev[2];
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/** Registers used in device specific PCI configuration */
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union {
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uint8_t data[22];
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struct {
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uint16_t idetim0;
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uint16_t idetim1;
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uint8_t sidetim;
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uint8_t reserved_0[3];
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uint8_t udmactl;
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uint8_t reserved_1;
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uint16_t udmatim;
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uint8_t reserved_2[8];
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uint16_t ideconfig;
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};
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} config_regs;
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uint16_t primaryTiming, secondaryTiming;
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uint8_t deviceTiming;
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uint8_t udmaControl;
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uint16_t udmaTiming;
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uint16_t ideConfig;
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// Internal management variables
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bool io_enabled;
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bool bm_enabled;
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bool cmd_in_progress[4];
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bool ioEnabled;
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bool bmEnabled;
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private:
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/** IDE disks connected to controller */
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IdeDisk *disks[4];
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private:
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/** Parse the access address to pass on to device */
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void parseAddr(const Addr &addr, Addr &offset, IdeChannel &channel,
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IdeRegType ®_type);
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/** Select the disk based on the channel and device bit */
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int getDisk(IdeChannel channel);
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/** Select the disk based on a pointer */
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int getDisk(IdeDisk *diskPtr);
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public:
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/** See if a disk is selected based on its pointer */
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bool isDiskSelected(IdeDisk *diskPtr);
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void dispatchAccess(PacketPtr pkt, bool read);
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public:
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typedef IdeControllerParams Params;
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const Params *params() const { return (const Params *)_params; }
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IdeController(Params *p);
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~IdeController();
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virtual Tick writeConfig(PacketPtr pkt);
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virtual Tick readConfig(PacketPtr pkt);
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/** See if a disk is selected based on its pointer */
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bool isDiskSelected(IdeDisk *diskPtr);
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void intrPost();
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Tick writeConfig(PacketPtr pkt);
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Tick readConfig(PacketPtr pkt);
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void setDmaComplete(IdeDisk *disk);
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/**
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* Read a done field for a given target.
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* @param pkt Packet describing what is to be read
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* @return The amount of time to complete this request
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*/
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virtual Tick read(PacketPtr pkt);
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/**
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* Write a done field for a given target.
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* @param pkt Packet describing what is to be written
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* @return The amount of time to complete this request
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*/
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virtual Tick write(PacketPtr pkt);
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/**
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* Serialize this object to the given output stream.
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* @param os The stream to serialize to.
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*/
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virtual void serialize(std::ostream &os);
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/**
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* Reconstruct the state of this object from a checkpoint.
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* @param cp The checkpoint use.
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* @param section The section name of this object
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*/
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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Tick read(PacketPtr pkt);
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Tick write(PacketPtr pkt);
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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};
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#endif // __IDE_CTRL_HH_
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@ -177,7 +177,7 @@ Addr
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IdeDisk::pciToDma(Addr pciAddr)
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{
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if (ctrl)
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return ctrl->plat->pciToDma(pciAddr);
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return ctrl->pciToDma(pciAddr);
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else
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panic("Access to unset controller!\n");
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}
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@ -187,18 +187,23 @@ IdeDisk::pciToDma(Addr pciAddr)
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////
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void
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IdeDisk::read(const Addr &offset, IdeRegType reg_type, uint8_t *data)
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IdeDisk::readCommand(const Addr offset, int size, uint8_t *data)
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{
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DevAction_t action = ACT_NONE;
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switch (reg_type) {
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case COMMAND_BLOCK:
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switch (offset) {
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// Data transfers occur two bytes at a time
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case DATA_OFFSET:
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if (offset == DATA_OFFSET) {
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if (size == sizeof(uint16_t)) {
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*(uint16_t *)data = cmdReg.data;
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action = ACT_DATA_READ_SHORT;
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break;
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} else if (size == sizeof(uint32_t)) {
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*(uint16_t *)data = cmdReg.data;
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updateState(ACT_DATA_READ_SHORT);
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*((uint16_t *)data + 1) = cmdReg.data;
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} else {
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panic("Data read of unsupported size %d.\n", size);
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}
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updateState(ACT_DATA_READ_SHORT);
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return;
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}
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assert(size == sizeof(uint8_t));
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switch (offset) {
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case ERROR_OFFSET:
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*data = cmdReg.error;
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break;
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@ -219,40 +224,43 @@ IdeDisk::read(const Addr &offset, IdeRegType reg_type, uint8_t *data)
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break;
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case STATUS_OFFSET:
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*data = status;
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action = ACT_STAT_READ;
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updateState(ACT_STAT_READ);
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break;
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default:
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panic("Invalid IDE command register offset: %#x\n", offset);
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}
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break;
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case CONTROL_BLOCK:
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if (offset == ALTSTAT_OFFSET)
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*data = status;
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else
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panic("Invalid IDE control register offset: %#x\n", offset);
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break;
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default:
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panic("Unknown register block!\n");
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}
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DPRINTF(IdeDisk, "Read to disk at offset: %#x data %#x\n", offset,
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(uint32_t)*data);
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if (action != ACT_NONE)
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updateState(action);
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DPRINTF(IdeDisk, "Read to disk at offset: %#x data %#x\n", offset, *data);
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}
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void
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IdeDisk::write(const Addr &offset, IdeRegType reg_type, const uint8_t *data)
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IdeDisk::readControl(const Addr offset, int size, uint8_t *data)
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{
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DevAction_t action = ACT_NONE;
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assert(size == sizeof(uint8_t));
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*data = status;
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if (offset != ALTSTAT_OFFSET)
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panic("Invalid IDE control register offset: %#x\n", offset);
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DPRINTF(IdeDisk, "Read to disk at offset: %#x data %#x\n", offset, *data);
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}
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switch (reg_type) {
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case COMMAND_BLOCK:
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void
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IdeDisk::writeCommand(const Addr offset, int size, const uint8_t *data)
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{
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if (offset == DATA_OFFSET) {
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if (size == sizeof(uint16_t)) {
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cmdReg.data = *(const uint16_t *)data;
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} else if (size == sizeof(uint32_t)) {
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cmdReg.data = *(const uint16_t *)data;
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updateState(ACT_DATA_WRITE_SHORT);
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cmdReg.data = *((const uint16_t *)data + 1);
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} else {
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panic("Data write of unsupported size %d.\n", size);
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}
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updateState(ACT_DATA_WRITE_SHORT);
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return;
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}
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assert(size == sizeof(uint8_t));
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switch (offset) {
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case DATA_OFFSET:
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cmdReg.data = *(uint16_t*)data;
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action = ACT_DATA_WRITE_SHORT;
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break;
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case FEATURES_OFFSET:
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break;
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case NSECTOR_OFFSET:
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@ -269,38 +277,37 @@ IdeDisk::write(const Addr &offset, IdeRegType reg_type, const uint8_t *data)
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break;
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case DRIVE_OFFSET:
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cmdReg.drive = *data;
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action = ACT_SELECT_WRITE;
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updateState(ACT_SELECT_WRITE);
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break;
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case COMMAND_OFFSET:
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cmdReg.command = *data;
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action = ACT_CMD_WRITE;
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updateState(ACT_CMD_WRITE);
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break;
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default:
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panic("Invalid IDE command register offset: %#x\n", offset);
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}
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break;
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case CONTROL_BLOCK:
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if (offset == CONTROL_OFFSET) {
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DPRINTF(IdeDisk, "Write to disk at offset: %#x data %#x\n", offset,
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(uint32_t)*data);
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}
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void
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IdeDisk::writeControl(const Addr offset, int size, const uint8_t *data)
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{
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if (offset != CONTROL_OFFSET)
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panic("Invalid IDE control register offset: %#x\n", offset);
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if (*data & CONTROL_RST_BIT) {
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// force the device into the reset state
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devState = Device_Srst;
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action = ACT_SRST_SET;
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} else if (devState == Device_Srst && !(*data & CONTROL_RST_BIT))
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action = ACT_SRST_CLEAR;
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updateState(ACT_SRST_SET);
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} else if (devState == Device_Srst && !(*data & CONTROL_RST_BIT)) {
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updateState(ACT_SRST_CLEAR);
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}
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nIENBit = (*data & CONTROL_IEN_BIT) ? true : false;
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}
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else
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panic("Invalid IDE control register offset: %#x\n", offset);
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break;
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default:
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panic("Unknown register block!\n");
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}
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nIENBit = *data & CONTROL_IEN_BIT;
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DPRINTF(IdeDisk, "Write to disk at offset: %#x data %#x\n", offset,
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(uint32_t)*data);
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if (action != ACT_NONE)
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updateState(action);
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}
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////
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@ -683,7 +690,6 @@ IdeDisk::intrPost()
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// talk to controller to set interrupt
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if (ctrl) {
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ctrl->bmi_regs.bmis0 |= IDEINTS;
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ctrl->intrPost();
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}
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}
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@ -278,8 +278,10 @@ class IdeDisk : public SimObject
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}
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// Device register read/write
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void read(const Addr &offset, IdeRegType regtype, uint8_t *data);
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void write(const Addr &offset, IdeRegType regtype, const uint8_t *data);
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void readCommand(const Addr offset, int size, uint8_t *data);
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void readControl(const Addr offset, int size, uint8_t *data);
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void writeCommand(const Addr offset, int size, const uint8_t *data);
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void writeControl(const Addr offset, int size, const uint8_t *data);
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// Start/abort functions
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void startDma(const uint32_t &prdTableBase);
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