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Devices: Clean up the IDE controller.

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This commit is contained in:
Gabe Black 2008-12-07 12:59:48 -08:00
parent 993b7be4bb
commit 9192b7f1ef
4 changed files with 530 additions and 772 deletions
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853
src/dev/ide_ctrl.cc
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243
src/dev/ide_ctrl.hh
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@ -37,61 +37,13 @@
#ifndef __IDE_CTRL_HH__ #ifndef __IDE_CTRL_HH__
#define __IDE_CTRL_HH__ #define __IDE_CTRL_HH__
#include "base/bitunion.hh"
#include "dev/pcidev.hh" #include "dev/pcidev.hh"
#include "dev/pcireg.h" #include "dev/pcireg.h"
#include "dev/io_device.hh" #include "dev/io_device.hh"
#include "params/IdeController.hh" #include "params/IdeController.hh"
#define BMIC0 0x0 // Bus master IDE command register
#define BMIS0 0x2 // Bus master IDE status register
#define BMIDTP0 0x4 // Bus master IDE descriptor table pointer register
#define BMIC1 0x8 // Bus master IDE command register
#define BMIS1 0xa // Bus master IDE status register
#define BMIDTP1 0xc // Bus master IDE descriptor table pointer register
// Bus master IDE command register bit fields
#define RWCON 0x08 // Bus master read/write control
#define SSBM 0x01 // Start/stop bus master
// Bus master IDE status register bit fields
#define DMA1CAP 0x40 // Drive 1 DMA capable
#define DMA0CAP 0x20 // Drive 0 DMA capable
#define IDEINTS 0x04 // IDE Interrupt Status
#define IDEDMAE 0x02 // IDE DMA error
#define BMIDEA 0x01 // Bus master IDE active
// IDE Command byte fields
#define IDE_SELECT_OFFSET (6)
#define IDE_SELECT_DEV_BIT 0x10
#define IDE_FEATURE_OFFSET IDE_ERROR_OFFSET
#define IDE_COMMAND_OFFSET IDE_STATUS_OFFSET
// IDE Timing Register bit fields
#define IDETIM_DECODE_EN 0x8000
// PCI device specific register byte offsets
#define IDE_CTRL_CONF_START 0x40
#define IDE_CTRL_CONF_END ((IDE_CTRL_CONF_START) + sizeof(config_regs))
#define IDE_CTRL_CONF_PRIM_TIMING 0x40
#define IDE_CTRL_CONF_SEC_TIMING 0x42
#define IDE_CTRL_CONF_DEV_TIMING 0x44
#define IDE_CTRL_CONF_UDMA_CNTRL 0x48
#define IDE_CTRL_CONF_UDMA_TIMING 0x4A
#define IDE_CTRL_CONF_IDE_CONFIG 0x54
enum IdeRegType {
COMMAND_BLOCK,
CONTROL_BLOCK,
BMI_BLOCK
};
class IdeDisk; class IdeDisk;
class IntrControl;
class PciConfigAll;
class Platform;
/** /**
* Device model for an Intel PIIX4 IDE controller * Device model for an Intel PIIX4 IDE controller
@ -99,137 +51,106 @@ class Platform;
class IdeController : public PciDev class IdeController : public PciDev
{ {
friend class IdeDisk;
enum IdeChannel {
PRIMARY = 0,
SECONDARY = 1
};
private: private:
/** Primary command block registers */ // Bus master IDE status register bit fields
Addr pri_cmd_addr; BitUnion8(BMIStatusReg)
Addr pri_cmd_size; Bitfield<6> dmaCap0;
/** Primary control block registers */ Bitfield<5> dmaCap1;
Addr pri_ctrl_addr; Bitfield<2> intStatus;
Addr pri_ctrl_size; Bitfield<1> dmaError;
/** Secondary command block registers */ Bitfield<0> active;
Addr sec_cmd_addr; EndBitUnion(BMIStatusReg)
Addr sec_cmd_size;
/** Secondary control block registers */
Addr sec_ctrl_addr;
Addr sec_ctrl_size;
/** Bus master interface (BMI) registers */
Addr bmi_addr;
Addr bmi_size;
private: BitUnion8(BMICommandReg)
/** Registers used for bus master interface */ Bitfield<3> rw;
union { Bitfield<0> startStop;
uint8_t data[16]; EndBitUnion(BMICommandReg)
struct { struct Channel
uint8_t bmic0; {
uint8_t reserved_0; std::string _name;
uint8_t bmis0;
uint8_t reserved_1;
uint32_t bmidtp0;
uint8_t bmic1;
uint8_t reserved_2;
uint8_t bmis1;
uint8_t reserved_3;
uint32_t bmidtp1;
};
struct { const std::string
uint8_t bmic; name()
uint8_t reserved_4; {
uint8_t bmis; return _name;
uint8_t reserved_5; }
/** Command and control block registers */
Addr cmdAddr, cmdSize, ctrlAddr, ctrlSize;
/** Registers used for bus master interface */
struct BMIRegs
{
BMICommandReg command;
uint8_t reserved0;
BMIStatusReg status;
uint8_t reserved1;
uint32_t bmidtp; uint32_t bmidtp;
} chan[2]; } bmiRegs;
/** IDE disks connected to this controller */
IdeDisk *master, *slave;
/** Currently selected disk */
IdeDisk *selected;
bool selectBit;
void
select(bool selSlave)
{
selectBit = selSlave;
selected = selectBit ? slave : master;
}
void accessCommand(Addr offset, int size, uint8_t *data, bool read);
void accessControl(Addr offset, int size, uint8_t *data, bool read);
void accessBMI(Addr offset, int size, uint8_t *data, bool read);
Channel(std::string newName, Addr _cmdSize, Addr _ctrlSize);
~Channel();
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
} primary, secondary;
/** Bus master interface (BMI) registers */
Addr bmiAddr, bmiSize;
} bmi_regs;
/** Shadows of the device select bit */
uint8_t dev[2];
/** Registers used in device specific PCI configuration */ /** Registers used in device specific PCI configuration */
union { uint16_t primaryTiming, secondaryTiming;
uint8_t data[22]; uint8_t deviceTiming;
uint8_t udmaControl;
struct { uint16_t udmaTiming;
uint16_t idetim0; uint16_t ideConfig;
uint16_t idetim1;
uint8_t sidetim;
uint8_t reserved_0[3];
uint8_t udmactl;
uint8_t reserved_1;
uint16_t udmatim;
uint8_t reserved_2[8];
uint16_t ideconfig;
};
} config_regs;
// Internal management variables // Internal management variables
bool io_enabled; bool ioEnabled;
bool bm_enabled; bool bmEnabled;
bool cmd_in_progress[4];
private: void dispatchAccess(PacketPtr pkt, bool read);
/** IDE disks connected to controller */
IdeDisk *disks[4];
private:
/** Parse the access address to pass on to device */
void parseAddr(const Addr &addr, Addr &offset, IdeChannel &channel,
IdeRegType &reg_type);
/** Select the disk based on the channel and device bit */
int getDisk(IdeChannel channel);
/** Select the disk based on a pointer */
int getDisk(IdeDisk *diskPtr);
public:
/** See if a disk is selected based on its pointer */
bool isDiskSelected(IdeDisk *diskPtr);
public: public:
typedef IdeControllerParams Params; typedef IdeControllerParams Params;
const Params *params() const { return (const Params *)_params; } const Params *params() const { return (const Params *)_params; }
IdeController(Params *p); IdeController(Params *p);
~IdeController();
virtual Tick writeConfig(PacketPtr pkt); /** See if a disk is selected based on its pointer */
virtual Tick readConfig(PacketPtr pkt); bool isDiskSelected(IdeDisk *diskPtr);
void intrPost();
Tick writeConfig(PacketPtr pkt);
Tick readConfig(PacketPtr pkt);
void setDmaComplete(IdeDisk *disk); void setDmaComplete(IdeDisk *disk);
/** Tick read(PacketPtr pkt);
* Read a done field for a given target. Tick write(PacketPtr pkt);
* @param pkt Packet describing what is to be read
* @return The amount of time to complete this request
*/
virtual Tick read(PacketPtr pkt);
/**
* Write a done field for a given target.
* @param pkt Packet describing what is to be written
* @return The amount of time to complete this request
*/
virtual Tick write(PacketPtr pkt);
/**
* Serialize this object to the given output stream.
* @param os The stream to serialize to.
*/
virtual void serialize(std::ostream &os);
/**
* Reconstruct the state of this object from a checkpoint.
* @param cp The checkpoint use.
* @param section The section name of this object
*/
virtual void unserialize(Checkpoint *cp, const std::string &section);
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
}; };
#endif // __IDE_CTRL_HH_ #endif // __IDE_CTRL_HH_

200
src/dev/ide_disk.cc
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@ -177,7 +177,7 @@ Addr
IdeDisk::pciToDma(Addr pciAddr) IdeDisk::pciToDma(Addr pciAddr)
{ {
if (ctrl) if (ctrl)
return ctrl->plat->pciToDma(pciAddr); return ctrl->pciToDma(pciAddr);
else else
panic("Access to unset controller!\n"); panic("Access to unset controller!\n");
} }
@ -187,120 +187,127 @@ IdeDisk::pciToDma(Addr pciAddr)
//// ////
void void
IdeDisk::read(const Addr &offset, IdeRegType reg_type, uint8_t *data) IdeDisk::readCommand(const Addr offset, int size, uint8_t *data)
{ {
DevAction_t action = ACT_NONE; if (offset == DATA_OFFSET) {
if (size == sizeof(uint16_t)) {
switch (reg_type) { *(uint16_t *)data = cmdReg.data;
case COMMAND_BLOCK: } else if (size == sizeof(uint32_t)) {
switch (offset) { *(uint16_t *)data = cmdReg.data;
// Data transfers occur two bytes at a time updateState(ACT_DATA_READ_SHORT);
case DATA_OFFSET: *((uint16_t *)data + 1) = cmdReg.data;
*(uint16_t*)data = cmdReg.data; } else {
action = ACT_DATA_READ_SHORT; panic("Data read of unsupported size %d.\n", size);
break;
case ERROR_OFFSET:
*data = cmdReg.error;
break;
case NSECTOR_OFFSET:
*data = cmdReg.sec_count;
break;
case SECTOR_OFFSET:
*data = cmdReg.sec_num;
break;
case LCYL_OFFSET:
*data = cmdReg.cyl_low;
break;
case HCYL_OFFSET:
*data = cmdReg.cyl_high;
break;
case DRIVE_OFFSET:
*data = cmdReg.drive;
break;
case STATUS_OFFSET:
*data = status;
action = ACT_STAT_READ;
break;
default:
panic("Invalid IDE command register offset: %#x\n", offset);
} }
updateState(ACT_DATA_READ_SHORT);
return;
}
assert(size == sizeof(uint8_t));
switch (offset) {
case ERROR_OFFSET:
*data = cmdReg.error;
break; break;
case CONTROL_BLOCK: case NSECTOR_OFFSET:
if (offset == ALTSTAT_OFFSET) *data = cmdReg.sec_count;
*data = status; break;
else case SECTOR_OFFSET:
panic("Invalid IDE control register offset: %#x\n", offset); *data = cmdReg.sec_num;
break;
case LCYL_OFFSET:
*data = cmdReg.cyl_low;
break;
case HCYL_OFFSET:
*data = cmdReg.cyl_high;
break;
case DRIVE_OFFSET:
*data = cmdReg.drive;
break;
case STATUS_OFFSET:
*data = status;
updateState(ACT_STAT_READ);
break; break;
default: default:
panic("Unknown register block!\n"); panic("Invalid IDE command register offset: %#x\n", offset);
} }
DPRINTF(IdeDisk, "Read to disk at offset: %#x data %#x\n", offset, DPRINTF(IdeDisk, "Read to disk at offset: %#x data %#x\n", offset, *data);
(uint32_t)*data);
if (action != ACT_NONE)
updateState(action);
} }
void void
IdeDisk::write(const Addr &offset, IdeRegType reg_type, const uint8_t *data) IdeDisk::readControl(const Addr offset, int size, uint8_t *data)
{ {
DevAction_t action = ACT_NONE; assert(size == sizeof(uint8_t));
*data = status;
if (offset != ALTSTAT_OFFSET)
panic("Invalid IDE control register offset: %#x\n", offset);
DPRINTF(IdeDisk, "Read to disk at offset: %#x data %#x\n", offset, *data);
}
switch (reg_type) { void
case COMMAND_BLOCK: IdeDisk::writeCommand(const Addr offset, int size, const uint8_t *data)
switch (offset) { {
case DATA_OFFSET: if (offset == DATA_OFFSET) {
cmdReg.data = *(uint16_t*)data; if (size == sizeof(uint16_t)) {
action = ACT_DATA_WRITE_SHORT; cmdReg.data = *(const uint16_t *)data;
break; } else if (size == sizeof(uint32_t)) {
case FEATURES_OFFSET: cmdReg.data = *(const uint16_t *)data;
break; updateState(ACT_DATA_WRITE_SHORT);
case NSECTOR_OFFSET: cmdReg.data = *((const uint16_t *)data + 1);
cmdReg.sec_count = *data; } else {
break; panic("Data write of unsupported size %d.\n", size);
case SECTOR_OFFSET:
cmdReg.sec_num = *data;
break;
case LCYL_OFFSET:
cmdReg.cyl_low = *data;
break;
case HCYL_OFFSET:
cmdReg.cyl_high = *data;
break;
case DRIVE_OFFSET:
cmdReg.drive = *data;
action = ACT_SELECT_WRITE;
break;
case COMMAND_OFFSET:
cmdReg.command = *data;
action = ACT_CMD_WRITE;
break;
default:
panic("Invalid IDE command register offset: %#x\n", offset);
} }
updateState(ACT_DATA_WRITE_SHORT);
return;
}
assert(size == sizeof(uint8_t));
switch (offset) {
case FEATURES_OFFSET:
break; break;
case CONTROL_BLOCK: case NSECTOR_OFFSET:
if (offset == CONTROL_OFFSET) { cmdReg.sec_count = *data;
if (*data & CONTROL_RST_BIT) { break;
// force the device into the reset state case SECTOR_OFFSET:
devState = Device_Srst; cmdReg.sec_num = *data;
action = ACT_SRST_SET; break;
} else if (devState == Device_Srst && !(*data & CONTROL_RST_BIT)) case LCYL_OFFSET:
action = ACT_SRST_CLEAR; cmdReg.cyl_low = *data;
break;
nIENBit = (*data & CONTROL_IEN_BIT) ? true : false; case HCYL_OFFSET:
} cmdReg.cyl_high = *data;
else break;
panic("Invalid IDE control register offset: %#x\n", offset); case DRIVE_OFFSET:
cmdReg.drive = *data;
updateState(ACT_SELECT_WRITE);
break;
case COMMAND_OFFSET:
cmdReg.command = *data;
updateState(ACT_CMD_WRITE);
break; break;
default: default:
panic("Unknown register block!\n"); panic("Invalid IDE command register offset: %#x\n", offset);
} }
DPRINTF(IdeDisk, "Write to disk at offset: %#x data %#x\n", offset,
(uint32_t)*data);
}
void
IdeDisk::writeControl(const Addr offset, int size, const uint8_t *data)
{
if (offset != CONTROL_OFFSET)
panic("Invalid IDE control register offset: %#x\n", offset);
if (*data & CONTROL_RST_BIT) {
// force the device into the reset state
devState = Device_Srst;
updateState(ACT_SRST_SET);
} else if (devState == Device_Srst && !(*data & CONTROL_RST_BIT)) {
updateState(ACT_SRST_CLEAR);
}
nIENBit = *data & CONTROL_IEN_BIT;
DPRINTF(IdeDisk, "Write to disk at offset: %#x data %#x\n", offset, DPRINTF(IdeDisk, "Write to disk at offset: %#x data %#x\n", offset,
(uint32_t)*data); (uint32_t)*data);
if (action != ACT_NONE)
updateState(action);
} }
//// ////
@ -683,7 +690,6 @@ IdeDisk::intrPost()
// talk to controller to set interrupt // talk to controller to set interrupt
if (ctrl) { if (ctrl) {
ctrl->bmi_regs.bmis0 |= IDEINTS;
ctrl->intrPost(); ctrl->intrPost();
} }
} }

6
src/dev/ide_disk.hh
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@ -278,8 +278,10 @@ class IdeDisk : public SimObject
} }
// Device register read/write // Device register read/write
void read(const Addr &offset, IdeRegType regtype, uint8_t *data); void readCommand(const Addr offset, int size, uint8_t *data);
void write(const Addr &offset, IdeRegType regtype, const uint8_t *data); void readControl(const Addr offset, int size, uint8_t *data);
void writeCommand(const Addr offset, int size, const uint8_t *data);
void writeControl(const Addr offset, int size, const uint8_t *data);
// Start/abort functions // Start/abort functions
void startDma(const uint32_t &prdTableBase); void startDma(const uint32_t &prdTableBase);