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x86: Add checkpointing capability to arch components

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Add checkpointing capability to the x86 interrupt device and the TLBs
This commit is contained in:
Joel Hestness 2011-02-06 22:14:17 -08:00
parent 38140b5519
commit 911ccef6c0
3 changed files with 79 additions and 11 deletions
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59
src/arch/x86/interrupts.cc
View file

@ -706,6 +706,65 @@ X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc)
} }
} }
void
X86ISA::Interrupts::serialize(std::ostream &os)
{
SERIALIZE_ARRAY(regs, NUM_APIC_REGS);
SERIALIZE_SCALAR(clock);
SERIALIZE_SCALAR(pendingSmi);
SERIALIZE_SCALAR(smiVector);
SERIALIZE_SCALAR(pendingNmi);
SERIALIZE_SCALAR(nmiVector);
SERIALIZE_SCALAR(pendingExtInt);
SERIALIZE_SCALAR(extIntVector);
SERIALIZE_SCALAR(pendingInit);
SERIALIZE_SCALAR(initVector);
SERIALIZE_SCALAR(pendingStartup);
SERIALIZE_SCALAR(startupVector);
SERIALIZE_SCALAR(startedUp);
SERIALIZE_SCALAR(pendingUnmaskableInt);
SERIALIZE_SCALAR(pendingIPIs);
SERIALIZE_SCALAR(IRRV);
SERIALIZE_SCALAR(ISRV);
bool apicTimerEventScheduled = apicTimerEvent.scheduled();
SERIALIZE_SCALAR(apicTimerEventScheduled);
Tick apicTimerEventTick = apicTimerEvent.when();
SERIALIZE_SCALAR(apicTimerEventTick);
}
void
X86ISA::Interrupts::unserialize(Checkpoint *cp, const std::string &section)
{
UNSERIALIZE_ARRAY(regs, NUM_APIC_REGS);
UNSERIALIZE_SCALAR(clock);
UNSERIALIZE_SCALAR(pendingSmi);
UNSERIALIZE_SCALAR(smiVector);
UNSERIALIZE_SCALAR(pendingNmi);
UNSERIALIZE_SCALAR(nmiVector);
UNSERIALIZE_SCALAR(pendingExtInt);
UNSERIALIZE_SCALAR(extIntVector);
UNSERIALIZE_SCALAR(pendingInit);
UNSERIALIZE_SCALAR(initVector);
UNSERIALIZE_SCALAR(pendingStartup);
UNSERIALIZE_SCALAR(startupVector);
UNSERIALIZE_SCALAR(startedUp);
UNSERIALIZE_SCALAR(pendingUnmaskableInt);
UNSERIALIZE_SCALAR(pendingIPIs);
UNSERIALIZE_SCALAR(IRRV);
UNSERIALIZE_SCALAR(ISRV);
bool apicTimerEventScheduled;
UNSERIALIZE_SCALAR(apicTimerEventScheduled);
if (apicTimerEventScheduled) {
Tick apicTimerEventTick;
UNSERIALIZE_SCALAR(apicTimerEventTick);
if (apicTimerEvent.scheduled()) {
reschedule(apicTimerEvent, apicTimerEventTick, true);
} else {
schedule(apicTimerEvent, apicTimerEventTick);
}
}
}
X86ISA::Interrupts * X86ISA::Interrupts *
X86LocalApicParams::create() X86LocalApicParams::create()
{ {

13
src/arch/x86/interrupts.hh
View file

@ -257,17 +257,8 @@ class Interrupts : public BasicPioDevice, IntDev
* Serialization. * Serialization.
*/ */
void virtual void serialize(std::ostream &os);
serialize(std::ostream &os) virtual void unserialize(Checkpoint *cp, const std::string &section);
{
warn("Interrupts::serialize unimplemented!\n");
}
void
unserialize(Checkpoint *cp, const std::string &section)
{
warn("Interrupts::unserialize unimplemented!\n");
}
/* /*
* Old functions needed for compatability but which will be phased out * Old functions needed for compatability but which will be phased out

18
src/arch/x86/pagetable.cc
View file

@ -52,11 +52,29 @@ TlbEntry::TlbEntry(Addr asn, Addr _vaddr, Addr _paddr) :
void void
TlbEntry::serialize(std::ostream &os) TlbEntry::serialize(std::ostream &os)
{ {
SERIALIZE_SCALAR(paddr);
SERIALIZE_SCALAR(vaddr);
SERIALIZE_SCALAR(size);
SERIALIZE_SCALAR(writable);
SERIALIZE_SCALAR(user);
SERIALIZE_SCALAR(uncacheable);
SERIALIZE_SCALAR(global);
SERIALIZE_SCALAR(patBit);
SERIALIZE_SCALAR(noExec);
} }
void void
TlbEntry::unserialize(Checkpoint *cp, const std::string &section) TlbEntry::unserialize(Checkpoint *cp, const std::string &section)
{ {
UNSERIALIZE_SCALAR(paddr);
UNSERIALIZE_SCALAR(vaddr);
UNSERIALIZE_SCALAR(size);
UNSERIALIZE_SCALAR(writable);
UNSERIALIZE_SCALAR(user);
UNSERIALIZE_SCALAR(uncacheable);
UNSERIALIZE_SCALAR(global);
UNSERIALIZE_SCALAR(patBit);
UNSERIALIZE_SCALAR(noExec);
} }
} }