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se.py Ruby: Connect TLB walker ports

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In order to ensure correct functionality of switch CPUs, the TLB walker ports
must be connected to the Ruby system in x86 simulation.

This fixes x86 assertion failures that the TLB walker ports are not connected
during the CPU switch process.
This commit is contained in:
Joel Hestness 2012-09-12 21:42:57 -05:00
parent 234fa4cf7e
commit 90dd745ff6
1 changed files with 3 additions and 0 deletions
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3
configs/example/se.py
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@ -198,6 +198,9 @@ if options.ruby:
# Connect the cpu's cache ports to Ruby # Connect the cpu's cache ports to Ruby
system.cpu[i].icache_port = ruby_port.slave system.cpu[i].icache_port = ruby_port.slave
system.cpu[i].dcache_port = ruby_port.slave system.cpu[i].dcache_port = ruby_port.slave
if buildEnv['TARGET_ISA'] == 'x86':
system.cpu[i].itb.walker.port = ruby_port.slave
system.cpu[i].dtb.walker.port = ruby_port.slave
else: else:
system.system_port = system.membus.slave system.system_port = system.membus.slave
system.physmem.port = system.membus.master system.physmem.port = system.membus.master