ARM: Implement the VFP version of vdiv and vsqrt.
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cc665240a4
commit
90d70a22cb
2 changed files with 89 additions and 2 deletions
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@ -552,7 +552,25 @@ let {{
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}
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case 0x8:
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if ((opc3 & 0x1) == 0) {
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return new WarnUnimplemented("vdiv", machInst);
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uint32_t vd;
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uint32_t vm;
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uint32_t vn;
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if (bits(machInst, 8) == 0) {
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vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
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vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
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vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
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return new VdivS(machInst, (IntRegIndex)vd,
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(IntRegIndex)vn, (IntRegIndex)vm);
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} else {
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vd = (bits(machInst, 22) << 5) |
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(bits(machInst, 15, 12) << 1);
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vm = (bits(machInst, 5) << 5) |
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(bits(machInst, 3, 0) << 1);
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vn = (bits(machInst, 7) << 5) |
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(bits(machInst, 19, 16) << 1);
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return new VdivD(machInst, (IntRegIndex)vd,
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(IntRegIndex)vn, (IntRegIndex)vm);
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}
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}
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break;
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case 0xb:
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@ -624,7 +642,21 @@ let {{
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(IntRegIndex)vd, (IntRegIndex)vm);
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}
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} else {
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return new WarnUnimplemented("vsqrt", machInst);
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uint32_t vd;
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uint32_t vm;
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if (bits(machInst, 8) == 0) {
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vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
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vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
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return new VsqrtS(machInst,
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(IntRegIndex)vd, (IntRegIndex)vm);
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} else {
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vd = (bits(machInst, 22) << 5) |
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(bits(machInst, 15, 12) << 1);
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vm = (bits(machInst, 5) << 5) |
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(bits(machInst, 3, 0) << 1);
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return new VsqrtD(machInst,
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(IntRegIndex)vd, (IntRegIndex)vm);
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}
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}
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case 0x2:
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case 0x3:
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@ -356,4 +356,59 @@ let {{
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header_output += RegRegRegOpDeclare.subst(vsubDIop);
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decoder_output += RegRegRegOpConstructor.subst(vsubDIop);
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exec_output += PredOpExecute.subst(vsubDIop);
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vdivSCode = '''
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FpDest = FpOp1 / FpOp2;
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'''
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vdivSIop = InstObjParams("vdivs", "VdivS", "RegRegRegOp",
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{ "code": vdivSCode,
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"predicate_test": predicateTest }, [])
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header_output += RegRegRegOpDeclare.subst(vdivSIop);
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decoder_output += RegRegRegOpConstructor.subst(vdivSIop);
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exec_output += PredOpExecute.subst(vdivSIop);
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vdivDCode = '''
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IntDoubleUnion cOp1, cOp2, cDest;
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cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
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cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
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cDest.fp = cOp1.fp / cOp2.fp;
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FpDestP0.uw = cDest.bits;
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FpDestP1.uw = cDest.bits >> 32;
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'''
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vdivDIop = InstObjParams("vdivd", "VdivD", "RegRegRegOp",
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{ "code": vdivDCode,
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"predicate_test": predicateTest }, [])
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header_output += RegRegRegOpDeclare.subst(vdivDIop);
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decoder_output += RegRegRegOpConstructor.subst(vdivDIop);
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exec_output += PredOpExecute.subst(vdivDIop);
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vsqrtSCode = '''
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FpDest = sqrtf(FpOp1);
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if (FpOp1 < 0) {
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FpDest = NAN;
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}
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'''
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vsqrtSIop = InstObjParams("vsqrts", "VsqrtS", "RegRegOp",
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{ "code": vsqrtSCode,
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"predicate_test": predicateTest }, [])
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header_output += RegRegOpDeclare.subst(vsqrtSIop);
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decoder_output += RegRegOpConstructor.subst(vsqrtSIop);
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exec_output += PredOpExecute.subst(vsqrtSIop);
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vsqrtDCode = '''
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IntDoubleUnion cOp1, cDest;
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cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
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cDest.fp = sqrt(cOp1.fp);
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if (cOp1.fp < 0) {
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cDest.fp = NAN;
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}
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FpDestP0.uw = cDest.bits;
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FpDestP1.uw = cDest.bits >> 32;
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'''
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vsqrtDIop = InstObjParams("vsqrtd", "VsqrtD", "RegRegOp",
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{ "code": vsqrtDCode,
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"predicate_test": predicateTest }, [])
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header_output += RegRegOpDeclare.subst(vsqrtDIop);
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decoder_output += RegRegOpConstructor.subst(vsqrtDIop);
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exec_output += PredOpExecute.subst(vsqrtDIop);
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}};
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