ruby: included ruby config parameter ports per core
Slightly improved the major hack need to correctly assign the number of ports per core. CPUs have two ports: icache + dcache. MemTester has one port.
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5 changed files with 16 additions and 8 deletions
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@ -86,8 +86,11 @@ cpus = [ MemTest(atomic=options.atomic, max_loads=options.maxloads, \
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for i in xrange(options.testers) ]
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for i in xrange(options.testers) ]
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# create the desired simulated system
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# create the desired simulated system
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# ruby memory
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# ruby memory must be at least 16 MB to work with the mem tester
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ruby_memory = ruby_config.generate("MI_example-homogeneous.rb", options.testers)
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ruby_memory = ruby_config.generate("MI_example-homogeneous.rb",
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cores = options.testers,
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memory_size = 16,
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ports_per_cpu = 1)
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system = System(cpu = cpus, funcmem = PhysicalMemory(),
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system = System(cpu = cpus, funcmem = PhysicalMemory(),
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physmem = ruby_memory)
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physmem = ruby_memory)
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@ -45,3 +45,4 @@ class RubyMemory(PhysicalMemory):
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num_dmas = Param.Int(0, "Number of DMA ports connected to the Ruby memory")
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num_dmas = Param.Int(0, "Number of DMA ports connected to the Ruby memory")
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dma_port = VectorPort("Ruby_dma_ports")
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dma_port = VectorPort("Ruby_dma_ports")
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pio_port = Port("Ruby_pio_port")
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pio_port = Port("Ruby_pio_port")
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ports_per_core = Param.Int(2, "Number of per core. Typical two: icache + dcache")
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@ -58,6 +58,8 @@ RubyMemory::RubyMemory(const Params *p)
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ruby_clock = p->clock;
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ruby_clock = p->clock;
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ruby_phase = p->phase;
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ruby_phase = p->phase;
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ports_per_cpu = p->ports_per_core;
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DPRINTF(Ruby, "creating Ruby Memory from file %s\n",
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DPRINTF(Ruby, "creating Ruby Memory from file %s\n",
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p->config_file.c_str());
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p->config_file.c_str());
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@ -230,14 +232,14 @@ RubyMemory::getPort(const std::string &if_name, int idx)
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//
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//
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// Currently this code assumes that each cpu has both a
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// Currently this code assumes that each cpu has both a
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// icache and dcache port and therefore divides by two. This will be
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// icache and dcache port and therefore divides by ports per cpu. This will
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// fixed once we unify the configuration systems and Ruby sequencers
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// be fixed once we unify the configuration systems and Ruby sequencers
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// directly support M5 ports.
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// directly support M5 ports.
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//
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//
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assert(idx/2 < ruby_ports.size());
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assert(idx/ports_per_cpu < ruby_ports.size());
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Port *port = new Port(csprintf("%s-port%d", name(), idx),
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Port *port = new Port(csprintf("%s-port%d", name(), idx),
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this,
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this,
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ruby_ports[idx/2]);
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ruby_ports[idx/ports_per_cpu]);
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ports[idx] = port;
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ports[idx] = port;
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return port;
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return port;
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@ -130,6 +130,7 @@ class RubyMemory : public PhysicalMemory
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Tick ruby_clock;
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Tick ruby_clock;
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Tick ruby_phase;
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Tick ruby_phase;
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RubyExitCallback* rubyExitCB;
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RubyExitCallback* rubyExitCB;
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int ports_per_cpu;
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public:
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public:
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static std::map<int64_t, PacketPtr> pending_requests;
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static std::map<int64_t, PacketPtr> pending_requests;
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@ -8,7 +8,7 @@ from m5.params import *
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def generate(config_file, cores=1, memories=1, memory_size=1024, \
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def generate(config_file, cores=1, memories=1, memory_size=1024, \
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cache_size=32768, cache_assoc=8, dmas=1,
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cache_size=32768, cache_assoc=8, dmas=1,
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ruby_tick='1t'):
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ruby_tick='1t', ports_per_cpu=2):
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default = joinpath(dirname(__file__), '../../src/mem/ruby/config')
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default = joinpath(dirname(__file__), '../../src/mem/ruby/config')
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ruby_config = os.environ.get('RUBY_CONFIG', default)
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ruby_config = os.environ.get('RUBY_CONFIG', default)
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args = [ "ruby", "-I", ruby_config, joinpath(ruby_config, "print_cfg.rb"),
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args = [ "ruby", "-I", ruby_config, joinpath(ruby_config, "print_cfg.rb"),
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@ -25,4 +25,5 @@ def generate(config_file, cores=1, memories=1, memory_size=1024, \
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config_file = temp_config,
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config_file = temp_config,
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num_cpus = cores,
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num_cpus = cores,
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range = AddrRange(str(memory_size)+"MB"),
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range = AddrRange(str(memory_size)+"MB"),
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num_dmas = dmas)
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num_dmas = dmas,
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ports_per_core = ports_per_cpu)
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