ruby: included ruby config parameter ports per core

Slightly improved the major hack need to correctly assign the number of ports
per core.  CPUs have two ports: icache + dcache.  MemTester has one port.
This commit is contained in:
Brad Beckmann 2009-11-18 13:55:58 -08:00
parent dce53610c3
commit 90d6e2652f
5 changed files with 16 additions and 8 deletions

View file

@ -86,8 +86,11 @@ cpus = [ MemTest(atomic=options.atomic, max_loads=options.maxloads, \
for i in xrange(options.testers) ] for i in xrange(options.testers) ]
# create the desired simulated system # create the desired simulated system
# ruby memory # ruby memory must be at least 16 MB to work with the mem tester
ruby_memory = ruby_config.generate("MI_example-homogeneous.rb", options.testers) ruby_memory = ruby_config.generate("MI_example-homogeneous.rb",
cores = options.testers,
memory_size = 16,
ports_per_cpu = 1)
system = System(cpu = cpus, funcmem = PhysicalMemory(), system = System(cpu = cpus, funcmem = PhysicalMemory(),
physmem = ruby_memory) physmem = ruby_memory)

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@ -45,3 +45,4 @@ class RubyMemory(PhysicalMemory):
num_dmas = Param.Int(0, "Number of DMA ports connected to the Ruby memory") num_dmas = Param.Int(0, "Number of DMA ports connected to the Ruby memory")
dma_port = VectorPort("Ruby_dma_ports") dma_port = VectorPort("Ruby_dma_ports")
pio_port = Port("Ruby_pio_port") pio_port = Port("Ruby_pio_port")
ports_per_core = Param.Int(2, "Number of per core. Typical two: icache + dcache")

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@ -58,6 +58,8 @@ RubyMemory::RubyMemory(const Params *p)
ruby_clock = p->clock; ruby_clock = p->clock;
ruby_phase = p->phase; ruby_phase = p->phase;
ports_per_cpu = p->ports_per_core;
DPRINTF(Ruby, "creating Ruby Memory from file %s\n", DPRINTF(Ruby, "creating Ruby Memory from file %s\n",
p->config_file.c_str()); p->config_file.c_str());
@ -230,14 +232,14 @@ RubyMemory::getPort(const std::string &if_name, int idx)
// //
// Currently this code assumes that each cpu has both a // Currently this code assumes that each cpu has both a
// icache and dcache port and therefore divides by two. This will be // icache and dcache port and therefore divides by ports per cpu. This will
// fixed once we unify the configuration systems and Ruby sequencers // be fixed once we unify the configuration systems and Ruby sequencers
// directly support M5 ports. // directly support M5 ports.
// //
assert(idx/2 < ruby_ports.size()); assert(idx/ports_per_cpu < ruby_ports.size());
Port *port = new Port(csprintf("%s-port%d", name(), idx), Port *port = new Port(csprintf("%s-port%d", name(), idx),
this, this,
ruby_ports[idx/2]); ruby_ports[idx/ports_per_cpu]);
ports[idx] = port; ports[idx] = port;
return port; return port;

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@ -130,6 +130,7 @@ class RubyMemory : public PhysicalMemory
Tick ruby_clock; Tick ruby_clock;
Tick ruby_phase; Tick ruby_phase;
RubyExitCallback* rubyExitCB; RubyExitCallback* rubyExitCB;
int ports_per_cpu;
public: public:
static std::map<int64_t, PacketPtr> pending_requests; static std::map<int64_t, PacketPtr> pending_requests;

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@ -8,7 +8,7 @@ from m5.params import *
def generate(config_file, cores=1, memories=1, memory_size=1024, \ def generate(config_file, cores=1, memories=1, memory_size=1024, \
cache_size=32768, cache_assoc=8, dmas=1, cache_size=32768, cache_assoc=8, dmas=1,
ruby_tick='1t'): ruby_tick='1t', ports_per_cpu=2):
default = joinpath(dirname(__file__), '../../src/mem/ruby/config') default = joinpath(dirname(__file__), '../../src/mem/ruby/config')
ruby_config = os.environ.get('RUBY_CONFIG', default) ruby_config = os.environ.get('RUBY_CONFIG', default)
args = [ "ruby", "-I", ruby_config, joinpath(ruby_config, "print_cfg.rb"), args = [ "ruby", "-I", ruby_config, joinpath(ruby_config, "print_cfg.rb"),
@ -25,4 +25,5 @@ def generate(config_file, cores=1, memories=1, memory_size=1024, \
config_file = temp_config, config_file = temp_config,
num_cpus = cores, num_cpus = cores,
range = AddrRange(str(memory_size)+"MB"), range = AddrRange(str(memory_size)+"MB"),
num_dmas = dmas) num_dmas = dmas,
ports_per_core = ports_per_cpu)