diff --git a/base/traceflags.py b/base/traceflags.py index a1fb45177..eb404fa54 100644 --- a/base/traceflags.py +++ b/base/traceflags.py @@ -136,7 +136,8 @@ baseFlags = [ 'StoreSet', 'MemDepUnit', 'DynInst', - 'FullCPU' + 'FullCPU', + 'CommitRate' ] # diff --git a/build/SConstruct b/build/SConstruct index 381b6ecda..22f39b72c 100644 --- a/build/SConstruct +++ b/build/SConstruct @@ -114,11 +114,16 @@ def MySqlOpt(env): def NoFastAllocOpt(env): env.Append(CPPDEFINES = 'NO_FAST_ALLOC') +# Enable efence +def EfenceOpt(env): + env.Append(LIBS=['efence']) + # Configuration options map. options_map = { 'MEASURE' : MeasureOpt, 'MYSQL' : MySqlOpt, - 'NO_FAST_ALLOC' : NoFastAllocOpt + 'NO_FAST_ALLOC' : NoFastAllocOpt, + 'EFENCE' : EfenceOpt } # The 'local_configs' file can be used to define additional base diff --git a/cpu/beta_cpu/alpha_full_cpu_impl.hh b/cpu/beta_cpu/alpha_full_cpu_impl.hh index ee8f9f33b..611a0d80d 100644 --- a/cpu/beta_cpu/alpha_full_cpu_impl.hh +++ b/cpu/beta_cpu/alpha_full_cpu_impl.hh @@ -127,7 +127,7 @@ AlphaFullCPU::copyToXC() for (int i = 0; i < AlphaISA::NumIntRegs; ++i) { renamed_reg = renameMap.lookup(i); - xc->regs.intRegFile[i] = regFile.intRegFile[renamed_reg]; + xc->regs.intRegFile[i] = regFile.readIntReg(renamed_reg); DPRINTF(FullCPU, "FullCPU: Copying register %i, has data %lli.\n", renamed_reg, regFile.intRegFile[renamed_reg]); } @@ -136,8 +136,8 @@ AlphaFullCPU::copyToXC() for (int i = 0; i < AlphaISA::NumFloatRegs; ++i) { renamed_reg = renameMap.lookup(i + AlphaISA::FP_Base_DepTag); - xc->regs.floatRegFile.d[i] = regFile.floatRegFile[renamed_reg].d; - xc->regs.floatRegFile.q[i] = regFile.floatRegFile[renamed_reg].q; + xc->regs.floatRegFile.d[i] = regFile.readFloatRegDouble(renamed_reg); + xc->regs.floatRegFile.q[i] = regFile.readFloatRegInt(renamed_reg); } xc->regs.miscRegs.fpcr = regFile.miscRegs.fpcr; @@ -169,15 +169,15 @@ AlphaFullCPU::copyFromXC() renamed_reg, regFile.intRegFile[renamed_reg], xc->regs.intRegFile[i]); - regFile.intRegFile[renamed_reg] = xc->regs.intRegFile[i]; + regFile.setIntReg(renamed_reg, xc->regs.intRegFile[i]); } // Then loop through the floating point registers. for (int i = 0; i < AlphaISA::NumFloatRegs; ++i) { renamed_reg = renameMap.lookup(i + AlphaISA::FP_Base_DepTag); - regFile.floatRegFile[renamed_reg].d = xc->regs.floatRegFile.d[i]; - regFile.floatRegFile[renamed_reg].q = xc->regs.floatRegFile.q[i] ; + regFile.setFloatRegDouble(renamed_reg, xc->regs.floatRegFile.d[i]); + regFile.setFloatRegInt(renamed_reg, xc->regs.floatRegFile.q[i]); } // Then loop through the misc registers. diff --git a/cpu/beta_cpu/commit_impl.hh b/cpu/beta_cpu/commit_impl.hh index 9a69c9259..3e97b980c 100644 --- a/cpu/beta_cpu/commit_impl.hh +++ b/cpu/beta_cpu/commit_impl.hh @@ -323,6 +323,7 @@ SimpleCommit::commitInsts() head_inst = rob->readHeadInst(); } + DPRINTF(CommitRate, "%i\n", num_committed); n_committed_dist.sample(num_committed); } diff --git a/cpu/beta_cpu/decode_impl.hh b/cpu/beta_cpu/decode_impl.hh index 8b20bf8bc..dd51f564d 100644 --- a/cpu/beta_cpu/decode_impl.hh +++ b/cpu/beta_cpu/decode_impl.hh @@ -147,7 +147,7 @@ SimpleDecode::squash(DynInstPtr &inst) { DPRINTF(Decode, "Decode: Squashing due to incorrect branch prediction " "detected at decode.\n"); - Addr new_PC = inst->nextPC; + Addr new_PC = inst->readNextPC(); toFetch->decodeInfo.branchMispredict = true; toFetch->decodeInfo.doneSeqNum = inst->seqNum; @@ -355,10 +355,9 @@ SimpleDecode::decode() // Go ahead and compute any PC-relative branches. - if (inst->isDirectCtrl() && inst->isUncondCtrl() && - inst->numDestRegs() == 0 && inst->numSrcRegs() == 0) { - inst->execute(); - inst->setExecuted(); + if (inst->isDirectCtrl() && inst->isUncondCtrl()) { + + inst->setNextPC(inst->branchTarget()); if (inst->mispredicted()) { ++decodeBranchMispred; diff --git a/cpu/beta_cpu/fetch_impl.hh b/cpu/beta_cpu/fetch_impl.hh index 8c9cf9f41..90caf9ffe 100644 --- a/cpu/beta_cpu/fetch_impl.hh +++ b/cpu/beta_cpu/fetch_impl.hh @@ -195,22 +195,6 @@ SimpleFetch::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC) predict_taken = branchPred.predict(inst, next_PC); -#if 0 - predict_taken = branchPred.BPLookup(next_PC) - - DPRINTF(Fetch, "Fetch: Branch predictor predicts taken? %i\n", - predict_taken); - - // Only check the BTB if the BP has predicted taken. - if (predict_taken && branchPred.BTBValid(next_PC)) { - predict_target = branchPred.BTBLookup(next_PC); - DPRINTF(Fetch, "Fetch: BTB target is %#x.\n", predict_target); - } else { - predict_taken = false; - DPRINTF(Fetch, "Fetch: BTB does not have a valid entry.\n"); - } - -#endif if (predict_taken) { ++predictedBranches; } diff --git a/cpu/beta_cpu/iew_impl.hh b/cpu/beta_cpu/iew_impl.hh index 2bfd6bae9..b718e6aa0 100644 --- a/cpu/beta_cpu/iew_impl.hh +++ b/cpu/beta_cpu/iew_impl.hh @@ -249,7 +249,6 @@ SimpleIEW::squashDueToBranch(DynInstPtr &inst) // Prediction was incorrect, so send back inverse. toCommit->branchTaken = inst->readCalcTarg() != (inst->readPC() + sizeof(MachInst)); -// toCommit->globalHist = inst->readGlobalHist(); } template @@ -363,10 +362,11 @@ SimpleIEW::dispatchInsts() continue; } else if (inst->isExecuted()) { + assert(0 && "Instruction shouldn't be executed.\n"); DPRINTF(IEW, "IEW: Issue: Executed branch encountered, " "skipping.\n"); - assert(inst->isDirectCtrl()); +// assert(inst->isDirectCtrl()); inst->setIssued(); inst->setCanCommit(); diff --git a/cpu/beta_cpu/regfile.hh b/cpu/beta_cpu/regfile.hh index 148d9408a..f6fb917ba 100644 --- a/cpu/beta_cpu/regfile.hh +++ b/cpu/beta_cpu/regfile.hh @@ -8,6 +8,8 @@ using namespace std; #include "arch/alpha/isa_traits.hh" #include "cpu/beta_cpu/comm.hh" +#include "base/trace.hh" + // This really only depends on the ISA, and not the Impl. It might be nicer // to see if I can make it depend on nothing... // Things that are in the ifdef FULL_SYSTEM are pretty dependent on the ISA,