Merge zizzer:/bk/newmem/
into zower.eecs.umich.edu:/eecshome/m5/newmem --HG-- extra : convert_revision : 17d6c49ee15af5d192dedf82871159219d4277cd
This commit is contained in:
commit
90907f6b3c
45 changed files with 755 additions and 3586 deletions
55
SConstruct
55
SConstruct
|
@ -66,6 +66,7 @@
|
|||
# Python library imports
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||||
import sys
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import os
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from os.path import join as joinpath
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# Check for recent-enough Python and SCons versions. If your system's
|
||||
# default installation of Python is not recent enough, you can use a
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||||
|
@ -89,11 +90,11 @@ except:
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|||
# The absolute path to the current directory (where this file lives).
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||||
ROOT = Dir('.').abspath
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# Paths to the M5 and external source trees.
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SRCDIR = os.path.join(ROOT, 'src')
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# Path to the M5 source tree.
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SRCDIR = joinpath(ROOT, 'src')
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# tell python where to find m5 python code
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sys.path.append(os.path.join(ROOT, 'src/python'))
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sys.path.append(joinpath(ROOT, 'src/python'))
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||||
|
||||
###################################################
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||||
#
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|
@ -105,13 +106,6 @@ sys.path.append(os.path.join(ROOT, 'src/python'))
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|||
# Find default configuration & binary.
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Default(os.environ.get('M5_DEFAULT_BINARY', 'build/ALPHA_SE/m5.debug'))
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|
||||
# Ask SCons which directory it was invoked from.
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||||
launch_dir = GetLaunchDir()
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|
||||
# Make targets relative to invocation directory
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abs_targets = map(lambda x: os.path.normpath(os.path.join(launch_dir, str(x))),
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BUILD_TARGETS)
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||||
# helper function: find last occurrence of element in list
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def rfind(l, elt, offs = -1):
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for i in range(len(l)+offs, 0, -1):
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|
@ -141,6 +135,19 @@ def compare_versions(v1, v2):
|
|||
# recognize that ALPHA_SE specifies the configuration because it
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||||
# follow 'build' in the bulid path.
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||||
|
||||
# Generate absolute paths to targets so we can see where the build dir is
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||||
if COMMAND_LINE_TARGETS:
|
||||
# Ask SCons which directory it was invoked from
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||||
launch_dir = GetLaunchDir()
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||||
# Make targets relative to invocation directory
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abs_targets = map(lambda x: os.path.normpath(joinpath(launch_dir, str(x))),
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COMMAND_LINE_TARGETS)
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else:
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||||
# Default targets are relative to root of tree
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abs_targets = map(lambda x: os.path.normpath(joinpath(ROOT, str(x))),
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DEFAULT_TARGETS)
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# Generate a list of the unique build roots and configs that the
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||||
# collected targets reference.
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||||
build_paths = []
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|
@ -152,7 +159,7 @@ for t in abs_targets:
|
|||
except:
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print "Error: no non-leaf 'build' dir found on target path", t
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Exit(1)
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this_build_root = os.path.join('/',*path_dirs[:build_top+1])
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this_build_root = joinpath('/',*path_dirs[:build_top+1])
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if not build_root:
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||||
build_root = this_build_root
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else:
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||||
|
@ -160,7 +167,7 @@ for t in abs_targets:
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|||
print "Error: build targets not under same build root\n"\
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" %s\n %s" % (build_root, this_build_root)
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Exit(1)
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build_path = os.path.join('/',*path_dirs[:build_top+2])
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build_path = joinpath('/',*path_dirs[:build_top+2])
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||||
if build_path not in build_paths:
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||||
build_paths.append(build_path)
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|
||||
|
@ -183,7 +190,7 @@ if ARGUMENTS.get('CC', None):
|
|||
if ARGUMENTS.get('CXX', None):
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||||
env['CXX'] = ARGUMENTS.get('CXX')
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||||
|
||||
env.SConsignFile(os.path.join(build_root,"sconsign"))
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env.SConsignFile(joinpath(build_root,"sconsign"))
|
||||
|
||||
# Default duplicate option is to use hard links, but this messes up
|
||||
# when you use emacs to edit a file in the target dir, as emacs moves
|
||||
|
@ -243,8 +250,8 @@ env.Append(SCANNERS = swig_scanner)
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|||
# Platform-specific configuration. Note again that we assume that all
|
||||
# builds under a given build root run on the same host platform.
|
||||
conf = Configure(env,
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conf_dir = os.path.join(build_root, '.scons_config'),
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log_file = os.path.join(build_root, 'scons_config.log'))
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||||
conf_dir = joinpath(build_root, '.scons_config'),
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log_file = joinpath(build_root, 'scons_config.log'))
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||||
|
||||
# Find Python include and library directories for embedding the
|
||||
# interpreter. For consistency, we will use the same Python
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||||
|
@ -257,7 +264,7 @@ conf = Configure(env,
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|||
py_version_name = 'python' + sys.version[:3]
|
||||
|
||||
# include path, e.g. /usr/local/include/python2.4
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py_header_path = os.path.join(sys.exec_prefix, 'include', py_version_name)
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py_header_path = joinpath(sys.exec_prefix, 'include', py_version_name)
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env.Append(CPPPATH = py_header_path)
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||||
# verify that it works
|
||||
if not conf.CheckHeader('Python.h', '<>'):
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|
@ -267,7 +274,7 @@ if not conf.CheckHeader('Python.h', '<>'):
|
|||
# add library path too if it's not in the default place
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||||
py_lib_path = None
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if sys.exec_prefix != '/usr':
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py_lib_path = os.path.join(sys.exec_prefix, 'lib')
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||||
py_lib_path = joinpath(sys.exec_prefix, 'lib')
|
||||
elif sys.platform == 'cygwin':
|
||||
# cygwin puts the .dll in /bin for some reason
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||||
py_lib_path = '/bin'
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||||
|
@ -330,7 +337,7 @@ env['ALL_ISA_LIST'] = ['alpha', 'sparc', 'mips']
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|||
env['ALL_CPU_LIST'] = ['AtomicSimpleCPU', 'TimingSimpleCPU',
|
||||
'O3CPU', 'OzoneCPU']
|
||||
|
||||
if os.path.isdir(os.path.join(SRCDIR, 'src/encumbered/cpu/full')):
|
||||
if os.path.isdir(joinpath(SRCDIR, 'encumbered/cpu/full')):
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env['ALL_CPU_LIST'] += ['FullCPU']
|
||||
|
||||
# Sticky options get saved in the options file so they persist from
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|
@ -417,7 +424,7 @@ def config_emitter(target, source, env):
|
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# extract option name from Builder arg
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option = str(target[0])
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# True target is config header file
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target = os.path.join('config', option.lower() + '.hh')
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target = joinpath('config', option.lower() + '.hh')
|
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val = env[option]
|
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if isinstance(val, bool):
|
||||
# Force value to 0/1
|
||||
|
@ -466,7 +473,7 @@ Usage: scons [scons options] [build options] [target(s)]
|
|||
|
||||
# libelf build is shared across all configs in the build root.
|
||||
env.SConscript('ext/libelf/SConscript',
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||||
build_dir = os.path.join(build_root, 'libelf'),
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||||
build_dir = joinpath(build_root, 'libelf'),
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||||
exports = 'env')
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||||
|
||||
###################################################
|
||||
|
@ -531,7 +538,7 @@ for build_path in build_paths:
|
|||
# Options for $BUILD_ROOT/$BUILD_DIR are stored in
|
||||
# $BUILD_ROOT/options/$BUILD_DIR so you can nuke
|
||||
# $BUILD_ROOT/$BUILD_DIR without losing your options settings.
|
||||
current_opts_file = os.path.join(build_root, 'options', build_dir)
|
||||
current_opts_file = joinpath(build_root, 'options', build_dir)
|
||||
if os.path.isfile(current_opts_file):
|
||||
sticky_opts.files.append(current_opts_file)
|
||||
print "Using saved options file %s" % current_opts_file
|
||||
|
@ -546,8 +553,8 @@ for build_path in build_paths:
|
|||
# Get default build options from source tree. Options are
|
||||
# normally determined by name of $BUILD_DIR, but can be
|
||||
# overriden by 'default=' arg on command line.
|
||||
default_opts_file = os.path.join('build_opts',
|
||||
ARGUMENTS.get('default', build_dir))
|
||||
default_opts_file = joinpath('build_opts',
|
||||
ARGUMENTS.get('default', build_dir))
|
||||
if os.path.isfile(default_opts_file):
|
||||
sticky_opts.files.append(default_opts_file)
|
||||
print "Options file %s not found,\n using defaults in %s" \
|
||||
|
@ -611,7 +618,7 @@ for build_path in build_paths:
|
|||
# Set up the regression tests for each build.
|
||||
for e in envList:
|
||||
SConscript('tests/SConscript',
|
||||
build_dir = os.path.join(build_path, 'tests', e.Label),
|
||||
build_dir = joinpath(build_path, 'tests', e.Label),
|
||||
exports = { 'env' : e }, duplicate = False)
|
||||
|
||||
Help(help_text)
|
||||
|
|
|
@ -108,6 +108,7 @@ base_sources = Split('''
|
|||
mem/cache/coherence/coherence_protocol.cc
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mem/cache/coherence/uni_coherence.cc
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||||
mem/cache/miss/blocking_buffer.cc
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||||
mem/cache/miss/miss_buffer.cc
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||||
mem/cache/miss/miss_queue.cc
|
||||
mem/cache/miss/mshr.cc
|
||||
mem/cache/miss/mshr_queue.cc
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||||
|
|
|
@ -1180,15 +1180,16 @@ class IntRegOperand(Operand):
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if (self.ctype == 'float' or self.ctype == 'double'):
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error(0, 'Attempt to read integer register as FP')
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if (self.size == self.dflt_size):
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return '%s = xc->readIntReg(this, %d);\n' % \
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return '%s = xc->readIntRegOperand(this, %d);\n' % \
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(self.base_name, self.src_reg_idx)
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elif (self.size > self.dflt_size):
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int_reg_val = 'xc->readIntReg(this, %d)' % (self.src_reg_idx)
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int_reg_val = 'xc->readIntRegOperand(this, %d)' % \
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(self.src_reg_idx)
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if (self.is_signed):
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int_reg_val = 'sext<%d>(%s)' % (self.dflt_size, int_reg_val)
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return '%s = %s;\n' % (self.base_name, int_reg_val)
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else:
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return '%s = bits(xc->readIntReg(this, %d), %d, 0);\n' % \
|
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return '%s = bits(xc->readIntRegOperand(this, %d), %d, 0);\n' % \
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(self.base_name, self.src_reg_idx, self.size-1)
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def makeWrite(self):
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|
@ -1201,7 +1202,7 @@ class IntRegOperand(Operand):
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wb = '''
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{
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%s final_val = %s;
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xc->setIntReg(this, %d, final_val);\n
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xc->setIntRegOperand(this, %d, final_val);\n
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if (traceData) { traceData->setData(final_val); }
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}''' % (self.dflt_ctype, final_val, self.dest_reg_idx)
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return wb
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|
@ -1227,13 +1228,13 @@ class FloatRegOperand(Operand):
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|||
bit_select = 0
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width = 0;
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||||
if (self.ctype == 'float'):
|
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func = 'readFloatReg'
|
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func = 'readFloatRegOperand'
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width = 32;
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||||
elif (self.ctype == 'double'):
|
||||
func = 'readFloatReg'
|
||||
func = 'readFloatRegOperand'
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width = 64;
|
||||
else:
|
||||
func = 'readFloatRegBits'
|
||||
func = 'readFloatRegOperandBits'
|
||||
if (self.ctype == 'uint32_t'):
|
||||
width = 32;
|
||||
elif (self.ctype == 'uint64_t'):
|
||||
|
@ -1259,18 +1260,18 @@ class FloatRegOperand(Operand):
|
|||
width = 0
|
||||
if (self.ctype == 'float'):
|
||||
width = 32
|
||||
func = 'setFloatReg'
|
||||
func = 'setFloatRegOperand'
|
||||
elif (self.ctype == 'double'):
|
||||
width = 64
|
||||
func = 'setFloatReg'
|
||||
func = 'setFloatRegOperand'
|
||||
elif (self.ctype == 'uint32_t'):
|
||||
func = 'setFloatRegBits'
|
||||
func = 'setFloatRegOperandBits'
|
||||
width = 32
|
||||
elif (self.ctype == 'uint64_t'):
|
||||
func = 'setFloatRegBits'
|
||||
func = 'setFloatRegOperandBits'
|
||||
width = 64
|
||||
else:
|
||||
func = 'setFloatRegBits'
|
||||
func = 'setFloatRegOperandBits'
|
||||
final_ctype = 'uint%d_t' % self.dflt_size
|
||||
if (self.size != self.dflt_size and self.is_signed):
|
||||
final_val = 'sext<%d>(%s)' % (self.size, self.base_name)
|
||||
|
|
|
@ -99,7 +99,7 @@ output exec {{
|
|||
int size = sizeof(src_op) * 8;
|
||||
|
||||
for (int i = 0; i < inst->numSrcRegs(); i++) {
|
||||
uint64_t src_bits = xc->readFloatRegBits(inst, 0, size);
|
||||
uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0, size);
|
||||
|
||||
if (isNan(&src_bits, size) ) {
|
||||
if (isSnan(&src_bits, size)) {
|
||||
|
@ -113,7 +113,7 @@ output exec {{
|
|||
mips_nan = src_bits;
|
||||
}
|
||||
|
||||
xc->setFloatRegBits(inst, 0, mips_nan, size);
|
||||
xc->setFloatRegOperandBits(inst, 0, mips_nan, size);
|
||||
if (traceData) { traceData->setData(mips_nan); }
|
||||
return true;
|
||||
}
|
||||
|
@ -139,7 +139,7 @@ output exec {{
|
|||
}
|
||||
|
||||
//Set value to QNAN
|
||||
cpu->setFloatRegBits(inst, 0, mips_nan, size);
|
||||
cpu->setFloatRegOperandBits(inst, 0, mips_nan, size);
|
||||
|
||||
//Read FCSR from FloatRegFile
|
||||
uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR);
|
||||
|
|
71
src/base/compression/base.hh
Normal file
71
src/base/compression/base.hh
Normal file
|
@ -0,0 +1,71 @@
|
|||
/*
|
||||
* Copyright (c) 2003-2005 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Erik Hallnor
|
||||
* Nathan Binkert
|
||||
*/
|
||||
|
||||
#ifndef __BASE_COMPRESSION_BASE_HH__
|
||||
#define __BASE_COMPRESSION_BASE_HH__
|
||||
|
||||
/**
|
||||
* @file
|
||||
* This file defines a base (abstract virtual) compression algorithm object.
|
||||
*/
|
||||
|
||||
#include <inttypes.h>
|
||||
|
||||
/**
|
||||
* Abstract virtual compression algorithm object.
|
||||
*/
|
||||
class CompressionAlgorithm
|
||||
{
|
||||
public:
|
||||
virtual ~CompressionAlgorithm() {}
|
||||
|
||||
/**
|
||||
* Uncompress the data, causes a fatal since no data should be compressed.
|
||||
* @param dest The output buffer.
|
||||
* @param src The compressed data.
|
||||
* @param size The number of bytes in src.
|
||||
*
|
||||
* @retval The size of the uncompressed data.
|
||||
*/
|
||||
virtual int uncompress(uint8_t * dest, uint8_t *src, int size) = 0;
|
||||
|
||||
/**
|
||||
* Compress the data, just returns the source data.
|
||||
* @param dest The output buffer.
|
||||
* @param src The data to be compressed.
|
||||
* @param size The number of bytes in src.
|
||||
*
|
||||
* @retval The size of the compressed data.
|
||||
*/
|
||||
virtual int compress(uint8_t *dest, uint8_t *src, int size) = 0;
|
||||
};
|
||||
|
||||
#endif //__BASE_COMPRESSION_BASE_HH__
|
|
@ -35,12 +35,12 @@
|
|||
* LZSSCompression declarations.
|
||||
*/
|
||||
|
||||
#include "sim/host.hh" // for uint8_t
|
||||
#include "base/compression/base.hh"
|
||||
|
||||
/**
|
||||
* Simple LZSS compression scheme.
|
||||
*/
|
||||
class LZSSCompression
|
||||
class LZSSCompression : public CompressionAlgorithm
|
||||
{
|
||||
/**
|
||||
* Finds the longest substring for the given offset.
|
||||
|
|
|
@ -38,41 +38,23 @@
|
|||
*/
|
||||
|
||||
#include "base/misc.hh" // for fatal()
|
||||
#include "sim/host.hh"
|
||||
#include "base/compression/base.hh"
|
||||
|
||||
|
||||
/**
|
||||
* A dummy compression class to use when no data compression is desired.
|
||||
*/
|
||||
class NullCompression
|
||||
class NullCompression : public CompressionAlgorithm
|
||||
{
|
||||
public:
|
||||
/**
|
||||
* Uncompress the data, causes a fatal since no data should be compressed.
|
||||
* @param dest The output buffer.
|
||||
* @param src The compressed data.
|
||||
* @param size The number of bytes in src.
|
||||
*
|
||||
* @retval The size of the uncompressed data.
|
||||
*/
|
||||
static int uncompress(uint8_t * dest, uint8_t *src, int size)
|
||||
int uncompress(uint8_t * dest, uint8_t *src, int size)
|
||||
{
|
||||
fatal("Can't uncompress data");
|
||||
}
|
||||
|
||||
/**
|
||||
* Compress the data, just returns the source data.
|
||||
* @param dest The output buffer.
|
||||
* @param src The data to be compressed.
|
||||
* @param size The number of bytes in src.
|
||||
*
|
||||
* @retval The size of the compressed data.
|
||||
*/
|
||||
|
||||
static int compress(uint8_t *dest, uint8_t *src, int size)
|
||||
int compress(uint8_t *dest, uint8_t *src, int size)
|
||||
{
|
||||
memcpy(dest,src,size);
|
||||
return size;
|
||||
fatal("Can't compress data");
|
||||
}
|
||||
};
|
||||
|
||||
|
|
|
@ -501,14 +501,15 @@ class BaseDynInst : public FastAlloc, public RefCounted
|
|||
double readDoubleResult() { return instResult.dbl; }
|
||||
|
||||
/** Records an integer register being set to a value. */
|
||||
void setIntReg(const StaticInst *si, int idx, uint64_t val)
|
||||
void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
|
||||
{
|
||||
if (recordResult)
|
||||
instResult.integer = val;
|
||||
}
|
||||
|
||||
/** Records an fp register being set to a value. */
|
||||
void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
|
||||
void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
|
||||
int width)
|
||||
{
|
||||
if (recordResult) {
|
||||
if (width == 32)
|
||||
|
@ -521,21 +522,22 @@ class BaseDynInst : public FastAlloc, public RefCounted
|
|||
}
|
||||
|
||||
/** Records an fp register being set to a value. */
|
||||
void setFloatReg(const StaticInst *si, int idx, FloatReg val)
|
||||
void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
|
||||
{
|
||||
if (recordResult)
|
||||
instResult.dbl = (double)val;
|
||||
}
|
||||
|
||||
/** Records an fp register being set to an integer value. */
|
||||
void setFloatRegBits(const StaticInst *si, int idx, uint64_t val, int width)
|
||||
void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
|
||||
int width)
|
||||
{
|
||||
if (recordResult)
|
||||
instResult.integer = val;
|
||||
}
|
||||
|
||||
/** Records an fp register being set to an integer value. */
|
||||
void setFloatRegBits(const StaticInst *si, int idx, uint64_t val)
|
||||
void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
|
||||
{
|
||||
if (recordResult)
|
||||
instResult.integer = val;
|
||||
|
|
|
@ -216,42 +216,44 @@ class CheckerCPU : public BaseCPU
|
|||
// storage (which is pretty hard to imagine they would have reason
|
||||
// to do).
|
||||
|
||||
uint64_t readIntReg(const StaticInst *si, int idx)
|
||||
uint64_t readIntRegOperand(const StaticInst *si, int idx)
|
||||
{
|
||||
return thread->readIntReg(si->srcRegIdx(idx));
|
||||
}
|
||||
|
||||
FloatReg readFloatReg(const StaticInst *si, int idx, int width)
|
||||
FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
|
||||
{
|
||||
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
|
||||
return thread->readFloatReg(reg_idx, width);
|
||||
}
|
||||
|
||||
FloatReg readFloatReg(const StaticInst *si, int idx)
|
||||
FloatReg readFloatRegOperand(const StaticInst *si, int idx)
|
||||
{
|
||||
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
|
||||
return thread->readFloatReg(reg_idx);
|
||||
}
|
||||
|
||||
FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
|
||||
FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
|
||||
int width)
|
||||
{
|
||||
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
|
||||
return thread->readFloatRegBits(reg_idx, width);
|
||||
}
|
||||
|
||||
FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
|
||||
FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
|
||||
{
|
||||
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
|
||||
return thread->readFloatRegBits(reg_idx);
|
||||
}
|
||||
|
||||
void setIntReg(const StaticInst *si, int idx, uint64_t val)
|
||||
void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
|
||||
{
|
||||
thread->setIntReg(si->destRegIdx(idx), val);
|
||||
result.integer = val;
|
||||
}
|
||||
|
||||
void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
|
||||
void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
|
||||
int width)
|
||||
{
|
||||
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
|
||||
thread->setFloatReg(reg_idx, val, width);
|
||||
|
@ -265,22 +267,23 @@ class CheckerCPU : public BaseCPU
|
|||
};
|
||||
}
|
||||
|
||||
void setFloatReg(const StaticInst *si, int idx, FloatReg val)
|
||||
void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
|
||||
{
|
||||
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
|
||||
thread->setFloatReg(reg_idx, val);
|
||||
result.dbl = (double)val;
|
||||
}
|
||||
|
||||
void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val,
|
||||
int width)
|
||||
void setFloatRegOperandBits(const StaticInst *si, int idx,
|
||||
FloatRegBits val, int width)
|
||||
{
|
||||
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
|
||||
thread->setFloatRegBits(reg_idx, val, width);
|
||||
result.integer = val;
|
||||
}
|
||||
|
||||
void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
|
||||
void setFloatRegOperandBits(const StaticInst *si, int idx,
|
||||
FloatRegBits val)
|
||||
{
|
||||
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
|
||||
thread->setFloatRegBits(reg_idx, val);
|
||||
|
|
|
@ -48,39 +48,42 @@ class ExecContext {
|
|||
// to do).
|
||||
|
||||
/** Reads an integer register. */
|
||||
uint64_t readIntReg(const StaticInst *si, int idx);
|
||||
uint64_t readIntRegOperand(const StaticInst *si, int idx);
|
||||
|
||||
/** Reads a floating point register of a specific width. */
|
||||
FloatReg readFloatReg(const StaticInst *si, int idx, int width);
|
||||
FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width);
|
||||
|
||||
/** Reads a floating point register of single register width. */
|
||||
FloatReg readFloatReg(const StaticInst *si, int idx);
|
||||
FloatReg readFloatRegOperand(const StaticInst *si, int idx);
|
||||
|
||||
/** Reads a floating point register of a specific width in its
|
||||
* binary format, instead of by value. */
|
||||
FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width);
|
||||
FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
|
||||
int width);
|
||||
|
||||
/** Reads a floating point register in its binary format, instead
|
||||
* of by value. */
|
||||
FloatRegBits readFloatRegBits(const StaticInst *si, int idx);
|
||||
FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx);
|
||||
|
||||
/** Sets an integer register to a value. */
|
||||
void setIntReg(const StaticInst *si, int idx, uint64_t val);
|
||||
void setIntRegOperand(const StaticInst *si, int idx, uint64_t val);
|
||||
|
||||
/** Sets a floating point register of a specific width to a value. */
|
||||
void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width);
|
||||
void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
|
||||
int width);
|
||||
|
||||
/** Sets a floating point register of single width to a value. */
|
||||
void setFloatReg(const StaticInst *si, int idx, FloatReg val);
|
||||
void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val);
|
||||
|
||||
/** Sets the bits of a floating point register of a specific width
|
||||
* to a binary value. */
|
||||
void setFloatRegBits(const StaticInst *si, int idx,
|
||||
FloatRegBits val, int width);
|
||||
void setFloatRegOperandBits(const StaticInst *si, int idx,
|
||||
FloatRegBits val, int width);
|
||||
|
||||
/** Sets the bits of a floating point register of single width
|
||||
* to a binary value. */
|
||||
void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val);
|
||||
void setFloatRegOperandBits(const StaticInst *si, int idx,
|
||||
FloatRegBits val);
|
||||
|
||||
/** Reads the PC. */
|
||||
uint64_t readPC();
|
||||
|
|
|
@ -147,27 +147,28 @@ class AlphaDynInst : public BaseDynInst<Impl>
|
|||
// storage (which is pretty hard to imagine they would have reason
|
||||
// to do).
|
||||
|
||||
uint64_t readIntReg(const StaticInst *si, int idx)
|
||||
uint64_t readIntRegOperand(const StaticInst *si, int idx)
|
||||
{
|
||||
return this->cpu->readIntReg(this->_srcRegIdx[idx]);
|
||||
}
|
||||
|
||||
FloatReg readFloatReg(const StaticInst *si, int idx, int width)
|
||||
FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
|
||||
{
|
||||
return this->cpu->readFloatReg(this->_srcRegIdx[idx], width);
|
||||
}
|
||||
|
||||
FloatReg readFloatReg(const StaticInst *si, int idx)
|
||||
FloatReg readFloatRegOperand(const StaticInst *si, int idx)
|
||||
{
|
||||
return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
|
||||
}
|
||||
|
||||
FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
|
||||
FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
|
||||
int width)
|
||||
{
|
||||
return this->cpu->readFloatRegBits(this->_srcRegIdx[idx], width);
|
||||
}
|
||||
|
||||
FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
|
||||
FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
|
||||
{
|
||||
return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]);
|
||||
}
|
||||
|
@ -175,35 +176,37 @@ class AlphaDynInst : public BaseDynInst<Impl>
|
|||
/** @todo: Make results into arrays so they can handle multiple dest
|
||||
* registers.
|
||||
*/
|
||||
void setIntReg(const StaticInst *si, int idx, uint64_t val)
|
||||
void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
|
||||
{
|
||||
this->cpu->setIntReg(this->_destRegIdx[idx], val);
|
||||
BaseDynInst<Impl>::setIntReg(si, idx, val);
|
||||
BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
|
||||
}
|
||||
|
||||
void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
|
||||
void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
|
||||
int width)
|
||||
{
|
||||
this->cpu->setFloatReg(this->_destRegIdx[idx], val, width);
|
||||
BaseDynInst<Impl>::setFloatReg(si, idx, val, width);
|
||||
BaseDynInst<Impl>::setFloatRegOperand(si, idx, val, width);
|
||||
}
|
||||
|
||||
void setFloatReg(const StaticInst *si, int idx, FloatReg val)
|
||||
void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
|
||||
{
|
||||
this->cpu->setFloatReg(this->_destRegIdx[idx], val);
|
||||
BaseDynInst<Impl>::setFloatReg(si, idx, val);
|
||||
BaseDynInst<Impl>::setFloatRegOperand(si, idx, val);
|
||||
}
|
||||
|
||||
void setFloatRegBits(const StaticInst *si, int idx,
|
||||
FloatRegBits val, int width)
|
||||
void setFloatRegOperandBits(const StaticInst *si, int idx,
|
||||
FloatRegBits val, int width)
|
||||
{
|
||||
this->cpu->setFloatRegBits(this->_destRegIdx[idx], val, width);
|
||||
BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
|
||||
BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
|
||||
}
|
||||
|
||||
void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
|
||||
void setFloatRegOperandBits(const StaticInst *si, int idx,
|
||||
FloatRegBits val)
|
||||
{
|
||||
this->cpu->setFloatRegBits(this->_destRegIdx[idx], val);
|
||||
BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
|
||||
BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
|
||||
}
|
||||
|
||||
public:
|
||||
|
|
|
@ -1180,16 +1180,16 @@ DefaultCommit<Impl>::getInsts()
|
|||
rename_idx < fromRename->size;
|
||||
rename_idx++) {
|
||||
DynInstPtr inst = fromRename->insts[rename_idx];
|
||||
int tid = inst->threadNumber;
|
||||
|
||||
if (!inst->isSquashed()) {
|
||||
DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
|
||||
"skidBuffer.\n", inst->readPC(), inst->seqNum, tid);
|
||||
"skidBuffer.\n", inst->readPC(), inst->seqNum,
|
||||
inst->threadNumber);
|
||||
skidBuffer.push(inst);
|
||||
} else {
|
||||
DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
|
||||
"squashed, skipping.\n",
|
||||
inst->readPC(), inst->seqNum, tid);
|
||||
inst->readPC(), inst->seqNum, inst->threadNumber);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -151,36 +151,6 @@ DefaultFetch<Impl>::DefaultFetch(Params *params)
|
|||
" RoundRobin,LSQcount,IQcount}\n");
|
||||
}
|
||||
|
||||
// Size of cache block.
|
||||
cacheBlkSize = 64;
|
||||
|
||||
// Create mask to get rid of offset bits.
|
||||
cacheBlkMask = (cacheBlkSize - 1);
|
||||
|
||||
for (int tid=0; tid < numThreads; tid++) {
|
||||
|
||||
fetchStatus[tid] = Running;
|
||||
|
||||
priorityList.push_back(tid);
|
||||
|
||||
memReq[tid] = NULL;
|
||||
|
||||
// Create space to store a cache line.
|
||||
cacheData[tid] = new uint8_t[cacheBlkSize];
|
||||
cacheDataPC[tid] = 0;
|
||||
cacheDataValid[tid] = false;
|
||||
|
||||
delaySlotInfo[tid].branchSeqNum = -1;
|
||||
delaySlotInfo[tid].numInsts = 0;
|
||||
delaySlotInfo[tid].targetAddr = 0;
|
||||
delaySlotInfo[tid].targetReady = false;
|
||||
|
||||
stalls[tid].decode = false;
|
||||
stalls[tid].rename = false;
|
||||
stalls[tid].iew = false;
|
||||
stalls[tid].commit = false;
|
||||
}
|
||||
|
||||
// Get the size of an instruction.
|
||||
instSize = sizeof(TheISA::MachInst);
|
||||
}
|
||||
|
@ -353,6 +323,36 @@ DefaultFetch<Impl>::initStage()
|
|||
nextNPC[tid] = cpu->readNextNPC(tid);
|
||||
#endif
|
||||
}
|
||||
|
||||
// Size of cache block.
|
||||
cacheBlkSize = icachePort->peerBlockSize();
|
||||
|
||||
// Create mask to get rid of offset bits.
|
||||
cacheBlkMask = (cacheBlkSize - 1);
|
||||
|
||||
for (int tid=0; tid < numThreads; tid++) {
|
||||
|
||||
fetchStatus[tid] = Running;
|
||||
|
||||
priorityList.push_back(tid);
|
||||
|
||||
memReq[tid] = NULL;
|
||||
|
||||
// Create space to store a cache line.
|
||||
cacheData[tid] = new uint8_t[cacheBlkSize];
|
||||
cacheDataPC[tid] = 0;
|
||||
cacheDataValid[tid] = false;
|
||||
|
||||
delaySlotInfo[tid].branchSeqNum = -1;
|
||||
delaySlotInfo[tid].numInsts = 0;
|
||||
delaySlotInfo[tid].targetAddr = 0;
|
||||
delaySlotInfo[tid].targetReady = false;
|
||||
|
||||
stalls[tid].decode = false;
|
||||
stalls[tid].rename = false;
|
||||
stalls[tid].iew = false;
|
||||
stalls[tid].commit = false;
|
||||
}
|
||||
}
|
||||
|
||||
template<class Impl>
|
||||
|
|
|
@ -418,7 +418,8 @@ LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
|
|||
// realizes there is activity.
|
||||
// Mark it as executed unless it is an uncached load that
|
||||
// needs to hit the head of commit.
|
||||
if (!(inst->req->isUncacheable()) || inst->isAtCommit()) {
|
||||
if (!(inst->req && inst->req->isUncacheable()) ||
|
||||
inst->isAtCommit()) {
|
||||
inst->setExecuted();
|
||||
}
|
||||
iewStage->instToCommit(inst);
|
||||
|
|
|
@ -136,27 +136,28 @@ class MipsDynInst : public BaseDynInst<Impl>
|
|||
// storage (which is pretty hard to imagine they would have reason
|
||||
// to do).
|
||||
|
||||
uint64_t readIntReg(const StaticInst *si, int idx)
|
||||
uint64_t readIntRegOperand(const StaticInst *si, int idx)
|
||||
{
|
||||
return this->cpu->readIntReg(this->_srcRegIdx[idx]);
|
||||
}
|
||||
|
||||
FloatReg readFloatReg(const StaticInst *si, int idx, int width)
|
||||
FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
|
||||
{
|
||||
return this->cpu->readFloatReg(this->_srcRegIdx[idx], width);
|
||||
}
|
||||
|
||||
FloatReg readFloatReg(const StaticInst *si, int idx)
|
||||
FloatReg readFloatRegOperand(const StaticInst *si, int idx)
|
||||
{
|
||||
return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
|
||||
}
|
||||
|
||||
FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
|
||||
FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
|
||||
int width)
|
||||
{
|
||||
return this->cpu->readFloatRegBits(this->_srcRegIdx[idx], width);
|
||||
}
|
||||
|
||||
FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
|
||||
FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
|
||||
{
|
||||
return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]);
|
||||
}
|
||||
|
@ -164,35 +165,37 @@ class MipsDynInst : public BaseDynInst<Impl>
|
|||
/** @todo: Make results into arrays so they can handle multiple dest
|
||||
* registers.
|
||||
*/
|
||||
void setIntReg(const StaticInst *si, int idx, uint64_t val)
|
||||
void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
|
||||
{
|
||||
this->cpu->setIntReg(this->_destRegIdx[idx], val);
|
||||
BaseDynInst<Impl>::setIntReg(si, idx, val);
|
||||
BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
|
||||
}
|
||||
|
||||
void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
|
||||
void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
|
||||
int width)
|
||||
{
|
||||
this->cpu->setFloatReg(this->_destRegIdx[idx], val, width);
|
||||
BaseDynInst<Impl>::setFloatReg(si, idx, val, width);
|
||||
BaseDynInst<Impl>::setFloatRegOperand(si, idx, val, width);
|
||||
}
|
||||
|
||||
void setFloatReg(const StaticInst *si, int idx, FloatReg val)
|
||||
void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
|
||||
{
|
||||
this->cpu->setFloatReg(this->_destRegIdx[idx], val);
|
||||
BaseDynInst<Impl>::setFloatReg(si, idx, val);
|
||||
BaseDynInst<Impl>::setFloatRegOperand(si, idx, val);
|
||||
}
|
||||
|
||||
void setFloatRegBits(const StaticInst *si, int idx,
|
||||
FloatRegBits val, int width)
|
||||
void setFloatRegOperandBits(const StaticInst *si, int idx,
|
||||
FloatRegBits val, int width)
|
||||
{
|
||||
this->cpu->setFloatRegBits(this->_destRegIdx[idx], val, width);
|
||||
BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
|
||||
BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
|
||||
}
|
||||
|
||||
void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
|
||||
void setFloatRegOperandBits(const StaticInst *si, int idx,
|
||||
FloatRegBits val)
|
||||
{
|
||||
this->cpu->setFloatRegBits(this->_destRegIdx[idx], val);
|
||||
BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
|
||||
BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
|
||||
}
|
||||
|
||||
public:
|
||||
|
|
|
@ -448,30 +448,6 @@ class OzoneCPU : public BaseCPU
|
|||
}
|
||||
#endif
|
||||
|
||||
/** Old CPU read from memory function. No longer used. */
|
||||
template <class T>
|
||||
Fault read(Request *req, T &data)
|
||||
{
|
||||
#if 0
|
||||
#if FULL_SYSTEM && defined(TARGET_ALPHA)
|
||||
if (req->isLocked()) {
|
||||
req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
|
||||
req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
|
||||
}
|
||||
#endif
|
||||
if (req->isLocked()) {
|
||||
lockAddrList.insert(req->paddr);
|
||||
lockFlag = true;
|
||||
}
|
||||
#endif
|
||||
Fault error;
|
||||
|
||||
error = this->mem->read(req, data);
|
||||
data = gtoh(data);
|
||||
return error;
|
||||
}
|
||||
|
||||
|
||||
/** CPU read function, forwards read to LSQ. */
|
||||
template <class T>
|
||||
Fault read(Request *req, T &data, int load_idx)
|
||||
|
@ -479,81 +455,6 @@ class OzoneCPU : public BaseCPU
|
|||
return backEnd->read(req, data, load_idx);
|
||||
}
|
||||
|
||||
/** Old CPU write to memory function. No longer used. */
|
||||
template <class T>
|
||||
Fault write(Request *req, T &data)
|
||||
{
|
||||
#if 0
|
||||
#if FULL_SYSTEM && defined(TARGET_ALPHA)
|
||||
ExecContext *xc;
|
||||
|
||||
// If this is a store conditional, act appropriately
|
||||
if (req->isLocked()) {
|
||||
xc = req->xc;
|
||||
|
||||
if (req->isUncacheable()) {
|
||||
// Don't update result register (see stq_c in isa_desc)
|
||||
req->result = 2;
|
||||
xc->setStCondFailures(0);//Needed? [RGD]
|
||||
} else {
|
||||
bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
|
||||
Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
|
||||
req->result = lock_flag;
|
||||
if (!lock_flag ||
|
||||
((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
|
||||
xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
|
||||
xc->setStCondFailures(xc->readStCondFailures() + 1);
|
||||
if (((xc->readStCondFailures()) % 100000) == 0) {
|
||||
std::cerr << "Warning: "
|
||||
<< xc->readStCondFailures()
|
||||
<< " consecutive store conditional failures "
|
||||
<< "on cpu " << req->xc->readCpuId()
|
||||
<< std::endl;
|
||||
}
|
||||
return NoFault;
|
||||
}
|
||||
else xc->setStCondFailures(0);
|
||||
}
|
||||
}
|
||||
|
||||
// Need to clear any locked flags on other proccessors for
|
||||
// this address. Only do this for succsful Store Conditionals
|
||||
// and all other stores (WH64?). Unsuccessful Store
|
||||
// Conditionals would have returned above, and wouldn't fall
|
||||
// through.
|
||||
for (int i = 0; i < this->system->threadContexts.size(); i++){
|
||||
xc = this->system->threadContexts[i];
|
||||
if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
|
||||
(req->paddr & ~0xf)) {
|
||||
xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
if (req->isLocked()) {
|
||||
if (req->isUncacheable()) {
|
||||
req->result = 2;
|
||||
} else {
|
||||
if (this->lockFlag) {
|
||||
if (lockAddrList.find(req->paddr) !=
|
||||
lockAddrList.end()) {
|
||||
req->result = 1;
|
||||
} else {
|
||||
req->result = 0;
|
||||
return NoFault;
|
||||
}
|
||||
} else {
|
||||
req->result = 0;
|
||||
return NoFault;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
return this->mem->write(req, (T)htog(data));
|
||||
}
|
||||
|
||||
/** CPU write function, forwards write to LSQ. */
|
||||
template <class T>
|
||||
Fault write(Request *req, T &data, int store_idx)
|
||||
|
|
|
@ -146,12 +146,12 @@ class OzoneDynInst : public BaseDynInst<Impl>
|
|||
// storage (which is pretty hard to imagine they would have reason
|
||||
// to do).
|
||||
|
||||
uint64_t readIntReg(const StaticInst *si, int idx)
|
||||
uint64_t readIntRegOperand(const StaticInst *si, int idx)
|
||||
{
|
||||
return srcInsts[idx]->readIntResult();
|
||||
}
|
||||
|
||||
FloatReg readFloatReg(const StaticInst *si, int idx, int width)
|
||||
FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
|
||||
{
|
||||
switch(width) {
|
||||
case 32:
|
||||
|
@ -164,17 +164,18 @@ class OzoneDynInst : public BaseDynInst<Impl>
|
|||
}
|
||||
}
|
||||
|
||||
FloatReg readFloatReg(const StaticInst *si, int idx)
|
||||
FloatReg readFloatRegOperand(const StaticInst *si, int idx)
|
||||
{
|
||||
return srcInsts[idx]->readFloatResult();
|
||||
}
|
||||
|
||||
FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
|
||||
FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
|
||||
int width)
|
||||
{
|
||||
return srcInsts[idx]->readIntResult();
|
||||
}
|
||||
|
||||
FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
|
||||
FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
|
||||
{
|
||||
return srcInsts[idx]->readIntResult();
|
||||
}
|
||||
|
@ -182,28 +183,30 @@ class OzoneDynInst : public BaseDynInst<Impl>
|
|||
/** @todo: Make results into arrays so they can handle multiple dest
|
||||
* registers.
|
||||
*/
|
||||
void setIntReg(const StaticInst *si, int idx, uint64_t val)
|
||||
void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
|
||||
{
|
||||
BaseDynInst<Impl>::setIntReg(si, idx, val);
|
||||
}
|
||||
|
||||
void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
|
||||
void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
|
||||
int width)
|
||||
{
|
||||
BaseDynInst<Impl>::setFloatReg(si, idx, val, width);
|
||||
}
|
||||
|
||||
void setFloatReg(const StaticInst *si, int idx, FloatReg val)
|
||||
void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
|
||||
{
|
||||
BaseDynInst<Impl>::setFloatReg(si, idx, val);
|
||||
}
|
||||
|
||||
void setFloatRegBits(const StaticInst *si, int idx,
|
||||
FloatRegBits val, int width)
|
||||
void setFloatRegOperandBits(const StaticInst *si, int idx,
|
||||
FloatRegBits val, int width)
|
||||
{
|
||||
BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
|
||||
}
|
||||
|
||||
void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
|
||||
void setFloatRegOperandBits(const StaticInst *si, int idx,
|
||||
FloatRegBits val)
|
||||
{
|
||||
BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
|
||||
}
|
||||
|
|
|
@ -236,25 +236,6 @@ InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags)
|
|||
*/
|
||||
return fault;
|
||||
}
|
||||
#if 0
|
||||
template <class Impl>
|
||||
template <class T>
|
||||
Fault
|
||||
InorderBackEnd<Impl>::read(MemReqPtr &req, T &data)
|
||||
{
|
||||
#if FULL_SYSTEM && defined(TARGET_ALPHA)
|
||||
if (req->isLocked()) {
|
||||
req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
|
||||
req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
|
||||
}
|
||||
#endif
|
||||
|
||||
Fault error;
|
||||
error = thread->mem->read(req, data);
|
||||
data = LittleEndianGuest::gtoh(data);
|
||||
return error;
|
||||
}
|
||||
#endif
|
||||
|
||||
template <class Impl>
|
||||
template <class T>
|
||||
|
@ -296,61 +277,6 @@ InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
|
|||
*/
|
||||
return fault;
|
||||
}
|
||||
#if 0
|
||||
template <class Impl>
|
||||
template <class T>
|
||||
Fault
|
||||
InorderBackEnd<Impl>::write(MemReqPtr &req, T &data)
|
||||
{
|
||||
#if FULL_SYSTEM && defined(TARGET_ALPHA)
|
||||
ExecContext *xc;
|
||||
|
||||
// If this is a store conditional, act appropriately
|
||||
if (req->isLocked()) {
|
||||
xc = req->xc;
|
||||
|
||||
if (req->isUncacheable()) {
|
||||
// Don't update result register (see stq_c in isa_desc)
|
||||
req->result = 2;
|
||||
xc->setStCondFailures(0);//Needed? [RGD]
|
||||
} else {
|
||||
bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
|
||||
Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
|
||||
req->result = lock_flag;
|
||||
if (!lock_flag ||
|
||||
((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
|
||||
xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
|
||||
xc->setStCondFailures(xc->readStCondFailures() + 1);
|
||||
if (((xc->readStCondFailures()) % 100000) == 0) {
|
||||
std::cerr << "Warning: "
|
||||
<< xc->readStCondFailures()
|
||||
<< " consecutive store conditional failures "
|
||||
<< "on cpu " << req->xc->readCpuId()
|
||||
<< std::endl;
|
||||
}
|
||||
return NoFault;
|
||||
}
|
||||
else xc->setStCondFailures(0);
|
||||
}
|
||||
}
|
||||
|
||||
// Need to clear any locked flags on other proccessors for
|
||||
// this address. Only do this for succsful Store Conditionals
|
||||
// and all other stores (WH64?). Unsuccessful Store
|
||||
// Conditionals would have returned above, and wouldn't fall
|
||||
// through.
|
||||
for (int i = 0; i < cpu->system->execContexts.size(); i++){
|
||||
xc = cpu->system->execContexts[i];
|
||||
if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
|
||||
(req->paddr & ~0xf)) {
|
||||
xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
return thread->mem->write(req, (T)LittleEndianGuest::htog(data));
|
||||
}
|
||||
#endif
|
||||
|
||||
template <class Impl>
|
||||
template <class T>
|
||||
|
|
|
@ -213,60 +213,63 @@ class BaseSimpleCPU : public BaseCPU
|
|||
// storage (which is pretty hard to imagine they would have reason
|
||||
// to do).
|
||||
|
||||
uint64_t readIntReg(const StaticInst *si, int idx)
|
||||
uint64_t readIntRegOperand(const StaticInst *si, int idx)
|
||||
{
|
||||
return thread->readIntReg(si->srcRegIdx(idx));
|
||||
}
|
||||
|
||||
FloatReg readFloatReg(const StaticInst *si, int idx, int width)
|
||||
FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
|
||||
{
|
||||
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
|
||||
return thread->readFloatReg(reg_idx, width);
|
||||
}
|
||||
|
||||
FloatReg readFloatReg(const StaticInst *si, int idx)
|
||||
FloatReg readFloatRegOperand(const StaticInst *si, int idx)
|
||||
{
|
||||
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
|
||||
return thread->readFloatReg(reg_idx);
|
||||
}
|
||||
|
||||
FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
|
||||
FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
|
||||
int width)
|
||||
{
|
||||
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
|
||||
return thread->readFloatRegBits(reg_idx, width);
|
||||
}
|
||||
|
||||
FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
|
||||
FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
|
||||
{
|
||||
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
|
||||
return thread->readFloatRegBits(reg_idx);
|
||||
}
|
||||
|
||||
void setIntReg(const StaticInst *si, int idx, uint64_t val)
|
||||
void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
|
||||
{
|
||||
thread->setIntReg(si->destRegIdx(idx), val);
|
||||
}
|
||||
|
||||
void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
|
||||
void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
|
||||
int width)
|
||||
{
|
||||
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
|
||||
thread->setFloatReg(reg_idx, val, width);
|
||||
}
|
||||
|
||||
void setFloatReg(const StaticInst *si, int idx, FloatReg val)
|
||||
void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
|
||||
{
|
||||
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
|
||||
thread->setFloatReg(reg_idx, val);
|
||||
}
|
||||
|
||||
void setFloatRegBits(const StaticInst *si, int idx,
|
||||
FloatRegBits val, int width)
|
||||
void setFloatRegOperandBits(const StaticInst *si, int idx,
|
||||
FloatRegBits val, int width)
|
||||
{
|
||||
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
|
||||
thread->setFloatRegBits(reg_idx, val, width);
|
||||
}
|
||||
|
||||
void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
|
||||
void setFloatRegOperandBits(const StaticInst *si, int idx,
|
||||
FloatRegBits val)
|
||||
{
|
||||
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
|
||||
thread->setFloatRegBits(reg_idx, val);
|
||||
|
|
|
@ -234,75 +234,6 @@ class SimpleThread : public ThreadState
|
|||
/// Set the status to Halted.
|
||||
void halt();
|
||||
|
||||
/*
|
||||
template <class T>
|
||||
Fault read(RequestPtr &req, T &data)
|
||||
{
|
||||
#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
|
||||
if (req->isLocked()) {
|
||||
req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
|
||||
req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
|
||||
}
|
||||
#endif
|
||||
|
||||
Fault error;
|
||||
error = mem->prot_read(req->paddr, data, req->size);
|
||||
data = LittleEndianGuest::gtoh(data);
|
||||
return error;
|
||||
}
|
||||
|
||||
template <class T>
|
||||
Fault write(RequestPtr &req, T &data)
|
||||
{
|
||||
#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
|
||||
ExecContext *xc;
|
||||
|
||||
// If this is a store conditional, act appropriately
|
||||
if (req->isLocked()) {
|
||||
xc = req->xc;
|
||||
|
||||
if (req->isUncacheable()) {
|
||||
// Don't update result register (see stq_c in isa_desc)
|
||||
req->result = 2;
|
||||
xc->setStCondFailures(0);//Needed? [RGD]
|
||||
} else {
|
||||
bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
|
||||
Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
|
||||
req->result = lock_flag;
|
||||
if (!lock_flag ||
|
||||
((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
|
||||
xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
|
||||
xc->setStCondFailures(xc->readStCondFailures() + 1);
|
||||
if (((xc->readStCondFailures()) % 100000) == 0) {
|
||||
std::cerr << "Warning: "
|
||||
<< xc->readStCondFailures()
|
||||
<< " consecutive store conditional failures "
|
||||
<< "on cpu " << req->xc->readCpuId()
|
||||
<< std::endl;
|
||||
}
|
||||
return NoFault;
|
||||
}
|
||||
else xc->setStCondFailures(0);
|
||||
}
|
||||
}
|
||||
|
||||
// Need to clear any locked flags on other proccessors for
|
||||
// this address. Only do this for succsful Store Conditionals
|
||||
// and all other stores (WH64?). Unsuccessful Store
|
||||
// Conditionals would have returned above, and wouldn't fall
|
||||
// through.
|
||||
for (int i = 0; i < system->execContexts.size(); i++){
|
||||
xc = system->execContexts[i];
|
||||
if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
|
||||
(req->paddr & ~0xf)) {
|
||||
xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
return mem->prot_write(req->paddr, (T)htog(data), req->size);
|
||||
}
|
||||
*/
|
||||
virtual bool misspeculating();
|
||||
|
||||
Fault instRead(RequestPtr &req)
|
||||
|
|
66
src/mem/cache/cache.cc
vendored
66
src/mem/cache/cache.cc
vendored
|
@ -37,7 +37,6 @@
|
|||
*/
|
||||
|
||||
#include "mem/config/cache.hh"
|
||||
#include "mem/config/compression.hh"
|
||||
|
||||
#include "mem/cache/tags/cache_tags.hh"
|
||||
|
||||
|
@ -61,11 +60,6 @@
|
|||
#include "mem/cache/tags/split_lifo.hh"
|
||||
#endif
|
||||
|
||||
#include "base/compression/null_compression.hh"
|
||||
#if defined(USE_LZSS_COMPRESSION)
|
||||
#include "base/compression/lzss_compression.hh"
|
||||
#endif
|
||||
|
||||
#include "mem/cache/miss/miss_queue.hh"
|
||||
#include "mem/cache/miss/blocking_buffer.hh"
|
||||
|
||||
|
@ -79,68 +73,28 @@
|
|||
|
||||
|
||||
#if defined(USE_CACHE_FALRU)
|
||||
template class Cache<CacheTags<FALRU,NullCompression>, BlockingBuffer, SimpleCoherence>;
|
||||
template class Cache<CacheTags<FALRU,NullCompression>, BlockingBuffer, UniCoherence>;
|
||||
template class Cache<CacheTags<FALRU,NullCompression>, MissQueue, SimpleCoherence>;
|
||||
template class Cache<CacheTags<FALRU,NullCompression>, MissQueue, UniCoherence>;
|
||||
#if defined(USE_LZSS_COMPRESSION)
|
||||
template class Cache<CacheTags<FALRU,LZSSCompression>, BlockingBuffer, SimpleCoherence>;
|
||||
template class Cache<CacheTags<FALRU,LZSSCompression>, BlockingBuffer, UniCoherence>;
|
||||
template class Cache<CacheTags<FALRU,LZSSCompression>, MissQueue, SimpleCoherence>;
|
||||
template class Cache<CacheTags<FALRU,LZSSCompression>, MissQueue, UniCoherence>;
|
||||
#endif
|
||||
template class Cache<CacheTags<FALRU>, SimpleCoherence>;
|
||||
template class Cache<CacheTags<FALRU>, UniCoherence>;
|
||||
#endif
|
||||
|
||||
#if defined(USE_CACHE_IIC)
|
||||
template class Cache<CacheTags<IIC,NullCompression>, BlockingBuffer, SimpleCoherence>;
|
||||
template class Cache<CacheTags<IIC,NullCompression>, BlockingBuffer, UniCoherence>;
|
||||
template class Cache<CacheTags<IIC,NullCompression>, MissQueue, SimpleCoherence>;
|
||||
template class Cache<CacheTags<IIC,NullCompression>, MissQueue, UniCoherence>;
|
||||
#if defined(USE_LZSS_COMPRESSION)
|
||||
template class Cache<CacheTags<IIC,LZSSCompression>, BlockingBuffer, SimpleCoherence>;
|
||||
template class Cache<CacheTags<IIC,LZSSCompression>, BlockingBuffer, UniCoherence>;
|
||||
template class Cache<CacheTags<IIC,LZSSCompression>, MissQueue, SimpleCoherence>;
|
||||
template class Cache<CacheTags<IIC,LZSSCompression>, MissQueue, UniCoherence>;
|
||||
#endif
|
||||
template class Cache<CacheTags<IIC>, SimpleCoherence>;
|
||||
template class Cache<CacheTags<IIC>, UniCoherence>;
|
||||
#endif
|
||||
|
||||
#if defined(USE_CACHE_LRU)
|
||||
template class Cache<CacheTags<LRU,NullCompression>, BlockingBuffer, SimpleCoherence>;
|
||||
template class Cache<CacheTags<LRU,NullCompression>, BlockingBuffer, UniCoherence>;
|
||||
template class Cache<CacheTags<LRU,NullCompression>, MissQueue, SimpleCoherence>;
|
||||
template class Cache<CacheTags<LRU,NullCompression>, MissQueue, UniCoherence>;
|
||||
#if defined(USE_LZSS_COMPRESSION)
|
||||
template class Cache<CacheTags<LRU,LZSSCompression>, BlockingBuffer, SimpleCoherence>;
|
||||
template class Cache<CacheTags<LRU,LZSSCompression>, BlockingBuffer, UniCoherence>;
|
||||
template class Cache<CacheTags<LRU,LZSSCompression>, MissQueue, SimpleCoherence>;
|
||||
template class Cache<CacheTags<LRU,LZSSCompression>, MissQueue, UniCoherence>;
|
||||
#endif
|
||||
template class Cache<CacheTags<LRU>, SimpleCoherence>;
|
||||
template class Cache<CacheTags<LRU>, UniCoherence>;
|
||||
#endif
|
||||
|
||||
#if defined(USE_CACHE_SPLIT)
|
||||
template class Cache<CacheTags<Split,NullCompression>, BlockingBuffer, SimpleCoherence>;
|
||||
template class Cache<CacheTags<Split,NullCompression>, BlockingBuffer, UniCoherence>;
|
||||
template class Cache<CacheTags<Split,NullCompression>, MissQueue, SimpleCoherence>;
|
||||
template class Cache<CacheTags<Split,NullCompression>, MissQueue, UniCoherence>;
|
||||
#if defined(USE_LZSS_COMPRESSION)
|
||||
template class Cache<CacheTags<Split,LZSSCompression>, BlockingBuffer, SimpleCoherence>;
|
||||
template class Cache<CacheTags<Split,LZSSCompression>, BlockingBuffer, UniCoherence>;
|
||||
template class Cache<CacheTags<Split,LZSSCompression>, MissQueue, SimpleCoherence>;
|
||||
template class Cache<CacheTags<Split,LZSSCompression>, MissQueue, UniCoherence>;
|
||||
#endif
|
||||
template class Cache<CacheTags<Split>, SimpleCoherence>;
|
||||
template class Cache<CacheTags<Split>, UniCoherence>;
|
||||
#endif
|
||||
|
||||
#if defined(USE_CACHE_SPLIT_LIFO)
|
||||
template class Cache<CacheTags<SplitLIFO,NullCompression>, BlockingBuffer, SimpleCoherence>;
|
||||
template class Cache<CacheTags<SplitLIFO,NullCompression>, BlockingBuffer, UniCoherence>;
|
||||
template class Cache<CacheTags<SplitLIFO,NullCompression>, MissQueue, SimpleCoherence>;
|
||||
template class Cache<CacheTags<SplitLIFO,NullCompression>, MissQueue, UniCoherence>;
|
||||
#if defined(USE_LZSS_COMPRESSION)
|
||||
template class Cache<CacheTags<SplitLIFO,LZSSCompression>, BlockingBuffer, SimpleCoherence>;
|
||||
template class Cache<CacheTags<SplitLIFO,LZSSCompression>, BlockingBuffer, UniCoherence>;
|
||||
template class Cache<CacheTags<SplitLIFO,LZSSCompression>, MissQueue, SimpleCoherence>;
|
||||
template class Cache<CacheTags<SplitLIFO,LZSSCompression>, MissQueue, UniCoherence>;
|
||||
#endif
|
||||
template class Cache<CacheTags<SplitLIFO>, SimpleCoherence>;
|
||||
template class Cache<CacheTags<SplitLIFO>, UniCoherence>;
|
||||
#endif
|
||||
|
||||
#endif //DOXYGEN_SHOULD_SKIP_THIS
|
||||
|
|
15
src/mem/cache/cache.hh
vendored
15
src/mem/cache/cache.hh
vendored
|
@ -42,6 +42,7 @@
|
|||
#include "cpu/smt.hh" // SMT_MAX_THREADS
|
||||
|
||||
#include "mem/cache/base_cache.hh"
|
||||
#include "mem/cache/miss/miss_buffer.hh"
|
||||
#include "mem/cache/prefetch/prefetcher.hh"
|
||||
|
||||
//Forward decleration
|
||||
|
@ -55,7 +56,7 @@ class MSHR;
|
|||
* @sa MissQueue. Coherence handles all coherence policy details @sa
|
||||
* UniCoherence, SimpleMultiCoherence.
|
||||
*/
|
||||
template <class TagStore, class Buffering, class Coherence>
|
||||
template <class TagStore, class Coherence>
|
||||
class Cache : public BaseCache
|
||||
{
|
||||
public:
|
||||
|
@ -68,12 +69,12 @@ class Cache : public BaseCache
|
|||
/** Tag and data Storage */
|
||||
TagStore *tags;
|
||||
/** Miss and Writeback handler */
|
||||
Buffering *missQueue;
|
||||
MissBuffer *missQueue;
|
||||
/** Coherence protocol. */
|
||||
Coherence *coherence;
|
||||
|
||||
/** Prefetcher */
|
||||
Prefetcher<TagStore, Buffering> *prefetcher;
|
||||
Prefetcher<TagStore> *prefetcher;
|
||||
|
||||
/**
|
||||
* The clock ratio of the outgoing bus.
|
||||
|
@ -105,16 +106,16 @@ class Cache : public BaseCache
|
|||
{
|
||||
public:
|
||||
TagStore *tags;
|
||||
Buffering *missQueue;
|
||||
MissBuffer *missQueue;
|
||||
Coherence *coherence;
|
||||
BaseCache::Params baseParams;
|
||||
Prefetcher<TagStore, Buffering> *prefetcher;
|
||||
Prefetcher<TagStore> *prefetcher;
|
||||
bool prefetchAccess;
|
||||
int hitLatency;
|
||||
|
||||
Params(TagStore *_tags, Buffering *mq, Coherence *coh,
|
||||
Params(TagStore *_tags, MissBuffer *mq, Coherence *coh,
|
||||
BaseCache::Params params,
|
||||
Prefetcher<TagStore, Buffering> *_prefetcher,
|
||||
Prefetcher<TagStore> *_prefetcher,
|
||||
bool prefetch_access, int hit_latency)
|
||||
: tags(_tags), missQueue(mq), coherence(coh),
|
||||
baseParams(params),
|
||||
|
|
148
src/mem/cache/cache_builder.cc
vendored
148
src/mem/cache/cache_builder.cc
vendored
|
@ -37,7 +37,6 @@
|
|||
|
||||
// Must be included first to determine which caches we want
|
||||
#include "mem/config/cache.hh"
|
||||
#include "mem/config/compression.hh"
|
||||
#include "mem/config/prefetch.hh"
|
||||
|
||||
#include "mem/cache/base_cache.hh"
|
||||
|
@ -69,9 +68,7 @@
|
|||
|
||||
// Compression Templates
|
||||
#include "base/compression/null_compression.hh"
|
||||
#if defined(USE_LZSS_COMPRESSION)
|
||||
#include "base/compression/lzss_compression.hh"
|
||||
#endif
|
||||
|
||||
// CacheTags Templates
|
||||
#include "mem/cache/tags/cache_tags.hh"
|
||||
|
@ -211,156 +208,127 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(BaseCache)
|
|||
END_INIT_SIM_OBJECT_PARAMS(BaseCache)
|
||||
|
||||
|
||||
#define BUILD_CACHE(t, comp, b, c) do { \
|
||||
Prefetcher<CacheTags<t, comp>, b> *pf; \
|
||||
#define BUILD_CACHE(t, c) do { \
|
||||
Prefetcher<CacheTags<t> > *pf; \
|
||||
if (pf_policy == "tagged") { \
|
||||
BUILD_TAGGED_PREFETCHER(t, comp, b); \
|
||||
BUILD_TAGGED_PREFETCHER(t); \
|
||||
} \
|
||||
else if (pf_policy == "stride") { \
|
||||
BUILD_STRIDED_PREFETCHER(t, comp, b); \
|
||||
BUILD_STRIDED_PREFETCHER(t); \
|
||||
} \
|
||||
else if (pf_policy == "ghb") { \
|
||||
BUILD_GHB_PREFETCHER(t, comp, b); \
|
||||
BUILD_GHB_PREFETCHER(t); \
|
||||
} \
|
||||
else { \
|
||||
BUILD_NULL_PREFETCHER(t, comp, b); \
|
||||
BUILD_NULL_PREFETCHER(t); \
|
||||
} \
|
||||
Cache<CacheTags<t, comp>, b, c>::Params params(tagStore, mq, coh, \
|
||||
Cache<CacheTags<t>, c>::Params params(tagStore, mq, coh, \
|
||||
base_params, \
|
||||
/*in_bus, out_bus,*/ pf, \
|
||||
pf, \
|
||||
prefetch_access, hit_latency); \
|
||||
Cache<CacheTags<t, comp>, b, c> *retval = \
|
||||
new Cache<CacheTags<t, comp>, b, c>(getInstanceName(), /*hier,*/ \
|
||||
params); \
|
||||
/* if (in_bus == NULL) { \
|
||||
retval->setSlaveInterface(new MemoryInterface<Cache<CacheTags<t, comp>, b, c> >(getInstanceName(), hier, retval, mem_trace)); \
|
||||
} else { \
|
||||
retval->setSlaveInterface(new SlaveInterface<Cache<CacheTags<t, comp>, b, c>, Bus>(getInstanceName(), hier, retval, in_bus, mem_trace)); \
|
||||
} \
|
||||
retval->setMasterInterface(new MasterInterface<Cache<CacheTags<t, comp>, b, c>, Bus>(getInstanceName(), hier, retval, out_bus)); \
|
||||
out_bus->rangeChange(); \
|
||||
return retval; \
|
||||
*/return retval; \
|
||||
Cache<CacheTags<t>, c> *retval = \
|
||||
new Cache<CacheTags<t>, c>(getInstanceName(), params); \
|
||||
return retval; \
|
||||
} while (0)
|
||||
|
||||
#define BUILD_CACHE_PANIC(x) do { \
|
||||
panic("%s not compiled into M5", x); \
|
||||
} while (0)
|
||||
|
||||
#if defined(USE_LZSS_COMPRESSION)
|
||||
#define BUILD_COMPRESSED_CACHE(TAGS, tags, b, c) do { \
|
||||
if (compressed_bus || store_compressed){ \
|
||||
CacheTags<TAGS, LZSSCompression> *tagStore = \
|
||||
new CacheTags<TAGS, LZSSCompression>(tags, \
|
||||
compression_latency, \
|
||||
true, store_compressed, \
|
||||
adaptive_compression, \
|
||||
prefetch_miss); \
|
||||
BUILD_CACHE(TAGS, LZSSCompression, b, c); \
|
||||
#define BUILD_COMPRESSED_CACHE(TAGS, tags, c) \
|
||||
do { \
|
||||
CompressionAlgorithm *compAlg; \
|
||||
if (compressed_bus || store_compressed) { \
|
||||
compAlg = new LZSSCompression(); \
|
||||
} else { \
|
||||
CacheTags<TAGS, NullCompression> *tagStore = \
|
||||
new CacheTags<TAGS, NullCompression>(tags, \
|
||||
compression_latency, \
|
||||
true, store_compressed, \
|
||||
adaptive_compression, \
|
||||
prefetch_miss); \
|
||||
BUILD_CACHE(TAGS, NullCompression, b, c); \
|
||||
compAlg = new NullCompression(); \
|
||||
} \
|
||||
CacheTags<TAGS> *tagStore = \
|
||||
new CacheTags<TAGS>(tags, compression_latency, true, \
|
||||
store_compressed, adaptive_compression, \
|
||||
compressed_bus, \
|
||||
compAlg, prefetch_miss); \
|
||||
BUILD_CACHE(TAGS, c); \
|
||||
} while (0)
|
||||
#else
|
||||
#define BUILD_COMPRESSED_CACHE(TAGS, tags, b, c) do { \
|
||||
if (compressed_bus || store_compressed){ \
|
||||
BUILD_CACHE_PANIC("compressed caches"); \
|
||||
} else { \
|
||||
CacheTags<TAGS, NullCompression> *tagStore = \
|
||||
new CacheTags<TAGS, NullCompression>(tags, \
|
||||
compression_latency, \
|
||||
true, store_compressed, \
|
||||
adaptive_compression \
|
||||
prefetch_miss); \
|
||||
BUILD_CACHE(TAGS, NullCompression, b, c); \
|
||||
} \
|
||||
} while (0)
|
||||
#endif
|
||||
|
||||
#if defined(USE_CACHE_FALRU)
|
||||
#define BUILD_FALRU_CACHE(b,c) do { \
|
||||
#define BUILD_FALRU_CACHE(c) do { \
|
||||
FALRU *tags = new FALRU(block_size, size, latency); \
|
||||
BUILD_COMPRESSED_CACHE(FALRU, tags, b, c); \
|
||||
BUILD_COMPRESSED_CACHE(FALRU, tags, c); \
|
||||
} while (0)
|
||||
#else
|
||||
#define BUILD_FALRU_CACHE(b, c) BUILD_CACHE_PANIC("falru cache")
|
||||
#define BUILD_FALRU_CACHE(c) BUILD_CACHE_PANIC("falru cache")
|
||||
#endif
|
||||
|
||||
#if defined(USE_CACHE_LRU)
|
||||
#define BUILD_LRU_CACHE(b, c) do { \
|
||||
#define BUILD_LRU_CACHE(c) do { \
|
||||
LRU *tags = new LRU(numSets, block_size, assoc, latency); \
|
||||
BUILD_COMPRESSED_CACHE(LRU, tags, b, c); \
|
||||
BUILD_COMPRESSED_CACHE(LRU, tags, c); \
|
||||
} while (0)
|
||||
#else
|
||||
#define BUILD_LRU_CACHE(b, c) BUILD_CACHE_PANIC("lru cache")
|
||||
#define BUILD_LRU_CACHE(c) BUILD_CACHE_PANIC("lru cache")
|
||||
#endif
|
||||
|
||||
#if defined(USE_CACHE_SPLIT)
|
||||
#define BUILD_SPLIT_CACHE(b, c) do { \
|
||||
#define BUILD_SPLIT_CACHE(c) do { \
|
||||
Split *tags = new Split(numSets, block_size, assoc, split_size, lifo, \
|
||||
two_queue, latency); \
|
||||
BUILD_COMPRESSED_CACHE(Split, tags, b, c); \
|
||||
BUILD_COMPRESSED_CACHE(Split, tags, c); \
|
||||
} while (0)
|
||||
#else
|
||||
#define BUILD_SPLIT_CACHE(b, c) BUILD_CACHE_PANIC("split cache")
|
||||
#define BUILD_SPLIT_CACHE(c) BUILD_CACHE_PANIC("split cache")
|
||||
#endif
|
||||
|
||||
#if defined(USE_CACHE_SPLIT_LIFO)
|
||||
#define BUILD_SPLIT_LIFO_CACHE(b, c) do { \
|
||||
#define BUILD_SPLIT_LIFO_CACHE(c) do { \
|
||||
SplitLIFO *tags = new SplitLIFO(block_size, size, assoc, \
|
||||
latency, two_queue, -1); \
|
||||
BUILD_COMPRESSED_CACHE(SplitLIFO, tags, b, c); \
|
||||
BUILD_COMPRESSED_CACHE(SplitLIFO, tags, c); \
|
||||
} while (0)
|
||||
#else
|
||||
#define BUILD_SPLIT_LIFO_CACHE(b, c) BUILD_CACHE_PANIC("lifo cache")
|
||||
#define BUILD_SPLIT_LIFO_CACHE(c) BUILD_CACHE_PANIC("lifo cache")
|
||||
#endif
|
||||
|
||||
#if defined(USE_CACHE_IIC)
|
||||
#define BUILD_IIC_CACHE(b ,c) do { \
|
||||
#define BUILD_IIC_CACHE(c) do { \
|
||||
IIC *tags = new IIC(iic_params); \
|
||||
BUILD_COMPRESSED_CACHE(IIC, tags, b, c); \
|
||||
BUILD_COMPRESSED_CACHE(IIC, tags, c); \
|
||||
} while (0)
|
||||
#else
|
||||
#define BUILD_IIC_CACHE(b, c) BUILD_CACHE_PANIC("iic")
|
||||
#define BUILD_IIC_CACHE(c) BUILD_CACHE_PANIC("iic")
|
||||
#endif
|
||||
|
||||
#define BUILD_CACHES(b, c) do { \
|
||||
#define BUILD_CACHES(c) do { \
|
||||
if (repl == NULL) { \
|
||||
if (numSets == 1) { \
|
||||
BUILD_FALRU_CACHE(b, c); \
|
||||
BUILD_FALRU_CACHE(c); \
|
||||
} else { \
|
||||
if (split == true) { \
|
||||
BUILD_SPLIT_CACHE(b, c); \
|
||||
BUILD_SPLIT_CACHE(c); \
|
||||
} else if (lifo == true) { \
|
||||
BUILD_SPLIT_LIFO_CACHE(b, c); \
|
||||
BUILD_SPLIT_LIFO_CACHE(c); \
|
||||
} else { \
|
||||
BUILD_LRU_CACHE(b, c); \
|
||||
BUILD_LRU_CACHE(c); \
|
||||
} \
|
||||
} \
|
||||
} else { \
|
||||
BUILD_IIC_CACHE(b, c); \
|
||||
BUILD_IIC_CACHE(c); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define BUILD_COHERENCE(b) do { \
|
||||
if (protocol == NULL) { \
|
||||
UniCoherence *coh = new UniCoherence(); \
|
||||
BUILD_CACHES(b, UniCoherence); \
|
||||
BUILD_CACHES(UniCoherence); \
|
||||
} else { \
|
||||
SimpleCoherence *coh = new SimpleCoherence(protocol); \
|
||||
BUILD_CACHES(b, SimpleCoherence); \
|
||||
BUILD_CACHES(SimpleCoherence); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#if defined(USE_TAGGED)
|
||||
#define BUILD_TAGGED_PREFETCHER(t, comp, b) pf = new \
|
||||
TaggedPrefetcher<CacheTags<t, comp>, b>(prefetcher_size, \
|
||||
#define BUILD_TAGGED_PREFETCHER(t) pf = new \
|
||||
TaggedPrefetcher<CacheTags<t> >(prefetcher_size, \
|
||||
!prefetch_past_page, \
|
||||
prefetch_serial_squash, \
|
||||
prefetch_cache_check_push, \
|
||||
|
@ -368,12 +336,12 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
|
|||
prefetch_latency, \
|
||||
prefetch_degree)
|
||||
#else
|
||||
#define BUILD_TAGGED_PREFETCHER(t, comp, b) BUILD_CACHE_PANIC("Tagged Prefetcher")
|
||||
#define BUILD_TAGGED_PREFETCHER(t) BUILD_CACHE_PANIC("Tagged Prefetcher")
|
||||
#endif
|
||||
|
||||
#if defined(USE_STRIDED)
|
||||
#define BUILD_STRIDED_PREFETCHER(t, comp, b) pf = new \
|
||||
StridePrefetcher<CacheTags<t, comp>, b>(prefetcher_size, \
|
||||
#define BUILD_STRIDED_PREFETCHER(t) pf = new \
|
||||
StridePrefetcher<CacheTags<t> >(prefetcher_size, \
|
||||
!prefetch_past_page, \
|
||||
prefetch_serial_squash, \
|
||||
prefetch_cache_check_push, \
|
||||
|
@ -382,12 +350,12 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
|
|||
prefetch_degree, \
|
||||
prefetch_use_cpu_id)
|
||||
#else
|
||||
#define BUILD_STRIDED_PREFETCHER(t, comp, b) BUILD_CACHE_PANIC("Stride Prefetcher")
|
||||
#define BUILD_STRIDED_PREFETCHER(t) BUILD_CACHE_PANIC("Stride Prefetcher")
|
||||
#endif
|
||||
|
||||
#if defined(USE_GHB)
|
||||
#define BUILD_GHB_PREFETCHER(t, comp, b) pf = new \
|
||||
GHBPrefetcher<CacheTags<t, comp>, b>(prefetcher_size, \
|
||||
#define BUILD_GHB_PREFETCHER(t) pf = new \
|
||||
GHBPrefetcher<CacheTags<t> >(prefetcher_size, \
|
||||
!prefetch_past_page, \
|
||||
prefetch_serial_squash, \
|
||||
prefetch_cache_check_push, \
|
||||
|
@ -396,12 +364,12 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
|
|||
prefetch_degree, \
|
||||
prefetch_use_cpu_id)
|
||||
#else
|
||||
#define BUILD_GHB_PREFETCHER(t, comp, b) BUILD_CACHE_PANIC("GHB Prefetcher")
|
||||
#define BUILD_GHB_PREFETCHER(t) BUILD_CACHE_PANIC("GHB Prefetcher")
|
||||
#endif
|
||||
|
||||
#if defined(USE_TAGGED)
|
||||
#define BUILD_NULL_PREFETCHER(t, comp, b) pf = new \
|
||||
TaggedPrefetcher<CacheTags<t, comp>, b>(prefetcher_size, \
|
||||
#define BUILD_NULL_PREFETCHER(t) pf = new \
|
||||
TaggedPrefetcher<CacheTags<t> >(prefetcher_size, \
|
||||
!prefetch_past_page, \
|
||||
prefetch_serial_squash, \
|
||||
prefetch_cache_check_push, \
|
||||
|
@ -409,7 +377,7 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
|
|||
prefetch_latency, \
|
||||
prefetch_degree)
|
||||
#else
|
||||
#define BUILD_NULL_PREFETCHER(t, comp, b) BUILD_CACHE_PANIC("NULL Prefetcher (uses Tagged)")
|
||||
#define BUILD_NULL_PREFETCHER(t) BUILD_CACHE_PANIC("NULL Prefetcher (uses Tagged)")
|
||||
#endif
|
||||
|
||||
CREATE_SIM_OBJECT(BaseCache)
|
||||
|
|
70
src/mem/cache/cache_impl.hh
vendored
70
src/mem/cache/cache_impl.hh
vendored
|
@ -55,9 +55,9 @@
|
|||
|
||||
bool SIGNAL_NACK_HACK;
|
||||
|
||||
template<class TagStore, class Buffering, class Coherence>
|
||||
template<class TagStore, class Coherence>
|
||||
bool
|
||||
Cache<TagStore,Buffering,Coherence>::
|
||||
Cache<TagStore,Coherence>::
|
||||
doTimingAccess(PacketPtr pkt, CachePort *cachePort, bool isCpuSide)
|
||||
{
|
||||
if (isCpuSide)
|
||||
|
@ -81,9 +81,9 @@ doTimingAccess(PacketPtr pkt, CachePort *cachePort, bool isCpuSide)
|
|||
return true;
|
||||
}
|
||||
|
||||
template<class TagStore, class Buffering, class Coherence>
|
||||
template<class TagStore, class Coherence>
|
||||
Tick
|
||||
Cache<TagStore,Buffering,Coherence>::
|
||||
Cache<TagStore,Coherence>::
|
||||
doAtomicAccess(PacketPtr pkt, bool isCpuSide)
|
||||
{
|
||||
if (isCpuSide)
|
||||
|
@ -103,9 +103,9 @@ doAtomicAccess(PacketPtr pkt, bool isCpuSide)
|
|||
return hitLatency;
|
||||
}
|
||||
|
||||
template<class TagStore, class Buffering, class Coherence>
|
||||
template<class TagStore, class Coherence>
|
||||
void
|
||||
Cache<TagStore,Buffering,Coherence>::
|
||||
Cache<TagStore,Coherence>::
|
||||
doFunctionalAccess(PacketPtr pkt, bool isCpuSide)
|
||||
{
|
||||
if (isCpuSide)
|
||||
|
@ -123,19 +123,19 @@ doFunctionalAccess(PacketPtr pkt, bool isCpuSide)
|
|||
}
|
||||
}
|
||||
|
||||
template<class TagStore, class Buffering, class Coherence>
|
||||
template<class TagStore, class Coherence>
|
||||
void
|
||||
Cache<TagStore,Buffering,Coherence>::
|
||||
Cache<TagStore,Coherence>::
|
||||
recvStatusChange(Port::Status status, bool isCpuSide)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
|
||||
template<class TagStore, class Buffering, class Coherence>
|
||||
Cache<TagStore,Buffering,Coherence>::
|
||||
template<class TagStore, class Coherence>
|
||||
Cache<TagStore,Coherence>::
|
||||
Cache(const std::string &_name,
|
||||
Cache<TagStore,Buffering,Coherence>::Params ¶ms)
|
||||
Cache<TagStore,Coherence>::Params ¶ms)
|
||||
: BaseCache(_name, params.baseParams),
|
||||
prefetchAccess(params.prefetchAccess),
|
||||
tags(params.tags), missQueue(params.missQueue),
|
||||
|
@ -154,9 +154,9 @@ Cache(const std::string &_name,
|
|||
invalidatePkt = new Packet(invalidateReq, Packet::InvalidateReq, 0);
|
||||
}
|
||||
|
||||
template<class TagStore, class Buffering, class Coherence>
|
||||
template<class TagStore, class Coherence>
|
||||
void
|
||||
Cache<TagStore,Buffering,Coherence>::regStats()
|
||||
Cache<TagStore,Coherence>::regStats()
|
||||
{
|
||||
BaseCache::regStats();
|
||||
tags->regStats(name());
|
||||
|
@ -165,9 +165,9 @@ Cache<TagStore,Buffering,Coherence>::regStats()
|
|||
prefetcher->regStats(name());
|
||||
}
|
||||
|
||||
template<class TagStore, class Buffering, class Coherence>
|
||||
template<class TagStore, class Coherence>
|
||||
bool
|
||||
Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
|
||||
Cache<TagStore,Coherence>::access(PacketPtr &pkt)
|
||||
{
|
||||
//@todo Add back in MemDebug Calls
|
||||
// MemDebug::cacheAccess(pkt);
|
||||
|
@ -253,9 +253,9 @@ Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
|
|||
}
|
||||
|
||||
|
||||
template<class TagStore, class Buffering, class Coherence>
|
||||
template<class TagStore, class Coherence>
|
||||
PacketPtr
|
||||
Cache<TagStore,Buffering,Coherence>::getPacket()
|
||||
Cache<TagStore,Coherence>::getPacket()
|
||||
{
|
||||
assert(missQueue->havePending());
|
||||
PacketPtr pkt = missQueue->getPacket();
|
||||
|
@ -276,9 +276,9 @@ Cache<TagStore,Buffering,Coherence>::getPacket()
|
|||
return pkt;
|
||||
}
|
||||
|
||||
template<class TagStore, class Buffering, class Coherence>
|
||||
template<class TagStore, class Coherence>
|
||||
void
|
||||
Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr,
|
||||
Cache<TagStore,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr,
|
||||
bool success)
|
||||
{
|
||||
if (success && !(SIGNAL_NACK_HACK)) {
|
||||
|
@ -319,9 +319,9 @@ Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr,
|
|||
}
|
||||
}
|
||||
|
||||
template<class TagStore, class Buffering, class Coherence>
|
||||
template<class TagStore, class Coherence>
|
||||
void
|
||||
Cache<TagStore,Buffering,Coherence>::handleResponse(PacketPtr &pkt)
|
||||
Cache<TagStore,Coherence>::handleResponse(PacketPtr &pkt)
|
||||
{
|
||||
BlkType *blk = NULL;
|
||||
if (pkt->senderState) {
|
||||
|
@ -363,16 +363,16 @@ Cache<TagStore,Buffering,Coherence>::handleResponse(PacketPtr &pkt)
|
|||
}
|
||||
}
|
||||
|
||||
template<class TagStore, class Buffering, class Coherence>
|
||||
template<class TagStore, class Coherence>
|
||||
PacketPtr
|
||||
Cache<TagStore,Buffering,Coherence>::getCoherencePacket()
|
||||
Cache<TagStore,Coherence>::getCoherencePacket()
|
||||
{
|
||||
return coherence->getPacket();
|
||||
}
|
||||
|
||||
template<class TagStore, class Buffering, class Coherence>
|
||||
template<class TagStore, class Coherence>
|
||||
void
|
||||
Cache<TagStore,Buffering,Coherence>::sendCoherenceResult(PacketPtr &pkt,
|
||||
Cache<TagStore,Coherence>::sendCoherenceResult(PacketPtr &pkt,
|
||||
MSHR *cshr,
|
||||
bool success)
|
||||
{
|
||||
|
@ -380,9 +380,9 @@ Cache<TagStore,Buffering,Coherence>::sendCoherenceResult(PacketPtr &pkt,
|
|||
}
|
||||
|
||||
|
||||
template<class TagStore, class Buffering, class Coherence>
|
||||
template<class TagStore, class Coherence>
|
||||
void
|
||||
Cache<TagStore,Buffering,Coherence>::snoop(PacketPtr &pkt)
|
||||
Cache<TagStore,Coherence>::snoop(PacketPtr &pkt)
|
||||
{
|
||||
if (pkt->req->isUncacheable()) {
|
||||
//Can't get a hit on an uncacheable address
|
||||
|
@ -514,9 +514,9 @@ Cache<TagStore,Buffering,Coherence>::snoop(PacketPtr &pkt)
|
|||
tags->handleSnoop(blk, new_state);
|
||||
}
|
||||
|
||||
template<class TagStore, class Buffering, class Coherence>
|
||||
template<class TagStore, class Coherence>
|
||||
void
|
||||
Cache<TagStore,Buffering,Coherence>::snoopResponse(PacketPtr &pkt)
|
||||
Cache<TagStore,Coherence>::snoopResponse(PacketPtr &pkt)
|
||||
{
|
||||
//Need to handle the response, if NACKED
|
||||
if (pkt->flags & NACKED_LINE) {
|
||||
|
@ -533,9 +533,9 @@ Cache<TagStore,Buffering,Coherence>::snoopResponse(PacketPtr &pkt)
|
|||
}
|
||||
}
|
||||
|
||||
template<class TagStore, class Buffering, class Coherence>
|
||||
template<class TagStore, class Coherence>
|
||||
void
|
||||
Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr)
|
||||
Cache<TagStore,Coherence>::invalidateBlk(Addr addr)
|
||||
{
|
||||
tags->invalidateBlk(addr);
|
||||
}
|
||||
|
@ -544,9 +544,9 @@ Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr)
|
|||
/**
|
||||
* @todo Fix to not assume write allocate
|
||||
*/
|
||||
template<class TagStore, class Buffering, class Coherence>
|
||||
template<class TagStore, class Coherence>
|
||||
Tick
|
||||
Cache<TagStore,Buffering,Coherence>::probe(PacketPtr &pkt, bool update,
|
||||
Cache<TagStore,Coherence>::probe(PacketPtr &pkt, bool update,
|
||||
CachePort* otherSidePort)
|
||||
{
|
||||
// MemDebug::cacheProbe(pkt);
|
||||
|
@ -694,9 +694,9 @@ return 0;
|
|||
return 0;
|
||||
}
|
||||
|
||||
template<class TagStore, class Buffering, class Coherence>
|
||||
template<class TagStore, class Coherence>
|
||||
Tick
|
||||
Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt)
|
||||
Cache<TagStore,Coherence>::snoopProbe(PacketPtr &pkt)
|
||||
{
|
||||
//Send a atomic (false) invalidate up if the protocol calls for it
|
||||
if (coherence->propogateInvalidate(pkt, false)) {
|
||||
|
|
41
src/mem/cache/miss/blocking_buffer.cc
vendored
41
src/mem/cache/miss/blocking_buffer.cc
vendored
|
@ -33,11 +33,9 @@
|
|||
* Definitions of a simple buffer for a blocking cache.
|
||||
*/
|
||||
|
||||
#include "cpu/smt.hh" //for maxThreadsPerCPU
|
||||
#include "mem/cache/base_cache.hh"
|
||||
#include "mem/cache/miss/blocking_buffer.hh"
|
||||
#include "mem/cache/prefetch/base_prefetcher.hh"
|
||||
#include "sim/eventq.hh" // for Event declaration.
|
||||
#include "mem/request.hh"
|
||||
|
||||
/**
|
||||
|
@ -46,27 +44,10 @@
|
|||
void
|
||||
BlockingBuffer::regStats(const std::string &name)
|
||||
{
|
||||
using namespace Stats;
|
||||
writebacks
|
||||
.init(maxThreadsPerCPU)
|
||||
.name(name + ".writebacks")
|
||||
.desc("number of writebacks")
|
||||
.flags(total)
|
||||
;
|
||||
MissBuffer::regStats(name);
|
||||
}
|
||||
|
||||
void
|
||||
BlockingBuffer::setCache(BaseCache *_cache)
|
||||
{
|
||||
cache = _cache;
|
||||
blkSize = cache->getBlockSize();
|
||||
}
|
||||
|
||||
void
|
||||
BlockingBuffer::setPrefetcher(BasePrefetcher *_prefetcher)
|
||||
{
|
||||
prefetcher = _prefetcher;
|
||||
}
|
||||
void
|
||||
BlockingBuffer::handleMiss(PacketPtr &pkt, int blk_size, Tick time)
|
||||
{
|
||||
|
@ -241,3 +222,23 @@ BlockingBuffer::doWriteback(PacketPtr &pkt)
|
|||
cache->setBlocked(Blocked_NoWBBuffers);
|
||||
cache->setMasterRequest(Request_WB, curTick);
|
||||
}
|
||||
|
||||
|
||||
MSHR *
|
||||
BlockingBuffer::findMSHR(Addr addr)
|
||||
{
|
||||
if (miss.addr == addr && miss.pkt)
|
||||
return &miss;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
|
||||
bool
|
||||
BlockingBuffer::findWrites(Addr addr, std::vector<MSHR*>& writes)
|
||||
{
|
||||
if (wb.addr == addr && wb.pkt) {
|
||||
writes.push_back(&wb);
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
|
61
src/mem/cache/miss/blocking_buffer.hh
vendored
61
src/mem/cache/miss/blocking_buffer.hh
vendored
|
@ -38,16 +38,14 @@
|
|||
|
||||
#include <vector>
|
||||
|
||||
#include "base/misc.hh" // for fatal()
|
||||
#include "mem/cache/miss/miss_buffer.hh"
|
||||
#include "mem/cache/miss/mshr.hh"
|
||||
#include "base/statistics.hh"
|
||||
|
||||
class BaseCache;
|
||||
class BasePrefetcher;
|
||||
|
||||
/**
|
||||
* Miss and writeback storage for a blocking cache.
|
||||
*/
|
||||
class BlockingBuffer
|
||||
class BlockingBuffer : public MissBuffer
|
||||
{
|
||||
protected:
|
||||
/** Miss storage. */
|
||||
|
@ -55,38 +53,13 @@ protected:
|
|||
/** WB storage. */
|
||||
MSHR wb;
|
||||
|
||||
//Params
|
||||
|
||||
/** Allocate on write misses. */
|
||||
const bool writeAllocate;
|
||||
|
||||
/** Pointer to the parent cache. */
|
||||
BaseCache* cache;
|
||||
|
||||
BasePrefetcher* prefetcher;
|
||||
|
||||
/** Block size of the parent cache. */
|
||||
int blkSize;
|
||||
|
||||
// Statistics
|
||||
/**
|
||||
* @addtogroup CacheStatistics
|
||||
* @{
|
||||
*/
|
||||
/** Number of blocks written back per thread. */
|
||||
Stats::Vector<> writebacks;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
public:
|
||||
/**
|
||||
* Builds and initializes this buffer.
|
||||
* @param write_allocate If true, treat write misses the same as reads.
|
||||
*/
|
||||
BlockingBuffer(bool write_allocate)
|
||||
: writeAllocate(write_allocate)
|
||||
: MissBuffer(write_allocate)
|
||||
{
|
||||
}
|
||||
|
||||
|
@ -96,14 +69,6 @@ public:
|
|||
*/
|
||||
void regStats(const std::string &name);
|
||||
|
||||
/**
|
||||
* Called by the parent cache to set the back pointer.
|
||||
* @param _cache A pointer to the parent cache.
|
||||
*/
|
||||
void setCache(BaseCache *_cache);
|
||||
|
||||
void setPrefetcher(BasePrefetcher *_prefetcher);
|
||||
|
||||
/**
|
||||
* Handle a cache miss properly. Requests the bus and marks the cache as
|
||||
* blocked.
|
||||
|
@ -183,12 +148,7 @@ public:
|
|||
* @param asid The address space id.
|
||||
* @return A pointer to miss if it matches.
|
||||
*/
|
||||
MSHR* findMSHR(Addr addr)
|
||||
{
|
||||
if (miss.addr == addr && miss.pkt)
|
||||
return &miss;
|
||||
return NULL;
|
||||
}
|
||||
MSHR* findMSHR(Addr addr);
|
||||
|
||||
/**
|
||||
* Searches for the supplied address in the write buffer.
|
||||
|
@ -197,16 +157,7 @@ public:
|
|||
* @param writes List of pointers to the matching writes.
|
||||
* @return True if there is a matching write.
|
||||
*/
|
||||
bool findWrites(Addr addr, std::vector<MSHR*>& writes)
|
||||
{
|
||||
if (wb.addr == addr && wb.pkt) {
|
||||
writes.push_back(&wb);
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
bool findWrites(Addr addr, std::vector<MSHR*>& writes);
|
||||
|
||||
/**
|
||||
* Perform a writeback of dirty data to the given address.
|
||||
|
|
62
src/mem/cache/miss/miss_buffer.cc
vendored
Normal file
62
src/mem/cache/miss/miss_buffer.cc
vendored
Normal file
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
* Copyright (c) 2003-2006 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Erik Hallnor
|
||||
*/
|
||||
|
||||
#include "cpu/smt.hh" //for maxThreadsPerCPU
|
||||
#include "mem/cache/base_cache.hh"
|
||||
#include "mem/cache/miss/miss_buffer.hh"
|
||||
#include "mem/cache/prefetch/base_prefetcher.hh"
|
||||
|
||||
/**
|
||||
* @todo Move writebacks into shared BaseBuffer class.
|
||||
*/
|
||||
void
|
||||
MissBuffer::regStats(const std::string &name)
|
||||
{
|
||||
using namespace Stats;
|
||||
writebacks
|
||||
.init(maxThreadsPerCPU)
|
||||
.name(name + ".writebacks")
|
||||
.desc("number of writebacks")
|
||||
.flags(total)
|
||||
;
|
||||
}
|
||||
|
||||
void
|
||||
MissBuffer::setCache(BaseCache *_cache)
|
||||
{
|
||||
cache = _cache;
|
||||
blkSize = cache->getBlockSize();
|
||||
}
|
||||
|
||||
void
|
||||
MissBuffer::setPrefetcher(BasePrefetcher *_prefetcher)
|
||||
{
|
||||
prefetcher = _prefetcher;
|
||||
}
|
223
src/mem/cache/miss/miss_buffer.hh
vendored
Normal file
223
src/mem/cache/miss/miss_buffer.hh
vendored
Normal file
|
@ -0,0 +1,223 @@
|
|||
/*
|
||||
* Copyright (c) 2003-2006 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Steve Reinhardt
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* MissBuffer declaration.
|
||||
*/
|
||||
|
||||
#ifndef __MISS_BUFFER_HH__
|
||||
#define __MISS_BUFFER_HH__
|
||||
|
||||
class BaseCache;
|
||||
class BasePrefetcher;
|
||||
class MSHR;
|
||||
|
||||
/**
|
||||
* Abstract base class for cache miss buffering.
|
||||
*/
|
||||
class MissBuffer
|
||||
{
|
||||
protected:
|
||||
/** True if the cache should allocate on a write miss. */
|
||||
const bool writeAllocate;
|
||||
|
||||
/** Pointer to the parent cache. */
|
||||
BaseCache *cache;
|
||||
|
||||
/** The Prefetcher */
|
||||
BasePrefetcher *prefetcher;
|
||||
|
||||
/** Block size of the parent cache. */
|
||||
int blkSize;
|
||||
|
||||
// Statistics
|
||||
/**
|
||||
* @addtogroup CacheStatistics
|
||||
* @{
|
||||
*/
|
||||
/** Number of blocks written back per thread. */
|
||||
Stats::Vector<> writebacks;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
public:
|
||||
MissBuffer(bool write_allocate)
|
||||
: writeAllocate(write_allocate)
|
||||
{
|
||||
}
|
||||
|
||||
virtual ~MissBuffer() {}
|
||||
|
||||
/**
|
||||
* Called by the parent cache to set the back pointer.
|
||||
* @param _cache A pointer to the parent cache.
|
||||
*/
|
||||
void setCache(BaseCache *_cache);
|
||||
|
||||
void setPrefetcher(BasePrefetcher *_prefetcher);
|
||||
|
||||
/**
|
||||
* Register statistics for this object.
|
||||
* @param name The name of the parent cache.
|
||||
*/
|
||||
virtual void regStats(const std::string &name);
|
||||
|
||||
/**
|
||||
* Handle a cache miss properly. Either allocate an MSHR for the request,
|
||||
* or forward it through the write buffer.
|
||||
* @param pkt The request that missed in the cache.
|
||||
* @param blk_size The block size of the cache.
|
||||
* @param time The time the miss is detected.
|
||||
*/
|
||||
virtual void handleMiss(PacketPtr &pkt, int blk_size, Tick time) = 0;
|
||||
|
||||
/**
|
||||
* Fetch the block for the given address and buffer the given target.
|
||||
* @param addr The address to fetch.
|
||||
* @param asid The address space of the address.
|
||||
* @param blk_size The block size of the cache.
|
||||
* @param time The time the miss is detected.
|
||||
* @param target The target for the fetch.
|
||||
*/
|
||||
virtual MSHR *fetchBlock(Addr addr, int blk_size, Tick time,
|
||||
PacketPtr &target) = 0;
|
||||
|
||||
/**
|
||||
* Selects a outstanding request to service.
|
||||
* @return The request to service, NULL if none found.
|
||||
*/
|
||||
virtual PacketPtr getPacket() = 0;
|
||||
|
||||
/**
|
||||
* Set the command to the given bus command.
|
||||
* @param pkt The request to update.
|
||||
* @param cmd The bus command to use.
|
||||
*/
|
||||
virtual void setBusCmd(PacketPtr &pkt, Packet::Command cmd) = 0;
|
||||
|
||||
/**
|
||||
* Restore the original command in case of a bus transmission error.
|
||||
* @param pkt The request to reset.
|
||||
*/
|
||||
virtual void restoreOrigCmd(PacketPtr &pkt) = 0;
|
||||
|
||||
/**
|
||||
* Marks a request as in service (sent on the bus). This can have side
|
||||
* effect since storage for no response commands is deallocated once they
|
||||
* are successfully sent.
|
||||
* @param pkt The request that was sent on the bus.
|
||||
*/
|
||||
virtual void markInService(PacketPtr &pkt, MSHR* mshr) = 0;
|
||||
|
||||
/**
|
||||
* Collect statistics and free resources of a satisfied request.
|
||||
* @param pkt The request that has been satisfied.
|
||||
* @param time The time when the request is satisfied.
|
||||
*/
|
||||
virtual void handleResponse(PacketPtr &pkt, Tick time) = 0;
|
||||
|
||||
/**
|
||||
* Removes all outstanding requests for a given thread number. If a request
|
||||
* has been sent to the bus, this function removes all of its targets.
|
||||
* @param threadNum The thread number of the requests to squash.
|
||||
*/
|
||||
virtual void squash(int threadNum) = 0;
|
||||
|
||||
/**
|
||||
* Return the current number of outstanding misses.
|
||||
* @return the number of outstanding misses.
|
||||
*/
|
||||
virtual int getMisses() = 0;
|
||||
|
||||
/**
|
||||
* Searches for the supplied address in the miss queue.
|
||||
* @param addr The address to look for.
|
||||
* @param asid The address space id.
|
||||
* @return The MSHR that contains the address, NULL if not found.
|
||||
* @warning Currently only searches the miss queue. If non write allocate
|
||||
* might need to search the write buffer for coherence.
|
||||
*/
|
||||
virtual MSHR* findMSHR(Addr addr) = 0;
|
||||
|
||||
/**
|
||||
* Searches for the supplied address in the write buffer.
|
||||
* @param addr The address to look for.
|
||||
* @param asid The address space id.
|
||||
* @param writes The list of writes that match the address.
|
||||
* @return True if any writes are found
|
||||
*/
|
||||
virtual bool findWrites(Addr addr, std::vector<MSHR*>& writes) = 0;
|
||||
|
||||
/**
|
||||
* Perform a writeback of dirty data to the given address.
|
||||
* @param addr The address to write to.
|
||||
* @param asid The address space id.
|
||||
* @param xc The execution context of the address space.
|
||||
* @param size The number of bytes to write.
|
||||
* @param data The data to write, can be NULL.
|
||||
* @param compressed True if the data is compressed.
|
||||
*/
|
||||
virtual void doWriteback(Addr addr, int size, uint8_t *data,
|
||||
bool compressed) = 0;
|
||||
|
||||
/**
|
||||
* Perform the given writeback request.
|
||||
* @param pkt The writeback request.
|
||||
*/
|
||||
virtual void doWriteback(PacketPtr &pkt) = 0;
|
||||
|
||||
/**
|
||||
* Returns true if there are outstanding requests.
|
||||
* @return True if there are outstanding requests.
|
||||
*/
|
||||
virtual bool havePending() = 0;
|
||||
|
||||
/**
|
||||
* Add a target to the given MSHR. This assumes it is in the miss queue.
|
||||
* @param mshr The mshr to add a target to.
|
||||
* @param pkt The target to add.
|
||||
*/
|
||||
virtual void addTarget(MSHR *mshr, PacketPtr &pkt) = 0;
|
||||
|
||||
/**
|
||||
* Allocate a MSHR to hold a list of targets to a block involved in a copy.
|
||||
* If the block is marked done then the MSHR already holds the data to
|
||||
* fill the block. Otherwise the block needs to be fetched.
|
||||
* @param addr The address to buffer.
|
||||
* @param asid The address space ID.
|
||||
* @return A pointer to the allocated MSHR.
|
||||
*/
|
||||
virtual MSHR* allocateTargetList(Addr addr) = 0;
|
||||
};
|
||||
|
||||
#endif //__MISS_BUFFER_HH__
|
36
src/mem/cache/miss/miss_queue.cc
vendored
36
src/mem/cache/miss/miss_queue.cc
vendored
|
@ -48,16 +48,25 @@ using namespace std;
|
|||
*/
|
||||
MissQueue::MissQueue(int numMSHRs, int numTargets, int write_buffers,
|
||||
bool write_allocate, bool prefetch_miss)
|
||||
: mq(numMSHRs, 4), wb(write_buffers,numMSHRs+1000), numMSHR(numMSHRs),
|
||||
: MissBuffer(write_allocate),
|
||||
mq(numMSHRs, 4), wb(write_buffers,numMSHRs+1000), numMSHR(numMSHRs),
|
||||
numTarget(numTargets), writeBuffers(write_buffers),
|
||||
writeAllocate(write_allocate), order(0), prefetchMiss(prefetch_miss)
|
||||
order(0), prefetchMiss(prefetch_miss)
|
||||
{
|
||||
noTargetMSHR = NULL;
|
||||
}
|
||||
|
||||
|
||||
MissQueue::~MissQueue()
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
MissQueue::regStats(const string &name)
|
||||
{
|
||||
MissBuffer::regStats(name);
|
||||
|
||||
Request temp_req((Addr) NULL, 4, 0);
|
||||
Packet::Command temp_cmd = Packet::ReadReq;
|
||||
Packet temp_pkt(&temp_req, temp_cmd, 0); //@todo FIx command strings so this isn't neccessary
|
||||
|
@ -65,13 +74,6 @@ MissQueue::regStats(const string &name)
|
|||
|
||||
using namespace Stats;
|
||||
|
||||
writebacks
|
||||
.init(maxThreadsPerCPU)
|
||||
.name(name + ".writebacks")
|
||||
.desc("number of writebacks")
|
||||
.flags(total)
|
||||
;
|
||||
|
||||
// MSHR hit statistics
|
||||
for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
|
||||
Packet::Command cmd = (Packet::Command)access_idx;
|
||||
|
@ -336,18 +338,6 @@ MissQueue::regStats(const string &name)
|
|||
|
||||
}
|
||||
|
||||
void
|
||||
MissQueue::setCache(BaseCache *_cache)
|
||||
{
|
||||
cache = _cache;
|
||||
blkSize = cache->getBlockSize();
|
||||
}
|
||||
|
||||
void
|
||||
MissQueue::setPrefetcher(BasePrefetcher *_prefetcher)
|
||||
{
|
||||
prefetcher = _prefetcher;
|
||||
}
|
||||
|
||||
MSHR*
|
||||
MissQueue::allocateMiss(PacketPtr &pkt, int size, Tick time)
|
||||
|
@ -706,13 +696,13 @@ MissQueue::squash(int threadNum)
|
|||
}
|
||||
|
||||
MSHR*
|
||||
MissQueue::findMSHR(Addr addr) const
|
||||
MissQueue::findMSHR(Addr addr)
|
||||
{
|
||||
return mq.findMatch(addr);
|
||||
}
|
||||
|
||||
bool
|
||||
MissQueue::findWrites(Addr addr, vector<MSHR*> &writes) const
|
||||
MissQueue::findWrites(Addr addr, vector<MSHR*> &writes)
|
||||
{
|
||||
return wb.findMatches(addr,writes);
|
||||
}
|
||||
|
|
30
src/mem/cache/miss/miss_queue.hh
vendored
30
src/mem/cache/miss/miss_queue.hh
vendored
|
@ -38,19 +38,18 @@
|
|||
|
||||
#include <vector>
|
||||
|
||||
#include "mem/cache/miss/miss_buffer.hh"
|
||||
#include "mem/cache/miss/mshr.hh"
|
||||
#include "mem/cache/miss/mshr_queue.hh"
|
||||
#include "base/statistics.hh"
|
||||
|
||||
class BaseCache;
|
||||
class BasePrefetcher;
|
||||
/**
|
||||
* Manages cache misses and writebacks. Contains MSHRs to store miss data
|
||||
* and the writebuffer for writes/writebacks.
|
||||
* @todo need to handle data on writes better (encapsulate).
|
||||
* @todo need to make replacements/writebacks happen in Cache::access
|
||||
*/
|
||||
class MissQueue
|
||||
class MissQueue : public MissBuffer
|
||||
{
|
||||
protected:
|
||||
/** The MSHRs. */
|
||||
|
@ -66,16 +65,6 @@ class MissQueue
|
|||
const int numTarget;
|
||||
/** The number of write buffers. */
|
||||
const int writeBuffers;
|
||||
/** True if the cache should allocate on a write miss. */
|
||||
const bool writeAllocate;
|
||||
/** Pointer to the parent cache. */
|
||||
BaseCache* cache;
|
||||
|
||||
/** The Prefetcher */
|
||||
BasePrefetcher *prefetcher;
|
||||
|
||||
/** The block size of the parent cache. */
|
||||
int blkSize;
|
||||
|
||||
/** Increasing order number assigned to each incoming request. */
|
||||
uint64_t order;
|
||||
|
@ -87,9 +76,6 @@ class MissQueue
|
|||
* @addtogroup CacheStatistics
|
||||
* @{
|
||||
*/
|
||||
/** Number of blocks written back per thread. */
|
||||
Stats::Vector<> writebacks;
|
||||
|
||||
/** Number of misses that hit in the MSHRs per command and thread. */
|
||||
Stats::Vector<> mshr_hits[NUM_MEM_CMDS];
|
||||
/** Demand misses that hit in the MSHRs. */
|
||||
|
@ -203,14 +189,6 @@ class MissQueue
|
|||
*/
|
||||
void regStats(const std::string &name);
|
||||
|
||||
/**
|
||||
* Called by the parent cache to set the back pointer.
|
||||
* @param _cache A pointer to the parent cache.
|
||||
*/
|
||||
void setCache(BaseCache *_cache);
|
||||
|
||||
void setPrefetcher(BasePrefetcher *_prefetcher);
|
||||
|
||||
/**
|
||||
* Handle a cache miss properly. Either allocate an MSHR for the request,
|
||||
* or forward it through the write buffer.
|
||||
|
@ -289,7 +267,7 @@ class MissQueue
|
|||
* @warning Currently only searches the miss queue. If non write allocate
|
||||
* might need to search the write buffer for coherence.
|
||||
*/
|
||||
MSHR* findMSHR(Addr addr) const;
|
||||
MSHR* findMSHR(Addr addr);
|
||||
|
||||
/**
|
||||
* Searches for the supplied address in the write buffer.
|
||||
|
@ -298,7 +276,7 @@ class MissQueue
|
|||
* @param writes The list of writes that match the address.
|
||||
* @return True if any writes are found
|
||||
*/
|
||||
bool findWrites(Addr addr, std::vector<MSHR*>& writes) const;
|
||||
bool findWrites(Addr addr, std::vector<MSHR*>& writes);
|
||||
|
||||
/**
|
||||
* Perform a writeback of dirty data to the given address.
|
||||
|
|
8
src/mem/cache/prefetch/ghb_prefetcher.cc
vendored
8
src/mem/cache/prefetch/ghb_prefetcher.cc
vendored
|
@ -38,17 +38,11 @@
|
|||
|
||||
#include "mem/cache/tags/lru.hh"
|
||||
|
||||
#include "base/compression/null_compression.hh"
|
||||
|
||||
#include "mem/cache/miss/miss_queue.hh"
|
||||
#include "mem/cache/miss/blocking_buffer.hh"
|
||||
|
||||
#include "mem/cache/prefetch/ghb_prefetcher.hh"
|
||||
|
||||
// Template Instantiations
|
||||
#ifndef DOXYGEN_SHOULD_SKIP_THIS
|
||||
|
||||
template class GHBPrefetcher<CacheTags<LRU,NullCompression>, MissQueue>;
|
||||
template class GHBPrefetcher<CacheTags<LRU,NullCompression>, BlockingBuffer>;
|
||||
template class GHBPrefetcher<CacheTags<LRU> >;
|
||||
|
||||
#endif //DOXYGEN_SHOULD_SKIP_THIS
|
||||
|
|
10
src/mem/cache/prefetch/ghb_prefetcher.hh
vendored
10
src/mem/cache/prefetch/ghb_prefetcher.hh
vendored
|
@ -43,16 +43,16 @@
|
|||
/**
|
||||
* A template-policy based cache. The behavior of the cache can be altered by
|
||||
* supplying different template policies. TagStore handles all tag and data
|
||||
* storage @sa TagStore. Buffering handles all misses and writes/writebacks
|
||||
* storage @sa TagStore. MissBuffer handles all misses and writes/writebacks
|
||||
* @sa MissQueue. Coherence handles all coherence policy details @sa
|
||||
* UniCoherence, SimpleMultiCoherence.
|
||||
*/
|
||||
template <class TagStore, class Buffering>
|
||||
class GHBPrefetcher : public Prefetcher<TagStore, Buffering>
|
||||
template <class TagStore>
|
||||
class GHBPrefetcher : public Prefetcher<TagStore>
|
||||
{
|
||||
protected:
|
||||
|
||||
Buffering* mq;
|
||||
MissBuffer* mq;
|
||||
TagStore* tags;
|
||||
|
||||
Addr second_last_miss_addr[64/*MAX_CPUS*/];
|
||||
|
@ -67,7 +67,7 @@ class GHBPrefetcher : public Prefetcher<TagStore, Buffering>
|
|||
GHBPrefetcher(int size, bool pageStop, bool serialSquash,
|
||||
bool cacheCheckPush, bool onlyData,
|
||||
Tick latency, int degree, bool useCPUId)
|
||||
:Prefetcher<TagStore, Buffering>(size, pageStop, serialSquash,
|
||||
:Prefetcher<TagStore>(size, pageStop, serialSquash,
|
||||
cacheCheckPush, onlyData),
|
||||
latency(latency), degree(degree), useCPUId(useCPUId)
|
||||
{
|
||||
|
|
8
src/mem/cache/prefetch/stride_prefetcher.cc
vendored
8
src/mem/cache/prefetch/stride_prefetcher.cc
vendored
|
@ -38,17 +38,11 @@
|
|||
|
||||
#include "mem/cache/tags/lru.hh"
|
||||
|
||||
#include "base/compression/null_compression.hh"
|
||||
|
||||
#include "mem/cache/miss/miss_queue.hh"
|
||||
#include "mem/cache/miss/blocking_buffer.hh"
|
||||
|
||||
#include "mem/cache/prefetch/stride_prefetcher.hh"
|
||||
|
||||
// Template Instantiations
|
||||
#ifndef DOXYGEN_SHOULD_SKIP_THIS
|
||||
|
||||
template class StridePrefetcher<CacheTags<LRU,NullCompression>, MissQueue>;
|
||||
template class StridePrefetcher<CacheTags<LRU,NullCompression>, BlockingBuffer>;
|
||||
template class StridePrefetcher<CacheTags<LRU> >;
|
||||
|
||||
#endif //DOXYGEN_SHOULD_SKIP_THIS
|
||||
|
|
10
src/mem/cache/prefetch/stride_prefetcher.hh
vendored
10
src/mem/cache/prefetch/stride_prefetcher.hh
vendored
|
@ -43,16 +43,16 @@
|
|||
/**
|
||||
* A template-policy based cache. The behavior of the cache can be altered by
|
||||
* supplying different template policies. TagStore handles all tag and data
|
||||
* storage @sa TagStore. Buffering handles all misses and writes/writebacks
|
||||
* storage @sa TagStore. MissBuffer handles all misses and writes/writebacks
|
||||
* @sa MissQueue. Coherence handles all coherence policy details @sa
|
||||
* UniCoherence, SimpleMultiCoherence.
|
||||
*/
|
||||
template <class TagStore, class Buffering>
|
||||
class StridePrefetcher : public Prefetcher<TagStore, Buffering>
|
||||
template <class TagStore>
|
||||
class StridePrefetcher : public Prefetcher<TagStore>
|
||||
{
|
||||
protected:
|
||||
|
||||
Buffering* mq;
|
||||
MissBuffer* mq;
|
||||
TagStore* tags;
|
||||
|
||||
class strideEntry
|
||||
|
@ -84,7 +84,7 @@ class StridePrefetcher : public Prefetcher<TagStore, Buffering>
|
|||
StridePrefetcher(int size, bool pageStop, bool serialSquash,
|
||||
bool cacheCheckPush, bool onlyData,
|
||||
Tick latency, int degree, bool useCPUId)
|
||||
:Prefetcher<TagStore, Buffering>(size, pageStop, serialSquash,
|
||||
:Prefetcher<TagStore>(size, pageStop, serialSquash,
|
||||
cacheCheckPush, onlyData),
|
||||
latency(latency), degree(degree), useCPUId(useCPUId)
|
||||
{
|
||||
|
|
8
src/mem/cache/prefetch/tagged_prefetcher.hh
vendored
8
src/mem/cache/prefetch/tagged_prefetcher.hh
vendored
|
@ -41,16 +41,16 @@
|
|||
/**
|
||||
* A template-policy based cache. The behavior of the cache can be altered by
|
||||
* supplying different template policies. TagStore handles all tag and data
|
||||
* storage @sa TagStore. Buffering handles all misses and writes/writebacks
|
||||
* storage @sa TagStore. MissBuffer handles all misses and writes/writebacks
|
||||
* @sa MissQueue. Coherence handles all coherence policy details @sa
|
||||
* UniCoherence, SimpleMultiCoherence.
|
||||
*/
|
||||
template <class TagStore, class Buffering>
|
||||
class TaggedPrefetcher : public Prefetcher<TagStore, Buffering>
|
||||
template <class TagStore>
|
||||
class TaggedPrefetcher : public Prefetcher<TagStore>
|
||||
{
|
||||
protected:
|
||||
|
||||
Buffering* mq;
|
||||
MissBuffer* mq;
|
||||
TagStore* tags;
|
||||
|
||||
Tick latency;
|
||||
|
|
10
src/mem/cache/prefetch/tagged_prefetcher_impl.hh
vendored
10
src/mem/cache/prefetch/tagged_prefetcher_impl.hh
vendored
|
@ -36,20 +36,20 @@
|
|||
#include "arch/isa_traits.hh"
|
||||
#include "mem/cache/prefetch/tagged_prefetcher.hh"
|
||||
|
||||
template <class TagStore, class Buffering>
|
||||
TaggedPrefetcher<TagStore, Buffering>::
|
||||
template <class TagStore>
|
||||
TaggedPrefetcher<TagStore>::
|
||||
TaggedPrefetcher(int size, bool pageStop, bool serialSquash,
|
||||
bool cacheCheckPush, bool onlyData,
|
||||
Tick latency, int degree)
|
||||
:Prefetcher<TagStore, Buffering>(size, pageStop, serialSquash,
|
||||
:Prefetcher<TagStore>(size, pageStop, serialSquash,
|
||||
cacheCheckPush, onlyData),
|
||||
latency(latency), degree(degree)
|
||||
{
|
||||
}
|
||||
|
||||
template <class TagStore, class Buffering>
|
||||
template <class TagStore>
|
||||
void
|
||||
TaggedPrefetcher<TagStore, Buffering>::
|
||||
TaggedPrefetcher<TagStore>::
|
||||
calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
|
||||
std::list<Tick> &delays)
|
||||
{
|
||||
|
|
|
@ -6,6 +6,6 @@ class Repl(SimObject):
|
|||
|
||||
class GenRepl(Repl):
|
||||
type = 'GenRepl'
|
||||
fresh_res = Param.Int("associativity")
|
||||
num_pools = Param.Int("capacity in bytes")
|
||||
pool_res = Param.Int("block size in bytes")
|
||||
fresh_res = Param.Int("Fresh pool residency time")
|
||||
num_pools = Param.Int("Number of priority pools")
|
||||
pool_res = Param.Int("Pool residency time")
|
||||
|
|
|
@ -237,6 +237,12 @@ class NumericParamValue(ParamValue):
|
|||
def __float__(self):
|
||||
return float(self.value)
|
||||
|
||||
def __long__(self):
|
||||
return long(self.value)
|
||||
|
||||
def __int__(self):
|
||||
return int(self.value)
|
||||
|
||||
# hook for bounds checking
|
||||
def _check(self):
|
||||
return
|
||||
|
@ -308,8 +314,11 @@ class CheckedInt(NumericParamValue):
|
|||
def __init__(self, value):
|
||||
if isinstance(value, str):
|
||||
self.value = convert.toInteger(value)
|
||||
elif isinstance(value, (int, long, float)):
|
||||
elif isinstance(value, (int, long, float, NumericParamValue)):
|
||||
self.value = long(value)
|
||||
else:
|
||||
raise TypeError, "Can't convert object of type %s to CheckedInt" \
|
||||
% type(value).__name__
|
||||
self._check()
|
||||
|
||||
class Int(CheckedInt): cxx_type = 'int'; size = 32; unsigned = False
|
||||
|
|
6
tests/long/20.parser/ref/alpha/linux/NOTE
Normal file
6
tests/long/20.parser/ref/alpha/linux/NOTE
Normal file
|
@ -0,0 +1,6 @@
|
|||
I removed the reference outputs for this program because it's taking
|
||||
way too long... over an hour for simple-atomic and over 19 hrs for
|
||||
o3-timing. We need to find a shorter input if we want to keep this
|
||||
in the regressions.
|
||||
|
||||
Steve
|
|
@ -1,417 +0,0 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
checkpoint=
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
print_data=true
|
||||
print_effaddr=true
|
||||
print_fetchseq=false
|
||||
print_iregs=false
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
speculative=true
|
||||
trace_system=client
|
||||
|
||||
[serialize]
|
||||
count=10
|
||||
cycle=0
|
||||
dir=cpt.%012d
|
||||
period=0
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
dump_reset=false
|
||||
ignore_events=
|
||||
mysql_db=
|
||||
mysql_host=
|
||||
mysql_password=
|
||||
mysql_user=
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_compat=true
|
||||
text_file=m5stats.txt
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache fuPool icache l2cache toL2Bus workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
RASSize=16
|
||||
SQEntries=32
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
clock=1
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
commitToRenameDelay=1
|
||||
commitWidth=8
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
defer_registration=false
|
||||
dispatchWidth=8
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
iewToCommitDelay=1
|
||||
iewToDecodeDelay=1
|
||||
iewToFetchDelay=1
|
||||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
mem=system.cpu.dcache
|
||||
numIQEntries=64
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
predType=tournament
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
squashWidth=8
|
||||
system=system
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
adaptive_compression=false
|
||||
assoc=2
|
||||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10
|
||||
prefetch_miss=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prioritizeRequests=false
|
||||
protocol=Null
|
||||
repl=Null
|
||||
size=262144
|
||||
split=false
|
||||
split_size=0
|
||||
store_compressed=false
|
||||
subblock_size=0
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.port[1]
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=6
|
||||
opList=system.cpu.fuPool.FUList0.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList4.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList5.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList7.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
adaptive_compression=false
|
||||
assoc=2
|
||||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10
|
||||
prefetch_miss=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prioritizeRequests=false
|
||||
protocol=Null
|
||||
repl=Null
|
||||
size=131072
|
||||
split=false
|
||||
split_size=0
|
||||
store_compressed=false
|
||||
subblock_size=0
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.port[0]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
adaptive_compression=false
|
||||
assoc=2
|
||||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10
|
||||
prefetch_miss=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prioritizeRequests=false
|
||||
protocol=Null
|
||||
repl=Null
|
||||
size=2097152
|
||||
split=false
|
||||
split_size=0
|
||||
store_compressed=false
|
||||
subblock_size=0
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
mem_side=system.membus.port[1]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
env=
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
input=cin
|
||||
output=cout
|
||||
system=system
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
port=system.physmem.port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=1
|
||||
range=0:134217727
|
||||
port=system.membus.port[0]
|
||||
|
||||
[trace]
|
||||
bufsize=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
ignore=
|
||||
start=0
|
||||
|
|
@ -1,403 +0,0 @@
|
|||
[root]
|
||||
type=Root
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
progress_interval=0
|
||||
output_file=cout
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
range=[0,134217727]
|
||||
latency=1
|
||||
|
||||
[system]
|
||||
type=System
|
||||
physmem=system.physmem
|
||||
mem_mode=atomic
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
system=system
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
size=262144
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList0.opList0
|
||||
count=6
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
issueLat=19
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
count=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
count=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
issueLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
issueLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
count=2
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList4.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList5.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
count=4
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
issueLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList7.opList0
|
||||
count=1
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
clock=1
|
||||
numThreads=1
|
||||
activity=0
|
||||
workload=system.cpu.workload
|
||||
mem=system.cpu.dcache
|
||||
checker=null
|
||||
max_insts_any_thread=0
|
||||
max_insts_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
cachePorts=200
|
||||
decodeToFetchDelay=1
|
||||
renameToFetchDelay=1
|
||||
iewToFetchDelay=1
|
||||
commitToFetchDelay=1
|
||||
fetchWidth=8
|
||||
renameToDecodeDelay=1
|
||||
iewToDecodeDelay=1
|
||||
commitToDecodeDelay=1
|
||||
fetchToDecodeDelay=1
|
||||
decodeWidth=8
|
||||
iewToRenameDelay=1
|
||||
commitToRenameDelay=1
|
||||
decodeToRenameDelay=1
|
||||
renameWidth=8
|
||||
commitToIEWDelay=1
|
||||
renameToIEWDelay=2
|
||||
issueToExecuteDelay=1
|
||||
dispatchWidth=8
|
||||
issueWidth=8
|
||||
wbWidth=8
|
||||
wbDepth=1
|
||||
fuPool=system.cpu.fuPool
|
||||
iewToCommitDelay=1
|
||||
renameToROBDelay=1
|
||||
commitWidth=8
|
||||
squashWidth=8
|
||||
trapLatency=13
|
||||
backComSize=5
|
||||
forwardComSize=5
|
||||
predType=tournament
|
||||
localPredictorSize=2048
|
||||
localCtrBits=2
|
||||
localHistoryTableSize=2048
|
||||
localHistoryBits=11
|
||||
globalPredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
choicePredictorSize=8192
|
||||
choiceCtrBits=2
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
RASSize=16
|
||||
LQEntries=32
|
||||
SQEntries=32
|
||||
LFSTSize=1024
|
||||
SSITSize=1024
|
||||
numPhysIntRegs=256
|
||||
numPhysFloatRegs=256
|
||||
numIQEntries=64
|
||||
numROBEntries=192
|
||||
smtNumFetchingThreads=1
|
||||
smtFetchPolicy=SingleThread
|
||||
smtLSQPolicy=Partitioned
|
||||
smtLSQThreshold=100
|
||||
smtIQPolicy=Partitioned
|
||||
smtIQThreshold=100
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
smtCommitPolicy=RoundRobin
|
||||
instShiftAmt=2
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
size=131072
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
size=2097152
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
ignore=
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_file=m5stats.txt
|
||||
text_compat=true
|
||||
mysql_db=
|
||||
mysql_user=
|
||||
mysql_password=
|
||||
mysql_host=
|
||||
events_start=-1
|
||||
dump_reset=false
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
ignore_events=
|
||||
|
||||
[random]
|
||||
seed=1
|
||||
|
||||
[exetrace]
|
||||
speculative=true
|
||||
print_cycle=true
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
print_effaddr=true
|
||||
print_data=true
|
||||
print_iregs=false
|
||||
print_fetchseq=false
|
||||
print_cpseq=false
|
||||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
trace_system=client
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
File diff suppressed because it is too large
Load diff
|
@ -1,3 +0,0 @@
|
|||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
|
|
@ -1,13 +0,0 @@
|
|||
Hello world!
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2006
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Sep 5 2006 15:28:48
|
||||
M5 started Tue Sep 5 15:42:12 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
|
||||
Exiting @ tick 6870 because target called exit()
|
19
util/regress
19
util/regress
|
@ -43,11 +43,13 @@ optparser.add_option('--builds', dest='builds',
|
|||
help='comma-separated list of build targets to test '
|
||||
" (default: '%default')" )
|
||||
optparser.add_option('--variants', dest='variants',
|
||||
default='opt',
|
||||
default='fast',
|
||||
help='comma-separated list of build variants to test '
|
||||
" (default: '%default')" )
|
||||
optparser.add_option('--scons-opts', dest='scons_opts', default='',
|
||||
help='scons options', metavar='OPTS')
|
||||
optparser.add_option('-j', '--jobs', type='int', default=1,
|
||||
help='number of parallel jobs to use')
|
||||
|
||||
(options, tests) = optparser.parse_args()
|
||||
|
||||
|
@ -75,10 +77,11 @@ def shellquote(s):
|
|||
|
||||
try:
|
||||
if not tests:
|
||||
print "No tests specified."
|
||||
sys.exit(1)
|
||||
|
||||
if 'all' in tests:
|
||||
print "No tests specified, just building binaries."
|
||||
targets = ['build/%s/m5.%s' % (build, variant)
|
||||
for build in builds
|
||||
for variant in variants]
|
||||
elif 'all' in tests:
|
||||
targets = ['build/%s/tests/%s' % (build, variant)
|
||||
for build in builds
|
||||
for variant in variants]
|
||||
|
@ -88,7 +91,11 @@ try:
|
|||
for variant in variants
|
||||
for test in tests]
|
||||
|
||||
system('scons %s %s' % (options.scons_opts, ' '.join(targets)))
|
||||
scons_opts = options.scons_opts
|
||||
if options.jobs != 1:
|
||||
scons_opts += ' -j %d' % options.jobs
|
||||
|
||||
system('scons %s %s' % (scons_opts, ' '.join(targets)))
|
||||
|
||||
sys.exit(0)
|
||||
|
||||
|
|
Loading…
Reference in a new issue