ARM: Create a new type of load uop that restores spsr into cpsr.
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@ -72,6 +72,18 @@ let {{
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'predicate_test': predicateTest},
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'predicate_test': predicateTest},
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['IsMicroop'])
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['IsMicroop'])
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microLdrRetUopCode = '''
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Ra = Mem;
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Cpsr = cpsrWriteByInstr(Cpsr, Spsr, 0xF, true);
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'''
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microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop',
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'MicroMemOp',
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{'memacc_code': microLdrRetUopCode,
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'ea_code':
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'EA = Rb + (UP ? imm : -imm);',
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'predicate_test': predicateTest},
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['IsMicroop'])
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microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
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microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
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'MicroMemOp',
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'MicroMemOp',
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{'memacc_code': 'Mem = Ra;',
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{'memacc_code': 'Mem = Ra;',
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@ -80,14 +92,19 @@ let {{
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['IsMicroop'])
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['IsMicroop'])
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header_output = MicroMemDeclare.subst(microLdrUopIop) + \
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header_output = MicroMemDeclare.subst(microLdrUopIop) + \
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MicroMemDeclare.subst(microLdrRetUopIop) + \
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MicroMemDeclare.subst(microStrUopIop)
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MicroMemDeclare.subst(microStrUopIop)
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decoder_output = MicroConstructor.subst(microLdrUopIop) + \
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decoder_output = MicroConstructor.subst(microLdrUopIop) + \
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MicroConstructor.subst(microLdrRetUopIop) + \
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MicroConstructor.subst(microStrUopIop)
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MicroConstructor.subst(microStrUopIop)
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exec_output = LoadExecute.subst(microLdrUopIop) + \
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exec_output = LoadExecute.subst(microLdrUopIop) + \
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LoadExecute.subst(microLdrRetUopIop) + \
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StoreExecute.subst(microStrUopIop) + \
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StoreExecute.subst(microStrUopIop) + \
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LoadInitiateAcc.subst(microLdrUopIop) + \
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LoadInitiateAcc.subst(microLdrUopIop) + \
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LoadInitiateAcc.subst(microLdrRetUopIop) + \
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StoreInitiateAcc.subst(microStrUopIop) + \
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StoreInitiateAcc.subst(microStrUopIop) + \
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LoadCompleteAcc.subst(microLdrUopIop) + \
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LoadCompleteAcc.subst(microLdrUopIop) + \
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LoadCompleteAcc.subst(microLdrRetUopIop) + \
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StoreCompleteAcc.subst(microStrUopIop)
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StoreCompleteAcc.subst(microStrUopIop)
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}};
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}};
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