X86: Make an x86 platform object.
--HG-- extra : convert_revision : 7d64d3e78960f3bb937579f5d10937bed5f197be
This commit is contained in:
Gabe Black
parent
22196f8885
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4 changed files with 245 additions and 0 deletions
10
src/dev/x86/Opteron.py
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10
src/dev/x86/Opteron.py
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from m5.params import *
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from m5.proxy import *
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from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
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from Uart import Uart8250
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from Platform import Platform
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from SimConsole import SimConsole
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class Opteron(Platform):
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type = 'Opteron'
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system = Param.System(Parent.any, "system")
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37
src/dev/x86/SConscript
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37
src/dev/x86/SConscript
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# -*- mode:python -*-
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# Copyright (c) 2006 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Steve Reinhardt
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# Gabe Black
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Import('*')
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if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'x86':
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SimObject('Opteron.py')
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Source('opteron.cc')
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106
src/dev/x86/opteron.cc
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106
src/dev/x86/opteron.cc
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/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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/** @file
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* Implementation of Opteron platform.
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*/
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#include <deque>
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#include <string>
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#include <vector>
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#include "cpu/intr_control.hh"
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#include "dev/simconsole.hh"
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#include "dev/x86/opteron.hh"
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#include "sim/system.hh"
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using namespace std;
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using namespace TheISA;
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Opteron::Opteron(const Params *p)
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: Platform(p), system(p->system)
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{
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// set the back pointer from the system to myself
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system->platform = this;
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}
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Tick
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Opteron::intrFrequency()
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{
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panic("Need implementation\n");
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M5_DUMMY_RETURN
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}
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void
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Opteron::postConsoleInt()
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{
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warn_once("Don't know what interrupt to post for console.\n");
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//panic("Need implementation\n");
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}
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void
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Opteron::clearConsoleInt()
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{
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warn_once("Don't know what interrupt to clear for console.\n");
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//panic("Need implementation\n");
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}
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void
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Opteron::postPciInt(int line)
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{
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panic("Need implementation\n");
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}
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void
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Opteron::clearPciInt(int line)
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{
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panic("Need implementation\n");
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}
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Addr
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Opteron::pciToDma(Addr pciAddr) const
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{
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panic("Need implementation\n");
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M5_DUMMY_RETURN
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}
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Addr
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Opteron::calcConfigAddr(int bus, int dev, int func)
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{
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panic("Need implementation\n");
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M5_DUMMY_RETURN
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}
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Opteron *
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OpteronParams::create()
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{
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return new Opteron(this);
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}
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92
src/dev/x86/opteron.hh
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92
src/dev/x86/opteron.hh
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@ -0,0 +1,92 @@
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/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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/**
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* @file
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* Declaration of top level class for the Opteron platform chips. This class
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* just retains pointers to all its children so the children can communicate.
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*/
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#ifndef __DEV_Opteron_HH__
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#define __DEV_Opteron_HH__
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#include "dev/platform.hh"
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#include "params/Opteron.hh"
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class IdeController;
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class System;
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class Opteron : public Platform
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{
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public:
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/** Pointer to the system */
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System *system;
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public:
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typedef OpteronParams Params;
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Opteron(const Params *p);
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/**
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* Return the interrupting frequency to AlphaAccess
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* @return frequency of RTC interrupts
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*/
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virtual Tick intrFrequency();
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/**
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* Cause the cpu to post a serial interrupt to the CPU.
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*/
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virtual void postConsoleInt();
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/**
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* Clear a posted CPU interrupt
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*/
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virtual void clearConsoleInt();
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/**
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* Cause the chipset to post a pci interrupt to the CPU.
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*/
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virtual void postPciInt(int line);
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/**
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* Clear a posted PCI->CPU interrupt
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*/
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virtual void clearPciInt(int line);
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virtual Addr pciToDma(Addr pciAddr) const;
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/**
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* Calculate the configuration address given a bus/dev/func.
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*/
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virtual Addr calcConfigAddr(int bus, int dev, int func);
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};
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#endif // __DEV_OPTERON_HH__
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