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stats: Update stats to reflect use of SimpleDRAM

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This patch bumps the stats to match the use of SimpleDRAM instead of
SimpleMemory in all inorder and O3 regressions, and also all
full-system regressions. A number of performance-related stats change,
and a whole bunch of stats are added for the memory controller.
This commit is contained in:
Andreas Hansson 2012-10-25 13:14:42 -04:00
parent 66e331c7bb
commit 8fe556338d
56 changed files with 37790 additions and 28461 deletions
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tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
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tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
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tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
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tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
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tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
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tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
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tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
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@ -1,77 +1,235 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 5.205007 # Number of seconds simulated sim_seconds 5.205006 # Number of seconds simulated
sim_ticks 5205006924000 # Number of ticks simulated sim_ticks 5205006494000 # Number of ticks simulated
final_tick 5205006924000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 5205006494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 143770 # Simulator instruction rate (inst/s) host_inst_rate 176611 # Simulator instruction rate (inst/s)
host_op_rate 275863 # Simulator op (including micro ops) rate (op/s) host_op_rate 338881 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 6917470976 # Simulator tick rate (ticks/s) host_tick_rate 8497542071 # Simulator tick rate (ticks/s)
host_mem_usage 505276 # Number of bytes of host memory used host_mem_usage 459536 # Number of bytes of host memory used
host_seconds 752.44 # Real time elapsed on the host host_seconds 612.53 # Real time elapsed on the host
sim_insts 108178578 # Number of instructions simulated sim_insts 108179755 # Number of instructions simulated
sim_ops 207571464 # Number of ops (including micro ops) simulated sim_ops 207574747 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 35216 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 35216 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 173936 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 174032 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 86216 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 86216 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 870514880 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 870539632 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 69689841 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 69693671 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 49504 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 49472 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 20312 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 20312 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 157070368 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 157047256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 27207776 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 27202450 # Number of bytes read from this memory
system.physmem.bytes_read::total 1124848049 # Number of bytes read from this memory system.physmem.bytes_read::total 1124848257 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 870514880 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 870539632 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 157070368 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 157047256 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1027585248 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1027586888 # Number of instructions bytes read from this memory
system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 48549302 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 48549554 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 21364054 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 21360352 # Number of bytes written to this memory
system.physmem.bytes_written::total 72904476 # Number of bytes written to this memory system.physmem.bytes_written::total 72901026 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 818 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 818 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 21742 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 21754 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 10777 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 10777 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 108814360 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 108817454 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 12175547 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 12176562 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 6188 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 6184 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 2539 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 2539 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 19633796 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 19630907 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 4005942 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 4005282 # Number of read requests responded to by this memory
system.physmem.num_reads::total 144671709 # Number of read requests responded to by this memory system.physmem.num_reads::total 144672277 # Number of read requests responded to by this memory
system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 7160367 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 7160394 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 2936343 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2935820 # Number of write requests responded to by this memory
system.physmem.num_writes::total 10143448 # Number of write requests responded to by this memory system.physmem.num_writes::total 10142952 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 6766 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::pc.south_bridge.ide 6766 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 33417 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 33436 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 16564 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 16564 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 167245672 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.inst 167250441 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 13389001 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.data 13389738 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 9511 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 9505 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 3902 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 3902 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 30176784 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 30172346 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 5227231 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 5226209 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 216108848 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 216108906 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 167245672 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 167250441 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 30176784 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 30172346 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 197422456 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 197422787 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::pc.south_bridge.ide 574659 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::pc.south_bridge.ide 574659 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 9327423 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 9327472 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 4104520 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 4103809 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 14006605 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 14005943 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 581425 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::pc.south_bridge.ide 581425 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 33417 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 33436 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 16567 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 16567 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 167245672 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 167250441 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 22716424 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.data 22717210 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 9511 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 9505 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 3902 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 3902 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 30176784 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 30172346 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 9331751 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 9330018 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 230115453 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 230114849 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 818 # Total number of read requests seen
system.physmem.writeReqs 46736 # Total number of write requests seen
system.physmem.cpureqs 47248 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 52352 # Total number of bytes read from memory
system.physmem.bytesWritten 2991104 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 35216 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 2991104 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 32 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 16 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 16 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 64 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 16 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 16 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 32 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 16 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 48 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 80 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 64 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 32 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 64 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 322 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 3080 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 3056 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 2944 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 2880 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 2912 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 2640 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 2864 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 2816 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 3024 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 2800 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 2800 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 2768 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 2992 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 3152 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 2992 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 3016 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 63209426000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 306 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 512 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 46736 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 336 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 30 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 30 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 30 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 30 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 30 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 30 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 30 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 30 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 30 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 30 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 30 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 30 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 30 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 40984666 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 52278666 # Sum of mem lat for all requests
system.physmem.totBusLat 3272000 # Total cycles spent in databus access
system.physmem.totBankLat 8022000 # Total cycles spent in bank access
system.physmem.avgQLat 50103.50 # Average queueing delay per request
system.physmem.avgBankLat 9806.85 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 63910.35 # Average memory access latency
system.physmem.avgRdBW 0.01 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.57 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 0.01 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.57 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.00 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.15 # Average write queue length over time
system.physmem.readRowHits 695 # Number of row buffer hits during reads
system.physmem.writeRowHits 45891 # Number of row buffer hits during writes
system.physmem.readRowHitRate 84.96 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 98.19 # Row buffer hit rate for writes
system.physmem.avgGap 1329213.65 # Average gap between requests
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
@ -114,52 +272,52 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
system.cpu0.numCycles 10410013848 # number of cpu cycles simulated system.cpu0.numCycles 10410012988 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 93129090 # Number of instructions committed system.cpu0.committedInsts 93132190 # Number of instructions committed
system.cpu0.committedOps 179514856 # Number of ops (including micro ops) committed system.cpu0.committedOps 179521943 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 169447650 # Number of integer alu accesses system.cpu0.num_int_alu_accesses 169453705 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu0.num_func_calls 0 # number of times a function call or return occured system.cpu0.num_func_calls 0 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 16553172 # number of instructions that are conditional controls system.cpu0.num_conditional_control_insts 16554212 # number of instructions that are conditional controls
system.cpu0.num_int_insts 169447650 # number of integer instructions system.cpu0.num_int_insts 169453705 # number of integer instructions
system.cpu0.num_fp_insts 0 # number of float instructions system.cpu0.num_fp_insts 0 # number of float instructions
system.cpu0.num_int_register_reads 418656867 # number of times the integer registers were read system.cpu0.num_int_register_reads 418670977 # number of times the integer registers were read
system.cpu0.num_int_register_writes 211655789 # number of times the integer registers were written system.cpu0.num_int_register_writes 211662649 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu0.num_mem_refs 20197632 # number of memory refs system.cpu0.num_mem_refs 20198672 # number of memory refs
system.cpu0.num_load_insts 13022518 # Number of load instructions system.cpu0.num_load_insts 13023532 # Number of load instructions
system.cpu0.num_store_insts 7175114 # Number of store instructions system.cpu0.num_store_insts 7175140 # Number of store instructions
system.cpu0.num_idle_cycles 9667682114.054142 # Number of idle cycles system.cpu0.num_idle_cycles 9667664508.054142 # Number of idle cycles
system.cpu0.num_busy_cycles 742331733.945857 # Number of busy cycles system.cpu0.num_busy_cycles 742348479.945857 # Number of busy cycles
system.cpu0.not_idle_fraction 0.071309 # Percentage of non-idle cycles system.cpu0.not_idle_fraction 0.071311 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.928691 # Percentage of idle cycles system.cpu0.idle_fraction 0.928689 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu1.numCycles 10407072224 # number of cpu cycles simulated system.cpu1.numCycles 10407071288 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 15049488 # Number of instructions committed system.cpu1.committedInsts 15047565 # Number of instructions committed
system.cpu1.committedOps 28056608 # Number of ops (including micro ops) committed system.cpu1.committedOps 28052804 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 27537877 # Number of integer alu accesses system.cpu1.num_int_alu_accesses 27533880 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu1.num_func_calls 0 # number of times a function call or return occured system.cpu1.num_func_calls 0 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 1864532 # number of instructions that are conditional controls system.cpu1.num_conditional_control_insts 1864518 # number of instructions that are conditional controls
system.cpu1.num_int_insts 27537877 # number of integer instructions system.cpu1.num_int_insts 27533880 # number of integer instructions
system.cpu1.num_fp_insts 0 # number of float instructions system.cpu1.num_fp_insts 0 # number of float instructions
system.cpu1.num_int_register_reads 71380294 # number of times the integer registers were read system.cpu1.num_int_register_reads 71369326 # number of times the integer registers were read
system.cpu1.num_int_register_writes 31003707 # number of times the integer registers were written system.cpu1.num_int_register_writes 30999444 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu1.num_mem_refs 6975131 # number of memory refs system.cpu1.num_mem_refs 6973948 # number of memory refs
system.cpu1.num_load_insts 4014934 # Number of load instructions system.cpu1.num_load_insts 4014274 # Number of load instructions
system.cpu1.num_store_insts 2960197 # Number of store instructions system.cpu1.num_store_insts 2959674 # Number of store instructions
system.cpu1.num_idle_cycles 10279839396.425842 # Number of idle cycles system.cpu1.num_idle_cycles 10279858503.692720 # Number of idle cycles
system.cpu1.num_busy_cycles 127232827.574158 # Number of busy cycles system.cpu1.num_busy_cycles 127212784.307279 # Number of busy cycles
system.cpu1.not_idle_fraction 0.012226 # Percentage of non-idle cycles system.cpu1.not_idle_fraction 0.012224 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.987774 # Percentage of idle cycles system.cpu1.idle_fraction 0.987776 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed

658
tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.271545 # Number of seconds simulated sim_seconds 0.271565 # Number of seconds simulated
sim_ticks 271544682500 # Number of ticks simulated sim_ticks 271565222500 # Number of ticks simulated
final_tick 271544682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 271565222500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 142205 # Simulator instruction rate (inst/s) host_inst_rate 118122 # Simulator instruction rate (inst/s)
host_op_rate 142205 # Simulator op (including micro ops) rate (op/s) host_op_rate 118122 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 64159611 # Simulator tick rate (ticks/s) host_tick_rate 53298093 # Simulator tick rate (ticks/s)
host_mem_usage 212920 # Number of bytes of host memory used host_mem_usage 217868 # Number of bytes of host memory used
host_seconds 4232.33 # Real time elapsed on the host host_seconds 5095.21 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory
@ -23,17 +23,175 @@ system.physmem.num_reads::cpu.data 25316 # Nu
system.physmem.num_reads::total 26157 # Number of read requests responded to by this memory system.physmem.num_reads::total 26157 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 891 # Number of write requests responded to by this memory system.physmem.num_writes::writebacks 891 # Number of write requests responded to by this memory
system.physmem.num_writes::total 891 # Number of write requests responded to by this memory system.physmem.num_writes::total 891 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 198214 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 198199 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 5966694 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 5966243 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 6164908 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 6164442 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 198214 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 198199 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 198214 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 198199 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 209999 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 209983 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 209999 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 209983 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 209999 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::writebacks 209983 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 198214 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 198199 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5966694 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5966243 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6374907 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 6374424 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 26157 # Total number of read requests seen
system.physmem.writeReqs 891 # Total number of write requests seen
system.physmem.cpureqs 27048 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 1674048 # Total number of bytes read from memory
system.physmem.bytesWritten 57024 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 1674048 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 57024 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 5 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 1710 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 1723 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 1560 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 1574 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 1699 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 1625 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 1662 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 1653 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 1553 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 1614 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 1596 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 1543 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 1643 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 1645 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 1686 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 1666 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 58 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 65 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 51 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 46 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 65 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 53 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 67 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 71 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 48 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 52 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 51 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 41 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 49 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 54 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 60 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 60 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 271565170500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 26157 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 891 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 22499 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 383 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 120 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 800 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1522 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 782 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 17 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 11 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 129156577 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 809724577 # Sum of mem lat for all requests
system.physmem.totBusLat 104608000 # Total cycles spent in databus access
system.physmem.totBankLat 575960000 # Total cycles spent in bank access
system.physmem.avgQLat 4938.69 # Average queueing delay per request
system.physmem.avgBankLat 22023.55 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 30962.24 # Average memory access latency
system.physmem.avgRdBW 6.16 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.21 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 6.16 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.21 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.04 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 7.68 # Average write queue length over time
system.physmem.readRowHits 17269 # Number of row buffer hits during reads
system.physmem.writeRowHits 120 # Number of row buffer hits during writes
system.physmem.readRowHitRate 66.03 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 13.47 # Row buffer hit rate for writes
system.physmem.avgGap 10040120.18 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_acv 0 # ITB acv
@ -42,18 +200,18 @@ system.cpu.dtb.read_hits 114517787 # DT
system.cpu.dtb.read_misses 2631 # DTB read misses system.cpu.dtb.read_misses 2631 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 114520418 # DTB read accesses system.cpu.dtb.read_accesses 114520418 # DTB read accesses
system.cpu.dtb.write_hits 39661840 # DTB write hits system.cpu.dtb.write_hits 39661841 # DTB write hits
system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.dtb.write_misses 2302 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 39664142 # DTB write accesses system.cpu.dtb.write_accesses 39664143 # DTB write accesses
system.cpu.dtb.data_hits 154179627 # DTB hits system.cpu.dtb.data_hits 154179628 # DTB hits
system.cpu.dtb.data_misses 4933 # DTB misses system.cpu.dtb.data_misses 4933 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 154184560 # DTB accesses system.cpu.dtb.data_accesses 154184561 # DTB accesses
system.cpu.itb.fetch_hits 25070818 # ITB hits system.cpu.itb.fetch_hits 25070821 # ITB hits
system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_misses 22 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 25070840 # ITB accesses system.cpu.itb.fetch_accesses 25070843 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_acv 0 # DTB read access violations
@ -67,42 +225,42 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 543089366 # number of cpu cycles simulated system.cpu.numCycles 543130446 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 86310005 # Number of BP lookups system.cpu.branch_predictor.lookups 86310002 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 81365597 # Number of conditional branches predicted system.cpu.branch_predictor.condPredicted 81365597 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 36354317 # Number of conditional branches incorrect system.cpu.branch_predictor.condIncorrect 36354316 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 52694904 # Number of BTB lookups system.cpu.branch_predictor.BTBLookups 52694902 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 34317639 # Number of BTB hits system.cpu.branch_predictor.BTBHits 34317638 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 65.125157 # BTB Hit Percentage system.cpu.branch_predictor.BTBHitPct 65.125158 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 36895090 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedTaken 36895088 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 49414915 # Number of Branches Predicted As Not Taken (False). system.cpu.branch_predictor.predictedNotTaken 49414914 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 541552617 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileReads 541552418 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 1005407463 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.intRegFileAccesses 1005407264 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 161 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileReads 161 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 203 # Total Accesses (Read+Write) to the FP Register File system.cpu.regfile_manager.floatRegFileAccesses 203 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 255071199 # Number of Registers Read Through Forwarding Logic system.cpu.regfile_manager.regForwards 255071398 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 155051796 # Number of Address Generations system.cpu.agen_unit.agens 155051796 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 33757784 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedTakenIncorrect 33757784 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 2591546 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.execution_unit.predictedNotTakenIncorrect 2591545 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 36349330 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.mispredicted 36349329 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 26198577 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.predicted 26198578 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 58.114383 # Percentage of Incorrect Branches Predicts system.cpu.execution_unit.mispredictPct 58.114381 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 412334991 # Number of Instructions Executed. system.cpu.execution_unit.executions 412334991 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 538349706 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.threadCycles 538350006 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 387700 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 387710 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 53984537 # Number of cycles cpu's stages were not processed system.cpu.idleCycles 54025519 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 489104829 # Number of cycles cpu stages are processed. system.cpu.runCycles 489104927 # Number of cycles cpu stages are processed.
system.cpu.activity 90.059732 # Percentage of cycles cpu is active system.cpu.activity 90.052939 # Percentage of cycles cpu is active
system.cpu.comLoads 114514042 # Number of Load instructions committed system.cpu.comLoads 114514042 # Number of Load instructions committed
system.cpu.comStores 39451321 # Number of Store instructions committed system.cpu.comStores 39451321 # Number of Store instructions committed
system.cpu.comBranches 62547159 # Number of Branches instructions committed system.cpu.comBranches 62547159 # Number of Branches instructions committed
@ -114,144 +272,144 @@ system.cpu.committedInsts 601856964 # Nu
system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread) system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total) system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total)
system.cpu.cpi 0.902356 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.cpi 0.902424 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 0.902356 # CPI: Total CPI of All Threads system.cpu.cpi_total 0.902424 # CPI: Total CPI of All Threads
system.cpu.ipc 1.108210 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.ipc 1.108126 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 1.108210 # IPC: Total IPC of All Threads system.cpu.ipc_total 1.108126 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 204234221 # Number of cycles 0 instructions are processed. system.cpu.stage0.idleCycles 204275308 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 338855145 # Number of cycles 1+ instructions are processed. system.cpu.stage0.runCycles 338855138 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 62.393994 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage0.utilization 62.389273 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 232262845 # Number of cycles 0 instructions are processed. system.cpu.stage1.idleCycles 232303926 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 310826521 # Number of cycles 1+ instructions are processed. system.cpu.stage1.runCycles 310826520 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 57.233034 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage1.utilization 57.228705 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 201309957 # Number of cycles 0 instructions are processed. system.cpu.stage2.idleCycles 201351117 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 341779409 # Number of cycles 1+ instructions are processed. system.cpu.stage2.runCycles 341779329 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 62.932444 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage2.utilization 62.927669 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 431519146 # Number of cycles 0 instructions are processed. system.cpu.stage3.idleCycles 431560271 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 111570220 # Number of cycles 1+ instructions are processed. system.cpu.stage3.runCycles 111570175 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 20.543621 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage3.utilization 20.542059 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 196111910 # Number of cycles 0 instructions are processed. system.cpu.stage4.idleCycles 196153041 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 346977456 # Number of cycles 1+ instructions are processed. system.cpu.stage4.runCycles 346977405 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 63.889569 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage4.utilization 63.884727 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 30 # number of replacements system.cpu.icache.replacements 30 # number of replacements
system.cpu.icache.tagsinuse 729.073717 # Cycle average of tags in use system.cpu.icache.tagsinuse 729.013382 # Cycle average of tags in use
system.cpu.icache.total_refs 25069794 # Total number of references to valid blocks. system.cpu.icache.total_refs 25069798 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 29321.396491 # Average number of references to valid blocks. system.cpu.icache.avg_refs 29321.401170 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 729.073717 # Average occupied blocks per requestor system.cpu.icache.occ_blocks::cpu.inst 729.013382 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.355993 # Average percentage of cache occupancy system.cpu.icache.occ_percent::cpu.inst 0.355964 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.355993 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.355964 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 25069794 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 25069798 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 25069794 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 25069798 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 25069794 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 25069798 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 25069794 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 25069798 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 25069794 # number of overall hits system.cpu.icache.overall_hits::cpu.inst 25069798 # number of overall hits
system.cpu.icache.overall_hits::total 25069794 # number of overall hits system.cpu.icache.overall_hits::total 25069798 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1022 # number of ReadReq misses system.cpu.icache.ReadReq_misses::cpu.inst 1021 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1022 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1021 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1022 # number of demand (read+write) misses system.cpu.icache.demand_misses::cpu.inst 1021 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1022 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1021 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1022 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 1021 # number of overall misses
system.cpu.icache.overall_misses::total 1022 # number of overall misses system.cpu.icache.overall_misses::total 1021 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 56347500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 53787000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 56347500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 53787000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 56347500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 53787000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 56347500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 53787000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 56347500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 53787000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 56347500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 53787000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 25070816 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 25070819 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 25070816 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 25070819 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 25070816 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 25070819 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 25070816 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 25070819 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 25070816 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 25070819 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 25070816 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 25070819 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55134.540117 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52680.705191 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 55134.540117 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 52680.705191 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55134.540117 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 52680.705191 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 55134.540117 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 52680.705191 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55134.540117 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 52680.705191 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 55134.540117 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 52680.705191 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 175 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 109 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 58.333333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 36.333333 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 167 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::cpu.inst 166 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 167 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 166 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 167 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 166 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 167 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 166 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 167 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 166 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 167 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 166 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46510500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43651000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 46510500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 43651000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46510500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43651000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 46510500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 43651000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46510500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43651000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 46510500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 43651000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54398.245614 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51053.801170 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54398.245614 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51053.801170 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54398.245614 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51053.801170 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 54398.245614 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 51053.801170 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54398.245614 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51053.801170 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 54398.245614 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 51053.801170 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 451299 # number of replacements system.cpu.dcache.replacements 451299 # number of replacements
system.cpu.dcache.tagsinuse 4094.014631 # Cycle average of tags in use system.cpu.dcache.tagsinuse 4093.593977 # Cycle average of tags in use
system.cpu.dcache.total_refs 152406162 # Total number of references to valid blocks. system.cpu.dcache.total_refs 152406549 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 334.668062 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 334.668912 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 268976000 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 342752000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.014631 # Average occupied blocks per requestor system.cpu.dcache.occ_blocks::cpu.data 4093.593977 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999515 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::cpu.data 0.999413 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999515 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999413 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 114120507 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 114120505 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 114120507 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 114120505 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 38285655 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 38286044 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 38285655 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 38286044 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 152406162 # number of demand (read+write) hits system.cpu.dcache.demand_hits::cpu.data 152406549 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 152406162 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 152406549 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 152406162 # number of overall hits system.cpu.dcache.overall_hits::cpu.data 152406549 # number of overall hits
system.cpu.dcache.overall_hits::total 152406162 # number of overall hits system.cpu.dcache.overall_hits::total 152406549 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 393535 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::cpu.data 393537 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 393535 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 393537 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1165666 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1165277 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1165666 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 1165277 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 1559201 # number of demand (read+write) misses system.cpu.dcache.demand_misses::cpu.data 1558814 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1559201 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 1558814 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1559201 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 1558814 # number of overall misses
system.cpu.dcache.overall_misses::total 1559201 # number of overall misses system.cpu.dcache.overall_misses::total 1558814 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5490501500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 5631779500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5490501500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 5631779500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 16777875500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 16513706000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 16777875500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 16513706000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 22268377000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 22145485500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 22268377000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 22145485500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 22268377000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 22145485500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 22268377000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 22145485500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
@ -262,38 +420,38 @@ system.cpu.dcache.overall_accesses::cpu.data 153965363
system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003437 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003437 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029547 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029537 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.029547 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.029537 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.010127 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.010124 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.010127 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.010124 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.010127 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.010124 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.010127 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.010124 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13951.748891 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14310.673456 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13951.748891 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 14310.673456 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14393.381552 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14171.485406 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 14393.381552 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 14171.485406 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14281.915545 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 14206.624716 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14281.915545 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 14206.624716 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14281.915545 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 14206.624716 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14281.915545 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 14206.624716 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 42145 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 44530 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 4093205 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 3993200 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 3164 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3165 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 211457 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 211455 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.320164 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.069510 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 19.357151 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 18.884396 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 436902 # number of writebacks system.cpu.dcache.writebacks::writebacks 436902 # number of writebacks
system.cpu.dcache.writebacks::total 436902 # number of writebacks system.cpu.dcache.writebacks::total 436902 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192303 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192305 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 192303 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 192305 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911503 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911114 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 911503 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 911114 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1103806 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 1103419 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1103806 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 1103419 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1103806 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 1103419 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1103806 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 1103419 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
@ -302,14 +460,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2395605000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2467175500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2395605000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 2467175500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3804662000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3742658000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3804662000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3742658000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6200267000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6209833500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6200267000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 6209833500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6200267000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6209833500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6200267000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 6209833500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
@ -318,28 +476,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958
system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11904.692097 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12260.353721 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11904.692097 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12260.353721 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14969.377919 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14725.424236 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14969.377919 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14725.424236 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13615.140702 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13636.147740 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13615.140702 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 13636.147740 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13615.140702 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13636.147740 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13615.140702 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 13636.147740 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 917 # number of replacements system.cpu.l2cache.replacements 917 # number of replacements
system.cpu.l2cache.tagsinuse 22852.343306 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 22846.870251 # Cycle average of tags in use
system.cpu.l2cache.total_refs 538836 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 538836 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 23142 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 23142 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 23.283899 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 23.283899 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 21651.877416 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::writebacks 21647.185426 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 719.990292 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 719.934202 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 480.475597 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 479.750624 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.660763 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::writebacks 0.660620 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.021972 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.021971 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.014663 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.014641 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.697398 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.697231 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 197087 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 197087 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 197101 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 197101 # number of ReadReq hits
@ -364,17 +522,17 @@ system.cpu.l2cache.demand_misses::total 26157 # nu
system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 25316 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 25316 # number of overall misses
system.cpu.l2cache.overall_misses::total 26157 # number of overall misses system.cpu.l2cache.overall_misses::total 26157 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45502000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42642500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 215882000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 287448500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 261384000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 330091000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1220308500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1158328500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1220308500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 1158328500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 45502000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 42642500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1436190500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 1445777000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1481692500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 1488419500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 45502000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 42642500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1436190500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 1445777000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1481692500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 1488419500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 201207 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 201207 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 202062 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 202062 # number of ReadReq accesses(hits+misses)
@ -399,22 +557,22 @@ system.cpu.l2cache.demand_miss_rate::total 0.057330 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.055591 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.055591 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.057330 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.057330 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54104.637337 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50704.518430 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52398.543689 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69769.053398 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52687.764564 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 66537.190083 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 57572.584450 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54648.447820 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 57572.584450 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54648.447820 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54104.637337 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50704.518430 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56730.545900 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57109.219466 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 56646.117674 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 56903.295485 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54104.637337 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50704.518430 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56730.545900 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57109.219466 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 56646.117674 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 56903.295485 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 217 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 2538 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 8 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 11 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 27.125000 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs 230.727273 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed
@ -431,17 +589,17 @@ system.cpu.l2cache.demand_mshr_misses::total 26157
system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 25316 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 25316 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 26157 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 26157 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35251500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32026854 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 165390500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 234985616 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 200642000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 267012470 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 961154000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 891005143 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 961154000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 891005143 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35251500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32026854 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1126544500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1125990759 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 1161796000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 1158017613 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35251500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32026854 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1126544500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1125990759 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 1161796000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 1158017613 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020476 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020476 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024552 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024552 # mshr miss rate for ReadReq accesses
@ -453,17 +611,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.057330
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.057330 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.057330 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41916.171225 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38081.871581 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40143.325243 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57035.343689 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40443.862125 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53822.308002 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45346.008681 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42036.475892 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45346.008681 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42036.475892 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41916.171225 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38081.871581 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44499.308738 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44477.435574 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44416.255687 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44271.805368 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41916.171225 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38081.871581 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44499.308738 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44477.435574 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44416.255687 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44271.805368 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

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@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.141181 # Number of seconds simulated sim_seconds 0.141149 # Number of seconds simulated
sim_ticks 141180939500 # Number of ticks simulated sim_ticks 141148809500 # Number of ticks simulated
final_tick 141180939500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 141148809500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 139974 # Simulator instruction rate (inst/s) host_inst_rate 76319 # Simulator instruction rate (inst/s)
host_op_rate 139974 # Simulator op (including micro ops) rate (op/s) host_op_rate 76319 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 49569488 # Simulator tick rate (ticks/s) host_tick_rate 27020959 # Simulator tick rate (ticks/s)
host_mem_usage 218836 # Number of bytes of host memory used host_mem_usage 222760 # Number of bytes of host memory used
host_seconds 2848.14 # Real time elapsed on the host host_seconds 5223.68 # Real time elapsed on the host
sim_insts 398664595 # Number of instructions simulated sim_insts 398664595 # Number of instructions simulated
sim_ops 398664595 # Number of ops (including micro ops) simulated sim_ops 398664595 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 214592 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 214592 # Number of bytes read from this memory
@ -19,14 +19,172 @@ system.physmem.bytes_inst_read::total 214592 # Nu
system.physmem.num_reads::cpu.inst 3353 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 3353 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7322 # Number of read requests responded to by this memory system.physmem.num_reads::total 7322 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1519979 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 1520325 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1799223 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 1799633 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 3319202 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 3319957 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1519979 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 1520325 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1519979 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 1520325 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1519979 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 1520325 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1799223 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1799633 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3319202 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 3319957 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 7322 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 7322 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 468608 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 468608 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 465 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 464 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 518 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 520 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 382 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 397 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 457 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 443 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 405 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 457 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 588 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 397 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 529 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 418 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 395 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 487 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 141148757500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 7322 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 0 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 5336 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1506 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 331 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 124 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 25 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 28738807 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 171664807 # Sum of mem lat for all requests
system.physmem.totBusLat 29288000 # Total cycles spent in databus access
system.physmem.totBankLat 113638000 # Total cycles spent in bank access
system.physmem.avgQLat 3924.99 # Average queueing delay per request
system.physmem.avgBankLat 15520.08 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 23445.07 # Average memory access latency
system.physmem.avgRdBW 3.32 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 3.32 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 6437 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 87.91 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 19277350.11 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_acv 0 # ITB acv
@ -35,18 +193,18 @@ system.cpu.dtb.read_hits 94755019 # DT
system.cpu.dtb.read_misses 21 # DTB read misses system.cpu.dtb.read_misses 21 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 94755040 # DTB read accesses system.cpu.dtb.read_accesses 94755040 # DTB read accesses
system.cpu.dtb.write_hits 73522102 # DTB write hits system.cpu.dtb.write_hits 73522092 # DTB write hits
system.cpu.dtb.write_misses 35 # DTB write misses system.cpu.dtb.write_misses 35 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 73522137 # DTB write accesses system.cpu.dtb.write_accesses 73522127 # DTB write accesses
system.cpu.dtb.data_hits 168277121 # DTB hits system.cpu.dtb.data_hits 168277111 # DTB hits
system.cpu.dtb.data_misses 56 # DTB misses system.cpu.dtb.data_misses 56 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 168277177 # DTB accesses system.cpu.dtb.data_accesses 168277167 # DTB accesses
system.cpu.itb.fetch_hits 49111833 # ITB hits system.cpu.itb.fetch_hits 49111843 # ITB hits
system.cpu.itb.fetch_misses 88782 # ITB misses system.cpu.itb.fetch_misses 88782 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 49200615 # ITB accesses system.cpu.itb.fetch_accesses 49200625 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_acv 0 # DTB read access violations
@ -60,26 +218,26 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls system.cpu.workload.num_syscalls 215 # Number of system calls
system.cpu.numCycles 282361880 # number of cpu cycles simulated system.cpu.numCycles 282297620 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 53870354 # Number of BP lookups system.cpu.branch_predictor.lookups 53870359 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 30921657 # Number of conditional branches predicted system.cpu.branch_predictor.condPredicted 30921660 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 16037209 # Number of conditional branches incorrect system.cpu.branch_predictor.condIncorrect 16037209 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 33426941 # Number of BTB lookups system.cpu.branch_predictor.BTBLookups 33426943 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 15653987 # Number of BTB hits system.cpu.branch_predictor.BTBHits 15653988 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 8007516 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.usedRAS 8007516 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 18 # Number of incorrect RAS predictions. system.cpu.branch_predictor.RASInCorrect 18 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 46.830450 # BTB Hit Percentage system.cpu.branch_predictor.BTBHitPct 46.830451 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 29683846 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedTaken 29683847 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 24186508 # Number of Branches Predicted As Not Taken (False). system.cpu.branch_predictor.predictedNotTaken 24186512 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 280818440 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileReads 280818433 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 440154299 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.intRegFileAccesses 440154292 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 119907695 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileReads 119907695 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 220104176 # Total Accesses (Read+Write) to the FP Register File system.cpu.regfile_manager.floatRegFileAccesses 220104176 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 100457653 # Number of Registers Read Through Forwarding Logic system.cpu.regfile_manager.regForwards 100457659 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 168700458 # Number of Address Generations system.cpu.agen_unit.agens 168700458 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 14475221 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedTakenIncorrect 14475221 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 1561329 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.execution_unit.predictedNotTakenIncorrect 1561329 # Number of Branches Incorrectly Predicted As Not Taken).
@ -90,12 +248,12 @@ system.cpu.execution_unit.executions 205750873 # Nu
system.cpu.mult_div_unit.multiplies 2124330 # Number of Multipy Operations Executed system.cpu.mult_div_unit.multiplies 2124330 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 281927927 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.threadCycles 281928004 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 8028 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 8014 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 13487383 # Number of cycles cpu's stages were not processed system.cpu.idleCycles 13423125 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 268874497 # Number of cycles cpu stages are processed. system.cpu.runCycles 268874495 # Number of cycles cpu stages are processed.
system.cpu.activity 95.223370 # Percentage of cycles cpu is active system.cpu.activity 95.245045 # Percentage of cycles cpu is active
system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comLoads 94754489 # Number of Load instructions committed
system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed
system.cpu.comBranches 44587532 # Number of Branches instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed
@ -107,78 +265,78 @@ system.cpu.committedInsts 398664595 # Nu
system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread) system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total) system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total)
system.cpu.cpi 0.708269 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.cpi 0.708108 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 0.708269 # CPI: Total CPI of All Threads system.cpu.cpi_total 0.708108 # CPI: Total CPI of All Threads
system.cpu.ipc 1.411892 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.ipc 1.412214 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 1.411892 # IPC: Total IPC of All Threads system.cpu.ipc_total 1.412214 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 78547913 # Number of cycles 0 instructions are processed. system.cpu.stage0.idleCycles 78483642 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 203813967 # Number of cycles 1+ instructions are processed. system.cpu.stage0.runCycles 203813978 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 72.181828 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage0.utilization 72.198263 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 108875170 # Number of cycles 0 instructions are processed. system.cpu.stage1.idleCycles 108810922 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 173486710 # Number of cycles 1+ instructions are processed. system.cpu.stage1.runCycles 173486698 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 61.441265 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage1.utilization 61.455246 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 104652466 # Number of cycles 0 instructions are processed. system.cpu.stage2.idleCycles 104588213 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 177709414 # Number of cycles 1+ instructions are processed. system.cpu.stage2.runCycles 177709407 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 62.936758 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage2.utilization 62.951082 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 183580459 # Number of cycles 0 instructions are processed. system.cpu.stage3.idleCycles 183516209 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 98781421 # Number of cycles 1+ instructions are processed. system.cpu.stage3.runCycles 98781411 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 34.983979 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage3.utilization 34.991939 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 92669372 # Number of cycles 0 instructions are processed. system.cpu.stage4.idleCycles 92605054 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 189692508 # Number of cycles 1+ instructions are processed. system.cpu.stage4.runCycles 189692566 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 67.180636 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage4.utilization 67.195949 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 1974 # number of replacements system.cpu.icache.replacements 1974 # number of replacements
system.cpu.icache.tagsinuse 1829.872355 # Cycle average of tags in use system.cpu.icache.tagsinuse 1830.000422 # Cycle average of tags in use
system.cpu.icache.total_refs 49107443 # Total number of references to valid blocks. system.cpu.icache.total_refs 49107453 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 3901 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 3901 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 12588.424250 # Average number of references to valid blocks. system.cpu.icache.avg_refs 12588.426814 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1829.872355 # Average occupied blocks per requestor system.cpu.icache.occ_blocks::cpu.inst 1830.000422 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.893492 # Average percentage of cache occupancy system.cpu.icache.occ_percent::cpu.inst 0.893555 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.893492 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.893555 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 49107443 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 49107453 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 49107443 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 49107453 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 49107443 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 49107453 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 49107443 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 49107453 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 49107443 # number of overall hits system.cpu.icache.overall_hits::cpu.inst 49107453 # number of overall hits
system.cpu.icache.overall_hits::total 49107443 # number of overall hits system.cpu.icache.overall_hits::total 49107453 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 4389 # number of ReadReq misses system.cpu.icache.ReadReq_misses::cpu.inst 4389 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 4389 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 4389 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 4389 # number of demand (read+write) misses system.cpu.icache.demand_misses::cpu.inst 4389 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 4389 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 4389 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 4389 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 4389 # number of overall misses
system.cpu.icache.overall_misses::total 4389 # number of overall misses system.cpu.icache.overall_misses::total 4389 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 215239500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 191814500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 215239500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 191814500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 215239500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 191814500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 215239500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 191814500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 215239500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 191814500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 215239500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 191814500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 49111832 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 49111842 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 49111832 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 49111842 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 49111832 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 49111842 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 49111832 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 49111842 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 49111832 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 49111842 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 49111832 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 49111842 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000089 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000089 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000089 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000089 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000089 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000089 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000089 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000089 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000089 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000089 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000089 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000089 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49040.669856 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43703.463203 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 49040.669856 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 43703.463203 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 49040.669856 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 43703.463203 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 49040.669856 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 43703.463203 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 49040.669856 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 43703.463203 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 49040.669856 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 43703.463203 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 90 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 66 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 90 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 66 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 488 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::cpu.inst 488 # number of ReadReq MSHR hits
@ -193,58 +351,58 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 3901
system.cpu.icache.demand_mshr_misses::total 3901 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 3901 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 3901 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3901 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 3901 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3901 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 190519000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 169767000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 190519000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 169767000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 190519000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 169767000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 190519000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 169767000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 190519000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 169767000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 190519000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 169767000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000079 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000079 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48838.502948 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43518.841323 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48838.502948 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43518.841323 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48838.502948 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43518.841323 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 48838.502948 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 43518.841323 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48838.502948 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43518.841323 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 48838.502948 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 43518.841323 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 764 # number of replacements system.cpu.dcache.replacements 764 # number of replacements
system.cpu.dcache.tagsinuse 3284.744401 # Cycle average of tags in use system.cpu.dcache.tagsinuse 3285.037423 # Cycle average of tags in use
system.cpu.dcache.total_refs 168261808 # Total number of references to valid blocks. system.cpu.dcache.total_refs 168261838 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 40525.483622 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 40525.490848 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 3284.744401 # Average occupied blocks per requestor system.cpu.dcache.occ_blocks::cpu.data 3285.037423 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.801940 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::cpu.data 0.802011 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.801940 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.802011 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 94753261 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 94753259 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 94753261 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753259 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 73508547 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 73508579 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 73508547 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 73508579 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 168261808 # number of demand (read+write) hits system.cpu.dcache.demand_hits::cpu.data 168261838 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 168261808 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 168261838 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 168261808 # number of overall hits system.cpu.dcache.overall_hits::cpu.data 168261838 # number of overall hits
system.cpu.dcache.overall_hits::total 168261808 # number of overall hits system.cpu.dcache.overall_hits::total 168261838 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1228 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::cpu.data 1230 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1228 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1230 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 12182 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::cpu.data 12150 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 12182 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 12150 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 13410 # number of demand (read+write) misses system.cpu.dcache.demand_misses::cpu.data 13380 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 13410 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 13380 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 13410 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 13380 # number of overall misses
system.cpu.dcache.overall_misses::total 13410 # number of overall misses system.cpu.dcache.overall_misses::total 13380 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 65498000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 62962000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 65498000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 62962000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 641953000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 525724500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 641953000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 525724500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 707451000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 588686500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 707451000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 588686500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 707451000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 588686500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 707451000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 588686500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
@ -255,38 +413,38 @@ system.cpu.dcache.overall_accesses::cpu.data 168275218
system.cpu.dcache.overall_accesses::total 168275218 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 168275218 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000013 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000013 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000013 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000013 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000166 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000165 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000166 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000165 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000080 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000080 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000080 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000080 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000080 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000080 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000080 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000080 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53337.133550 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51188.617886 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 53337.133550 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 51188.617886 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52696.847808 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43269.506173 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 52696.847808 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 43269.506173 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 52755.480984 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 43997.496263 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 52755.480984 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 43997.496263 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 52755.480984 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 43997.496263 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 52755.480984 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 43997.496263 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 171928 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 132949 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1907 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1897 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 90.156266 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 70.083817 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 649 # number of writebacks system.cpu.dcache.writebacks::writebacks 649 # number of writebacks
system.cpu.dcache.writebacks::total 649 # number of writebacks system.cpu.dcache.writebacks::total 649 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 278 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::cpu.data 280 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 278 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 280 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 8980 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 8948 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 8980 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 8948 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 9258 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 9228 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 9258 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 9228 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 9258 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 9228 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 9258 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 9228 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses
@ -295,14 +453,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152
system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48495500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47641000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 48495500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 47641000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 175965000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 148441000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 175965000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 148441000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 224460500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 196082000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 224460500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 196082000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 224460500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 196082000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 224460500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 196082000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
@ -311,28 +469,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51047.894737 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50148.421053 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51047.894737 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50148.421053 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54954.715803 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46358.838226 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54954.715803 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46358.838226 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54060.814066 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 47225.915222 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 54060.814066 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 47225.915222 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54060.814066 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 47225.915222 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 54060.814066 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 47225.915222 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 3900.293758 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 3900.679461 # Cycle average of tags in use
system.cpu.l2cache.total_refs 754 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 754 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 4711 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 4711 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.160051 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 0.160051 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 370.502388 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::writebacks 370.560631 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 2902.254610 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 2902.521753 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 627.536760 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 627.597077 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.011307 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::writebacks 0.011309 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.088570 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.088578 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.019151 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.019153 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.119028 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.119039 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 548 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 548 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 671 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 671 # number of ReadReq hits
@ -357,17 +515,17 @@ system.cpu.l2cache.demand_misses::total 7322 # nu
system.cpu.l2cache.overall_misses::cpu.inst 3353 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 3353 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses
system.cpu.l2cache.overall_misses::total 7322 # number of overall misses system.cpu.l2cache.overall_misses::total 7322 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 181079500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 160328500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 46077000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 45215500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 227156500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 205544000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 172190500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 144675500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 172190500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 144675500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 181079500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 160328500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 218267500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 189891000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 399347000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 350219500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 181079500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 160328500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 218267500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 189891000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 399347000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 350219500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 3901 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 3901 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 4848 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 4848 # number of ReadReq accesses(hits+misses)
@ -392,17 +550,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.909226 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.859523 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.859523 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.909226 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.909226 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54005.219207 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47816.433045 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55918.689320 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54873.179612 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 54382.690927 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 49208.522863 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54750.556439 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46001.748808 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54750.556439 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46001.748808 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54005.219207 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47816.433045 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54993.071303 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47843.537415 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 54540.699262 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 47831.125376 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54005.219207 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47816.433045 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54993.071303 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47843.537415 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 54540.699262 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 47831.125376 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -422,17 +580,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7322
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3353 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 3353 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 7322 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7322 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 140250000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117992891 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 36053500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 34864220 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 176303500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 152857111 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 133849000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 105232120 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 133849000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 105232120 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 140250000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117992891 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 169902500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 140096340 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 310152500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 258089231 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 140250000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117992891 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 169902500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 140096340 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 310152500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 258089231 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.861592 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.861592 # mshr miss rate for ReadReq accesses
@ -444,17 +602,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.909226
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.909226 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.909226 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41828.213540 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35190.244855 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43754.247573 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42310.946602 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42208.163754 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36594.951161 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42559.300477 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33460.133545 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42559.300477 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33460.133545 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41828.213540 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35190.244855 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42807.382212 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35297.641723 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42358.986616 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35248.460940 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41828.213540 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35190.244855 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42807.382212 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35297.641723 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42358.986616 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35248.460940 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

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@ -1,59 +1,217 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.046793 # Number of seconds simulated sim_seconds 0.046394 # Number of seconds simulated
sim_ticks 46793182500 # Number of ticks simulated sim_ticks 46393648500 # Number of ticks simulated
final_tick 46793182500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 46393648500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 131801 # Simulator instruction rate (inst/s) host_inst_rate 96549 # Simulator instruction rate (inst/s)
host_op_rate 131801 # Simulator op (including micro ops) rate (op/s) host_op_rate 96549 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 69813482 # Simulator tick rate (ticks/s) host_tick_rate 50704548 # Simulator tick rate (ticks/s)
host_mem_usage 220956 # Number of bytes of host memory used host_mem_usage 252684 # Number of bytes of host memory used
host_seconds 670.26 # Real time elapsed on the host host_seconds 914.98 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated sim_ops 88340673 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 514880 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 514944 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10272832 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10272704 # Number of bytes read from this memory
system.physmem.bytes_read::total 10787712 # Number of bytes read from this memory system.physmem.bytes_read::total 10787648 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 514880 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 514944 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 514880 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 514944 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7422400 # Number of bytes written to this memory system.physmem.bytes_written::writebacks 7422400 # Number of bytes written to this memory
system.physmem.bytes_written::total 7422400 # Number of bytes written to this memory system.physmem.bytes_written::total 7422400 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 8045 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 8046 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 160513 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 160511 # Number of read requests responded to by this memory
system.physmem.num_reads::total 168558 # Number of read requests responded to by this memory system.physmem.num_reads::total 168557 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 115975 # Number of write requests responded to by this memory system.physmem.num_writes::writebacks 115975 # Number of write requests responded to by this memory
system.physmem.num_writes::total 115975 # Number of write requests responded to by this memory system.physmem.num_writes::total 115975 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 11003312 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 11099450 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 219536938 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 221424793 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 230540250 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 232524243 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 11003312 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 11099450 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 11003312 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 11099450 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 158621397 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 159987417 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 158621397 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 159987417 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 158621397 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::writebacks 159987417 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 11003312 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 11099450 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 219536938 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 221424793 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 389161648 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 392511660 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 168557 # Total number of read requests seen
system.physmem.writeReqs 115975 # Total number of write requests seen
system.physmem.cpureqs 284532 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 10787648 # Total number of bytes read from memory
system.physmem.bytesWritten 7422400 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 10787648 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 7422400 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 12 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 10983 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 10544 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 10882 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 10471 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 10736 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 10499 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 10300 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 10074 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 10523 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 10483 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 10797 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 10531 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 10543 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 10030 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 10827 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 10322 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 7511 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 7019 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 7391 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 7077 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 7441 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 7201 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 7286 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 6969 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 7287 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 6971 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 7555 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 7177 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 7254 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 7052 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 7484 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 7300 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 46393600000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 168557 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 115975 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 162958 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 3658 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 1045 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 825 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 26 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 4989 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 5035 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 5042 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 5042 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 5043 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 5043 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 5043 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 5043 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 5043 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 5042 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 5042 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 5042 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 5042 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 5042 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 5042 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 5042 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 5042 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5042 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5042 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5042 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5042 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5042 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 5042 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 54 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 1271098054 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 4666794054 # Sum of mem lat for all requests
system.physmem.totBusLat 674180000 # Total cycles spent in databus access
system.physmem.totBankLat 2721516000 # Total cycles spent in bank access
system.physmem.avgQLat 7541.59 # Average queueing delay per request
system.physmem.avgBankLat 16147.12 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 27688.71 # Average memory access latency
system.physmem.avgRdBW 232.52 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 159.99 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 232.52 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 159.99 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 2.45 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.10 # Average read queue length over time
system.physmem.avgWrQLen 10.39 # Average write queue length over time
system.physmem.readRowHits 152922 # Number of row buffer hits during reads
system.physmem.writeRowHits 84722 # Number of row buffer hits during writes
system.physmem.readRowHitRate 90.73 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 73.05 # Row buffer hit rate for writes
system.physmem.avgGap 163052.31 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 20277225 # DTB read hits system.cpu.dtb.read_hits 20277224 # DTB read hits
system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_misses 90148 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 20367373 # DTB read accesses system.cpu.dtb.read_accesses 20367372 # DTB read accesses
system.cpu.dtb.write_hits 14736820 # DTB write hits system.cpu.dtb.write_hits 14736801 # DTB write hits
system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_misses 7252 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 14744072 # DTB write accesses system.cpu.dtb.write_accesses 14744053 # DTB write accesses
system.cpu.dtb.data_hits 35014045 # DTB hits system.cpu.dtb.data_hits 35014025 # DTB hits
system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_misses 97400 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 35111445 # DTB accesses system.cpu.dtb.data_accesses 35111425 # DTB accesses
system.cpu.itb.fetch_hits 12477645 # ITB hits system.cpu.itb.fetch_hits 12475425 # ITB hits
system.cpu.itb.fetch_misses 12958 # ITB misses system.cpu.itb.fetch_misses 12954 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 12490603 # ITB accesses system.cpu.itb.fetch_accesses 12488379 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_acv 0 # DTB read access violations
@ -67,42 +225,42 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls system.cpu.workload.num_syscalls 4583 # Number of system calls
system.cpu.numCycles 93586366 # number of cpu cycles simulated system.cpu.numCycles 92787298 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 18829185 # Number of BP lookups system.cpu.branch_predictor.lookups 18828887 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 12442057 # Number of conditional branches predicted system.cpu.branch_predictor.condPredicted 12440846 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 5026145 # Number of conditional branches incorrect system.cpu.branch_predictor.condIncorrect 5023695 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 16204746 # Number of BTB lookups system.cpu.branch_predictor.BTBLookups 16217673 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 5047870 # Number of BTB hits system.cpu.branch_predictor.BTBHits 5047073 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 1660949 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.usedRAS 1660946 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 1031 # Number of incorrect RAS predictions. system.cpu.branch_predictor.RASInCorrect 1031 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 31.150565 # BTB Hit Percentage system.cpu.branch_predictor.BTBHitPct 31.120821 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 8475762 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedTaken 8474385 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 10353423 # Number of Branches Predicted As Not Taken (False). system.cpu.branch_predictor.predictedNotTaken 10354502 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 74332851 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileReads 74331965 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 126652101 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.intRegFileAccesses 126651215 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 65265 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileReads 65206 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 292895 # Total Accesses (Read+Write) to the FP Register File system.cpu.regfile_manager.floatRegFileAccesses 292836 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 14120054 # Number of Registers Read Through Forwarding Logic system.cpu.regfile_manager.regForwards 14119774 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 35064610 # Number of Address Generations system.cpu.agen_unit.agens 35064022 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 4681911 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedTakenIncorrect 4679410 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 233734 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.execution_unit.predictedNotTakenIncorrect 233785 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 4915645 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.mispredicted 4913195 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 8856618 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.predicted 8859107 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 35.692355 # Percentage of Incorrect Branches Predicts system.cpu.execution_unit.mispredictPct 35.674465 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 44775927 # Number of Instructions Executed. system.cpu.execution_unit.executions 44776036 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 78075293 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.threadCycles 78069956 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 311800 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 311324 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 23300937 # Number of cycles cpu's stages were not processed system.cpu.idleCycles 22508104 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 70285429 # Number of cycles cpu stages are processed. system.cpu.runCycles 70279194 # Number of cycles cpu stages are processed.
system.cpu.activity 75.102210 # Percentage of cycles cpu is active system.cpu.activity 75.742257 # Percentage of cycles cpu is active
system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comLoads 20276638 # Number of Load instructions committed
system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed
system.cpu.comBranches 13754477 # Number of Branches instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed
@ -114,144 +272,144 @@ system.cpu.committedInsts 88340673 # Nu
system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total)
system.cpu.cpi 1.059380 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.cpi 1.050335 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 1.059380 # CPI: Total CPI of All Threads system.cpu.cpi_total 1.050335 # CPI: Total CPI of All Threads
system.cpu.ipc 0.943948 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.ipc 0.952077 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.943948 # IPC: Total IPC of All Threads system.cpu.ipc_total 0.952077 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 40161098 # Number of cycles 0 instructions are processed. system.cpu.stage0.idleCycles 39364116 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 53425268 # Number of cycles 1+ instructions are processed. system.cpu.stage0.runCycles 53423182 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 57.086593 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage0.utilization 57.575965 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 50931554 # Number of cycles 0 instructions are processed. system.cpu.stage1.idleCycles 50132225 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 42654812 # Number of cycles 1+ instructions are processed. system.cpu.stage1.runCycles 42655073 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 45.578019 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage1.utilization 45.970811 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 50461046 # Number of cycles 0 instructions are processed. system.cpu.stage2.idleCycles 49662532 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 43125320 # Number of cycles 1+ instructions are processed. system.cpu.stage2.runCycles 43124766 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 46.080772 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage2.utilization 46.477015 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 71466223 # Number of cycles 0 instructions are processed. system.cpu.stage3.idleCycles 70666607 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 22120143 # Number of cycles 1+ instructions are processed. system.cpu.stage3.runCycles 22120691 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 23.636074 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage3.utilization 23.840215 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 47482076 # Number of cycles 0 instructions are processed. system.cpu.stage4.idleCycles 46683402 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 46104290 # Number of cycles 1+ instructions are processed. system.cpu.stage4.runCycles 46103896 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 49.263896 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage4.utilization 49.687723 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 85221 # number of replacements system.cpu.icache.replacements 85246 # number of replacements
system.cpu.icache.tagsinuse 1887.407088 # Cycle average of tags in use system.cpu.icache.tagsinuse 1892.367381 # Cycle average of tags in use
system.cpu.icache.total_refs 12359392 # Total number of references to valid blocks. system.cpu.icache.total_refs 12357191 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 87267 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 87292 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 141.627328 # Average number of references to valid blocks. system.cpu.icache.avg_refs 141.561552 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1887.407088 # Average occupied blocks per requestor system.cpu.icache.occ_blocks::cpu.inst 1892.367381 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.921585 # Average percentage of cache occupancy system.cpu.icache.occ_percent::cpu.inst 0.924008 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.921585 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.924008 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 12359392 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 12357191 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 12359392 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 12357191 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 12359392 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 12357191 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 12359392 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 12357191 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 12359392 # number of overall hits system.cpu.icache.overall_hits::cpu.inst 12357191 # number of overall hits
system.cpu.icache.overall_hits::total 12359392 # number of overall hits system.cpu.icache.overall_hits::total 12357191 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 118206 # number of ReadReq misses system.cpu.icache.ReadReq_misses::cpu.inst 118187 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 118206 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 118187 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 118206 # number of demand (read+write) misses system.cpu.icache.demand_misses::cpu.inst 118187 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 118206 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 118187 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 118206 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 118187 # number of overall misses
system.cpu.icache.overall_misses::total 118206 # number of overall misses system.cpu.icache.overall_misses::total 118187 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1871587000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 1883931500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 1871587000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 1883931500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 1871587000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 1883931500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 1871587000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 1883931500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 1871587000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 1883931500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 1871587000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 1883931500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 12477598 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 12475378 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 12477598 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 12475378 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 12477598 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 12475378 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 12477598 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 12475378 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 12477598 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 12475378 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 12477598 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 12475378 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009473 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009474 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.009473 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.009474 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.009473 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.009474 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.009473 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.009474 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.009473 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.009474 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.009473 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.009474 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15833.265655 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15940.259927 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 15833.265655 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 15940.259927 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 15833.265655 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 15940.259927 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 15833.265655 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 15940.259927 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 15833.265655 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 15940.259927 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 15833.265655 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 15940.259927 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 2050 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 1882 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 94 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 108 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 21.808511 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 17.425926 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30939 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30895 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 30939 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 30895 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 30939 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 30895 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 30939 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 30895 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 30939 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 30895 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 30939 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 30895 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 87267 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::cpu.inst 87292 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 87267 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 87292 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 87267 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 87292 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 87267 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 87292 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 87267 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 87292 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 87267 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 87292 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1309592500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1323717000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 1309592500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 1323717000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1309592500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1323717000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 1309592500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 1323717000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1309592500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1323717000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 1309592500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 1323717000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006994 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006997 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006994 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006997 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006994 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006997 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.006994 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.006997 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006994 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006997 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.006994 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.006997 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15006.732213 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15164.241855 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15006.732213 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15164.241855 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15006.732213 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15164.241855 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 15006.732213 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 15164.241855 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15006.732213 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15164.241855 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 15006.732213 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 15164.241855 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 200251 # number of replacements system.cpu.dcache.replacements 200251 # number of replacements
system.cpu.dcache.tagsinuse 4072.865489 # Cycle average of tags in use system.cpu.dcache.tagsinuse 4074.773035 # Cycle average of tags in use
system.cpu.dcache.total_refs 34126021 # Total number of references to valid blocks. system.cpu.dcache.total_refs 34126001 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 167.000352 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 167.000254 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 486992000 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 420616000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4072.865489 # Average occupied blocks per requestor system.cpu.dcache.occ_blocks::cpu.data 4074.773035 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.994352 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::cpu.data 0.994818 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.994352 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.994818 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 20180532 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 20180529 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 20180532 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20180529 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 13945489 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 13945472 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 13945489 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 13945472 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 34126021 # number of demand (read+write) hits system.cpu.dcache.demand_hits::cpu.data 34126001 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 34126021 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 34126001 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 34126021 # number of overall hits system.cpu.dcache.overall_hits::cpu.data 34126001 # number of overall hits
system.cpu.dcache.overall_hits::total 34126021 # number of overall hits system.cpu.dcache.overall_hits::total 34126001 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 96106 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::cpu.data 96109 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 96106 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 96109 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 667888 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::cpu.data 667905 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 667888 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 667905 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 763994 # number of demand (read+write) misses system.cpu.dcache.demand_misses::cpu.data 764014 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 763994 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 764014 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 763994 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 764014 # number of overall misses
system.cpu.dcache.overall_misses::total 763994 # number of overall misses system.cpu.dcache.overall_misses::total 764014 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3881207000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 3658302500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 3881207000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 3658302500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 34562623000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 32880134000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 34562623000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 32880134000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 38443830000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 36538436500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 38443830000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 36538436500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 38443830000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 36538436500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 38443830000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 36538436500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
@ -262,38 +420,38 @@ system.cpu.dcache.overall_accesses::cpu.data 34890015
system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004740 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004740 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.004740 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004740 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045704 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045705 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.045704 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.045705 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.021897 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.021898 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.021897 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.021898 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.021897 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.021898 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.021897 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.021898 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40384.648201 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38064.099096 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 40384.648201 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 38064.099096 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51749.130094 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49228.758581 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 51749.130094 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 49228.758581 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 50319.544394 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 47824.302303 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 50319.544394 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 47824.302303 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 50319.544394 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 47824.302303 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 50319.544394 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 47824.302303 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 1355 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 12521367 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 11803841 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 124119 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 124100 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 271 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 100.881952 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 95.115560 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 165811 # number of writebacks system.cpu.dcache.writebacks::writebacks 165814 # number of writebacks
system.cpu.dcache.writebacks::total 165811 # number of writebacks system.cpu.dcache.writebacks::total 165814 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35339 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35342 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 35339 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 35342 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524308 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524325 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 524308 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 524325 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 559647 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 559667 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 559647 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 559667 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 559647 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 559667 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 559647 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 559667 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses
@ -302,14 +460,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204347
system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1916080000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1847026500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1916080000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 1847026500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7177771000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6899064500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 7177771000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 6899064500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9093851000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8746091000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 9093851000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 8746091000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9093851000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8746091000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 9093851000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 8746091000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
@ -318,152 +476,152 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857
system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
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system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.092188 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.092173 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.785492 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.785483 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.578018 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.577965 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.092188 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.092173 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.785492 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.785483 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.578018 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.577965 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40934.369173 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42158.812205 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40104.136971 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37131.710969 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40282.197222 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38210.038256 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40232.698955 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38046.806154 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40232.698955 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38046.806154 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40934.369173 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42158.812205 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40209.098328 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37878.827856 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40243.714330 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38083.131172 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40934.369173 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42158.812205 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40209.098328 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37878.827856 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40243.714330 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38083.131172 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

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tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
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tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
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tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
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@ -1,59 +1,217 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.983203 # Number of seconds simulated sim_seconds 0.998096 # Number of seconds simulated
sim_ticks 983202553500 # Number of ticks simulated sim_ticks 998095972500 # Number of ticks simulated
final_tick 983202553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 998095972500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 119503 # Simulator instruction rate (inst/s) host_inst_rate 135518 # Simulator instruction rate (inst/s)
host_op_rate 119503 # Simulator op (including micro ops) rate (op/s) host_op_rate 135518 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 64565869 # Simulator tick rate (ticks/s) host_tick_rate 74327611 # Simulator tick rate (ticks/s)
host_mem_usage 212872 # Number of bytes of host memory used host_mem_usage 465236 # Number of bytes of host memory used
host_seconds 15227.90 # Real time elapsed on the host host_seconds 13428.33 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 137579776 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 137579264 # Number of bytes read from this memory
system.physmem.bytes_read::total 137634752 # Number of bytes read from this memory system.physmem.bytes_read::total 137634240 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 67105088 # Number of bytes written to this memory system.physmem.bytes_written::writebacks 67104640 # Number of bytes written to this memory
system.physmem.bytes_written::total 67105088 # Number of bytes written to this memory system.physmem.bytes_written::total 67104640 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2149684 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2149676 # Number of read requests responded to by this memory
system.physmem.num_reads::total 2150543 # Number of read requests responded to by this memory system.physmem.num_reads::total 2150535 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1048517 # Number of write requests responded to by this memory system.physmem.num_writes::writebacks 1048510 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1048517 # Number of write requests responded to by this memory system.physmem.num_writes::total 1048510 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 55915 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 55081 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 139930247 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 137841718 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 139986162 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 137896799 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 55915 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 55081 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 55915 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 55081 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 68251540 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 67232653 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 68251540 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 67232653 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 68251540 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::writebacks 67232653 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 55915 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 55081 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 139930247 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 137841718 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 208237702 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 205129452 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 2150535 # Total number of read requests seen
system.physmem.writeReqs 1048510 # Total number of write requests seen
system.physmem.cpureqs 3199045 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 137634240 # Total number of bytes read from memory
system.physmem.bytesWritten 67104640 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 137634240 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 67104640 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 1104 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 134750 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 134519 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 135461 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 133443 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 134821 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 134519 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 135107 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 134152 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 133438 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 134313 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 134956 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 130690 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 131784 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 134689 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 137104 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 135685 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 65615 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 65313 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 65943 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 64961 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 65149 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 64711 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 65179 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 65010 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 64600 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 65119 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 65708 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 64486 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 65220 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 66941 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 67682 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 66873 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 998095934500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 2150535 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 1048510 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 1835130 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 153641 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 61976 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 38042 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 24246 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 14808 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 8848 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 5750 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 4166 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 2824 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 43501 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 44806 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 45260 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 45477 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 45551 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 45580 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 45587 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 45587 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 45588 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 45587 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 45587 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 45587 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 45587 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 45587 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 45587 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 45587 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 45587 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 45587 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 45587 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 45587 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 45587 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 45587 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 45587 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 2087 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 782 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 328 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 37 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 19730119710 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 92821713710 # Sum of mem lat for all requests
system.physmem.totBusLat 8597724000 # Total cycles spent in databus access
system.physmem.totBankLat 64493870000 # Total cycles spent in bank access
system.physmem.avgQLat 9179.23 # Average queueing delay per request
system.physmem.avgBankLat 30005.09 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 43184.32 # Average memory access latency
system.physmem.avgRdBW 137.90 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 67.23 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 137.90 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 67.23 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 1.28 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.09 # Average read queue length over time
system.physmem.avgWrQLen 11.29 # Average write queue length over time
system.physmem.readRowHits 884898 # Number of row buffer hits during reads
system.physmem.writeRowHits 338451 # Number of row buffer hits during writes
system.physmem.readRowHitRate 41.17 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 32.28 # Row buffer hit rate for writes
system.physmem.avgGap 311998.09 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 444615529 # DTB read hits system.cpu.dtb.read_hits 444628016 # DTB read hits
system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_misses 4897078 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 449512607 # DTB read accesses system.cpu.dtb.read_accesses 449525094 # DTB read accesses
system.cpu.dtb.write_hits 160920414 # DTB write hits system.cpu.dtb.write_hits 160917908 # DTB write hits
system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_misses 1701304 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 162621718 # DTB write accesses system.cpu.dtb.write_accesses 162619212 # DTB write accesses
system.cpu.dtb.data_hits 605535943 # DTB hits system.cpu.dtb.data_hits 605545924 # DTB hits
system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_misses 6598382 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 612134325 # DTB accesses system.cpu.dtb.data_accesses 612144306 # DTB accesses
system.cpu.itb.fetch_hits 232170189 # ITB hits system.cpu.itb.fetch_hits 232077768 # ITB hits
system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_misses 22 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 232170211 # ITB accesses system.cpu.itb.fetch_accesses 232077790 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_acv 0 # DTB read access violations
@ -67,42 +225,42 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls system.cpu.workload.num_syscalls 29 # Number of system calls
system.cpu.numCycles 1966405108 # number of cpu cycles simulated system.cpu.numCycles 1996191946 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 328916467 # Number of BP lookups system.cpu.branch_predictor.lookups 328934492 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 253806684 # Number of conditional branches predicted system.cpu.branch_predictor.condPredicted 253834142 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 140065896 # Number of conditional branches incorrect system.cpu.branch_predictor.condIncorrect 140072594 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 232656738 # Number of BTB lookups system.cpu.branch_predictor.BTBLookups 232648931 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 138122512 # Number of BTB hits system.cpu.branch_predictor.BTBHits 138176846 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 59.367510 # BTB Hit Percentage system.cpu.branch_predictor.BTBHitPct 59.392857 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 175157469 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedTaken 175181145 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 153758998 # Number of Branches Predicted As Not Taken (False). system.cpu.branch_predictor.predictedNotTaken 153753347 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 1669786412 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileReads 1669765696 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 3045989029 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.intRegFileAccesses 3045968313 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 236 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileReads 235 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 581 # Total Accesses (Read+Write) to the FP Register File system.cpu.regfile_manager.floatRegFileAccesses 580 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 650997764 # Number of Registers Read Through Forwarding Logic system.cpu.regfile_manager.regForwards 651043890 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 617989099 # Number of Address Generations system.cpu.agen_unit.agens 617989866 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 121287494 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedTakenIncorrect 121337623 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 12179944 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.execution_unit.predictedNotTakenIncorrect 12136513 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 133467438 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.mispredicted 133474136 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 81732764 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.predicted 81726090 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 62.020127 # Percentage of Incorrect Branches Predicts system.cpu.execution_unit.mispredictPct 62.023232 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 1139628962 # Number of Instructions Executed. system.cpu.execution_unit.executions 1139616626 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 1746556255 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.threadCycles 1746553256 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 7516835 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 7548952 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 389335212 # Number of cycles cpu's stages were not processed system.cpu.idleCycles 419177402 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 1577069896 # Number of cycles cpu stages are processed. system.cpu.runCycles 1577014544 # Number of cycles cpu stages are processed.
system.cpu.activity 80.200661 # Percentage of cycles cpu is active system.cpu.activity 79.001148 # Percentage of cycles cpu is active
system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comLoads 444595663 # Number of Load instructions committed
system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed
system.cpu.comBranches 214632552 # Number of Branches instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed
@ -114,144 +272,144 @@ system.cpu.committedInsts 1819780127 # Nu
system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total)
system.cpu.cpi 1.080573 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.cpi 1.096941 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 1.080573 # CPI: Total CPI of All Threads system.cpu.cpi_total 1.096941 # CPI: Total CPI of All Threads
system.cpu.ipc 0.925435 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.ipc 0.911626 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.925435 # IPC: Total IPC of All Threads system.cpu.ipc_total 0.911626 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 775560339 # Number of cycles 0 instructions are processed. system.cpu.stage0.idleCycles 805412484 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 1190844769 # Number of cycles 1+ instructions are processed. system.cpu.stage0.runCycles 1190779462 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 60.559483 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage0.utilization 59.652553 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 1034052370 # Number of cycles 0 instructions are processed. system.cpu.stage1.idleCycles 1063871870 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 932352738 # Number of cycles 1+ instructions are processed. system.cpu.stage1.runCycles 932320076 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 47.414072 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage1.utilization 46.704931 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 992429233 # Number of cycles 0 instructions are processed. system.cpu.stage2.idleCycles 1022192992 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 973975875 # Number of cycles 1+ instructions are processed. system.cpu.stage2.runCycles 973998954 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 49.530784 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage2.utilization 48.792851 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 1556696076 # Number of cycles 0 instructions are processed. system.cpu.stage3.idleCycles 1586493403 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 409709032 # Number of cycles 1+ instructions are processed. system.cpu.stage3.runCycles 409698543 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 20.835434 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage3.utilization 20.524005 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 943449824 # Number of cycles 0 instructions are processed. system.cpu.stage4.idleCycles 973220385 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 1022955284 # Number of cycles 1+ instructions are processed. system.cpu.stage4.runCycles 1022971561 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 52.021594 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage4.utilization 51.246152 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 1 # number of replacements system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.tagsinuse 666.559426 # Cycle average of tags in use system.cpu.icache.tagsinuse 667.791202 # Cycle average of tags in use
system.cpu.icache.total_refs 232169108 # Total number of references to valid blocks. system.cpu.icache.total_refs 232076694 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 270278.356228 # Average number of references to valid blocks. system.cpu.icache.avg_refs 270170.772992 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 666.559426 # Average occupied blocks per requestor system.cpu.icache.occ_blocks::cpu.inst 667.791202 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.325468 # Average percentage of cache occupancy system.cpu.icache.occ_percent::cpu.inst 0.326070 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.325468 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.326070 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 232169108 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 232076694 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 232169108 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 232076694 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 232169108 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 232076694 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 232169108 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 232076694 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 232169108 # number of overall hits system.cpu.icache.overall_hits::cpu.inst 232076694 # number of overall hits
system.cpu.icache.overall_hits::total 232169108 # number of overall hits system.cpu.icache.overall_hits::total 232076694 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1077 # number of ReadReq misses system.cpu.icache.ReadReq_misses::cpu.inst 1072 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1077 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1072 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1077 # number of demand (read+write) misses system.cpu.icache.demand_misses::cpu.inst 1072 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1077 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1072 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1077 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 1072 # number of overall misses
system.cpu.icache.overall_misses::total 1077 # number of overall misses system.cpu.icache.overall_misses::total 1072 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 58736500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 56100000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 58736500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 56100000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 58736500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 56100000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 58736500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 56100000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 58736500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 56100000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 58736500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 56100000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 232170185 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 232077766 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 232170185 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 232077766 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 232170185 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 232077766 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 232170185 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 232077766 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 232170185 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 232077766 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 232170185 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 232077766 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54537.140204 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52332.089552 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 54537.140204 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 52332.089552 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54537.140204 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 52332.089552 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 54537.140204 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 52332.089552 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54537.140204 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 52332.089552 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 54537.140204 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 52332.089552 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 210 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 99 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 52.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 218 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::cpu.inst 213 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 218 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 213 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 218 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 213 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 218 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 213 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 218 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 213 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 218 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 213 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47121000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45656000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 47121000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 45656000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47121000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45656000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 47121000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 45656000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47121000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45656000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 47121000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 45656000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54855.646100 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53150.174622 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54855.646100 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53150.174622 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54855.646100 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53150.174622 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 54855.646100 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 53150.174622 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54855.646100 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53150.174622 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 54855.646100 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 53150.174622 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9107371 # number of replacements system.cpu.dcache.replacements 9107316 # number of replacements
system.cpu.dcache.tagsinuse 4082.143149 # Cycle average of tags in use system.cpu.dcache.tagsinuse 4082.375203 # Cycle average of tags in use
system.cpu.dcache.total_refs 595063275 # Total number of references to valid blocks. system.cpu.dcache.total_refs 595069266 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9111467 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 9111412 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 65.309272 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 65.310324 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 12675157000 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 12653266000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4082.143149 # Average occupied blocks per requestor system.cpu.dcache.occ_blocks::cpu.data 4082.375203 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.996617 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::cpu.data 0.996674 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.996617 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.996674 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 437271434 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 437271434 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 437271434 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437271434 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 157791841 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 157797832 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 157791841 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 157797832 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 595063275 # number of demand (read+write) hits system.cpu.dcache.demand_hits::cpu.data 595069266 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 595063275 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 595069266 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 595063275 # number of overall hits system.cpu.dcache.overall_hits::cpu.data 595069266 # number of overall hits
system.cpu.dcache.overall_hits::total 595063275 # number of overall hits system.cpu.dcache.overall_hits::total 595069266 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 7324229 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::cpu.data 7324229 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 7324229 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 7324229 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2936661 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::cpu.data 2930670 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2936661 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 2930670 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 10260890 # number of demand (read+write) misses system.cpu.dcache.demand_misses::cpu.data 10254899 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 10260890 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 10254899 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 10260890 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 10254899 # number of overall misses
system.cpu.dcache.overall_misses::total 10260890 # number of overall misses system.cpu.dcache.overall_misses::total 10254899 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 153812326500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 169482879500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 153812326500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 169482879500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 102755788500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 114253006500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 102755788500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 114253006500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 256568115000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 283735886000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 256568115000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 283735886000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 256568115000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 283735886000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 256568115000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 283735886000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
@ -262,54 +420,54 @@ system.cpu.dcache.overall_accesses::cpu.data 605324165
system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016474 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016474 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.016474 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016474 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018271 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018234 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.018271 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.018234 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.016951 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.016941 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.016951 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.016941 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.016951 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016941 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.016951 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016941 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21000.480255 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23140.030097 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 21000.480255 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 23140.030097 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34990.687893 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38985.285447 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 34990.687893 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 38985.285447 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 25004.469885 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 27668.325744 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 25004.469885 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 27668.325744 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 25004.469885 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 27668.325744 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 25004.469885 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 27668.325744 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 52857 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 791552 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 15792734 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 14185855 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 4352 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 26512 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 208446 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 205984 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.145450 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.856367 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 75.764150 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 68.868723 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 3389692 # number of writebacks system.cpu.dcache.writebacks::writebacks 3389638 # number of writebacks
system.cpu.dcache.writebacks::total 3389692 # number of writebacks system.cpu.dcache.writebacks::total 3389638 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101949 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101954 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 101949 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 101954 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1047474 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1041533 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1047474 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 1041533 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1149423 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 1143487 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1149423 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 1143487 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1149423 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 1143487 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1149423 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 1143487 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222280 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222275 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7222280 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7222275 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889187 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889137 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1889187 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1889137 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9111467 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 9111412 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9111467 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 9111412 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9111467 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9111412 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9111467 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9111412 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137359214000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 153198656000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 137359214000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 153198656000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 55152222500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 69357589500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 55152222500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 69357589500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 192511436500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 222556245500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 192511436500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 222556245500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 192511436500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 222556245500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 192511436500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 222556245500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses
@ -318,149 +476,149 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052
system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19018.815942 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21211.966589 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19018.815942 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21211.966589 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29193.628000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36713.901374 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29193.628000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36713.901374 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21128.478707 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24426.098337 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 21128.478707 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 24426.098337 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21128.478707 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24426.098337 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 21128.478707 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 24426.098337 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2133758 # number of replacements system.cpu.l2cache.replacements 2133754 # number of replacements
system.cpu.l2cache.tagsinuse 30529.573479 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 30562.068421 # Cycle average of tags in use
system.cpu.l2cache.total_refs 8448408 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 8448353 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2163449 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 2163445 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 3.905065 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 3.905046 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 182812071500 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 183967255500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 14439.033310 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::writebacks 14375.476614 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 34.753993 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 34.146879 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 16055.786176 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 16152.444929 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.440644 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::writebacks 0.438705 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.001061 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.001042 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.489984 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.492934 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.931689 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.932680 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.data 5860987 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 5860981 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 5860987 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 5860981 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 3389692 # number of Writeback hits system.cpu.l2cache.Writeback_hits::writebacks 3389638 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 3389692 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 3389638 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1100796 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 1100755 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1100796 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 1100755 # number of ReadExReq hits
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system.cpu.l2cache.overall_hits::cpu.data 6961783 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 6961736 # number of overall hits
system.cpu.l2cache.overall_hits::total 6961783 # number of overall hits system.cpu.l2cache.overall_hits::total 6961736 # number of overall hits
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system.cpu.l2cache.ReadReq_misses::cpu.data 1360851 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 1360852 # number of ReadReq misses
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system.cpu.l2cache.overall_misses::cpu.data 2149684 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2149676 # number of overall misses
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system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71433605500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 87269885000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 71479862000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 87314676500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 42030855000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56286735500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 42030855000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 56286735500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 46256500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 44791500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 113464460500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 143556620500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 113510717000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 143601412000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 46256500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 44791500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 113464460500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 143556620500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 113510717000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 143601412000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 7221838 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7221833 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 7222697 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7222692 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 3389692 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 3389638 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 3389692 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 3389638 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889629 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889579 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1889629 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1889579 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 859 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.inst 859 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 9111467 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 9111412 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9112326 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 9112271 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 859 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 859 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 9111467 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 9111412 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9112326 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 9112271 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188436 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188436 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.188532 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.188532 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.417454 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.417460 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.417454 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.417460 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.235932 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.235932 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.236004 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.236004 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.235932 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.235932 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.236004 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.236004 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53849.243306 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52143.771828 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52491.863915 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64128.858245 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52492.720183 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 64121.297764 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53282.323382 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71355.252249 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53282.323382 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71355.252249 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53849.243306 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52143.771828 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52781.925390 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66780.584842 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52782.351713 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 66774.738379 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53849.243306 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52143.771828 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52781.925390 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66780.584842 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52782.351713 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 66774.738379 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 1081 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 438308 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 42 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 3445 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 25.738095 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs 127.230189 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 1048517 # number of writebacks system.cpu.l2cache.writebacks::writebacks 1048510 # number of writebacks
system.cpu.l2cache.writebacks::total 1048517 # number of writebacks system.cpu.l2cache.writebacks::total 1048510 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1360851 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1360852 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1361710 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 1361711 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 788833 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 788824 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 788833 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 788824 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2149684 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 2149676 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 2150543 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 2150535 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2149684 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2149676 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 2150543 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 2150535 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35788000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 33924935 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54811327000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 69917631981 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54847115000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 69951556916 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32423383500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 46302511646 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32423383500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 46302511646 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35788000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33924935 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87234710500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 116220143627 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 87270498500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 116254068562 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35788000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33924935 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87234710500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 116220143627 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 87270498500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 116254068562 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188436 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188436 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188532 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188532 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417454 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417460 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417454 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417460 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235932 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235932 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.236004 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.236004 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235932 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235932 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.236004 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.236004 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41662.398137 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39493.521537 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40277.243431 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 51377.836812 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40278.117220 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 51370.339900 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41102.975535 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58698.152751 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41102.975535 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58698.152751 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41662.398137 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39493.521537 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40580.248306 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54064.028080 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40580.680554 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54058.208103 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41662.398137 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39493.521537 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40580.248306 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54064.028080 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40580.680554 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54058.208103 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

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tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
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tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
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tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
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@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.042001 # Number of seconds simulated sim_seconds 0.041975 # Number of seconds simulated
sim_ticks 42001440000 # Number of ticks simulated sim_ticks 41974805000 # Number of ticks simulated
final_tick 42001440000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 41974805000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 134131 # Simulator instruction rate (inst/s) host_inst_rate 82989 # Simulator instruction rate (inst/s)
host_op_rate 134131 # Simulator op (including micro ops) rate (op/s) host_op_rate 82989 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 61300636 # Simulator tick rate (ticks/s) host_tick_rate 37903288 # Simulator tick rate (ticks/s)
host_mem_usage 216520 # Number of bytes of host memory used host_mem_usage 220440 # Number of bytes of host memory used
host_seconds 685.17 # Real time elapsed on the host host_seconds 1107.42 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated sim_ops 91903056 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory
@ -19,14 +19,172 @@ system.physmem.bytes_inst_read::total 178816 # Nu
system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory
system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 4257378 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 4260079 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3266936 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 3269009 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 7524313 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 7529088 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 4257378 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 4260079 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 4257378 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 4260079 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 4257378 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 4260079 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3266936 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3269009 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 7524313 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 7529088 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 4938 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 4938 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 316032 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 316032 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 349 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 313 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 229 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 290 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 250 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 283 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 352 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 383 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 306 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 282 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 254 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 283 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 313 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 363 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 356 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 332 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 41974753000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 4938 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 0 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 3879 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 789 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 235 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 24 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 15273921 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 109715921 # Sum of mem lat for all requests
system.physmem.totBusLat 19752000 # Total cycles spent in databus access
system.physmem.totBankLat 74690000 # Total cycles spent in bank access
system.physmem.avgQLat 3093.14 # Average queueing delay per request
system.physmem.avgBankLat 15125.56 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 22218.70 # Average memory access latency
system.physmem.avgRdBW 7.53 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 7.53 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.05 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 4458 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 90.28 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 8500355.00 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_acv 0 # ITB acv
@ -43,10 +201,10 @@ system.cpu.dtb.data_hits 26498122 # DT
system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_misses 33 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 26498155 # DTB accesses system.cpu.dtb.data_accesses 26498155 # DTB accesses
system.cpu.itb.fetch_hits 10035828 # ITB hits system.cpu.itb.fetch_hits 10035744 # ITB hits
system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_misses 49 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 10035877 # ITB accesses system.cpu.itb.fetch_accesses 10035793 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_acv 0 # DTB read access violations
@ -60,42 +218,42 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls system.cpu.workload.num_syscalls 389 # Number of system calls
system.cpu.numCycles 84002881 # number of cpu cycles simulated system.cpu.numCycles 83949611 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 13564877 # Number of BP lookups system.cpu.branch_predictor.lookups 13564912 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 9782208 # Number of conditional branches predicted system.cpu.branch_predictor.condPredicted 9782242 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 4497797 # Number of conditional branches incorrect system.cpu.branch_predictor.condIncorrect 4497823 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 7992443 # Number of BTB lookups system.cpu.branch_predictor.BTBLookups 7992579 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 3850454 # Number of BTB hits system.cpu.branch_predictor.BTBHits 3850502 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 122 # Number of incorrect RAS predictions. system.cpu.branch_predictor.RASInCorrect 122 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 48.176183 # BTB Hit Percentage system.cpu.branch_predictor.BTBHitPct 48.175964 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 5999677 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedTaken 5999728 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 7565200 # Number of Branches Predicted As Not Taken (False). system.cpu.branch_predictor.predictedNotTaken 7565184 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 73745294 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileReads 73745301 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 136320766 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.intRegFileAccesses 136320773 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 2206799 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileReads 2206799 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 8058687 # Total Accesses (Read+Write) to the FP Register File system.cpu.regfile_manager.floatRegFileAccesses 8058687 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 38528678 # Number of Registers Read Through Forwarding Logic system.cpu.regfile_manager.regForwards 38528717 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 26769096 # Number of Address Generations system.cpu.agen_unit.agens 26769089 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 3520460 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedTakenIncorrect 3520477 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 976479 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.execution_unit.predictedNotTakenIncorrect 976488 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 4496939 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.mispredicted 4496965 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 5743763 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.predicted 5743737 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 43.912410 # Percentage of Incorrect Branches Predicts system.cpu.execution_unit.mispredictPct 43.912663 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 57470351 # Number of Instructions Executed. system.cpu.execution_unit.executions 57470360 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 458258 # Number of Multipy Operations Executed system.cpu.mult_div_unit.multiplies 458258 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 83639631 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.threadCycles 83639616 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 11378 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 11375 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 7720370 # Number of cycles cpu's stages were not processed system.cpu.idleCycles 7667023 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 76282511 # Number of cycles cpu stages are processed. system.cpu.runCycles 76282588 # Number of cycles cpu stages are processed.
system.cpu.activity 90.809399 # Percentage of cycles cpu is active system.cpu.activity 90.867113 # Percentage of cycles cpu is active
system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comLoads 19996198 # Number of Load instructions committed
system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed
system.cpu.comBranches 10240685 # Number of Branches instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed
@ -107,144 +265,144 @@ system.cpu.committedInsts 91903056 # Nu
system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total)
system.cpu.cpi 0.914038 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.cpi 0.913458 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 0.914038 # CPI: Total CPI of All Threads system.cpu.cpi_total 0.913458 # CPI: Total CPI of All Threads
system.cpu.ipc 1.094046 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.ipc 1.094741 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 1.094046 # IPC: Total IPC of All Threads system.cpu.ipc_total 1.094741 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 27781439 # Number of cycles 0 instructions are processed. system.cpu.stage0.idleCycles 27728071 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 56221442 # Number of cycles 1+ instructions are processed. system.cpu.stage0.runCycles 56221540 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 66.927993 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage0.utilization 66.970578 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 34555420 # Number of cycles 0 instructions are processed. system.cpu.stage1.idleCycles 34502106 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 49447461 # Number of cycles 1+ instructions are processed. system.cpu.stage1.runCycles 49447505 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 58.864006 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage1.utilization 58.901411 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 34024816 # Number of cycles 0 instructions are processed. system.cpu.stage2.idleCycles 33971546 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 49978065 # Number of cycles 1+ instructions are processed. system.cpu.stage2.runCycles 49978065 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 59.495656 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage2.utilization 59.533409 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 65973303 # Number of cycles 0 instructions are processed. system.cpu.stage3.idleCycles 65920043 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 18029578 # Number of cycles 1+ instructions are processed. system.cpu.stage3.runCycles 18029568 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 21.463047 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage3.utilization 21.476655 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 30058791 # Number of cycles 0 instructions are processed. system.cpu.stage4.idleCycles 30005535 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 53944090 # Number of cycles 1+ instructions are processed. system.cpu.stage4.runCycles 53944076 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 64.216952 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage4.utilization 64.257684 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 8127 # number of replacements system.cpu.icache.replacements 8127 # number of replacements
system.cpu.icache.tagsinuse 1492.293343 # Cycle average of tags in use system.cpu.icache.tagsinuse 1492.468291 # Cycle average of tags in use
system.cpu.icache.total_refs 10024070 # Total number of references to valid blocks. system.cpu.icache.total_refs 10023999 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 10012 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 10012 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1001.205553 # Average number of references to valid blocks. system.cpu.icache.avg_refs 1001.198462 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1492.293343 # Average occupied blocks per requestor system.cpu.icache.occ_blocks::cpu.inst 1492.468291 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.728659 # Average percentage of cache occupancy system.cpu.icache.occ_percent::cpu.inst 0.728744 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.728659 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.728744 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 10024070 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 10023999 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 10024070 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 10023999 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 10024070 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 10023999 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 10024070 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 10023999 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 10024070 # number of overall hits system.cpu.icache.overall_hits::cpu.inst 10023999 # number of overall hits
system.cpu.icache.overall_hits::total 10024070 # number of overall hits system.cpu.icache.overall_hits::total 10023999 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 11754 # number of ReadReq misses system.cpu.icache.ReadReq_misses::cpu.inst 11743 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 11754 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 11743 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 11754 # number of demand (read+write) misses system.cpu.icache.demand_misses::cpu.inst 11743 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 11754 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 11743 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 11754 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 11743 # number of overall misses
system.cpu.icache.overall_misses::total 11754 # number of overall misses system.cpu.icache.overall_misses::total 11743 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 284626500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 259067500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 284626500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 259067500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 284626500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 259067500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 284626500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 259067500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 284626500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 259067500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 284626500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 259067500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 10035824 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 10035742 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 10035824 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 10035742 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 10035824 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 10035742 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 10035824 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 10035742 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 10035824 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 10035742 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 10035824 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 10035742 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001171 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001170 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.001171 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001170 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.001171 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001170 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.001171 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001170 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.001171 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001170 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.001171 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001170 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24215.288412 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22061.440858 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 24215.288412 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 22061.440858 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 24215.288412 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 22061.440858 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 24215.288412 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 22061.440858 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 24215.288412 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 22061.440858 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 24215.288412 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 22061.440858 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 184 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 67 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 30.666667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 16.750000 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1742 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1731 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 1742 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 1731 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 1742 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 1731 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 1742 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 1731 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 1742 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 1731 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 1742 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 1731 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10012 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10012 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 10012 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 10012 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 10012 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 10012 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 10012 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 10012 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 10012 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 10012 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 10012 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 10012 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 231904000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 210374500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 231904000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 210374500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 231904000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 210374500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 231904000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 210374500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 231904000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 210374500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 231904000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 210374500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000998 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000998 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000998 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000998 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000998 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000998 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23162.604874 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21012.235318 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23162.604874 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21012.235318 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23162.604874 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21012.235318 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 23162.604874 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 21012.235318 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23162.604874 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21012.235318 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 23162.604874 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 21012.235318 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.replacements 157 # number of replacements
system.cpu.dcache.tagsinuse 1441.465399 # Cycle average of tags in use system.cpu.dcache.tagsinuse 1441.629591 # Cycle average of tags in use
system.cpu.dcache.total_refs 26491189 # Total number of references to valid blocks. system.cpu.dcache.total_refs 26491183 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 11916.864148 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 11916.861448 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 1441.465399 # Average occupied blocks per requestor system.cpu.dcache.occ_blocks::cpu.data 1441.629591 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.351920 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::cpu.data 0.351960 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.351920 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.351960 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 19995639 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 19995637 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 19995639 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 19995637 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 6495550 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6495546 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 6495550 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 6495546 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 26491189 # number of demand (read+write) hits system.cpu.dcache.demand_hits::cpu.data 26491183 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 26491189 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 26491183 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 26491189 # number of overall hits system.cpu.dcache.overall_hits::cpu.data 26491183 # number of overall hits
system.cpu.dcache.overall_hits::total 26491189 # number of overall hits system.cpu.dcache.overall_hits::total 26491183 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 559 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::cpu.data 561 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 559 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 561 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 5553 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::cpu.data 5557 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 5553 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 5557 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 6112 # number of demand (read+write) misses system.cpu.dcache.demand_misses::cpu.data 6118 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 6112 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 6118 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 6112 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 6118 # number of overall misses
system.cpu.dcache.overall_misses::total 6112 # number of overall misses system.cpu.dcache.overall_misses::total 6118 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 28955000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 28389500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 28955000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 28389500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 305088500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 249397000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 305088500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 249397000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 334043500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 277786500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 334043500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 277786500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 334043500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 277786500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 334043500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 277786500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
@ -255,38 +413,38 @@ system.cpu.dcache.overall_accesses::cpu.data 26497301
system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000854 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000855 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000854 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000855 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000231 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000231 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000231 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000231 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000231 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000231 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000231 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000231 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51797.853309 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50605.169340 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 51797.853309 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 50605.169340 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54941.202953 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44879.791254 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 54941.202953 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 44879.791254 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54653.714005 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 45404.789147 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 54653.714005 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 45404.789147 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54653.714005 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 45404.789147 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 54653.714005 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 45404.789147 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 82457 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 63919 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 827 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 827 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 99.706167 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 77.290206 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 107 # number of writebacks system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
system.cpu.dcache.writebacks::total 107 # number of writebacks system.cpu.dcache.writebacks::total 107 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 84 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::cpu.data 86 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3805 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3809 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 3805 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 3809 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 3889 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 3895 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 3889 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 3895 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 3889 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 3895 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 3889 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 3895 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses
@ -295,14 +453,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223
system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24156000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23282500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 24156000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 23282500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 96637000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 80468500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 96637000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 80468500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 120793000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 103751000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 120793000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 103751000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 120793000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 103751000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 120793000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 103751000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
@ -311,28 +469,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50854.736842 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49015.789474 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50854.736842 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49015.789474 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55284.324943 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46034.610984 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55284.324943 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46034.610984 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54337.831759 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46671.614935 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 54337.831759 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 46671.614935 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54337.831759 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46671.614935 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 54337.831759 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 46671.614935 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 2189.683531 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 2189.948520 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7285 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 7285 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.219683 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 2.219683 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 17.845444 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::writebacks 17.843388 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 1820.840268 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 1821.063413 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 350.997820 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 351.041719 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.055568 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.055574 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.010712 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.010713 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.066824 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.066832 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 7218 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 7218 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 7271 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 7271 # number of ReadReq hits
@ -357,17 +515,17 @@ system.cpu.l2cache.demand_misses::total 4938 # nu
system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses
system.cpu.l2cache.overall_misses::total 4938 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 149399500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 127870000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 23132500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22259000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 172532000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 150129000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 94615000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 78446500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 94615000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 78446500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 149399500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 127870000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 117747500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 100705500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 267147000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 228575500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 149399500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 127870000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 117747500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 100705500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 267147000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 228575500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 10012 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 10012 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 10487 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 10487 # number of ReadReq accesses(hits+misses)
@ -392,17 +550,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.403596 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.279065 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.279065 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.403596 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.403596 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53471.546170 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 45765.926986 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54816.350711 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52746.445498 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 53648.009950 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 46681.902985 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54944.831591 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45555.458769 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54944.831591 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45555.458769 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53471.546170 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 45765.926986 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54919.542910 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46970.848881 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 54100.243013 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 46289.084650 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53471.546170 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 45765.926986 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54919.542910 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46970.848881 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 54100.243013 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 46289.084650 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -422,17 +580,17 @@ system.cpu.l2cache.demand_mshr_misses::total 4938
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115312500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 92500808 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17984000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16940683 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 133296500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 109441491 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73481500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 57047489 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73481500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 57047489 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115312500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 92500808 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 91465500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 73988172 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 206778000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 166488980 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115312500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 92500808 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 91465500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 73988172 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 206778000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 166488980 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.306665 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.306665 # mshr miss rate for ReadReq accesses
@ -444,17 +602,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.403596
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.403596 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.403596 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41271.474588 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33106.946314 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42616.113744 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40143.798578 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41447.916667 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34030.314366 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42672.183508 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33128.623113 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42672.183508 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33128.623113 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41271.474588 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33106.946314 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42661.147388 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34509.408582 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41874.848117 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33715.872823 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41271.474588 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33106.946314 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42661.147388 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34509.408582 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41874.848117 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33715.872823 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

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tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
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tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
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tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
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tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
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@ -4,11 +4,11 @@ sim_seconds 1.870325 # Nu
sim_ticks 1870325497500 # Number of ticks simulated sim_ticks 1870325497500 # Number of ticks simulated
final_tick 1870325497500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 1870325497500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2529303 # Simulator instruction rate (inst/s) host_inst_rate 1528286 # Simulator instruction rate (inst/s)
host_op_rate 2529302 # Simulator op (including micro ops) rate (op/s) host_op_rate 1528286 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 74909435310 # Simulator tick rate (ticks/s) host_tick_rate 45262701867 # Simulator tick rate (ticks/s)
host_mem_usage 298360 # Number of bytes of host memory used host_mem_usage 296828 # Number of bytes of host memory used
host_seconds 24.97 # Real time elapsed on the host host_seconds 41.32 # Real time elapsed on the host
sim_insts 63151114 # Number of instructions simulated sim_insts 63151114 # Number of instructions simulated
sim_ops 63151114 # Number of ops (including micro ops) simulated sim_ops 63151114 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 760896 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 760896 # Number of bytes read from this memory
@ -48,16 +48,174 @@ system.physmem.bw_total::tsunami.ide 1416652 # To
system.physmem.bw_total::cpu1.inst 59438 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 59438 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 364531 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 364531 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 42090265 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 42090265 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 0 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 0 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 0 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 0 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 0 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 0 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
system.physmem.totBusLat 0 # Total cycles spent in databus access
system.physmem.totBankLat 0 # Total cycles spent in bank access
system.physmem.avgQLat nan # Average queueing delay per request
system.physmem.avgBankLat nan # Average bank access latency per request
system.physmem.avgBusLat nan # Average bus latency per request
system.physmem.avgMemAccLat nan # Average memory access latency
system.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.00 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 0 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate nan # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap nan # Average gap between requests
system.l2c.replacements 1000406 # number of replacements system.l2c.replacements 1000406 # number of replacements
system.l2c.tagsinuse 65381.817479 # Cycle average of tags in use system.l2c.tagsinuse 65381.817483 # Cycle average of tags in use
system.l2c.total_refs 2465974 # Total number of references to valid blocks. system.l2c.total_refs 2465980 # Total number of references to valid blocks.
system.l2c.sampled_refs 1065550 # Sample count of references to valid blocks. system.l2c.sampled_refs 1065550 # Sample count of references to valid blocks.
system.l2c.avg_refs 2.314273 # Average number of references to valid blocks. system.l2c.avg_refs 2.314279 # Average number of references to valid blocks.
system.l2c.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. system.l2c.warmup_cycle 838081000 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 56158.126687 # Average occupied blocks per requestor system.l2c.occ_blocks::writebacks 56158.126694 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 4894.240577 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.inst 4894.240575 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 4135.004263 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.data 4135.004261 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 174.436812 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.inst 174.436811 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 20.009142 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.data 20.009142 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.856905 # Average percentage of cache occupancy system.l2c.occ_percent::writebacks 0.856905 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy
@ -66,10 +224,10 @@ system.l2c.occ_percent::cpu1.inst 0.002662 # Av
system.l2c.occ_percent::cpu1.data 0.000305 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.data 0.000305 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.997647 # Average percentage of cache occupancy system.l2c.occ_percent::total 0.997647 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst 872724 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.inst 872724 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 763058 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 763064 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 102911 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 102911 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 36889 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.data 36889 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1775582 # number of ReadReq hits system.l2c.ReadReq_hits::total 1775588 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 816811 # number of Writeback hits system.l2c.Writeback_hits::writebacks 816811 # number of Writeback hits
system.l2c.Writeback_hits::total 816811 # number of Writeback hits system.l2c.Writeback_hits::total 816811 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 138 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu0.data 138 # number of UpgradeReq hits
@ -82,15 +240,15 @@ system.l2c.ReadExReq_hits::cpu0.data 166434 # nu
system.l2c.ReadExReq_hits::cpu1.data 14300 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 14300 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 180734 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 180734 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst 872724 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.inst 872724 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 929492 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 929498 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 102911 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 102911 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 51189 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 51189 # number of demand (read+write) hits
system.l2c.demand_hits::total 1956316 # number of demand (read+write) hits system.l2c.demand_hits::total 1956322 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 872724 # number of overall hits system.l2c.overall_hits::cpu0.inst 872724 # number of overall hits
system.l2c.overall_hits::cpu0.data 929492 # number of overall hits system.l2c.overall_hits::cpu0.data 929498 # number of overall hits
system.l2c.overall_hits::cpu1.inst 102911 # number of overall hits system.l2c.overall_hits::cpu1.inst 102911 # number of overall hits
system.l2c.overall_hits::cpu1.data 51189 # number of overall hits system.l2c.overall_hits::cpu1.data 51189 # number of overall hits
system.l2c.overall_hits::total 1956316 # number of overall hits system.l2c.overall_hits::total 1956322 # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst 11889 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.inst 11889 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 926770 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 926770 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 1737 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 1737 # number of ReadReq misses
@ -116,10 +274,10 @@ system.l2c.overall_misses::cpu1.inst 1737 # nu
system.l2c.overall_misses::cpu1.data 10780 # number of overall misses system.l2c.overall_misses::cpu1.data 10780 # number of overall misses
system.l2c.overall_misses::total 1066458 # number of overall misses system.l2c.overall_misses::total 1066458 # number of overall misses
system.l2c.ReadReq_accesses::cpu0.inst 884613 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.inst 884613 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 1689828 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 1689834 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 104648 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 104648 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 37807 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.data 37807 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2716896 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 2716902 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 816811 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 816811 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 816811 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 816811 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 2579 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 2579 # number of UpgradeReq accesses(hits+misses)
@ -132,20 +290,20 @@ system.l2c.ReadExReq_accesses::cpu0.data 281716 # nu
system.l2c.ReadExReq_accesses::cpu1.data 24162 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 24162 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 305878 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 305878 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst 884613 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.inst 884613 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 1971544 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 1971550 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 104648 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 104648 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 61969 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.data 61969 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 3022774 # number of demand (read+write) accesses system.l2c.demand_accesses::total 3022780 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 884613 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.inst 884613 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 1971544 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 1971550 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 104648 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 104648 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 61969 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.data 61969 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 3022774 # number of overall (read+write) accesses system.l2c.overall_accesses::total 3022780 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.013440 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.013440 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.548440 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.data 0.548438 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.016599 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.016599 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.024281 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.024281 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.346467 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.346466 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.946491 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.946491 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.939542 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.939542 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.945158 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.945158 # miss rate for UpgradeReq accesses
@ -156,15 +314,15 @@ system.l2c.ReadExReq_miss_rate::cpu0.data 0.409214 # m
system.l2c.ReadExReq_miss_rate::cpu1.data 0.408162 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.408162 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.409130 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 0.409130 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.013440 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.inst 0.013440 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.528546 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.528545 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.016599 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.016599 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.173958 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.173958 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.352808 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.352807 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.013440 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.inst 0.013440 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.528546 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.528545 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.016599 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.016599 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.173958 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.173958 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.352808 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.352807 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
@ -282,8 +440,8 @@ system.cpu0.num_fp_register_writes 150767 # nu
system.cpu0.num_mem_refs 15124548 # number of memory refs system.cpu0.num_mem_refs 15124548 # number of memory refs
system.cpu0.num_load_insts 9178366 # Number of load instructions system.cpu0.num_load_insts 9178366 # Number of load instructions
system.cpu0.num_store_insts 5946182 # Number of store instructions system.cpu0.num_store_insts 5946182 # Number of store instructions
system.cpu0.num_idle_cycles 3683454679.572560 # Number of idle cycles system.cpu0.num_idle_cycles 3683454681.836560 # Number of idle cycles
system.cpu0.num_busy_cycles 57196203.427440 # Number of busy cycles system.cpu0.num_busy_cycles 57196201.163440 # Number of busy cycles
system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed
@ -449,39 +607,39 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan
system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 1978242 # number of replacements system.cpu0.dcache.replacements 1978248 # number of replacements
system.cpu0.dcache.tagsinuse 507.129590 # Cycle average of tags in use system.cpu0.dcache.tagsinuse 507.129590 # Cycle average of tags in use
system.cpu0.dcache.total_refs 13113201 # Total number of references to valid blocks. system.cpu0.dcache.total_refs 13113195 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 1978754 # Sample count of references to valid blocks. system.cpu0.dcache.sampled_refs 1978760 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 6.626999 # Average number of references to valid blocks. system.cpu0.dcache.avg_refs 6.626976 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data 507.129590 # Average occupied blocks per requestor system.cpu0.dcache.occ_blocks::cpu0.data 507.129590 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.990487 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::cpu0.data 0.990487 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.990487 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.990487 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 7292600 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu0.data 7292594 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 7292600 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 7292594 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 5457787 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 5457787 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 5457787 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 5457787 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 171977 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 171977 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 171977 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 171977 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186443 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186443 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 186443 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 186443 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 12750387 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::cpu0.data 12750381 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 12750387 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 12750381 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 12750387 # number of overall hits system.cpu0.dcache.overall_hits::cpu0.data 12750381 # number of overall hits
system.cpu0.dcache.overall_hits::total 12750387 # number of overall hits system.cpu0.dcache.overall_hits::total 12750381 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 1683130 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::cpu0.data 1683136 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 1683130 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 1683136 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 285798 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 285798 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 285798 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 285798 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16152 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16152 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 16152 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 16152 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 726 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 726 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 726 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 726 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 1968928 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::cpu0.data 1968934 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 1968928 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 1968934 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 1968928 # number of overall misses system.cpu0.dcache.overall_misses::cpu0.data 1968934 # number of overall misses
system.cpu0.dcache.overall_misses::total 1968928 # number of overall misses system.cpu0.dcache.overall_misses::total 1968934 # number of overall misses
system.cpu0.dcache.ReadReq_accesses::cpu0.data 8975730 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::cpu0.data 8975730 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 8975730 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 8975730 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5743585 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 5743585 # number of WriteReq accesses(hits+misses)
@ -494,8 +652,8 @@ system.cpu0.dcache.demand_accesses::cpu0.data 14719315
system.cpu0.dcache.demand_accesses::total 14719315 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 14719315 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 14719315 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.data 14719315 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 14719315 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 14719315 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187520 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187521 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.187520 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.187521 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049760 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049760 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.049760 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.049760 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085856 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085856 # miss rate for LoadLockedReq accesses

244
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 1.829331 # Nu
sim_ticks 1829330593000 # Number of ticks simulated sim_ticks 1829330593000 # Number of ticks simulated
final_tick 1829330593000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 1829330593000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2569577 # Simulator instruction rate (inst/s) host_inst_rate 1577718 # Simulator instruction rate (inst/s)
host_op_rate 2569575 # Simulator op (including micro ops) rate (op/s) host_op_rate 1577717 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 78294086451 # Simulator tick rate (ticks/s) host_tick_rate 48072530632 # Simulator tick rate (ticks/s)
host_mem_usage 295292 # Number of bytes of host memory used host_mem_usage 294780 # Number of bytes of host memory used
host_seconds 23.37 # Real time elapsed on the host host_seconds 38.05 # Real time elapsed on the host
sim_insts 60037737 # Number of instructions simulated sim_insts 60037737 # Number of instructions simulated
sim_ops 60037737 # Number of ops (including micro ops) simulated sim_ops 60037737 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 857856 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 857856 # Number of bytes read from this memory
@ -38,6 +38,164 @@ system.physmem.bw_total::cpu.inst 468945 # To
system.physmem.bw_total::cpu.data 36537571 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 36537571 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1449868 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1449868 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 42507667 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 42507667 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 0 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 0 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 0 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 0 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 0 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 0 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
system.physmem.totBusLat 0 # Total cycles spent in databus access
system.physmem.totBankLat 0 # Total cycles spent in bank access
system.physmem.avgQLat nan # Average queueing delay per request
system.physmem.avgBankLat nan # Average bank access latency per request
system.physmem.avgBusLat nan # Average bus latency per request
system.physmem.avgMemAccLat nan # Average memory access latency
system.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.00 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 0 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate nan # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap nan # Average gap between requests
system.iocache.replacements 41686 # number of replacements system.iocache.replacements 41686 # number of replacements
system.iocache.tagsinuse 1.225558 # Cycle average of tags in use system.iocache.tagsinuse 1.225558 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.total_refs 0 # Total number of references to valid blocks.
@ -144,8 +302,8 @@ system.cpu.num_fp_register_writes 166520 # nu
system.cpu.num_mem_refs 16115688 # number of memory refs system.cpu.num_mem_refs 16115688 # number of memory refs
system.cpu.num_load_insts 9747503 # Number of load instructions system.cpu.num_load_insts 9747503 # Number of load instructions
system.cpu.num_store_insts 6368185 # Number of store instructions system.cpu.num_store_insts 6368185 # Number of store instructions
system.cpu.num_idle_cycles 3598606247.544791 # Number of idle cycles system.cpu.num_idle_cycles 3598606250.520791 # Number of idle cycles
system.cpu.num_busy_cycles 60054830.455209 # Number of busy cycles system.cpu.num_busy_cycles 60054827.479209 # Number of busy cycles
system.cpu.not_idle_fraction 0.016414 # Percentage of non-idle cycles system.cpu.not_idle_fraction 0.016414 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.983586 # Percentage of idle cycles system.cpu.idle_fraction 0.983586 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.arm 0 # number of arm instructions executed
@ -306,37 +464,37 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2042708 # number of replacements system.cpu.dcache.replacements 2042707 # number of replacements
system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use
system.cpu.dcache.total_refs 14038404 # Total number of references to valid blocks. system.cpu.dcache.total_refs 14038405 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2043220 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 2043219 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 6.870726 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 6.870729 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 7807768 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 7807769 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 7807768 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 7807769 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 5848199 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 5848199 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 5848199 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 5848199 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 199281 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 199281 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 199281 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 199281 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 13655967 # number of demand (read+write) hits system.cpu.dcache.demand_hits::cpu.data 13655968 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 13655967 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 13655968 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 13655967 # number of overall hits system.cpu.dcache.overall_hits::cpu.data 13655968 # number of overall hits
system.cpu.dcache.overall_hits::total 13655967 # number of overall hits system.cpu.dcache.overall_hits::total 13655968 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1721710 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::cpu.data 1721709 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1721710 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1721709 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 304365 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::cpu.data 304365 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 304365 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 304365 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 2026075 # number of demand (read+write) misses system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2026075 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2026075 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses
system.cpu.dcache.overall_misses::total 2026075 # number of overall misses system.cpu.dcache.overall_misses::total 2026074 # number of overall misses
system.cpu.dcache.ReadReq_accesses::cpu.data 9529478 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 9529478 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 9529478 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 9529478 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6152564 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6152564 # number of WriteReq accesses(hits+misses)
@ -372,20 +530,20 @@ system.cpu.dcache.writebacks::total 833491 # nu
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 992297 # number of replacements system.cpu.l2cache.replacements 992297 # number of replacements
system.cpu.l2cache.tagsinuse 65424.375500 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 65424.375500 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2433229 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 2433228 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 1057460 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 1057460 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.301013 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 2.301012 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 56309.097195 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::writebacks 56309.097197 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 4867.351144 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 4867.351143 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 4247.927161 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 4247.927159 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.998297 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.998297 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 906782 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 906782 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 811232 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 811231 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1718014 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1718013 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 833491 # number of Writeback hits system.cpu.l2cache.Writeback_hits::writebacks 833491 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 833491 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 833491 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
@ -393,11 +551,11 @@ system.cpu.l2cache.UpgradeReq_hits::total 4 # n
system.cpu.l2cache.ReadExReq_hits::cpu.data 187234 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 187234 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 187234 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 187234 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 906782 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.inst 906782 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 998466 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 998465 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1905248 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1905247 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 906782 # number of overall hits system.cpu.l2cache.overall_hits::cpu.inst 906782 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 998466 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 998465 # number of overall hits
system.cpu.l2cache.overall_hits::total 1905248 # number of overall hits system.cpu.l2cache.overall_hits::total 1905247 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 13404 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 13404 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 941044 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 941044 # number of ReadReq misses
@ -412,8 +570,8 @@ system.cpu.l2cache.overall_misses::cpu.inst 13404 #
system.cpu.l2cache.overall_misses::cpu.data 1044755 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1044755 # number of overall misses
system.cpu.l2cache.overall_misses::total 1058159 # number of overall misses system.cpu.l2cache.overall_misses::total 1058159 # number of overall misses
system.cpu.l2cache.ReadReq_accesses::cpu.inst 920186 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 920186 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1738872 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1738871 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2659058 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 2659057 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 833491 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 833491 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses)
@ -421,23 +579,23 @@ system.cpu.l2cache.UpgradeReq_accesses::total 16
system.cpu.l2cache.ReadExReq_accesses::cpu.data 304349 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 304349 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 304349 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 304349 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 920186 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.inst 920186 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2043221 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2043220 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2963407 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 2963406 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 920186 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 920186 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2043221 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2043220 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2963407 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 2963406 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014567 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014567 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533472 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533473 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.353901 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.353901 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384805 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384805 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.384805 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.384805 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014567 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014567 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.511327 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.511328 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.357075 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.357075 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014567 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014567 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.511327 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.511328 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.357075 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.357075 # miss rate for overall accesses
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked

1986
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
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File diff suppressed because it is too large Load diff

1066
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
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File diff suppressed because it is too large Load diff

168
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.912097 # Nu
sim_ticks 912096763500 # Number of ticks simulated sim_ticks 912096763500 # Number of ticks simulated
final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1783031 # Simulator instruction rate (inst/s) host_inst_rate 1752000 # Simulator instruction rate (inst/s)
host_op_rate 2295648 # Simulator op (including micro ops) rate (op/s) host_op_rate 2255696 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 26389770183 # Simulator tick rate (ticks/s) host_tick_rate 25930494646 # Simulator tick rate (ticks/s)
host_mem_usage 380112 # Number of bytes of host memory used host_mem_usage 382232 # Number of bytes of host memory used
host_seconds 34.56 # Real time elapsed on the host host_seconds 35.17 # Real time elapsed on the host
sim_insts 61625970 # Number of instructions simulated sim_insts 61625970 # Number of instructions simulated
sim_ops 79343340 # Number of ops (including micro ops) simulated sim_ops 79343340 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory
@ -66,6 +66,164 @@ system.physmem.bw_total::cpu1.dtb.walker 211 # To
system.physmem.bw_total::cpu1.inst 235234 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 235234 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 6988969 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 6988969 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 62341162 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 62341162 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 0 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 0 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 0 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 0 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 0 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 0 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
system.physmem.totBusLat 0 # Total cycles spent in databus access
system.physmem.totBankLat 0 # Total cycles spent in bank access
system.physmem.avgQLat nan # Average queueing delay per request
system.physmem.avgBankLat nan # Average bank access latency per request
system.physmem.avgBusLat nan # Average bus latency per request
system.physmem.avgMemAccLat nan # Average memory access latency
system.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.00 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 0 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate nan # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap nan # Average gap between requests
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory

384
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 2.332810 # Nu
sim_ticks 2332810264000 # Number of ticks simulated sim_ticks 2332810264000 # Number of ticks simulated
final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1681370 # Simulator instruction rate (inst/s) host_inst_rate 1184768 # Simulator instruction rate (inst/s)
host_op_rate 2162138 # Simulator op (including micro ops) rate (op/s) host_op_rate 1523538 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 64929680145 # Simulator tick rate (ticks/s) host_tick_rate 45752340761 # Simulator tick rate (ticks/s)
host_mem_usage 380112 # Number of bytes of host memory used host_mem_usage 382236 # Number of bytes of host memory used
host_seconds 35.93 # Real time elapsed on the host host_seconds 50.99 # Real time elapsed on the host
sim_insts 60408639 # Number of instructions simulated sim_insts 60408639 # Number of instructions simulated
sim_ops 77681819 # Number of ops (including micro ops) simulated sim_ops 77681819 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
@ -49,6 +49,164 @@ system.physmem.bw_total::cpu.itb.walker 82 # To
system.physmem.bw_total::cpu.inst 302262 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 302262 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5181496 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5181496 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 54942169 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 54942169 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 0 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 0 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 0 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 0 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 0 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 0 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
system.physmem.totBusLat 0 # Total cycles spent in databus access
system.physmem.totBankLat 0 # Total cycles spent in bank access
system.physmem.avgQLat nan # Average queueing delay per request
system.physmem.avgBankLat nan # Average bank access latency per request
system.physmem.avgBusLat nan # Average bus latency per request
system.physmem.avgMemAccLat nan # Average memory access latency
system.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.00 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 0 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate nan # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap nan # Average gap between requests
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
@ -61,114 +219,6 @@ system.realview.nvmem.bw_inst_read::cpu.inst 9
system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
system.cpu.l2cache.replacements 62243 # number of replacements
system.cpu.l2cache.tagsinuse 50007.272909 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1669922 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 127628 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 13.084292 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 36899.582990 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 7014.720482 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 6089.015357 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.763050 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7507 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3129 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 838871 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 366771 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1216278 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 592643 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 592643 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 113739 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 113739 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 7507 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 3129 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 838871 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 480510 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1330017 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 7507 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 3129 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 838871 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 480510 # number of overall hits
system.cpu.l2cache.overall_hits::total 1330017 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst 10604 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 9871 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 20483 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2919 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 2919 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 133468 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 133468 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 10604 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 143339 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 153951 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 10604 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 143339 # number of overall misses
system.cpu.l2cache.overall_misses::total 153951 # number of overall misses
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7512 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3132 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 849475 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 376642 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1236761 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 592643 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 592643 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2945 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2945 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247207 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 247207 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7512 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3132 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 849475 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 623849 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1483968 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7512 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3132 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 849475 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 623849 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1483968 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000666 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000958 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012483 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026208 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.016562 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991171 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539904 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.539904 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000666 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000958 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012483 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.229766 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.103743 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000666 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000958 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012483 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.229766 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.103743 # miss rate for overall accesses
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 57863 # number of writebacks
system.cpu.l2cache.writebacks::total 57863 # number of writebacks
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
@ -347,6 +397,114 @@ system.cpu.dcache.cache_copies 0 # nu
system.cpu.dcache.writebacks::writebacks 592643 # number of writebacks system.cpu.dcache.writebacks::writebacks 592643 # number of writebacks
system.cpu.dcache.writebacks::total 592643 # number of writebacks system.cpu.dcache.writebacks::total 592643 # number of writebacks
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 62243 # number of replacements
system.cpu.l2cache.tagsinuse 50007.272909 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1669922 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 127628 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 13.084292 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 36899.582990 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 7014.720482 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 6089.015357 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.763050 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7507 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3129 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 838871 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 366771 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1216278 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 592643 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 592643 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 113739 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 113739 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 7507 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 3129 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 838871 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 480510 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1330017 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 7507 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 3129 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 838871 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 480510 # number of overall hits
system.cpu.l2cache.overall_hits::total 1330017 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst 10604 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 9871 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 20483 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2919 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 2919 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 133468 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 133468 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 10604 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 143339 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 153951 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 10604 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 143339 # number of overall misses
system.cpu.l2cache.overall_misses::total 153951 # number of overall misses
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7512 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3132 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 849475 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 376642 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1236761 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 592643 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 592643 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2945 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2945 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247207 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 247207 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7512 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3132 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 849475 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 623849 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1483968 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7512 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3132 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 849475 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 623849 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1483968 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000666 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000958 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012483 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026208 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.016562 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991171 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539904 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.539904 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000666 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000958 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012483 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.229766 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.103743 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000666 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000958 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012483 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.229766 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.103743 # miss rate for overall accesses
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 57863 # number of writebacks
system.cpu.l2cache.writebacks::total 57863 # number of writebacks
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.total_refs 0 # Total number of references to valid blocks.

2034
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
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1098
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
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196
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
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@ -4,13 +4,13 @@ sim_seconds 5.112041 # Nu
sim_ticks 5112040968500 # Number of ticks simulated sim_ticks 5112040968500 # Number of ticks simulated
final_tick 5112040968500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 5112040968500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 923075 # Simulator instruction rate (inst/s) host_inst_rate 468346 # Simulator instruction rate (inst/s)
host_op_rate 1890063 # Simulator op (including micro ops) rate (op/s) host_op_rate 958973 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 23616389220 # Simulator tick rate (ticks/s) host_tick_rate 11982395829 # Simulator tick rate (ticks/s)
host_mem_usage 353316 # Number of bytes of host memory used host_mem_usage 354180 # Number of bytes of host memory used
host_seconds 216.46 # Real time elapsed on the host host_seconds 426.63 # Real time elapsed on the host
sim_insts 199810236 # Number of instructions simulated sim_insts 199810236 # Number of instructions simulated
sim_ops 409125915 # Number of ops (including micro ops) simulated sim_ops 409125920 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2464640 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 2464640 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
@ -46,6 +46,164 @@ system.physmem.bw_total::cpu.itb.walker 63 # To
system.physmem.bw_total::cpu.inst 167022 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 167022 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2073561 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2073561 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4540583 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 4540583 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 0 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 0 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 0 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 0 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 0 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 0 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
system.physmem.totBusLat 0 # Total cycles spent in databus access
system.physmem.totBankLat 0 # Total cycles spent in bank access
system.physmem.avgQLat nan # Average queueing delay per request
system.physmem.avgBankLat nan # Average bank access latency per request
system.physmem.avgBusLat nan # Average bus latency per request
system.physmem.avgMemAccLat nan # Average memory access latency
system.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.00 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 0 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate nan # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap nan # Average gap between requests
system.iocache.replacements 47569 # number of replacements system.iocache.replacements 47569 # number of replacements
system.iocache.tagsinuse 0.042402 # Cycle average of tags in use system.iocache.tagsinuse 0.042402 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.total_refs 0 # Total number of references to valid blocks.
@ -106,22 +264,22 @@ system.cpu.numCycles 10224081960 # nu
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 199810236 # Number of instructions committed system.cpu.committedInsts 199810236 # Number of instructions committed
system.cpu.committedOps 409125915 # Number of ops (including micro ops) committed system.cpu.committedOps 409125920 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 374289906 # Number of integer alu accesses system.cpu.num_int_alu_accesses 374289911 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 39954535 # number of instructions that are conditional controls system.cpu.num_conditional_control_insts 39954536 # number of instructions that are conditional controls
system.cpu.num_int_insts 374289906 # number of integer instructions system.cpu.num_int_insts 374289911 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 915450684 # number of times the integer registers were read system.cpu.num_int_register_reads 915450709 # number of times the integer registers were read
system.cpu.num_int_register_writes 480322735 # number of times the integer registers were written system.cpu.num_int_register_writes 480322748 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 35624588 # number of memory refs system.cpu.num_mem_refs 35624588 # number of memory refs
system.cpu.num_load_insts 27216588 # Number of load instructions system.cpu.num_load_insts 27216588 # Number of load instructions
system.cpu.num_store_insts 8408000 # Number of store instructions system.cpu.num_store_insts 8408000 # Number of store instructions
system.cpu.num_idle_cycles 9770609605.299961 # Number of idle cycles system.cpu.num_idle_cycles 9770609595.971962 # Number of idle cycles
system.cpu.num_busy_cycles 453472354.700038 # Number of busy cycles system.cpu.num_busy_cycles 453472364.028039 # Number of busy cycles
system.cpu.not_idle_fraction 0.044353 # Percentage of non-idle cycles system.cpu.not_idle_fraction 0.044353 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.955647 # Percentage of idle cycles system.cpu.idle_fraction 0.955647 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.arm 0 # number of arm instructions executed
@ -173,7 +331,7 @@ system.cpu.itb_walker_cache.tagsinuse 3.026483 # Cy
system.cpu.itb_walker_cache.total_refs 8029 # Total number of references to valid blocks. system.cpu.itb_walker_cache.total_refs 8029 # Total number of references to valid blocks.
system.cpu.itb_walker_cache.sampled_refs 3346 # Sample count of references to valid blocks. system.cpu.itb_walker_cache.sampled_refs 3346 # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.avg_refs 2.399582 # Average number of references to valid blocks. system.cpu.itb_walker_cache.avg_refs 2.399582 # Average number of references to valid blocks.
system.cpu.itb_walker_cache.warmup_cycle 5102019603000 # Cycle when the warmup percentage was hit. system.cpu.itb_walker_cache.warmup_cycle 5102019608500 # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026483 # Average occupied blocks per requestor system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026483 # Average occupied blocks per requestor
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189155 # Average percentage of cache occupancy system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189155 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.occ_percent::total 0.189155 # Average percentage of cache occupancy system.cpu.itb_walker_cache.occ_percent::total 0.189155 # Average percentage of cache occupancy
@ -221,7 +379,7 @@ system.cpu.dtb_walker_cache.tagsinuse 5.013746 # Cy
system.cpu.dtb_walker_cache.total_refs 13015 # Total number of references to valid blocks. system.cpu.dtb_walker_cache.total_refs 13015 # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.sampled_refs 7611 # Sample count of references to valid blocks. system.cpu.dtb_walker_cache.sampled_refs 7611 # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.avg_refs 1.710025 # Average number of references to valid blocks. system.cpu.dtb_walker_cache.avg_refs 1.710025 # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.warmup_cycle 5101206381500 # Cycle when the warmup percentage was hit. system.cpu.dtb_walker_cache.warmup_cycle 5101206384000 # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013746 # Average occupied blocks per requestor system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013746 # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313359 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313359 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.occ_percent::total 0.313359 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.occ_percent::total 0.313359 # Average percentage of cache occupancy
@ -313,7 +471,7 @@ system.cpu.dcache.writebacks::writebacks 1534848 # nu
system.cpu.dcache.writebacks::total 1534848 # number of writebacks system.cpu.dcache.writebacks::total 1534848 # number of writebacks
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 106558 # number of replacements system.cpu.l2cache.replacements 106558 # number of replacements
system.cpu.l2cache.tagsinuse 64822.149249 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 64822.149247 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3456224 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 3456224 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 170677 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 170677 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 20.250086 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 20.250086 # Average number of references to valid blocks.
@ -321,8 +479,8 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
system.cpu.l2cache.occ_blocks::writebacks 51981.453140 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::writebacks 51981.453140 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132114 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132114 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 2434.994085 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 2434.994083 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 10405.564956 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 10405.564957 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy

1368
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
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786
tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
View file

@ -2,44 +2,202 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.200392 # Number of seconds simulated sim_seconds 0.200392 # Number of seconds simulated
sim_ticks 200392337000 # Number of ticks simulated sim_ticks 200392337000 # Number of ticks simulated
final_tick 4320161594000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 4320161528000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 246693534 # Simulator instruction rate (inst/s) host_inst_rate 90899186 # Simulator instruction rate (inst/s)
host_op_rate 246690485 # Simulator op (including micro ops) rate (op/s) host_op_rate 90898450 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 182041258854 # Simulator tick rate (ticks/s) host_tick_rate 67078334403 # Simulator tick rate (ticks/s)
host_mem_usage 459700 # Number of bytes of host memory used host_mem_usage 463260 # Number of bytes of host memory used
host_seconds 1.10 # Real time elapsed on the host host_seconds 2.99 # Real time elapsed on the host
sim_insts 271555592 # Number of instructions simulated sim_insts 271551386 # Number of instructions simulated
sim_ops 271555592 # Number of ops (including micro ops) simulated sim_ops 271551386 # Number of ops (including micro ops) simulated
testsys.physmem.bytes_read::cpu.inst 13229896 # Number of bytes read from this memory testsys.physmem.bytes_read::cpu.inst 13230208 # Number of bytes read from this memory
testsys.physmem.bytes_read::cpu.data 4514804 # Number of bytes read from this memory testsys.physmem.bytes_read::cpu.data 4514888 # Number of bytes read from this memory
testsys.physmem.bytes_read::tsunami.ethernet 1464 # Number of bytes read from this memory testsys.physmem.bytes_read::tsunami.ethernet 1464 # Number of bytes read from this memory
testsys.physmem.bytes_read::total 17746164 # Number of bytes read from this memory testsys.physmem.bytes_read::total 17746560 # Number of bytes read from this memory
testsys.physmem.bytes_inst_read::cpu.inst 13229896 # Number of instructions bytes read from this memory testsys.physmem.bytes_inst_read::cpu.inst 13230208 # Number of instructions bytes read from this memory
testsys.physmem.bytes_inst_read::total 13229896 # Number of instructions bytes read from this memory testsys.physmem.bytes_inst_read::total 13230208 # Number of instructions bytes read from this memory
testsys.physmem.bytes_written::cpu.data 3697636 # Number of bytes written to this memory testsys.physmem.bytes_written::cpu.data 3697656 # Number of bytes written to this memory
testsys.physmem.bytes_written::tsunami.ethernet 902 # Number of bytes written to this memory testsys.physmem.bytes_written::tsunami.ethernet 902 # Number of bytes written to this memory
testsys.physmem.bytes_written::total 3698538 # Number of bytes written to this memory testsys.physmem.bytes_written::total 3698558 # Number of bytes written to this memory
testsys.physmem.num_reads::cpu.inst 3307474 # Number of read requests responded to by this memory testsys.physmem.num_reads::cpu.inst 3307552 # Number of read requests responded to by this memory
testsys.physmem.num_reads::cpu.data 615757 # Number of read requests responded to by this memory testsys.physmem.num_reads::cpu.data 615769 # Number of read requests responded to by this memory
testsys.physmem.num_reads::tsunami.ethernet 43 # Number of read requests responded to by this memory testsys.physmem.num_reads::tsunami.ethernet 43 # Number of read requests responded to by this memory
testsys.physmem.num_reads::total 3923274 # Number of read requests responded to by this memory testsys.physmem.num_reads::total 3923364 # Number of read requests responded to by this memory
testsys.physmem.num_writes::cpu.data 478509 # Number of write requests responded to by this memory testsys.physmem.num_writes::cpu.data 478513 # Number of write requests responded to by this memory
testsys.physmem.num_writes::tsunami.ethernet 31 # Number of write requests responded to by this memory testsys.physmem.num_writes::tsunami.ethernet 31 # Number of write requests responded to by this memory
testsys.physmem.num_writes::total 478540 # Number of write requests responded to by this memory testsys.physmem.num_writes::total 478544 # Number of write requests responded to by this memory
testsys.physmem.bw_read::cpu.inst 66019970 # Total read bandwidth from this memory (bytes/s) testsys.physmem.bw_read::cpu.inst 66021527 # Total read bandwidth from this memory (bytes/s)
testsys.physmem.bw_read::cpu.data 22529824 # Total read bandwidth from this memory (bytes/s) testsys.physmem.bw_read::cpu.data 22530243 # Total read bandwidth from this memory (bytes/s)
testsys.physmem.bw_read::tsunami.ethernet 7306 # Total read bandwidth from this memory (bytes/s) testsys.physmem.bw_read::tsunami.ethernet 7306 # Total read bandwidth from this memory (bytes/s)
testsys.physmem.bw_read::total 88557099 # Total read bandwidth from this memory (bytes/s) testsys.physmem.bw_read::total 88559075 # Total read bandwidth from this memory (bytes/s)
testsys.physmem.bw_inst_read::cpu.inst 66019970 # Instruction read bandwidth from this memory (bytes/s) testsys.physmem.bw_inst_read::cpu.inst 66021527 # Instruction read bandwidth from this memory (bytes/s)
testsys.physmem.bw_inst_read::total 66019970 # Instruction read bandwidth from this memory (bytes/s) testsys.physmem.bw_inst_read::total 66021527 # Instruction read bandwidth from this memory (bytes/s)
testsys.physmem.bw_write::cpu.data 18451983 # Write bandwidth from this memory (bytes/s) testsys.physmem.bw_write::cpu.data 18452083 # Write bandwidth from this memory (bytes/s)
testsys.physmem.bw_write::tsunami.ethernet 4501 # Write bandwidth from this memory (bytes/s) testsys.physmem.bw_write::tsunami.ethernet 4501 # Write bandwidth from this memory (bytes/s)
testsys.physmem.bw_write::total 18456484 # Write bandwidth from this memory (bytes/s) testsys.physmem.bw_write::total 18456584 # Write bandwidth from this memory (bytes/s)
testsys.physmem.bw_total::cpu.inst 66019970 # Total bandwidth to/from this memory (bytes/s) testsys.physmem.bw_total::cpu.inst 66021527 # Total bandwidth to/from this memory (bytes/s)
testsys.physmem.bw_total::cpu.data 40981807 # Total bandwidth to/from this memory (bytes/s) testsys.physmem.bw_total::cpu.data 40982326 # Total bandwidth to/from this memory (bytes/s)
testsys.physmem.bw_total::tsunami.ethernet 11807 # Total bandwidth to/from this memory (bytes/s) testsys.physmem.bw_total::tsunami.ethernet 11807 # Total bandwidth to/from this memory (bytes/s)
testsys.physmem.bw_total::total 107013583 # Total bandwidth to/from this memory (bytes/s) testsys.physmem.bw_total::total 107015659 # Total bandwidth to/from this memory (bytes/s)
testsys.physmem.readReqs 0 # Total number of read requests seen
testsys.physmem.writeReqs 0 # Total number of write requests seen
testsys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
testsys.physmem.bytesRead 0 # Total number of bytes read from memory
testsys.physmem.bytesWritten 0 # Total number of bytes written to memory
testsys.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
testsys.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
testsys.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
testsys.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
testsys.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
testsys.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
testsys.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
testsys.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
testsys.physmem.totGap 0 # Total gap between requests
testsys.physmem.readPktSize::0 0 # Categorize read packet sizes
testsys.physmem.readPktSize::1 0 # Categorize read packet sizes
testsys.physmem.readPktSize::2 0 # Categorize read packet sizes
testsys.physmem.readPktSize::3 0 # Categorize read packet sizes
testsys.physmem.readPktSize::4 0 # Categorize read packet sizes
testsys.physmem.readPktSize::5 0 # Categorize read packet sizes
testsys.physmem.readPktSize::6 0 # Categorize read packet sizes
testsys.physmem.readPktSize::7 0 # Categorize read packet sizes
testsys.physmem.readPktSize::8 0 # Categorize read packet sizes
testsys.physmem.writePktSize::0 0 # categorize write packet sizes
testsys.physmem.writePktSize::1 0 # categorize write packet sizes
testsys.physmem.writePktSize::2 0 # categorize write packet sizes
testsys.physmem.writePktSize::3 0 # categorize write packet sizes
testsys.physmem.writePktSize::4 0 # categorize write packet sizes
testsys.physmem.writePktSize::5 0 # categorize write packet sizes
testsys.physmem.writePktSize::6 0 # categorize write packet sizes
testsys.physmem.writePktSize::7 0 # categorize write packet sizes
testsys.physmem.writePktSize::8 0 # categorize write packet sizes
testsys.physmem.neitherpktsize::0 0 # categorize neither packet sizes
testsys.physmem.neitherpktsize::1 0 # categorize neither packet sizes
testsys.physmem.neitherpktsize::2 0 # categorize neither packet sizes
testsys.physmem.neitherpktsize::3 0 # categorize neither packet sizes
testsys.physmem.neitherpktsize::4 0 # categorize neither packet sizes
testsys.physmem.neitherpktsize::5 0 # categorize neither packet sizes
testsys.physmem.neitherpktsize::6 0 # categorize neither packet sizes
testsys.physmem.neitherpktsize::7 0 # categorize neither packet sizes
testsys.physmem.neitherpktsize::8 0 # categorize neither packet sizes
testsys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
testsys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
testsys.physmem.totQLat 0 # Total cycles spent in queuing delays
testsys.physmem.totMemAccLat 0 # Sum of mem lat for all requests
testsys.physmem.totBusLat 0 # Total cycles spent in databus access
testsys.physmem.totBankLat 0 # Total cycles spent in bank access
testsys.physmem.avgQLat nan # Average queueing delay per request
testsys.physmem.avgBankLat nan # Average bank access latency per request
testsys.physmem.avgBusLat nan # Average bus latency per request
testsys.physmem.avgMemAccLat nan # Average memory access latency
testsys.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
testsys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
testsys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
testsys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
testsys.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
testsys.physmem.busUtil 0.00 # Data bus utilization in percentage
testsys.physmem.avgRdQLen 0.00 # Average read queue length over time
testsys.physmem.avgWrQLen 0.00 # Average write queue length over time
testsys.physmem.readRowHits 0 # Number of row buffer hits during reads
testsys.physmem.writeRowHits 0 # Number of row buffer hits during writes
testsys.physmem.readRowHitRate nan # Row buffer hit rate for reads
testsys.physmem.writeRowHitRate nan # Row buffer hit rate for writes
testsys.physmem.avgGap nan # Average gap between requests
testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
@ -56,22 +214,22 @@ testsys.cpu.dtb.fetch_hits 0 # IT
testsys.cpu.dtb.fetch_misses 0 # ITB misses testsys.cpu.dtb.fetch_misses 0 # ITB misses
testsys.cpu.dtb.fetch_acv 0 # ITB acv testsys.cpu.dtb.fetch_acv 0 # ITB acv
testsys.cpu.dtb.fetch_accesses 0 # ITB accesses testsys.cpu.dtb.fetch_accesses 0 # ITB accesses
testsys.cpu.dtb.read_hits 611875 # DTB read hits testsys.cpu.dtb.read_hits 611887 # DTB read hits
testsys.cpu.dtb.read_misses 3287 # DTB read misses testsys.cpu.dtb.read_misses 3287 # DTB read misses
testsys.cpu.dtb.read_acv 80 # DTB read access violations testsys.cpu.dtb.read_acv 80 # DTB read access violations
testsys.cpu.dtb.read_accesses 225414 # DTB read accesses testsys.cpu.dtb.read_accesses 225414 # DTB read accesses
testsys.cpu.dtb.write_hits 478325 # DTB write hits testsys.cpu.dtb.write_hits 478329 # DTB write hits
testsys.cpu.dtb.write_misses 528 # DTB write misses testsys.cpu.dtb.write_misses 528 # DTB write misses
testsys.cpu.dtb.write_acv 81 # DTB write access violations testsys.cpu.dtb.write_acv 81 # DTB write access violations
testsys.cpu.dtb.write_accesses 109988 # DTB write accesses testsys.cpu.dtb.write_accesses 109988 # DTB write accesses
testsys.cpu.dtb.data_hits 1090200 # DTB hits testsys.cpu.dtb.data_hits 1090216 # DTB hits
testsys.cpu.dtb.data_misses 3815 # DTB misses testsys.cpu.dtb.data_misses 3815 # DTB misses
testsys.cpu.dtb.data_acv 161 # DTB access violations testsys.cpu.dtb.data_acv 161 # DTB access violations
testsys.cpu.dtb.data_accesses 335402 # DTB accesses testsys.cpu.dtb.data_accesses 335402 # DTB accesses
testsys.cpu.itb.fetch_hits 1215641 # ITB hits testsys.cpu.itb.fetch_hits 1215659 # ITB hits
testsys.cpu.itb.fetch_misses 1497 # ITB misses testsys.cpu.itb.fetch_misses 1497 # ITB misses
testsys.cpu.itb.fetch_acv 69 # ITB acv testsys.cpu.itb.fetch_acv 69 # ITB acv
testsys.cpu.itb.fetch_accesses 1217138 # ITB accesses testsys.cpu.itb.fetch_accesses 1217156 # ITB accesses
testsys.cpu.itb.read_hits 0 # DTB read hits testsys.cpu.itb.read_hits 0 # DTB read hits
testsys.cpu.itb.read_misses 0 # DTB read misses testsys.cpu.itb.read_misses 0 # DTB read misses
testsys.cpu.itb.read_acv 0 # DTB read access violations testsys.cpu.itb.read_acv 0 # DTB read access violations
@ -84,51 +242,51 @@ testsys.cpu.itb.data_hits 0 # DT
testsys.cpu.itb.data_misses 0 # DTB misses testsys.cpu.itb.data_misses 0 # DTB misses
testsys.cpu.itb.data_acv 0 # DTB access violations testsys.cpu.itb.data_acv 0 # DTB access violations
testsys.cpu.itb.data_accesses 0 # DTB accesses testsys.cpu.itb.data_accesses 0 # DTB accesses
testsys.cpu.numCycles 399134827 # number of cpu cycles simulated testsys.cpu.numCycles 399134959 # number of cpu cycles simulated
testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
testsys.cpu.committedInsts 3303498 # Number of instructions committed testsys.cpu.committedInsts 3303576 # Number of instructions committed
testsys.cpu.committedOps 3303498 # Number of ops (including micro ops) committed testsys.cpu.committedOps 3303576 # Number of ops (including micro ops) committed
testsys.cpu.num_int_alu_accesses 3114409 # Number of integer alu accesses testsys.cpu.num_int_alu_accesses 3114478 # Number of integer alu accesses
testsys.cpu.num_fp_alu_accesses 17380 # Number of float alu accesses testsys.cpu.num_fp_alu_accesses 17380 # Number of float alu accesses
testsys.cpu.num_func_calls 87506 # number of times a function call or return occured testsys.cpu.num_func_calls 87508 # number of times a function call or return occured
testsys.cpu.num_conditional_control_insts 347031 # number of instructions that are conditional controls testsys.cpu.num_conditional_control_insts 347037 # number of instructions that are conditional controls
testsys.cpu.num_int_insts 3114409 # number of integer instructions testsys.cpu.num_int_insts 3114478 # number of integer instructions
testsys.cpu.num_fp_insts 17380 # number of float instructions testsys.cpu.num_fp_insts 17380 # number of float instructions
testsys.cpu.num_int_register_reads 4292439 # number of times the integer registers were read testsys.cpu.num_int_register_reads 4292532 # number of times the integer registers were read
testsys.cpu.num_int_register_writes 2256595 # number of times the integer registers were written testsys.cpu.num_int_register_writes 2256656 # number of times the integer registers were written
testsys.cpu.num_fp_register_reads 11166 # number of times the floating registers were read testsys.cpu.num_fp_register_reads 11166 # number of times the floating registers were read
testsys.cpu.num_fp_register_writes 10823 # number of times the floating registers were written testsys.cpu.num_fp_register_writes 10823 # number of times the floating registers were written
testsys.cpu.num_mem_refs 1099884 # number of memory refs testsys.cpu.num_mem_refs 1099900 # number of memory refs
testsys.cpu.num_load_insts 619431 # Number of load instructions testsys.cpu.num_load_insts 619443 # Number of load instructions
testsys.cpu.num_store_insts 480453 # Number of store instructions testsys.cpu.num_store_insts 480457 # Number of store instructions
testsys.cpu.num_idle_cycles 395839404.829048 # Number of idle cycles testsys.cpu.num_idle_cycles 395839458.060266 # Number of idle cycles
testsys.cpu.num_busy_cycles 3295422.170952 # Number of busy cycles testsys.cpu.num_busy_cycles 3295500.939734 # Number of busy cycles
testsys.cpu.not_idle_fraction 0.008256 # Percentage of non-idle cycles testsys.cpu.not_idle_fraction 0.008257 # Percentage of non-idle cycles
testsys.cpu.idle_fraction 0.991744 # Percentage of idle cycles testsys.cpu.idle_fraction 0.991743 # Percentage of idle cycles
testsys.cpu.kern.inst.arm 0 # number of arm instructions executed testsys.cpu.kern.inst.arm 0 # number of arm instructions executed
testsys.cpu.kern.inst.quiesce 213 # number of quiesce instructions executed testsys.cpu.kern.inst.quiesce 213 # number of quiesce instructions executed
testsys.cpu.kern.inst.hwrei 16709 # number of hwrei instructions executed testsys.cpu.kern.inst.hwrei 16711 # number of hwrei instructions executed
testsys.cpu.kern.ipl_count::0 4122 40.57% 40.57% # number of times we switched to this ipl testsys.cpu.kern.ipl_count::0 4122 40.56% 40.56% # number of times we switched to this ipl
testsys.cpu.kern.ipl_count::21 54 0.53% 41.10% # number of times we switched to this ipl testsys.cpu.kern.ipl_count::21 54 0.53% 41.09% # number of times we switched to this ipl
testsys.cpu.kern.ipl_count::22 205 2.02% 43.12% # number of times we switched to this ipl testsys.cpu.kern.ipl_count::22 205 2.02% 43.11% # number of times we switched to this ipl
testsys.cpu.kern.ipl_count::31 5779 56.88% 100.00% # number of times we switched to this ipl testsys.cpu.kern.ipl_count::31 5781 56.89% 100.00% # number of times we switched to this ipl
testsys.cpu.kern.ipl_count::total 10160 # number of times we switched to this ipl testsys.cpu.kern.ipl_count::total 10162 # number of times we switched to this ipl
testsys.cpu.kern.ipl_good::0 4116 48.47% 48.47% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good::0 4116 48.47% 48.47% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good::21 54 0.64% 49.11% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good::21 54 0.64% 49.11% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good::22 205 2.41% 51.53% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good::22 205 2.41% 51.53% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good::31 4116 48.47% 100.00% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good::31 4116 48.47% 100.00% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good::total 8491 # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good::total 8491 # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_ticks::0 199321085500 99.88% 99.88% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_ticks::0 199321108000 99.88% 99.88% # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_ticks::21 4521000 0.00% 99.88% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_ticks::21 4521000 0.00% 99.88% # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_ticks::22 8815000 0.00% 99.88% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_ticks::22 8815000 0.00% 99.88% # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_ticks::31 233213000 0.12% 100.00% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_ticks::31 233256500 0.12% 100.00% # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_ticks::total 199567634500 # number of cycles we spent at this ipl testsys.cpu.kern.ipl_ticks::total 199567700500 # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_used::0 0.998544 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used::0 0.998544 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.ipl_used::31 0.712234 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used::31 0.711988 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.ipl_used::total 0.835728 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used::total 0.835564 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.syscall::2 3 3.61% 3.61% # number of syscalls executed testsys.cpu.kern.syscall::2 3 3.61% 3.61% # number of syscalls executed
testsys.cpu.kern.syscall::3 7 8.43% 12.05% # number of syscalls executed testsys.cpu.kern.syscall::3 7 8.43% 12.05% # number of syscalls executed
testsys.cpu.kern.syscall::4 1 1.20% 13.25% # number of syscalls executed testsys.cpu.kern.syscall::4 1 1.20% 13.25% # number of syscalls executed
@ -151,16 +309,16 @@ testsys.cpu.kern.syscall::104 1 1.20% 93.98% # nu
testsys.cpu.kern.syscall::105 3 3.61% 97.59% # number of syscalls executed testsys.cpu.kern.syscall::105 3 3.61% 97.59% # number of syscalls executed
testsys.cpu.kern.syscall::118 2 2.41% 100.00% # number of syscalls executed testsys.cpu.kern.syscall::118 2 2.41% 100.00% # number of syscalls executed
testsys.cpu.kern.syscall::total 83 # number of syscalls executed testsys.cpu.kern.syscall::total 83 # number of syscalls executed
testsys.cpu.kern.callpal::swpctx 438 4.02% 4.02% # number of callpals executed testsys.cpu.kern.callpal::swpctx 438 4.01% 4.01% # number of callpals executed
testsys.cpu.kern.callpal::tbi 20 0.18% 4.20% # number of callpals executed testsys.cpu.kern.callpal::tbi 20 0.18% 4.20% # number of callpals executed
testsys.cpu.kern.callpal::swpipl 8990 82.42% 86.62% # number of callpals executed testsys.cpu.kern.callpal::swpipl 8992 82.42% 86.62% # number of callpals executed
testsys.cpu.kern.callpal::rdps 359 3.29% 89.91% # number of callpals executed testsys.cpu.kern.callpal::rdps 359 3.29% 89.91% # number of callpals executed
testsys.cpu.kern.callpal::wrusp 3 0.03% 89.93% # number of callpals executed testsys.cpu.kern.callpal::wrusp 3 0.03% 89.94% # number of callpals executed
testsys.cpu.kern.callpal::rdusp 3 0.03% 89.96% # number of callpals executed testsys.cpu.kern.callpal::rdusp 3 0.03% 89.96% # number of callpals executed
testsys.cpu.kern.callpal::rti 911 8.35% 98.31% # number of callpals executed testsys.cpu.kern.callpal::rti 911 8.35% 98.31% # number of callpals executed
testsys.cpu.kern.callpal::callsys 140 1.28% 99.60% # number of callpals executed testsys.cpu.kern.callpal::callsys 140 1.28% 99.60% # number of callpals executed
testsys.cpu.kern.callpal::imb 44 0.40% 100.00% # number of callpals executed testsys.cpu.kern.callpal::imb 44 0.40% 100.00% # number of callpals executed
testsys.cpu.kern.callpal::total 10908 # number of callpals executed testsys.cpu.kern.callpal::total 10910 # number of callpals executed
testsys.cpu.kern.mode_switch::kernel 1133 # number of protection mode switches testsys.cpu.kern.mode_switch::kernel 1133 # number of protection mode switches
testsys.cpu.kern.mode_switch::user 647 # number of protection mode switches testsys.cpu.kern.mode_switch::user 647 # number of protection mode switches
testsys.cpu.kern.mode_switch::idle 217 # number of protection mode switches testsys.cpu.kern.mode_switch::idle 217 # number of protection mode switches
@ -171,9 +329,9 @@ testsys.cpu.kern.mode_switch_good::kernel 0.575463 # f
testsys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches testsys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
testsys.cpu.kern.mode_switch_good::idle 0.023041 # fraction of useful protection mode switches testsys.cpu.kern.mode_switch_good::idle 0.023041 # fraction of useful protection mode switches
testsys.cpu.kern.mode_switch_good::total 0.652979 # fraction of useful protection mode switches testsys.cpu.kern.mode_switch_good::total 0.652979 # fraction of useful protection mode switches
testsys.cpu.kern.mode_ticks::kernel 931595000 57.07% 57.07% # number of ticks spent at the given mode testsys.cpu.kern.mode_ticks::kernel 931596000 57.08% 57.08% # number of ticks spent at the given mode
testsys.cpu.kern.mode_ticks::user 532793000 32.64% 89.71% # number of ticks spent at the given mode testsys.cpu.kern.mode_ticks::user 532793000 32.64% 89.72% # number of ticks spent at the given mode
testsys.cpu.kern.mode_ticks::idle 168009000 10.29% 100.00% # number of ticks spent at the given mode testsys.cpu.kern.mode_ticks::idle 167721000 10.28% 100.00% # number of ticks spent at the given mode
testsys.cpu.kern.swap_context 438 # number of times the context was actually changed testsys.cpu.kern.swap_context 438 # number of times the context was actually changed
testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted
testsys.tsunami.ethernet.rxBytes 798 # Bytes Received testsys.tsunami.ethernet.rxBytes 798 # Bytes Received
@ -253,6 +411,164 @@ drivesys.physmem.bw_total::cpu.inst 39070237 # To
drivesys.physmem.bw_total::cpu.data 21904410 # Total bandwidth to/from this memory (bytes/s) drivesys.physmem.bw_total::cpu.data 21904410 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.bw_total::tsunami.ethernet 11448 # Total bandwidth to/from this memory (bytes/s) drivesys.physmem.bw_total::tsunami.ethernet 11448 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.bw_total::total 60986094 # Total bandwidth to/from this memory (bytes/s) drivesys.physmem.bw_total::total 60986094 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.readReqs 0 # Total number of read requests seen
drivesys.physmem.writeReqs 0 # Total number of write requests seen
drivesys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
drivesys.physmem.bytesRead 0 # Total number of bytes read from memory
drivesys.physmem.bytesWritten 0 # Total number of bytes written to memory
drivesys.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
drivesys.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
drivesys.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
drivesys.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
drivesys.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
drivesys.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
drivesys.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
drivesys.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
drivesys.physmem.totGap 0 # Total gap between requests
drivesys.physmem.readPktSize::0 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::1 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::2 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::3 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::4 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::5 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::6 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::7 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::8 0 # Categorize read packet sizes
drivesys.physmem.writePktSize::0 0 # categorize write packet sizes
drivesys.physmem.writePktSize::1 0 # categorize write packet sizes
drivesys.physmem.writePktSize::2 0 # categorize write packet sizes
drivesys.physmem.writePktSize::3 0 # categorize write packet sizes
drivesys.physmem.writePktSize::4 0 # categorize write packet sizes
drivesys.physmem.writePktSize::5 0 # categorize write packet sizes
drivesys.physmem.writePktSize::6 0 # categorize write packet sizes
drivesys.physmem.writePktSize::7 0 # categorize write packet sizes
drivesys.physmem.writePktSize::8 0 # categorize write packet sizes
drivesys.physmem.neitherpktsize::0 0 # categorize neither packet sizes
drivesys.physmem.neitherpktsize::1 0 # categorize neither packet sizes
drivesys.physmem.neitherpktsize::2 0 # categorize neither packet sizes
drivesys.physmem.neitherpktsize::3 0 # categorize neither packet sizes
drivesys.physmem.neitherpktsize::4 0 # categorize neither packet sizes
drivesys.physmem.neitherpktsize::5 0 # categorize neither packet sizes
drivesys.physmem.neitherpktsize::6 0 # categorize neither packet sizes
drivesys.physmem.neitherpktsize::7 0 # categorize neither packet sizes
drivesys.physmem.neitherpktsize::8 0 # categorize neither packet sizes
drivesys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
drivesys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
drivesys.physmem.totQLat 0 # Total cycles spent in queuing delays
drivesys.physmem.totMemAccLat 0 # Sum of mem lat for all requests
drivesys.physmem.totBusLat 0 # Total cycles spent in databus access
drivesys.physmem.totBankLat 0 # Total cycles spent in bank access
drivesys.physmem.avgQLat nan # Average queueing delay per request
drivesys.physmem.avgBankLat nan # Average bank access latency per request
drivesys.physmem.avgBusLat nan # Average bus latency per request
drivesys.physmem.avgMemAccLat nan # Average memory access latency
drivesys.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
drivesys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
drivesys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
drivesys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
drivesys.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
drivesys.physmem.busUtil 0.00 # Data bus utilization in percentage
drivesys.physmem.avgRdQLen 0.00 # Average read queue length over time
drivesys.physmem.avgWrQLen 0.00 # Average write queue length over time
drivesys.physmem.readRowHits 0 # Number of row buffer hits during reads
drivesys.physmem.writeRowHits 0 # Number of row buffer hits during writes
drivesys.physmem.readRowHitRate nan # Row buffer hit rate for reads
drivesys.physmem.writeRowHitRate nan # Row buffer hit rate for writes
drivesys.physmem.avgGap nan # Average gap between requests
drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
@ -376,7 +692,7 @@ drivesys.cpu.kern.mode_switch_good::idle 0.018265 # fr
drivesys.cpu.kern.mode_switch_good::total 0.441352 # fraction of useful protection mode switches drivesys.cpu.kern.mode_switch_good::total 0.441352 # fraction of useful protection mode switches
drivesys.cpu.kern.mode_ticks::kernel 66889000 2.31% 2.31% # number of ticks spent at the given mode drivesys.cpu.kern.mode_ticks::kernel 66889000 2.31% 2.31% # number of ticks spent at the given mode
drivesys.cpu.kern.mode_ticks::user 319585750 11.03% 13.34% # number of ticks spent at the given mode drivesys.cpu.kern.mode_ticks::user 319585750 11.03% 13.34% # number of ticks spent at the given mode
drivesys.cpu.kern.mode_ticks::idle 2511439250 86.66% 100.00% # number of ticks spent at the given mode drivesys.cpu.kern.mode_ticks::idle 2511080250 86.66% 100.00% # number of ticks spent at the given mode
drivesys.cpu.kern.swap_context 72 # number of times the context was actually changed drivesys.cpu.kern.swap_context 72 # number of times the context was actually changed
drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted
drivesys.tsunami.ethernet.rxBytes 960 # Bytes Received drivesys.tsunami.ethernet.rxBytes 960 # Bytes Received
@ -433,15 +749,15 @@ drivesys.tsunami.ethernet.droppedPackets 0 # nu
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.000390 # Number of seconds simulated sim_seconds 0.000390 # Number of seconds simulated
sim_ticks 390393500 # Number of ticks simulated sim_ticks 390393500 # Number of ticks simulated
final_tick 4320551987500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 4320551921500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 309018358448 # Simulator instruction rate (inst/s) host_inst_rate 123937139701 # Simulator instruction rate (inst/s)
host_op_rate 304755215914 # Simulator op (including micro ops) rate (op/s) host_op_rate 122659857960 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 428792748186 # Simulator tick rate (ticks/s) host_tick_rate 174562814371 # Simulator tick rate (ticks/s)
host_mem_usage 459700 # Number of bytes of host memory used host_mem_usage 463260 # Number of bytes of host memory used
host_seconds 0.00 # Real time elapsed on the host host_seconds 0.00 # Real time elapsed on the host
sim_insts 271558535 # Number of instructions simulated sim_insts 271554329 # Number of instructions simulated
sim_ops 271558535 # Number of ops (including micro ops) simulated sim_ops 271554329 # Number of ops (including micro ops) simulated
testsys.physmem.bytes_read::cpu.inst 5888 # Number of bytes read from this memory testsys.physmem.bytes_read::cpu.inst 5888 # Number of bytes read from this memory
testsys.physmem.bytes_read::cpu.data 2272 # Number of bytes read from this memory testsys.physmem.bytes_read::cpu.data 2272 # Number of bytes read from this memory
testsys.physmem.bytes_read::total 8160 # Number of bytes read from this memory testsys.physmem.bytes_read::total 8160 # Number of bytes read from this memory
@ -464,6 +780,164 @@ testsys.physmem.bw_write::total 3299235 # Wr
testsys.physmem.bw_total::cpu.inst 15082218 # Total bandwidth to/from this memory (bytes/s) testsys.physmem.bw_total::cpu.inst 15082218 # Total bandwidth to/from this memory (bytes/s)
testsys.physmem.bw_total::cpu.data 9119004 # Total bandwidth to/from this memory (bytes/s) testsys.physmem.bw_total::cpu.data 9119004 # Total bandwidth to/from this memory (bytes/s)
testsys.physmem.bw_total::total 24201223 # Total bandwidth to/from this memory (bytes/s) testsys.physmem.bw_total::total 24201223 # Total bandwidth to/from this memory (bytes/s)
testsys.physmem.readReqs 0 # Total number of read requests seen
testsys.physmem.writeReqs 0 # Total number of write requests seen
testsys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
testsys.physmem.bytesRead 0 # Total number of bytes read from memory
testsys.physmem.bytesWritten 0 # Total number of bytes written to memory
testsys.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
testsys.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
testsys.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
testsys.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
testsys.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
testsys.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
testsys.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
testsys.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
testsys.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
testsys.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
testsys.physmem.totGap 0 # Total gap between requests
testsys.physmem.readPktSize::0 0 # Categorize read packet sizes
testsys.physmem.readPktSize::1 0 # Categorize read packet sizes
testsys.physmem.readPktSize::2 0 # Categorize read packet sizes
testsys.physmem.readPktSize::3 0 # Categorize read packet sizes
testsys.physmem.readPktSize::4 0 # Categorize read packet sizes
testsys.physmem.readPktSize::5 0 # Categorize read packet sizes
testsys.physmem.readPktSize::6 0 # Categorize read packet sizes
testsys.physmem.readPktSize::7 0 # Categorize read packet sizes
testsys.physmem.readPktSize::8 0 # Categorize read packet sizes
testsys.physmem.writePktSize::0 0 # categorize write packet sizes
testsys.physmem.writePktSize::1 0 # categorize write packet sizes
testsys.physmem.writePktSize::2 0 # categorize write packet sizes
testsys.physmem.writePktSize::3 0 # categorize write packet sizes
testsys.physmem.writePktSize::4 0 # categorize write packet sizes
testsys.physmem.writePktSize::5 0 # categorize write packet sizes
testsys.physmem.writePktSize::6 0 # categorize write packet sizes
testsys.physmem.writePktSize::7 0 # categorize write packet sizes
testsys.physmem.writePktSize::8 0 # categorize write packet sizes
testsys.physmem.neitherpktsize::0 0 # categorize neither packet sizes
testsys.physmem.neitherpktsize::1 0 # categorize neither packet sizes
testsys.physmem.neitherpktsize::2 0 # categorize neither packet sizes
testsys.physmem.neitherpktsize::3 0 # categorize neither packet sizes
testsys.physmem.neitherpktsize::4 0 # categorize neither packet sizes
testsys.physmem.neitherpktsize::5 0 # categorize neither packet sizes
testsys.physmem.neitherpktsize::6 0 # categorize neither packet sizes
testsys.physmem.neitherpktsize::7 0 # categorize neither packet sizes
testsys.physmem.neitherpktsize::8 0 # categorize neither packet sizes
testsys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
testsys.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
testsys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
testsys.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
testsys.physmem.totQLat 0 # Total cycles spent in queuing delays
testsys.physmem.totMemAccLat 0 # Sum of mem lat for all requests
testsys.physmem.totBusLat 0 # Total cycles spent in databus access
testsys.physmem.totBankLat 0 # Total cycles spent in bank access
testsys.physmem.avgQLat nan # Average queueing delay per request
testsys.physmem.avgBankLat nan # Average bank access latency per request
testsys.physmem.avgBusLat nan # Average bus latency per request
testsys.physmem.avgMemAccLat nan # Average memory access latency
testsys.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
testsys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
testsys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
testsys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
testsys.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
testsys.physmem.busUtil 0.00 # Data bus utilization in percentage
testsys.physmem.avgRdQLen 0.00 # Average read queue length over time
testsys.physmem.avgWrQLen 0.00 # Average write queue length over time
testsys.physmem.readRowHits 0 # Number of row buffer hits during reads
testsys.physmem.writeRowHits 0 # Number of row buffer hits during writes
testsys.physmem.readRowHitRate nan # Row buffer hit rate for reads
testsys.physmem.writeRowHitRate nan # Row buffer hit rate for writes
testsys.physmem.avgGap nan # Average gap between requests
testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
@ -620,6 +1094,164 @@ drivesys.physmem.bw_write::total 3299235 # Wr
drivesys.physmem.bw_total::cpu.inst 15071972 # Total bandwidth to/from this memory (bytes/s) drivesys.physmem.bw_total::cpu.inst 15071972 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.bw_total::cpu.data 9119004 # Total bandwidth to/from this memory (bytes/s) drivesys.physmem.bw_total::cpu.data 9119004 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.bw_total::total 24190977 # Total bandwidth to/from this memory (bytes/s) drivesys.physmem.bw_total::total 24190977 # Total bandwidth to/from this memory (bytes/s)
drivesys.physmem.readReqs 0 # Total number of read requests seen
drivesys.physmem.writeReqs 0 # Total number of write requests seen
drivesys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
drivesys.physmem.bytesRead 0 # Total number of bytes read from memory
drivesys.physmem.bytesWritten 0 # Total number of bytes written to memory
drivesys.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
drivesys.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
drivesys.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
drivesys.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
drivesys.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
drivesys.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
drivesys.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
drivesys.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
drivesys.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
drivesys.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
drivesys.physmem.totGap 0 # Total gap between requests
drivesys.physmem.readPktSize::0 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::1 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::2 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::3 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::4 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::5 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::6 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::7 0 # Categorize read packet sizes
drivesys.physmem.readPktSize::8 0 # Categorize read packet sizes
drivesys.physmem.writePktSize::0 0 # categorize write packet sizes
drivesys.physmem.writePktSize::1 0 # categorize write packet sizes
drivesys.physmem.writePktSize::2 0 # categorize write packet sizes
drivesys.physmem.writePktSize::3 0 # categorize write packet sizes
drivesys.physmem.writePktSize::4 0 # categorize write packet sizes
drivesys.physmem.writePktSize::5 0 # categorize write packet sizes
drivesys.physmem.writePktSize::6 0 # categorize write packet sizes
drivesys.physmem.writePktSize::7 0 # categorize write packet sizes
drivesys.physmem.writePktSize::8 0 # categorize write packet sizes
drivesys.physmem.neitherpktsize::0 0 # categorize neither packet sizes
drivesys.physmem.neitherpktsize::1 0 # categorize neither packet sizes
drivesys.physmem.neitherpktsize::2 0 # categorize neither packet sizes
drivesys.physmem.neitherpktsize::3 0 # categorize neither packet sizes
drivesys.physmem.neitherpktsize::4 0 # categorize neither packet sizes
drivesys.physmem.neitherpktsize::5 0 # categorize neither packet sizes
drivesys.physmem.neitherpktsize::6 0 # categorize neither packet sizes
drivesys.physmem.neitherpktsize::7 0 # categorize neither packet sizes
drivesys.physmem.neitherpktsize::8 0 # categorize neither packet sizes
drivesys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
drivesys.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
drivesys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
drivesys.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
drivesys.physmem.totQLat 0 # Total cycles spent in queuing delays
drivesys.physmem.totMemAccLat 0 # Sum of mem lat for all requests
drivesys.physmem.totBusLat 0 # Total cycles spent in databus access
drivesys.physmem.totBankLat 0 # Total cycles spent in bank access
drivesys.physmem.avgQLat nan # Average queueing delay per request
drivesys.physmem.avgBankLat nan # Average bank access latency per request
drivesys.physmem.avgBusLat nan # Average bus latency per request
drivesys.physmem.avgMemAccLat nan # Average memory access latency
drivesys.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
drivesys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
drivesys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
drivesys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
drivesys.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
drivesys.physmem.busUtil 0.00 # Data bus utilization in percentage
drivesys.physmem.avgRdQLen 0.00 # Average read queue length over time
drivesys.physmem.avgWrQLen 0.00 # Average write queue length over time
drivesys.physmem.readRowHits 0 # Number of row buffer hits during reads
drivesys.physmem.writeRowHits 0 # Number of row buffer hits during writes
drivesys.physmem.readRowHitRate nan # Row buffer hit rate for reads
drivesys.physmem.writeRowHitRate nan # Row buffer hit rate for writes
drivesys.physmem.avgGap nan # Average gap between requests
drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).

528
tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
View file

@ -1,32 +1,190 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.000022 # Number of seconds simulated sim_seconds 0.000020 # Number of seconds simulated
sim_ticks 21628500 # Number of ticks simulated sim_ticks 19841500 # Number of ticks simulated
final_tick 21628500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 19841500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 34038 # Simulator instruction rate (inst/s) host_inst_rate 31060 # Simulator instruction rate (inst/s)
host_op_rate 34033 # Simulator op (including micro ops) rate (op/s) host_op_rate 31057 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 115179622 # Simulator tick rate (ticks/s) host_tick_rate 96425663 # Simulator tick rate (ticks/s)
host_mem_usage 212112 # Number of bytes of host memory used host_mem_usage 216044 # Number of bytes of host memory used
host_seconds 0.19 # Real time elapsed on the host host_seconds 0.21 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated sim_ops 6390 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory
system.physmem.bytes_read::total 30016 # Number of bytes read from this memory system.physmem.bytes_read::total 29952 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 19264 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 19200 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 19264 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 19200 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
system.physmem.num_reads::total 469 # Number of read requests responded to by this memory system.physmem.num_reads::total 468 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 890676653 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 967668775 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 497121853 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 541894514 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1387798507 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 1509563289 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 890676653 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 967668775 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 890676653 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 967668775 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 890676653 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 967668775 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 497121853 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 541894514 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1387798507 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1509563289 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 469 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 469 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 29952 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 29952 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 50 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 15 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 4 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 26 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 25 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 21 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 3 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 69 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 23 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 33 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 72 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 66 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 45 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 2 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 7 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 19827000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 469 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 0 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 334 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 108 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 1719468 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 11463468 # Sum of mem lat for all requests
system.physmem.totBusLat 1876000 # Total cycles spent in databus access
system.physmem.totBankLat 7868000 # Total cycles spent in bank access
system.physmem.avgQLat 3666.24 # Average queueing delay per request
system.physmem.avgBankLat 16776.12 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 24442.36 # Average memory access latency
system.physmem.avgRdBW 1509.56 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 1509.56 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 9.43 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.58 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 401 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 85.50 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 42275.05 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_acv 0 # ITB acv
@ -60,7 +218,7 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 43258 # number of cpu cycles simulated system.cpu.numCycles 39684 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 1606 # Number of BP lookups system.cpu.branch_predictor.lookups 1606 # Number of BP lookups
@ -90,12 +248,12 @@ system.cpu.execution_unit.executions 4463 # Nu
system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 11927 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.threadCycles 11913 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 526 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 522 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 35855 # Number of cycles cpu's stages were not processed system.cpu.idleCycles 32282 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 7403 # Number of cycles cpu stages are processed. system.cpu.runCycles 7402 # Number of cycles cpu stages are processed.
system.cpu.activity 17.113597 # Percentage of cycles cpu is active system.cpu.activity 18.652354 # Percentage of cycles cpu is active
system.cpu.comLoads 1183 # Number of Load instructions committed system.cpu.comLoads 1183 # Number of Load instructions committed
system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comStores 865 # Number of Store instructions committed
system.cpu.comBranches 1050 # Number of Branches instructions committed system.cpu.comBranches 1050 # Number of Branches instructions committed
@ -107,72 +265,72 @@ system.cpu.committedInsts 6390 # Nu
system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread) system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total) system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total)
system.cpu.cpi 6.769640 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.cpi 6.210329 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 6.769640 # CPI: Total CPI of All Threads system.cpu.cpi_total 6.210329 # CPI: Total CPI of All Threads
system.cpu.ipc 0.147718 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.ipc 0.161022 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.147718 # IPC: Total IPC of All Threads system.cpu.ipc_total 0.161022 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 38346 # Number of cycles 0 instructions are processed. system.cpu.stage0.idleCycles 34772 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 4912 # Number of cycles 1+ instructions are processed. system.cpu.stage0.runCycles 4912 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 11.355125 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage0.utilization 12.377784 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 39380 # Number of cycles 0 instructions are processed. system.cpu.stage1.idleCycles 35806 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 3878 # Number of cycles 1+ instructions are processed. system.cpu.stage1.runCycles 3878 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 8.964816 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage1.utilization 9.772200 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 39087 # Number of cycles 0 instructions are processed. system.cpu.stage2.idleCycles 35512 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 4171 # Number of cycles 1+ instructions are processed. system.cpu.stage2.runCycles 4172 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 9.642147 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage2.utilization 10.513053 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 41918 # Number of cycles 0 instructions are processed. system.cpu.stage3.idleCycles 38344 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 1340 # Number of cycles 1+ instructions are processed. system.cpu.stage3.runCycles 1340 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 3.097693 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage3.utilization 3.376676 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 38800 # Number of cycles 0 instructions are processed. system.cpu.stage4.idleCycles 35226 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed. system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 10.305608 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage4.utilization 11.233747 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 138.677886 # Cycle average of tags in use system.cpu.icache.tagsinuse 142.150123 # Cycle average of tags in use
system.cpu.icache.total_refs 557 # Total number of references to valid blocks. system.cpu.icache.total_refs 558 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1.850498 # Average number of references to valid blocks. system.cpu.icache.avg_refs 1.853821 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 138.677886 # Average occupied blocks per requestor system.cpu.icache.occ_blocks::cpu.inst 142.150123 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.067714 # Average percentage of cache occupancy system.cpu.icache.occ_percent::cpu.inst 0.069409 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.067714 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.069409 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 557 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 558 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 557 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 558 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 557 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 558 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 557 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 558 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 557 # number of overall hits system.cpu.icache.overall_hits::cpu.inst 558 # number of overall hits
system.cpu.icache.overall_hits::total 557 # number of overall hits system.cpu.icache.overall_hits::total 558 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 351 # number of ReadReq misses system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 351 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 351 # number of demand (read+write) misses system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 351 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 351 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses
system.cpu.icache.overall_misses::total 351 # number of overall misses system.cpu.icache.overall_misses::total 350 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 19444500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 17305000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 19444500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 17305000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 19444500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 17305000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 19444500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 17305000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 19444500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 17305000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 19444500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 17305000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 908 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 908 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 908 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 908 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 908 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 908 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 908 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 908 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 908 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 908 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.386564 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.385463 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.386564 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.385463 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.386564 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.385463 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.386564 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.385463 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.386564 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.385463 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.386564 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.385463 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55397.435897 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49442.857143 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 55397.435897 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 49442.857143 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55397.435897 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 49442.857143 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 55397.435897 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 49442.857143 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55397.435897 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 49442.857143 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 55397.435897 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 49442.857143 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -181,46 +339,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 49 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::cpu.inst 48 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 49 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 48 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 49 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 49 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 48 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 49 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 48 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16495000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14791500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 16495000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 14791500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16495000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14791500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 16495000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 14791500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16495000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14791500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 16495000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 14791500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.332599 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.332599 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.332599 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.332599 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.332599 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.332599 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54619.205298 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48978.476821 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54619.205298 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48978.476821 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54619.205298 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48978.476821 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 54619.205298 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 48978.476821 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54619.205298 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48978.476821 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 54619.205298 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 48978.476821 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 102.512660 # Cycle average of tags in use system.cpu.dcache.tagsinuse 104.047429 # Cycle average of tags in use
system.cpu.dcache.total_refs 1700 # Total number of references to valid blocks. system.cpu.dcache.total_refs 1700 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 10.119048 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 10.119048 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 102.512660 # Average occupied blocks per requestor system.cpu.dcache.occ_blocks::cpu.data 104.047429 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.025028 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::cpu.data 0.025402 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.025028 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.025402 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 614 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 614 # number of WriteReq hits
@ -237,14 +395,14 @@ system.cpu.dcache.demand_misses::cpu.data 348 # n
system.cpu.dcache.demand_misses::total 348 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 348 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 348 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 348 # number of overall misses
system.cpu.dcache.overall_misses::total 348 # number of overall misses system.cpu.dcache.overall_misses::total 348 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5810500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 5354000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5810500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 5354000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 13883000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 11296500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 13883000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 11296500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 19693500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 16650500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 19693500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 16650500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 19693500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 16650500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 19693500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 16650500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
@ -261,20 +419,20 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.169922
system.cpu.dcache.demand_miss_rate::total 0.169922 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.169922 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.169922 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.169922 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.169922 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.169922 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59902.061856 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55195.876289 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 59902.061856 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 55195.876289 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55310.756972 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45005.976096 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 55310.756972 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 45005.976096 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56590.517241 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 47846.264368 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 56590.517241 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 47846.264368 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 56590.517241 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 47846.264368 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 56590.517241 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 47846.264368 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 3380 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 2586 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 37 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 37 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 91.351351 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 69.891892 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits
@ -293,14 +451,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168
system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5512000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5078500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5512000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 5078500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4096500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3447000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4096500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3447000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9608500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8525500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 9608500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 8525500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9608500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8525500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 9608500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 8525500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
@ -309,26 +467,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031
system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58021.052632 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53457.894737 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58021.052632 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53457.894737 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56116.438356 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47219.178082 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56116.438356 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47219.178082 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57193.452381 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50747.023810 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 57193.452381 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 50747.023810 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57193.452381 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50747.023810 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 57193.452381 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 50747.023810 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 194.915514 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 199.193487 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 138.751655 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 142.245680 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 56.163860 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 56.947807 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.004234 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.004341 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.001714 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001738 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.005948 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.006079 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
@ -346,17 +504,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu
system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses
system.cpu.l2cache.overall_misses::total 469 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16176500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14473000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5410500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4977000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 21587000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 19450000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4019000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3369500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 4019000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3369500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 16176500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 14473000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 9429500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 8346500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 25606000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 22819500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 16176500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 14473000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 9429500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 8346500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 25606000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 22819500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses)
@ -379,17 +537,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53742.524917 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48083.056478 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56952.631579 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52389.473684 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 54512.626263 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 49116.161616 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55054.794521 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46157.534247 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55054.794521 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46157.534247 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53742.524917 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48083.056478 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56127.976190 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 49681.547619 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 54597.014925 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 48655.650320 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53742.524917 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48083.056478 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56127.976190 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 49681.547619 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 54597.014925 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 48655.650320 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -409,17 +567,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469
system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12511500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10688499 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4259000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3791620 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16770500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14480119 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3141000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2447596 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3141000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2447596 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12511500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10688499 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7400000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6239216 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 19911500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 16927715 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12511500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10688499 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7400000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6239216 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 19911500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 16927715 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses
@ -431,17 +589,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41566.445183 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35509.963455 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44831.578947 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39911.789474 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42349.747475 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36565.957071 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43027.397260 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33528.712329 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43027.397260 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33528.712329 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41566.445183 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35509.963455 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44047.619048 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37138.190476 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42455.223881 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36093.208955 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41566.445183 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35509.963455 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44047.619048 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37138.190476 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42455.223881 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36093.208955 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

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@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.000020 # Number of seconds simulated sim_seconds 0.000019 # Number of seconds simulated
sim_ticks 20184000 # Number of ticks simulated sim_ticks 19373000 # Number of ticks simulated
final_tick 20184000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 19373000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 91753 # Simulator instruction rate (inst/s) host_inst_rate 54522 # Simulator instruction rate (inst/s)
host_op_rate 91718 # Simulator op (including micro ops) rate (op/s) host_op_rate 54510 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 318298211 # Simulator tick rate (ticks/s) host_tick_rate 181593348 # Simulator tick rate (ticks/s)
host_mem_usage 212944 # Number of bytes of host memory used host_mem_usage 216696 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host host_seconds 0.11 # Real time elapsed on the host
sim_insts 5814 # Number of instructions simulated sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated sim_ops 5814 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory
@ -19,14 +19,172 @@ system.physmem.bytes_inst_read::total 20288 # Nu
system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
system.physmem.num_reads::total 455 # Number of read requests responded to by this memory system.physmem.num_reads::total 455 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1005152596 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 1047230682 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 437574316 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 455892221 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1442726912 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 1503122903 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1005152596 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 1047230682 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1005152596 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 1047230682 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1005152596 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 1047230682 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 437574316 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 455892221 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1442726912 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1503122903 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 455 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 455 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 29120 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 29120 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 60 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 27 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 22 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 53 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 5 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 31 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 19 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 40 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 20 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 15 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 16 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 39 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 50 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 30 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 28 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 19298000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 455 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 0 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 311 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 2404453 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 12694453 # Sum of mem lat for all requests
system.physmem.totBusLat 1820000 # Total cycles spent in databus access
system.physmem.totBankLat 8470000 # Total cycles spent in bank access
system.physmem.avgQLat 5284.51 # Average queueing delay per request
system.physmem.avgBankLat 18615.38 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 27899.90 # Average memory access latency
system.physmem.avgRdBW 1503.12 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 1503.12 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 9.39 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.66 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 357 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 78.46 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 42413.19 # Average gap between requests
system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.read_accesses 0 # DTB read accesses
@ -46,7 +204,7 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 8 # Number of system calls system.cpu.workload.num_syscalls 8 # Number of system calls
system.cpu.numCycles 40369 # number of cpu cycles simulated system.cpu.numCycles 38747 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 1146 # Number of BP lookups system.cpu.branch_predictor.lookups 1146 # Number of BP lookups
@ -79,9 +237,9 @@ system.cpu.contextSwitches 1 # Nu
system.cpu.threadCycles 9675 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.threadCycles 9675 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 483 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 483 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 34984 # Number of cycles cpu's stages were not processed system.cpu.idleCycles 33362 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 5385 # Number of cycles cpu stages are processed. system.cpu.runCycles 5385 # Number of cycles cpu stages are processed.
system.cpu.activity 13.339444 # Percentage of cycles cpu is active system.cpu.activity 13.897850 # Percentage of cycles cpu is active
system.cpu.comLoads 1163 # Number of Load instructions committed system.cpu.comLoads 1163 # Number of Load instructions committed
system.cpu.comStores 925 # Number of Store instructions committed system.cpu.comStores 925 # Number of Store instructions committed
system.cpu.comBranches 915 # Number of Branches instructions committed system.cpu.comBranches 915 # Number of Branches instructions committed
@ -93,36 +251,36 @@ system.cpu.committedInsts 5814 # Nu
system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread) system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total) system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total)
system.cpu.cpi 6.943412 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.cpi 6.664431 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 6.943412 # CPI: Total CPI of All Threads system.cpu.cpi_total 6.664431 # CPI: Total CPI of All Threads
system.cpu.ipc 0.144021 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.ipc 0.150050 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.144021 # IPC: Total IPC of All Threads system.cpu.ipc_total 0.150050 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 36744 # Number of cycles 0 instructions are processed. system.cpu.stage0.idleCycles 35122 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 3625 # Number of cycles 1+ instructions are processed. system.cpu.stage0.runCycles 3625 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 8.979663 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage0.utilization 9.355563 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 37547 # Number of cycles 0 instructions are processed. system.cpu.stage1.idleCycles 35925 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 2822 # Number of cycles 1+ instructions are processed. system.cpu.stage1.runCycles 2822 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 6.990513 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage1.utilization 7.283145 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 37585 # Number of cycles 0 instructions are processed. system.cpu.stage2.idleCycles 35963 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 2784 # Number of cycles 1+ instructions are processed. system.cpu.stage2.runCycles 2784 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 6.896381 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage2.utilization 7.185072 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 39127 # Number of cycles 0 instructions are processed. system.cpu.stage3.idleCycles 37505 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 1242 # Number of cycles 1+ instructions are processed. system.cpu.stage3.runCycles 1242 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 3.076618 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage3.utilization 3.205409 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 37465 # Number of cycles 0 instructions are processed. system.cpu.stage4.idleCycles 35843 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 2904 # Number of cycles 1+ instructions are processed. system.cpu.stage4.runCycles 2904 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 7.193639 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage4.utilization 7.494774 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 13 # number of replacements system.cpu.icache.replacements 13 # number of replacements
system.cpu.icache.tagsinuse 147.108411 # Cycle average of tags in use system.cpu.icache.tagsinuse 148.105671 # Cycle average of tags in use
system.cpu.icache.total_refs 410 # Total number of references to valid blocks. system.cpu.icache.total_refs 410 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1.285266 # Average number of references to valid blocks. system.cpu.icache.avg_refs 1.285266 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 147.108411 # Average occupied blocks per requestor system.cpu.icache.occ_blocks::cpu.inst 148.105671 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.071830 # Average percentage of cache occupancy system.cpu.icache.occ_percent::cpu.inst 0.072317 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.071830 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.072317 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 410 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 410 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 410 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 410 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 410 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 410 # number of demand (read+write) hits
@ -135,12 +293,12 @@ system.cpu.icache.demand_misses::cpu.inst 344 # n
system.cpu.icache.demand_misses::total 344 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 344 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 344 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 344 # number of overall misses
system.cpu.icache.overall_misses::total 344 # number of overall misses system.cpu.icache.overall_misses::total 344 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 19298000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 18000000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 19298000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 18000000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 19298000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 18000000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 19298000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 18000000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 19298000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 18000000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 19298000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 18000000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 754 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 754 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 754 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 754 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 754 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 754 # number of demand (read+write) accesses
@ -153,18 +311,18 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.456233
system.cpu.icache.demand_miss_rate::total 0.456233 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.456233 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.456233 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.456233 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.456233 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.456233 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56098.837209 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52325.581395 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 56098.837209 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 52325.581395 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56098.837209 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 52325.581395 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 56098.837209 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 52325.581395 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56098.837209 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 52325.581395 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 56098.837209 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 52325.581395 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 58 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 34 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 58 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 34 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 25 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::cpu.inst 25 # number of ReadReq MSHR hits
@ -179,34 +337,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 319
system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17456000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16448000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 17456000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 16448000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17456000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16448000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 17456000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 16448000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17456000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16448000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 17456000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 16448000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.423077 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.423077 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.423077 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.423077 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.423077 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.423077 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54721.003135 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51561.128527 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54721.003135 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51561.128527 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54721.003135 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51561.128527 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 54721.003135 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 51561.128527 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54721.003135 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51561.128527 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 54721.003135 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 51561.128527 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 89.235833 # Cycle average of tags in use system.cpu.dcache.tagsinuse 89.430963 # Cycle average of tags in use
system.cpu.dcache.total_refs 1834 # Total number of references to valid blocks. system.cpu.dcache.total_refs 1834 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 13.289855 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 13.289855 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 89.235833 # Average occupied blocks per requestor system.cpu.dcache.occ_blocks::cpu.data 89.430963 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.021786 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::cpu.data 0.021834 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.021786 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.021834 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1072 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 1072 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1072 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1072 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 762 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 762 # number of WriteReq hits
@ -223,14 +381,14 @@ system.cpu.dcache.demand_misses::cpu.data 254 # n
system.cpu.dcache.demand_misses::total 254 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 254 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 254 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 254 # number of overall misses
system.cpu.dcache.overall_misses::total 254 # number of overall misses system.cpu.dcache.overall_misses::total 254 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5402500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 5497500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5402500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 5497500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9244000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 8188000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 9244000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 8188000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 14646500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 13685500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 14646500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 13685500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 14646500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 13685500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 14646500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 13685500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
@ -247,20 +405,20 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.121648
system.cpu.dcache.demand_miss_rate::total 0.121648 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.121648 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.121648 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.121648 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.121648 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.121648 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59368.131868 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60412.087912 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 59368.131868 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 60412.087912 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56711.656442 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 50233.128834 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 56711.656442 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 50233.128834 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 57663.385827 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 53879.921260 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 57663.385827 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 53879.921260 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 57663.385827 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 53879.921260 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 57663.385827 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 53879.921260 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 2389 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 2069 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 103.869565 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 89.956522 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits
@ -279,14 +437,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5111000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5201000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5111000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 5201000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2905000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2605000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2905000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 2605000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8016000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7806000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 8016000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 7806000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8016000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7806000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 8016000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 7806000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
@ -295,26 +453,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092
system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58747.126437 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59781.609195 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58747.126437 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59781.609195 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56960.784314 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51078.431373 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56960.784314 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51078.431373 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58086.956522 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56565.217391 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 58086.956522 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 56565.217391 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58086.956522 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56565.217391 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 58086.956522 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 56565.217391 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 204.139180 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 205.347343 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 148.719836 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 149.740781 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 55.419344 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 55.606562 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.004539 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.004570 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.001691 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001697 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.006230 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.006267 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
@ -332,17 +490,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu
system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
system.cpu.l2cache.overall_misses::total 455 # number of overall misses system.cpu.l2cache.overall_misses::total 455 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 17110500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16102500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5017500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5107500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 22128000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 21210000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2851000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2551000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 2851000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2551000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 17110500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 16102500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 7868500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 7658500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 24979000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 23761000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 17110500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 16102500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 7868500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 7658500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 24979000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 23761000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses)
@ -365,17 +523,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53976.340694 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50796.529968 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57672.413793 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58706.896552 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 54772.277228 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55901.960784 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50019.607843 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55901.960784 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50019.607843 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53976.340694 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50796.529968 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57018.115942 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55496.376812 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 54898.901099 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 52221.978022 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53976.340694 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50796.529968 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57018.115942 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55496.376812 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 54898.901099 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 52221.978022 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -395,17 +553,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455
system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13248500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12097521 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3962500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4026597 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17211000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16124118 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2227500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1915572 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2227500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1915572 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13248500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12097521 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6190000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5942169 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 19438500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 18039690 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13248500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12097521 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6190000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5942169 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 19438500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 18039690 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses
@ -417,17 +575,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41793.375394 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38162.526814 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45545.977011 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46282.724138 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42601.485149 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39911.183168 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43676.470588 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37560.235294 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43676.470588 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37560.235294 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41793.375394 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38162.526814 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44855.072464 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43059.195652 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42721.978022 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39647.670330 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41793.375394 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38162.526814 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44855.072464 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43059.195652 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42721.978022 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39647.670330 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

982
tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
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tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
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tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
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@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.000019 # Number of seconds simulated sim_seconds 0.000018 # Number of seconds simulated
sim_ticks 18570500 # Number of ticks simulated sim_ticks 17991500 # Number of ticks simulated
final_tick 18570500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 17991500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 78205 # Simulator instruction rate (inst/s) host_inst_rate 44971 # Simulator instruction rate (inst/s)
host_op_rate 78177 # Simulator op (including micro ops) rate (op/s) host_op_rate 44961 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 272440141 # Simulator tick rate (ticks/s) host_tick_rate 151823718 # Simulator tick rate (ticks/s)
host_mem_usage 214124 # Number of bytes of host memory used host_mem_usage 222708 # Number of bytes of host memory used
host_seconds 0.07 # Real time elapsed on the host host_seconds 0.12 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated sim_ops 5327 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory
@ -19,28 +19,186 @@ system.physmem.bytes_inst_read::total 18496 # Nu
system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
system.physmem.num_reads::total 423 # Number of read requests responded to by this memory system.physmem.num_reads::total 423 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 995988261 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 1028041019 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 461807706 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 476669538 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1457795967 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 1504710558 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 995988261 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 1028041019 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 995988261 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 1028041019 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 995988261 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 1028041019 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 461807706 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 476669538 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1457795967 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1504710558 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 423 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 423 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 27072 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 27072 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 35 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 24 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 10 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 15 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 2 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 9 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 28 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 32 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 7 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 5 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 40 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 59 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 62 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 25 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 16 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 54 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 17940000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 423 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 0 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 281 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 113 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 25 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 1964422 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 11356422 # Sum of mem lat for all requests
system.physmem.totBusLat 1692000 # Total cycles spent in databus access
system.physmem.totBankLat 7700000 # Total cycles spent in bank access
system.physmem.avgQLat 4644.02 # Average queueing delay per request
system.physmem.avgBankLat 18203.31 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 26847.33 # Average memory access latency
system.physmem.avgRdBW 1504.71 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 1504.71 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 9.40 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.63 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 336 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 79.43 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 42411.35 # Average gap between requests
system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 37142 # number of cpu cycles simulated system.cpu.numCycles 35984 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 1632 # Number of BP lookups system.cpu.branch_predictor.lookups 1634 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 1036 # Number of conditional branches predicted system.cpu.branch_predictor.condPredicted 1036 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 901 # Number of conditional branches incorrect system.cpu.branch_predictor.condIncorrect 901 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 1167 # Number of BTB lookups system.cpu.branch_predictor.BTBLookups 1169 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 438 # Number of BTB hits system.cpu.branch_predictor.BTBHits 438 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 37.532134 # BTB Hit Percentage system.cpu.branch_predictor.BTBHitPct 37.467921 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 505 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedTaken 505 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 1127 # Number of Branches Predicted As Not Taken (False). system.cpu.branch_predictor.predictedNotTaken 1129 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 5626 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileReads 5626 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 3988 # Number of Writes to Int. Register File system.cpu.regfile_manager.intRegFileWrites 3988 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 9614 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.intRegFileAccesses 9614 # Total Accesses (Read+Write) to the Int. Register File
@ -58,12 +216,12 @@ system.cpu.execution_unit.executions 3966 # Nu
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 9963 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.threadCycles 9941 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 471 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 470 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 30915 # Number of cycles cpu's stages were not processed system.cpu.idleCycles 29760 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 6227 # Number of cycles cpu stages are processed. system.cpu.runCycles 6224 # Number of cycles cpu stages are processed.
system.cpu.activity 16.765387 # Percentage of cycles cpu is active system.cpu.activity 17.296576 # Percentage of cycles cpu is active
system.cpu.comLoads 715 # Number of Load instructions committed system.cpu.comLoads 715 # Number of Load instructions committed
system.cpu.comStores 673 # Number of Store instructions committed system.cpu.comStores 673 # Number of Store instructions committed
system.cpu.comBranches 1115 # Number of Branches instructions committed system.cpu.comBranches 1115 # Number of Branches instructions committed
@ -75,120 +233,120 @@ system.cpu.committedInsts 5327 # Nu
system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread) system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total) system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total)
system.cpu.cpi 6.972405 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.cpi 6.755022 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 6.972405 # CPI: Total CPI of All Threads system.cpu.cpi_total 6.755022 # CPI: Total CPI of All Threads
system.cpu.ipc 0.143423 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.ipc 0.148038 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.143423 # IPC: Total IPC of All Threads system.cpu.ipc_total 0.148038 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 32576 # Number of cycles 0 instructions are processed. system.cpu.stage0.idleCycles 31416 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 4566 # Number of cycles 1+ instructions are processed. system.cpu.stage0.runCycles 4568 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 12.293361 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage0.utilization 12.694531 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 33943 # Number of cycles 0 instructions are processed. system.cpu.stage1.idleCycles 32782 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 3199 # Number of cycles 1+ instructions are processed. system.cpu.stage1.runCycles 3202 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 8.612891 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage1.utilization 8.898399 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 34098 # Number of cycles 0 instructions are processed. system.cpu.stage2.idleCycles 32940 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 3044 # Number of cycles 1+ instructions are processed. system.cpu.stage2.runCycles 3044 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 8.195574 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage2.utilization 8.459315 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 36160 # Number of cycles 0 instructions are processed. system.cpu.stage3.idleCycles 35002 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 982 # Number of cycles 1+ instructions are processed. system.cpu.stage3.runCycles 982 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 2.643907 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage3.utilization 2.728991 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 33973 # Number of cycles 0 instructions are processed. system.cpu.stage4.idleCycles 32815 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 3169 # Number of cycles 1+ instructions are processed. system.cpu.stage4.runCycles 3169 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 8.532120 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage4.utilization 8.806692 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 136.328432 # Cycle average of tags in use system.cpu.icache.tagsinuse 138.057869 # Cycle average of tags in use
system.cpu.icache.total_refs 828 # Total number of references to valid blocks. system.cpu.icache.total_refs 829 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 2.845361 # Average number of references to valid blocks. system.cpu.icache.avg_refs 2.848797 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 136.328432 # Average occupied blocks per requestor system.cpu.icache.occ_blocks::cpu.inst 138.057869 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.066567 # Average percentage of cache occupancy system.cpu.icache.occ_percent::cpu.inst 0.067411 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.066567 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.067411 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 828 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 829 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 828 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 829 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 828 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 829 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 828 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 829 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 828 # number of overall hits system.cpu.icache.overall_hits::cpu.inst 829 # number of overall hits
system.cpu.icache.overall_hits::total 828 # number of overall hits system.cpu.icache.overall_hits::total 829 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses system.cpu.icache.ReadReq_misses::cpu.inst 348 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 348 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses system.cpu.icache.demand_misses::cpu.inst 348 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 348 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 348 # number of overall misses
system.cpu.icache.overall_misses::total 350 # number of overall misses system.cpu.icache.overall_misses::total 348 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 19327000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 18017500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 19327000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 18017500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 19327000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 18017500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 19327000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 18017500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 19327000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 18017500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 19327000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 18017500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1178 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 1177 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1178 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1177 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1178 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 1177 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1178 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 1177 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1178 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 1177 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1178 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1177 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.297114 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.295667 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.297114 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.295667 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.297114 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.295667 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.297114 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.295667 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.297114 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.295667 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.297114 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.295667 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55220 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51774.425287 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 55220 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 51774.425287 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55220 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 51774.425287 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 55220 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 51774.425287 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55220 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 51774.425287 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 55220 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 51774.425287 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 218 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 148 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 72.666667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 49.333333 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 59 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::cpu.inst 57 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 59 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 57 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 59 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 57 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 59 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 57 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 59 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 57 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15994000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15219500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 15994000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 15219500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15994000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15219500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 15994000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 15219500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15994000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15219500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 15994000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 15219500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.247239 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.247029 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.247239 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.247239 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.247029 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.247239 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.247239 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.247029 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.247239 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54962.199313 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52300.687285 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54962.199313 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52300.687285 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54962.199313 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52300.687285 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 54962.199313 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 52300.687285 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54962.199313 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52300.687285 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 54962.199313 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52300.687285 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 82.607202 # Cycle average of tags in use system.cpu.dcache.tagsinuse 83.298060 # Cycle average of tags in use
system.cpu.dcache.total_refs 1045 # Total number of references to valid blocks. system.cpu.dcache.total_refs 1045 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 7.740741 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 7.740741 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 82.607202 # Average occupied blocks per requestor system.cpu.dcache.occ_blocks::cpu.data 83.298060 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.020168 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::cpu.data 0.020336 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.020168 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.020336 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 391 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 391 # number of WriteReq hits
@ -205,14 +363,14 @@ system.cpu.dcache.demand_misses::cpu.data 343 # n
system.cpu.dcache.demand_misses::total 343 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 343 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 343 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 343 # number of overall misses
system.cpu.dcache.overall_misses::total 343 # number of overall misses system.cpu.dcache.overall_misses::total 343 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3485500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 3323500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 3485500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 3323500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 15720000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 13337500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 15720000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 13337500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 19205500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 16661000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 19205500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 16661000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 19205500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 16661000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 19205500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 16661000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
@ -229,20 +387,20 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.247118
system.cpu.dcache.demand_miss_rate::total 0.247118 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.247118 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.247118 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.247118 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.247118 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.247118 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 57139.344262 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54483.606557 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 57139.344262 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 54483.606557 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55744.680851 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47296.099291 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 55744.680851 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 47296.099291 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55992.711370 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 48574.344023 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 55992.711370 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 48574.344023 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55992.711370 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 48574.344023 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 55992.711370 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 48574.344023 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 4614 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 3752 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 102.533333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 83.377778 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits
@ -261,14 +419,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135
system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3073000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3073000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4525000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3959500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4525000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3959500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7598000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6874500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7598000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 6874500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7598000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6874500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7598000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 6874500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
@ -277,26 +435,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262
system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56907.407407 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53981.481481 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56907.407407 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53981.481481 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55864.197531 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48882.716049 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55864.197531 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48882.716049 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56281.481481 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50922.222222 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 56281.481481 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 50922.222222 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56281.481481 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50922.222222 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 56281.481481 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 50922.222222 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 161.896728 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 163.809669 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 135.841585 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 137.551022 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 26.055143 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 26.258647 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.004146 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.004198 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.000795 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000801 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.004941 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.004999 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
@ -317,17 +475,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu
system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
system.cpu.l2cache.overall_misses::total 423 # number of overall misses system.cpu.l2cache.overall_misses::total 423 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15675500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14901000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3006500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2848500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 18682000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 17749500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4441500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3876000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 4441500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3876000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 15675500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 14901000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 7448000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 6724500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 23123500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 21625500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 15675500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 14901000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 7448000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 6724500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 23123500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 21625500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses)
@ -350,17 +508,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54240.484429 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51560.553633 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56726.415094 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53745.283019 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 54625.730994 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 51899.122807 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54833.333333 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 47851.851852 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54833.333333 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 47851.851852 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54240.484429 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51560.553633 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55582.089552 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50182.835821 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 54665.484634 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 51124.113475 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54240.484429 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51560.553633 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55582.089552 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50182.835821 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 54665.484634 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 51124.113475 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -380,17 +538,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423
system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12160000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11259441 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2365000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2182574 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14525000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13442015 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3462500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2846130 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3462500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2846130 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12160000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11259441 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5827500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5028704 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 17987500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 16288145 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12160000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11259441 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5827500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5028704 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 17987500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 16288145 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses
@ -402,17 +560,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42076.124567 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38960.003460 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44622.641509 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41180.641509 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42470.760234 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39304.137427 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42746.913580 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35137.407407 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42746.913580 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35137.407407 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42076.124567 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38960.003460 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43488.805970 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37527.641791 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42523.640662 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38506.252955 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42076.124567 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38960.003460 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43488.805970 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37527.641791 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42523.640662 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38506.252955 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

1086
tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
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1305
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
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tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
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@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.000025 # Number of seconds simulated sim_seconds 0.000024 # Number of seconds simulated
sim_ticks 25317500 # Number of ticks simulated sim_ticks 24110500 # Number of ticks simulated
final_tick 25317500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 24110500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 84248 # Simulator instruction rate (inst/s) host_inst_rate 94813 # Simulator instruction rate (inst/s)
host_op_rate 84237 # Simulator op (including micro ops) rate (op/s) host_op_rate 94805 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 140641450 # Simulator tick rate (ticks/s) host_tick_rate 150747979 # Simulator tick rate (ticks/s)
host_mem_usage 214032 # Number of bytes of host memory used host_mem_usage 222632 # Number of bytes of host memory used
host_seconds 0.18 # Real time elapsed on the host host_seconds 0.16 # Real time elapsed on the host
sim_insts 15162 # Number of instructions simulated sim_insts 15162 # Number of instructions simulated
sim_ops 15162 # Number of ops (including micro ops) simulated sim_ops 15162 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory
@ -19,27 +19,185 @@ system.physmem.bytes_inst_read::total 19072 # Nu
system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
system.physmem.num_reads::total 436 # Number of read requests responded to by this memory system.physmem.num_reads::total 436 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 753312926 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 791024657 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 348849610 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 366313432 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1102162536 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 1157338089 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 753312926 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 791024657 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 753312926 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 791024657 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 753312926 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 791024657 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 348849610 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 366313432 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1102162536 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1157338089 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 436 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 436 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 27904 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 27904 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 69 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 32 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 25 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 4 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 5 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 34 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 3 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 17 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 37 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 27 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 31 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 11 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 76 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 43 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 22 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 24077000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 436 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 0 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 305 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 107 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 1670434 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 11016434 # Sum of mem lat for all requests
system.physmem.totBusLat 1744000 # Total cycles spent in databus access
system.physmem.totBankLat 7602000 # Total cycles spent in bank access
system.physmem.avgQLat 3831.27 # Average queueing delay per request
system.physmem.avgBankLat 17435.78 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 25267.05 # Average memory access latency
system.physmem.avgRdBW 1157.34 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 1157.34 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 7.23 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.46 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 359 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.34 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 55222.48 # Average gap between requests
system.cpu.workload.num_syscalls 18 # Number of system calls system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 50636 # number of cpu cycles simulated system.cpu.numCycles 48222 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 5020 # Number of BP lookups system.cpu.branch_predictor.lookups 5021 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 3412 # Number of conditional branches predicted system.cpu.branch_predictor.condPredicted 3412 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 2378 # Number of conditional branches incorrect system.cpu.branch_predictor.condIncorrect 2378 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 3517 # Number of BTB lookups system.cpu.branch_predictor.BTBLookups 3518 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 2141 # Number of BTB hits system.cpu.branch_predictor.BTBHits 2142 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 176 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.usedRAS 176 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 5 # Number of incorrect RAS predictions. system.cpu.branch_predictor.RASInCorrect 5 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 60.875746 # BTB Hit Percentage system.cpu.branch_predictor.BTBHitPct 60.886868 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 2317 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedTaken 2318 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 2703 # Number of Branches Predicted As Not Taken (False). system.cpu.branch_predictor.predictedNotTaken 2703 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 14367 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileReads 14367 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 11099 # Number of Writes to Int. Register File system.cpu.regfile_manager.intRegFileWrites 11099 # Number of Writes to Int. Register File
@ -58,12 +216,12 @@ system.cpu.execution_unit.executions 11058 # Nu
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 22132 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.threadCycles 22133 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 497 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 497 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 33281 # Number of cycles cpu's stages were not processed system.cpu.idleCycles 30866 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 17355 # Number of cycles cpu stages are processed. system.cpu.runCycles 17356 # Number of cycles cpu stages are processed.
system.cpu.activity 34.274034 # Percentage of cycles cpu is active system.cpu.activity 35.991871 # Percentage of cycles cpu is active
system.cpu.comLoads 2225 # Number of Load instructions committed system.cpu.comLoads 2225 # Number of Load instructions committed
system.cpu.comStores 1448 # Number of Store instructions committed system.cpu.comStores 1448 # Number of Store instructions committed
system.cpu.comBranches 3358 # Number of Branches instructions committed system.cpu.comBranches 3358 # Number of Branches instructions committed
@ -75,36 +233,36 @@ system.cpu.committedInsts 15162 # Nu
system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread) system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total) system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total)
system.cpu.cpi 3.339665 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.cpi 3.180451 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 3.339665 # CPI: Total CPI of All Threads system.cpu.cpi_total 3.180451 # CPI: Total CPI of All Threads
system.cpu.ipc 0.299431 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.ipc 0.314421 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.299431 # IPC: Total IPC of All Threads system.cpu.ipc_total 0.314421 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 37504 # Number of cycles 0 instructions are processed. system.cpu.stage0.idleCycles 35090 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 13132 # Number of cycles 1+ instructions are processed. system.cpu.stage0.runCycles 13132 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 25.934118 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage0.utilization 27.232384 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 41449 # Number of cycles 0 instructions are processed. system.cpu.stage1.idleCycles 39034 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 9187 # Number of cycles 1+ instructions are processed. system.cpu.stage1.runCycles 9188 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 18.143218 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage1.utilization 19.053544 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 41821 # Number of cycles 0 instructions are processed. system.cpu.stage2.idleCycles 39406 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 8815 # Number of cycles 1+ instructions are processed. system.cpu.stage2.runCycles 8816 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 17.408563 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage2.utilization 18.282112 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 47752 # Number of cycles 0 instructions are processed. system.cpu.stage3.idleCycles 45338 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 2884 # Number of cycles 1+ instructions are processed. system.cpu.stage3.runCycles 2884 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 5.695553 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage3.utilization 5.980673 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 41318 # Number of cycles 0 instructions are processed. system.cpu.stage4.idleCycles 38904 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 9318 # Number of cycles 1+ instructions are processed. system.cpu.stage4.runCycles 9318 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 18.401927 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage4.utilization 19.323131 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 164.702089 # Cycle average of tags in use system.cpu.icache.tagsinuse 166.100833 # Cycle average of tags in use
system.cpu.icache.total_refs 2586 # Total number of references to valid blocks. system.cpu.icache.total_refs 2586 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 8.648829 # Average number of references to valid blocks. system.cpu.icache.avg_refs 8.648829 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 164.702089 # Average occupied blocks per requestor system.cpu.icache.occ_blocks::cpu.inst 166.100833 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.080421 # Average percentage of cache occupancy system.cpu.icache.occ_percent::cpu.inst 0.081104 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.080421 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.081104 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 2586 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 2586 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 2586 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2586 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 2586 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 2586 # number of demand (read+write) hits
@ -117,12 +275,12 @@ system.cpu.icache.demand_misses::cpu.inst 369 # n
system.cpu.icache.demand_misses::total 369 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 369 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 369 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 369 # number of overall misses
system.cpu.icache.overall_misses::total 369 # number of overall misses system.cpu.icache.overall_misses::total 369 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 20235000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 18278500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 20235000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 18278500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 20235000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 18278500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 20235000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 18278500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 20235000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 18278500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 20235000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 18278500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 2955 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 2955 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2955 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2955 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2955 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 2955 # number of demand (read+write) accesses
@ -135,18 +293,18 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.124873
system.cpu.icache.demand_miss_rate::total 0.124873 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.124873 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.124873 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.124873 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.124873 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.124873 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54837.398374 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49535.230352 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 54837.398374 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 49535.230352 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54837.398374 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 49535.230352 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 54837.398374 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 49535.230352 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54837.398374 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 49535.230352 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 54837.398374 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 49535.230352 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 131 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 85 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 65.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 42.500000 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits
@ -161,34 +319,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 301
system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16329000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14783500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 16329000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 14783500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16329000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14783500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 16329000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 14783500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16329000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14783500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 16329000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 14783500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.101861 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.101861 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.101861 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.101861 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.101861 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.101861 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54249.169435 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49114.617940 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54249.169435 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49114.617940 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54249.169435 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49114.617940 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 54249.169435 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 49114.617940 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54249.169435 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49114.617940 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 54249.169435 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 49114.617940 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 96.602865 # Cycle average of tags in use system.cpu.dcache.tagsinuse 97.064476 # Cycle average of tags in use
system.cpu.dcache.total_refs 3314 # Total number of references to valid blocks. system.cpu.dcache.total_refs 3314 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 24.014493 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 24.014493 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 96.602865 # Average occupied blocks per requestor system.cpu.dcache.occ_blocks::cpu.data 97.064476 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.023585 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::cpu.data 0.023697 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.023585 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.023697 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 1141 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1141 # number of WriteReq hits
@ -207,14 +365,14 @@ system.cpu.dcache.demand_misses::cpu.data 359 # n
system.cpu.dcache.demand_misses::total 359 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 359 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 359 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 359 # number of overall misses
system.cpu.dcache.overall_misses::total 359 # number of overall misses system.cpu.dcache.overall_misses::total 359 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3411000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 3241000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 3411000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 3241000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 16758500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 14317500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 16758500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 14317500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 20169500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 17558500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 20169500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 17558500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 20169500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 17558500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 20169500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 17558500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
@ -233,20 +391,20 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.097900
system.cpu.dcache.demand_miss_rate::total 0.097900 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.097900 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.097900 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.097900 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.097900 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.097900 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58810.344828 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55879.310345 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 58810.344828 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 55879.310345 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55676.079734 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47566.445183 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 55676.079734 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 47566.445183 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56182.451253 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 48909.470752 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 56182.451253 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 48909.470752 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 56182.451253 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 48909.470752 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 56182.451253 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 48909.470752 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 4519 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 3701 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 100.422222 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 82.244444 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits
@ -265,14 +423,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2994500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2840500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2994500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 2840500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4733000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4329000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4733000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 4329000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7727500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7169500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7727500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 7169500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7727500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7169500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7727500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 7169500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
@ -281,26 +439,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633
system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56500 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53594.339623 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56500 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53594.339623 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55682.352941 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50929.411765 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55682.352941 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50929.411765 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55996.376812 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51952.898551 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 55996.376812 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 51952.898551 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55996.376812 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51952.898551 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 55996.376812 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 51952.898551 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 195.229432 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 196.769171 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 350 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 351 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.005714 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 0.005698 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 164.095749 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 165.497362 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 31.133683 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 31.271809 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.005008 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.005051 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.000950 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000954 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.005958 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.006005 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
@ -318,17 +476,17 @@ system.cpu.l2cache.demand_misses::total 437 # nu
system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
system.cpu.l2cache.overall_misses::total 437 # number of overall misses system.cpu.l2cache.overall_misses::total 437 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16005500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14500500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2940000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2786000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 18945500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 17286500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4645500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4241500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 4645500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 4241500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 16005500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 14500500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 7585500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 7027500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 23591000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 21528000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 16005500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 14500500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 7585500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 7027500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 23591000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 21528000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses)
@ -351,17 +509,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53530.100334 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48496.655518 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55471.698113 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52566.037736 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 53822.443182 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 49109.375000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54652.941176 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49900 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54652.941176 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49900 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53530.100334 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48496.655518 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54967.391304 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50923.913043 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 53983.981693 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 49263.157895 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53530.100334 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48496.655518 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54967.391304 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50923.913043 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 53983.981693 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 49263.157895 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -381,17 +539,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437
system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12396000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10728482 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2298500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2122568 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14694500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12851050 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3614500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3166632 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3614500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3166632 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12396000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10728482 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5913000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5289200 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 18309000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 16017682 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12396000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10728482 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5913000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5289200 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 18309000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 16017682 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses
@ -403,17 +561,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41458.193980 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35881.210702 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43367.924528 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40048.452830 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41745.738636 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36508.664773 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42523.529412 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37254.494118 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42523.529412 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37254.494118 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41458.193980 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35881.210702 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42847.826087 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38327.536232 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41897.025172 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36653.734554 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41458.193980 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35881.210702 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42847.826087 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38327.536232 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41897.025172 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36653.734554 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

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tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
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tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
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